imx6qdl-sabreauto.dtsi 2.0 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. / {
  13. memory {
  14. reg = <0x10000000 0x80000000>;
  15. };
  16. };
  17. &ecspi1 {
  18. fsl,spi-num-chipselects = <1>;
  19. cs-gpios = <&gpio3 19 0>;
  20. pinctrl-names = "default";
  21. pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>;
  22. status = "disabled"; /* pin conflict with WEIM NOR */
  23. flash: m25p80@0 {
  24. #address-cells = <1>;
  25. #size-cells = <1>;
  26. compatible = "st,m25p32";
  27. spi-max-frequency = <20000000>;
  28. reg = <0>;
  29. };
  30. };
  31. &fec {
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&pinctrl_enet_2>;
  34. phy-mode = "rgmii";
  35. status = "okay";
  36. };
  37. &gpmi {
  38. pinctrl-names = "default";
  39. pinctrl-0 = <&pinctrl_gpmi_nand_1>;
  40. status = "okay";
  41. };
  42. &iomuxc {
  43. pinctrl-names = "default";
  44. pinctrl-0 = <&pinctrl_hog>;
  45. hog {
  46. pinctrl_hog: hoggrp {
  47. fsl,pins = <
  48. MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
  49. MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
  50. >;
  51. };
  52. };
  53. ecspi1 {
  54. pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
  55. fsl,pins = <
  56. MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
  57. >;
  58. };
  59. };
  60. };
  61. &uart4 {
  62. pinctrl-names = "default";
  63. pinctrl-0 = <&pinctrl_uart4_1>;
  64. status = "okay";
  65. };
  66. &usdhc3 {
  67. pinctrl-names = "default";
  68. pinctrl-0 = <&pinctrl_usdhc3_1>;
  69. cd-gpios = <&gpio6 15 0>;
  70. wp-gpios = <&gpio1 13 0>;
  71. status = "okay";
  72. };
  73. &weim {
  74. pinctrl-names = "default";
  75. pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
  76. #address-cells = <2>;
  77. #size-cells = <1>;
  78. ranges = <0 0 0x08000000 0x08000000>;
  79. status = "disabled"; /* pin conflict with SPI NOR */
  80. nor@0,0 {
  81. compatible = "cfi-flash";
  82. reg = <0 0 0x02000000>;
  83. #address-cells = <1>;
  84. #size-cells = <1>;
  85. bank-width = <2>;
  86. fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
  87. 0x0000c000 0x1404a38e 0x00000000>;
  88. };
  89. };