57xx_hsi_bnx2fc.h 26 KB

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  1. #ifndef __57XX_FCOE_HSI_LINUX_LE__
  2. #define __57XX_FCOE_HSI_LINUX_LE__
  3. /*
  4. * common data for all protocols
  5. */
  6. struct b577xx_doorbell_hdr {
  7. u8 header;
  8. #define B577XX_DOORBELL_HDR_RX (0x1<<0)
  9. #define B577XX_DOORBELL_HDR_RX_SHIFT 0
  10. #define B577XX_DOORBELL_HDR_DB_TYPE (0x1<<1)
  11. #define B577XX_DOORBELL_HDR_DB_TYPE_SHIFT 1
  12. #define B577XX_DOORBELL_HDR_DPM_SIZE (0x3<<2)
  13. #define B577XX_DOORBELL_HDR_DPM_SIZE_SHIFT 2
  14. #define B577XX_DOORBELL_HDR_CONN_TYPE (0xF<<4)
  15. #define B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT 4
  16. };
  17. /*
  18. * doorbell message sent to the chip
  19. */
  20. struct b577xx_doorbell_set_prod {
  21. #if defined(__BIG_ENDIAN)
  22. u16 prod;
  23. u8 zero_fill1;
  24. struct b577xx_doorbell_hdr header;
  25. #elif defined(__LITTLE_ENDIAN)
  26. struct b577xx_doorbell_hdr header;
  27. u8 zero_fill1;
  28. u16 prod;
  29. #endif
  30. };
  31. struct regpair {
  32. __le32 lo;
  33. __le32 hi;
  34. };
  35. /*
  36. * Fixed size structure in order to plant it in Union structure
  37. */
  38. struct fcoe_abts_rsp_union {
  39. u32 r_ctl;
  40. u32 abts_rsp_payload[7];
  41. };
  42. /*
  43. * 4 regs size
  44. */
  45. struct fcoe_bd_ctx {
  46. u32 buf_addr_hi;
  47. u32 buf_addr_lo;
  48. #if defined(__BIG_ENDIAN)
  49. u16 rsrv0;
  50. u16 buf_len;
  51. #elif defined(__LITTLE_ENDIAN)
  52. u16 buf_len;
  53. u16 rsrv0;
  54. #endif
  55. #if defined(__BIG_ENDIAN)
  56. u16 rsrv1;
  57. u16 flags;
  58. #elif defined(__LITTLE_ENDIAN)
  59. u16 flags;
  60. u16 rsrv1;
  61. #endif
  62. };
  63. struct fcoe_cleanup_flow_info {
  64. #if defined(__BIG_ENDIAN)
  65. u16 reserved1;
  66. u16 task_id;
  67. #elif defined(__LITTLE_ENDIAN)
  68. u16 task_id;
  69. u16 reserved1;
  70. #endif
  71. u32 reserved2[7];
  72. };
  73. struct fcoe_fcp_cmd_payload {
  74. u32 opaque[8];
  75. };
  76. struct fcoe_fc_hdr {
  77. #if defined(__BIG_ENDIAN)
  78. u8 cs_ctl;
  79. u8 s_id[3];
  80. #elif defined(__LITTLE_ENDIAN)
  81. u8 s_id[3];
  82. u8 cs_ctl;
  83. #endif
  84. #if defined(__BIG_ENDIAN)
  85. u8 r_ctl;
  86. u8 d_id[3];
  87. #elif defined(__LITTLE_ENDIAN)
  88. u8 d_id[3];
  89. u8 r_ctl;
  90. #endif
  91. #if defined(__BIG_ENDIAN)
  92. u8 seq_id;
  93. u8 df_ctl;
  94. u16 seq_cnt;
  95. #elif defined(__LITTLE_ENDIAN)
  96. u16 seq_cnt;
  97. u8 df_ctl;
  98. u8 seq_id;
  99. #endif
  100. #if defined(__BIG_ENDIAN)
  101. u8 type;
  102. u8 f_ctl[3];
  103. #elif defined(__LITTLE_ENDIAN)
  104. u8 f_ctl[3];
  105. u8 type;
  106. #endif
  107. u32 parameters;
  108. #if defined(__BIG_ENDIAN)
  109. u16 ox_id;
  110. u16 rx_id;
  111. #elif defined(__LITTLE_ENDIAN)
  112. u16 rx_id;
  113. u16 ox_id;
  114. #endif
  115. };
  116. struct fcoe_fc_frame {
  117. struct fcoe_fc_hdr fc_hdr;
  118. u32 reserved0[2];
  119. };
  120. union fcoe_cmd_flow_info {
  121. struct fcoe_fcp_cmd_payload fcp_cmd_payload;
  122. struct fcoe_fc_frame mp_fc_frame;
  123. };
  124. struct fcoe_fcp_rsp_flags {
  125. u8 flags;
  126. #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
  127. #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0
  128. #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1)
  129. #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1
  130. #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2)
  131. #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2
  132. #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3)
  133. #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3
  134. #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4)
  135. #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4
  136. #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5)
  137. #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
  138. };
  139. struct fcoe_fcp_rsp_payload {
  140. struct regpair reserved0;
  141. u32 fcp_resid;
  142. #if defined(__BIG_ENDIAN)
  143. u16 retry_delay_timer;
  144. struct fcoe_fcp_rsp_flags fcp_flags;
  145. u8 scsi_status_code;
  146. #elif defined(__LITTLE_ENDIAN)
  147. u8 scsi_status_code;
  148. struct fcoe_fcp_rsp_flags fcp_flags;
  149. u16 retry_delay_timer;
  150. #endif
  151. u32 fcp_rsp_len;
  152. u32 fcp_sns_len;
  153. };
  154. /*
  155. * Fixed size structure in order to plant it in Union structure
  156. */
  157. struct fcoe_fcp_rsp_union {
  158. struct fcoe_fcp_rsp_payload payload;
  159. struct regpair reserved0;
  160. };
  161. struct fcoe_fcp_xfr_rdy_payload {
  162. u32 burst_len;
  163. u32 data_ro;
  164. };
  165. struct fcoe_read_flow_info {
  166. struct fcoe_fc_hdr fc_data_in_hdr;
  167. u32 reserved[2];
  168. };
  169. struct fcoe_write_flow_info {
  170. struct fcoe_fc_hdr fc_data_out_hdr;
  171. struct fcoe_fcp_xfr_rdy_payload fcp_xfr_payload;
  172. };
  173. union fcoe_rsp_flow_info {
  174. struct fcoe_fcp_rsp_union fcp_rsp;
  175. struct fcoe_abts_rsp_union abts_rsp;
  176. };
  177. /*
  178. * 32 bytes used for general purposes
  179. */
  180. union fcoe_general_task_ctx {
  181. union fcoe_cmd_flow_info cmd_info;
  182. struct fcoe_read_flow_info read_info;
  183. struct fcoe_write_flow_info write_info;
  184. union fcoe_rsp_flow_info rsp_info;
  185. struct fcoe_cleanup_flow_info cleanup_info;
  186. u32 comp_info[8];
  187. };
  188. /*
  189. * FCoE KCQ CQE parameters
  190. */
  191. union fcoe_kcqe_params {
  192. u32 reserved0[4];
  193. };
  194. /*
  195. * FCoE KCQ CQE
  196. */
  197. struct fcoe_kcqe {
  198. u32 fcoe_conn_id;
  199. u32 completion_status;
  200. u32 fcoe_conn_context_id;
  201. union fcoe_kcqe_params params;
  202. #if defined(__BIG_ENDIAN)
  203. u8 flags;
  204. #define FCOE_KCQE_RESERVED0 (0x7<<0)
  205. #define FCOE_KCQE_RESERVED0_SHIFT 0
  206. #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
  207. #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
  208. #define FCOE_KCQE_LAYER_CODE (0x7<<4)
  209. #define FCOE_KCQE_LAYER_CODE_SHIFT 4
  210. #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
  211. #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
  212. u8 op_code;
  213. u16 qe_self_seq;
  214. #elif defined(__LITTLE_ENDIAN)
  215. u16 qe_self_seq;
  216. u8 op_code;
  217. u8 flags;
  218. #define FCOE_KCQE_RESERVED0 (0x7<<0)
  219. #define FCOE_KCQE_RESERVED0_SHIFT 0
  220. #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
  221. #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
  222. #define FCOE_KCQE_LAYER_CODE (0x7<<4)
  223. #define FCOE_KCQE_LAYER_CODE_SHIFT 4
  224. #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
  225. #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
  226. #endif
  227. };
  228. /*
  229. * FCoE KWQE header
  230. */
  231. struct fcoe_kwqe_header {
  232. #if defined(__BIG_ENDIAN)
  233. u8 flags;
  234. #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
  235. #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
  236. #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
  237. #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
  238. #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
  239. #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
  240. u8 op_code;
  241. #elif defined(__LITTLE_ENDIAN)
  242. u8 op_code;
  243. u8 flags;
  244. #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
  245. #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
  246. #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
  247. #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
  248. #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
  249. #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
  250. #endif
  251. };
  252. /*
  253. * FCoE firmware init request 1
  254. */
  255. struct fcoe_kwqe_init1 {
  256. #if defined(__BIG_ENDIAN)
  257. struct fcoe_kwqe_header hdr;
  258. u16 num_tasks;
  259. #elif defined(__LITTLE_ENDIAN)
  260. u16 num_tasks;
  261. struct fcoe_kwqe_header hdr;
  262. #endif
  263. u32 task_list_pbl_addr_lo;
  264. u32 task_list_pbl_addr_hi;
  265. u32 dummy_buffer_addr_lo;
  266. u32 dummy_buffer_addr_hi;
  267. #if defined(__BIG_ENDIAN)
  268. u16 rq_num_wqes;
  269. u16 sq_num_wqes;
  270. #elif defined(__LITTLE_ENDIAN)
  271. u16 sq_num_wqes;
  272. u16 rq_num_wqes;
  273. #endif
  274. #if defined(__BIG_ENDIAN)
  275. u16 cq_num_wqes;
  276. u16 rq_buffer_log_size;
  277. #elif defined(__LITTLE_ENDIAN)
  278. u16 rq_buffer_log_size;
  279. u16 cq_num_wqes;
  280. #endif
  281. #if defined(__BIG_ENDIAN)
  282. u8 flags;
  283. #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
  284. #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
  285. #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
  286. #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
  287. #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
  288. #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
  289. u8 num_sessions_log;
  290. u16 mtu;
  291. #elif defined(__LITTLE_ENDIAN)
  292. u16 mtu;
  293. u8 num_sessions_log;
  294. u8 flags;
  295. #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
  296. #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
  297. #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
  298. #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
  299. #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
  300. #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
  301. #endif
  302. };
  303. /*
  304. * FCoE firmware init request 2
  305. */
  306. struct fcoe_kwqe_init2 {
  307. #if defined(__BIG_ENDIAN)
  308. struct fcoe_kwqe_header hdr;
  309. u16 reserved0;
  310. #elif defined(__LITTLE_ENDIAN)
  311. u16 reserved0;
  312. struct fcoe_kwqe_header hdr;
  313. #endif
  314. u32 hash_tbl_pbl_addr_lo;
  315. u32 hash_tbl_pbl_addr_hi;
  316. u32 t2_hash_tbl_addr_lo;
  317. u32 t2_hash_tbl_addr_hi;
  318. u32 t2_ptr_hash_tbl_addr_lo;
  319. u32 t2_ptr_hash_tbl_addr_hi;
  320. u32 free_list_count;
  321. };
  322. /*
  323. * FCoE firmware init request 3
  324. */
  325. struct fcoe_kwqe_init3 {
  326. #if defined(__BIG_ENDIAN)
  327. struct fcoe_kwqe_header hdr;
  328. u16 reserved0;
  329. #elif defined(__LITTLE_ENDIAN)
  330. u16 reserved0;
  331. struct fcoe_kwqe_header hdr;
  332. #endif
  333. u32 error_bit_map_lo;
  334. u32 error_bit_map_hi;
  335. #if defined(__BIG_ENDIAN)
  336. u8 reserved21[3];
  337. u8 cached_session_enable;
  338. #elif defined(__LITTLE_ENDIAN)
  339. u8 cached_session_enable;
  340. u8 reserved21[3];
  341. #endif
  342. u32 reserved2[4];
  343. };
  344. /*
  345. * FCoE connection offload request 1
  346. */
  347. struct fcoe_kwqe_conn_offload1 {
  348. #if defined(__BIG_ENDIAN)
  349. struct fcoe_kwqe_header hdr;
  350. u16 fcoe_conn_id;
  351. #elif defined(__LITTLE_ENDIAN)
  352. u16 fcoe_conn_id;
  353. struct fcoe_kwqe_header hdr;
  354. #endif
  355. u32 sq_addr_lo;
  356. u32 sq_addr_hi;
  357. u32 rq_pbl_addr_lo;
  358. u32 rq_pbl_addr_hi;
  359. u32 rq_first_pbe_addr_lo;
  360. u32 rq_first_pbe_addr_hi;
  361. #if defined(__BIG_ENDIAN)
  362. u16 reserved0;
  363. u16 rq_prod;
  364. #elif defined(__LITTLE_ENDIAN)
  365. u16 rq_prod;
  366. u16 reserved0;
  367. #endif
  368. };
  369. /*
  370. * FCoE connection offload request 2
  371. */
  372. struct fcoe_kwqe_conn_offload2 {
  373. #if defined(__BIG_ENDIAN)
  374. struct fcoe_kwqe_header hdr;
  375. u16 tx_max_fc_pay_len;
  376. #elif defined(__LITTLE_ENDIAN)
  377. u16 tx_max_fc_pay_len;
  378. struct fcoe_kwqe_header hdr;
  379. #endif
  380. u32 cq_addr_lo;
  381. u32 cq_addr_hi;
  382. u32 xferq_addr_lo;
  383. u32 xferq_addr_hi;
  384. u32 conn_db_addr_lo;
  385. u32 conn_db_addr_hi;
  386. u32 reserved1;
  387. };
  388. /*
  389. * FCoE connection offload request 3
  390. */
  391. struct fcoe_kwqe_conn_offload3 {
  392. #if defined(__BIG_ENDIAN)
  393. struct fcoe_kwqe_header hdr;
  394. u16 vlan_tag;
  395. #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
  396. #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
  397. #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
  398. #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
  399. #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
  400. #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
  401. #elif defined(__LITTLE_ENDIAN)
  402. u16 vlan_tag;
  403. #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
  404. #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
  405. #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
  406. #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
  407. #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
  408. #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
  409. struct fcoe_kwqe_header hdr;
  410. #endif
  411. #if defined(__BIG_ENDIAN)
  412. u8 tx_max_conc_seqs_c3;
  413. u8 s_id[3];
  414. #elif defined(__LITTLE_ENDIAN)
  415. u8 s_id[3];
  416. u8 tx_max_conc_seqs_c3;
  417. #endif
  418. #if defined(__BIG_ENDIAN)
  419. u8 flags;
  420. #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
  421. #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
  422. #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
  423. #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
  424. #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
  425. #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
  426. #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
  427. #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
  428. #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
  429. #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
  430. #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
  431. #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
  432. #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
  433. #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
  434. #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
  435. #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
  436. u8 d_id[3];
  437. #elif defined(__LITTLE_ENDIAN)
  438. u8 d_id[3];
  439. u8 flags;
  440. #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
  441. #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
  442. #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
  443. #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
  444. #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
  445. #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
  446. #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
  447. #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
  448. #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
  449. #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
  450. #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
  451. #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
  452. #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
  453. #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
  454. #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
  455. #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
  456. #endif
  457. u32 reserved;
  458. u32 confq_first_pbe_addr_lo;
  459. u32 confq_first_pbe_addr_hi;
  460. #if defined(__BIG_ENDIAN)
  461. u16 rx_max_fc_pay_len;
  462. u16 tx_total_conc_seqs;
  463. #elif defined(__LITTLE_ENDIAN)
  464. u16 tx_total_conc_seqs;
  465. u16 rx_max_fc_pay_len;
  466. #endif
  467. #if defined(__BIG_ENDIAN)
  468. u8 rx_open_seqs_exch_c3;
  469. u8 rx_max_conc_seqs_c3;
  470. u16 rx_total_conc_seqs;
  471. #elif defined(__LITTLE_ENDIAN)
  472. u16 rx_total_conc_seqs;
  473. u8 rx_max_conc_seqs_c3;
  474. u8 rx_open_seqs_exch_c3;
  475. #endif
  476. };
  477. /*
  478. * FCoE connection offload request 4
  479. */
  480. struct fcoe_kwqe_conn_offload4 {
  481. #if defined(__BIG_ENDIAN)
  482. struct fcoe_kwqe_header hdr;
  483. u8 reserved2;
  484. u8 e_d_tov_timer_val;
  485. #elif defined(__LITTLE_ENDIAN)
  486. u8 e_d_tov_timer_val;
  487. u8 reserved2;
  488. struct fcoe_kwqe_header hdr;
  489. #endif
  490. u8 src_mac_addr_lo32[4];
  491. #if defined(__BIG_ENDIAN)
  492. u8 dst_mac_addr_hi16[2];
  493. u8 src_mac_addr_hi16[2];
  494. #elif defined(__LITTLE_ENDIAN)
  495. u8 src_mac_addr_hi16[2];
  496. u8 dst_mac_addr_hi16[2];
  497. #endif
  498. u8 dst_mac_addr_lo32[4];
  499. u32 lcq_addr_lo;
  500. u32 lcq_addr_hi;
  501. u32 confq_pbl_base_addr_lo;
  502. u32 confq_pbl_base_addr_hi;
  503. };
  504. /*
  505. * FCoE connection enable request
  506. */
  507. struct fcoe_kwqe_conn_enable_disable {
  508. #if defined(__BIG_ENDIAN)
  509. struct fcoe_kwqe_header hdr;
  510. u16 reserved0;
  511. #elif defined(__LITTLE_ENDIAN)
  512. u16 reserved0;
  513. struct fcoe_kwqe_header hdr;
  514. #endif
  515. u8 src_mac_addr_lo32[4];
  516. #if defined(__BIG_ENDIAN)
  517. u16 vlan_tag;
  518. #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
  519. #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
  520. #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
  521. #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
  522. #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
  523. #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
  524. u8 src_mac_addr_hi16[2];
  525. #elif defined(__LITTLE_ENDIAN)
  526. u8 src_mac_addr_hi16[2];
  527. u16 vlan_tag;
  528. #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
  529. #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
  530. #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
  531. #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
  532. #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
  533. #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
  534. #endif
  535. u8 dst_mac_addr_lo32[4];
  536. #if defined(__BIG_ENDIAN)
  537. u16 reserved1;
  538. u8 dst_mac_addr_hi16[2];
  539. #elif defined(__LITTLE_ENDIAN)
  540. u8 dst_mac_addr_hi16[2];
  541. u16 reserved1;
  542. #endif
  543. #if defined(__BIG_ENDIAN)
  544. u8 vlan_flag;
  545. u8 s_id[3];
  546. #elif defined(__LITTLE_ENDIAN)
  547. u8 s_id[3];
  548. u8 vlan_flag;
  549. #endif
  550. #if defined(__BIG_ENDIAN)
  551. u8 reserved3;
  552. u8 d_id[3];
  553. #elif defined(__LITTLE_ENDIAN)
  554. u8 d_id[3];
  555. u8 reserved3;
  556. #endif
  557. u32 context_id;
  558. u32 conn_id;
  559. u32 reserved4;
  560. };
  561. /*
  562. * FCoE connection destroy request
  563. */
  564. struct fcoe_kwqe_conn_destroy {
  565. #if defined(__BIG_ENDIAN)
  566. struct fcoe_kwqe_header hdr;
  567. u16 reserved0;
  568. #elif defined(__LITTLE_ENDIAN)
  569. u16 reserved0;
  570. struct fcoe_kwqe_header hdr;
  571. #endif
  572. u32 context_id;
  573. u32 conn_id;
  574. u32 reserved1[5];
  575. };
  576. /*
  577. * FCoe destroy request
  578. */
  579. struct fcoe_kwqe_destroy {
  580. #if defined(__BIG_ENDIAN)
  581. struct fcoe_kwqe_header hdr;
  582. u16 reserved0;
  583. #elif defined(__LITTLE_ENDIAN)
  584. u16 reserved0;
  585. struct fcoe_kwqe_header hdr;
  586. #endif
  587. u32 reserved1[7];
  588. };
  589. /*
  590. * FCoe statistics request
  591. */
  592. struct fcoe_kwqe_stat {
  593. #if defined(__BIG_ENDIAN)
  594. struct fcoe_kwqe_header hdr;
  595. u16 reserved0;
  596. #elif defined(__LITTLE_ENDIAN)
  597. u16 reserved0;
  598. struct fcoe_kwqe_header hdr;
  599. #endif
  600. u32 stat_params_addr_lo;
  601. u32 stat_params_addr_hi;
  602. u32 reserved1[5];
  603. };
  604. /*
  605. * FCoE KWQ WQE
  606. */
  607. union fcoe_kwqe {
  608. struct fcoe_kwqe_init1 init1;
  609. struct fcoe_kwqe_init2 init2;
  610. struct fcoe_kwqe_init3 init3;
  611. struct fcoe_kwqe_conn_offload1 conn_offload1;
  612. struct fcoe_kwqe_conn_offload2 conn_offload2;
  613. struct fcoe_kwqe_conn_offload3 conn_offload3;
  614. struct fcoe_kwqe_conn_offload4 conn_offload4;
  615. struct fcoe_kwqe_conn_enable_disable conn_enable_disable;
  616. struct fcoe_kwqe_conn_destroy conn_destroy;
  617. struct fcoe_kwqe_destroy destroy;
  618. struct fcoe_kwqe_stat statistics;
  619. };
  620. struct fcoe_mul_sges_ctx {
  621. struct regpair cur_sge_addr;
  622. #if defined(__BIG_ENDIAN)
  623. u8 sgl_size;
  624. u8 cur_sge_idx;
  625. u16 cur_sge_off;
  626. #elif defined(__LITTLE_ENDIAN)
  627. u16 cur_sge_off;
  628. u8 cur_sge_idx;
  629. u8 sgl_size;
  630. #endif
  631. };
  632. struct fcoe_s_stat_ctx {
  633. u8 flags;
  634. #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0)
  635. #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0
  636. #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1)
  637. #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1
  638. #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2)
  639. #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2
  640. #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3)
  641. #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3
  642. #define FCOE_S_STAT_CTX_P_RJT (0x1<<4)
  643. #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4
  644. #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5)
  645. #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5
  646. #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6)
  647. #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
  648. };
  649. struct fcoe_seq_ctx {
  650. #if defined(__BIG_ENDIAN)
  651. u16 low_seq_cnt;
  652. struct fcoe_s_stat_ctx s_stat;
  653. u8 seq_id;
  654. #elif defined(__LITTLE_ENDIAN)
  655. u8 seq_id;
  656. struct fcoe_s_stat_ctx s_stat;
  657. u16 low_seq_cnt;
  658. #endif
  659. #if defined(__BIG_ENDIAN)
  660. u16 err_seq_cnt;
  661. u16 high_seq_cnt;
  662. #elif defined(__LITTLE_ENDIAN)
  663. u16 high_seq_cnt;
  664. u16 err_seq_cnt;
  665. #endif
  666. u32 low_exp_ro;
  667. u32 high_exp_ro;
  668. };
  669. struct fcoe_single_sge_ctx {
  670. struct regpair cur_buf_addr;
  671. #if defined(__BIG_ENDIAN)
  672. u16 reserved0;
  673. u16 cur_buf_rem;
  674. #elif defined(__LITTLE_ENDIAN)
  675. u16 cur_buf_rem;
  676. u16 reserved0;
  677. #endif
  678. };
  679. union fcoe_sgl_ctx {
  680. struct fcoe_single_sge_ctx single_sge;
  681. struct fcoe_mul_sges_ctx mul_sges;
  682. };
  683. /*
  684. * FCoE SQ element
  685. */
  686. struct fcoe_sqe {
  687. u16 wqe;
  688. #define FCOE_SQE_TASK_ID (0x7FFF<<0)
  689. #define FCOE_SQE_TASK_ID_SHIFT 0
  690. #define FCOE_SQE_TOGGLE_BIT (0x1<<15)
  691. #define FCOE_SQE_TOGGLE_BIT_SHIFT 15
  692. };
  693. struct fcoe_task_ctx_entry_tx_only {
  694. union fcoe_sgl_ctx sgl_ctx;
  695. };
  696. struct fcoe_task_ctx_entry_txwr_rxrd {
  697. #if defined(__BIG_ENDIAN)
  698. u16 verify_tx_seq;
  699. u8 init_flags;
  700. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0)
  701. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0
  702. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3)
  703. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3
  704. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4)
  705. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4
  706. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5)
  707. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5
  708. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6)
  709. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6
  710. u8 tx_flags;
  711. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0)
  712. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0
  713. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4)
  714. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4
  715. #elif defined(__LITTLE_ENDIAN)
  716. u8 tx_flags;
  717. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0)
  718. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0
  719. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4)
  720. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4
  721. u8 init_flags;
  722. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0)
  723. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0
  724. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3)
  725. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3
  726. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4)
  727. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4
  728. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5)
  729. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5
  730. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6)
  731. #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6
  732. u16 verify_tx_seq;
  733. #endif
  734. };
  735. /*
  736. * Common section. Both TX and RX processing might write and read from it in
  737. * different flows
  738. */
  739. struct fcoe_task_ctx_entry_tx_rx_cmn {
  740. u32 data_2_trns;
  741. union fcoe_general_task_ctx general;
  742. #if defined(__BIG_ENDIAN)
  743. u16 tx_low_seq_cnt;
  744. struct fcoe_s_stat_ctx tx_s_stat;
  745. u8 tx_seq_id;
  746. #elif defined(__LITTLE_ENDIAN)
  747. u8 tx_seq_id;
  748. struct fcoe_s_stat_ctx tx_s_stat;
  749. u16 tx_low_seq_cnt;
  750. #endif
  751. u32 common_flags;
  752. #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID (0xFFFFFF<<0)
  753. #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT 0
  754. #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID (0x1<<24)
  755. #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT 24
  756. #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT (0x1<<25)
  757. #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT_SHIFT 25
  758. #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER (0x1<<26)
  759. #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER_SHIFT 26
  760. #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF (0x1<<27)
  761. #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF_SHIFT 27
  762. #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME (0x1<<28)
  763. #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT 28
  764. #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV (0x7<<29)
  765. #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV_SHIFT 29
  766. };
  767. struct fcoe_task_ctx_entry_rxwr_txrd {
  768. #if defined(__BIG_ENDIAN)
  769. u16 rx_id;
  770. u16 rx_flags;
  771. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0)
  772. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0
  773. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4)
  774. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4
  775. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7)
  776. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7
  777. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8)
  778. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8
  779. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9)
  780. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9
  781. #elif defined(__LITTLE_ENDIAN)
  782. u16 rx_flags;
  783. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0)
  784. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0
  785. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4)
  786. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4
  787. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7)
  788. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7
  789. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8)
  790. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8
  791. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9)
  792. #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9
  793. u16 rx_id;
  794. #endif
  795. };
  796. struct fcoe_task_ctx_entry_rx_only {
  797. struct fcoe_seq_ctx seq_ctx;
  798. struct fcoe_seq_ctx ooo_seq_ctx;
  799. u32 rsrv3;
  800. union fcoe_sgl_ctx sgl_ctx;
  801. };
  802. struct fcoe_task_ctx_entry {
  803. struct fcoe_task_ctx_entry_tx_only tx_wr_only;
  804. struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd;
  805. struct fcoe_task_ctx_entry_tx_rx_cmn cmn;
  806. struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd;
  807. struct fcoe_task_ctx_entry_rx_only rx_wr_only;
  808. u32 reserved[4];
  809. };
  810. /*
  811. * FCoE XFRQ element
  812. */
  813. struct fcoe_xfrqe {
  814. u16 wqe;
  815. #define FCOE_XFRQE_TASK_ID (0x7FFF<<0)
  816. #define FCOE_XFRQE_TASK_ID_SHIFT 0
  817. #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15)
  818. #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15
  819. };
  820. /*
  821. * FCoE CONFQ element
  822. */
  823. struct fcoe_confqe {
  824. #if defined(__BIG_ENDIAN)
  825. u16 rx_id;
  826. u16 ox_id;
  827. #elif defined(__LITTLE_ENDIAN)
  828. u16 ox_id;
  829. u16 rx_id;
  830. #endif
  831. u32 param;
  832. };
  833. /*
  834. * FCoE conection data base
  835. */
  836. struct fcoe_conn_db {
  837. #if defined(__BIG_ENDIAN)
  838. u16 rsrv0;
  839. u16 rq_prod;
  840. #elif defined(__LITTLE_ENDIAN)
  841. u16 rq_prod;
  842. u16 rsrv0;
  843. #endif
  844. u32 rsrv1;
  845. struct regpair cq_arm;
  846. };
  847. /*
  848. * FCoE CQ element
  849. */
  850. struct fcoe_cqe {
  851. u16 wqe;
  852. #define FCOE_CQE_CQE_INFO (0x3FFF<<0)
  853. #define FCOE_CQE_CQE_INFO_SHIFT 0
  854. #define FCOE_CQE_CQE_TYPE (0x1<<14)
  855. #define FCOE_CQE_CQE_TYPE_SHIFT 14
  856. #define FCOE_CQE_TOGGLE_BIT (0x1<<15)
  857. #define FCOE_CQE_TOGGLE_BIT_SHIFT 15
  858. };
  859. /*
  860. * FCoE error/warning resporting entry
  861. */
  862. struct fcoe_err_report_entry {
  863. u32 err_warn_bitmap_lo;
  864. u32 err_warn_bitmap_hi;
  865. u32 tx_buf_off;
  866. u32 rx_buf_off;
  867. struct fcoe_fc_hdr fc_hdr;
  868. };
  869. /*
  870. * FCoE hash table entry (32 bytes)
  871. */
  872. struct fcoe_hash_table_entry {
  873. #if defined(__BIG_ENDIAN)
  874. u8 d_id_0;
  875. u8 s_id_2;
  876. u8 s_id_1;
  877. u8 s_id_0;
  878. #elif defined(__LITTLE_ENDIAN)
  879. u8 s_id_0;
  880. u8 s_id_1;
  881. u8 s_id_2;
  882. u8 d_id_0;
  883. #endif
  884. #if defined(__BIG_ENDIAN)
  885. u16 dst_mac_addr_hi;
  886. u8 d_id_2;
  887. u8 d_id_1;
  888. #elif defined(__LITTLE_ENDIAN)
  889. u8 d_id_1;
  890. u8 d_id_2;
  891. u16 dst_mac_addr_hi;
  892. #endif
  893. u32 dst_mac_addr_lo;
  894. #if defined(__BIG_ENDIAN)
  895. u16 vlan_id;
  896. u16 src_mac_addr_hi;
  897. #elif defined(__LITTLE_ENDIAN)
  898. u16 src_mac_addr_hi;
  899. u16 vlan_id;
  900. #endif
  901. u32 src_mac_addr_lo;
  902. #if defined(__BIG_ENDIAN)
  903. u16 reserved1;
  904. u8 reserved0;
  905. u8 vlan_flag;
  906. #elif defined(__LITTLE_ENDIAN)
  907. u8 vlan_flag;
  908. u8 reserved0;
  909. u16 reserved1;
  910. #endif
  911. u32 reserved2;
  912. u32 field_id;
  913. #define FCOE_HASH_TABLE_ENTRY_CID (0xFFFFFF<<0)
  914. #define FCOE_HASH_TABLE_ENTRY_CID_SHIFT 0
  915. #define FCOE_HASH_TABLE_ENTRY_RESERVED3 (0x7F<<24)
  916. #define FCOE_HASH_TABLE_ENTRY_RESERVED3_SHIFT 24
  917. #define FCOE_HASH_TABLE_ENTRY_VALID (0x1<<31)
  918. #define FCOE_HASH_TABLE_ENTRY_VALID_SHIFT 31
  919. };
  920. /*
  921. * FCoE pending work request CQE
  922. */
  923. struct fcoe_pend_wq_cqe {
  924. u16 wqe;
  925. #define FCOE_PEND_WQ_CQE_TASK_ID (0x3FFF<<0)
  926. #define FCOE_PEND_WQ_CQE_TASK_ID_SHIFT 0
  927. #define FCOE_PEND_WQ_CQE_CQE_TYPE (0x1<<14)
  928. #define FCOE_PEND_WQ_CQE_CQE_TYPE_SHIFT 14
  929. #define FCOE_PEND_WQ_CQE_TOGGLE_BIT (0x1<<15)
  930. #define FCOE_PEND_WQ_CQE_TOGGLE_BIT_SHIFT 15
  931. };
  932. /*
  933. * FCoE RX statistics parameters section#0
  934. */
  935. struct fcoe_rx_stat_params_section0 {
  936. u32 fcoe_ver_cnt;
  937. u32 fcoe_rx_pkt_cnt;
  938. u32 fcoe_rx_byte_cnt;
  939. u32 fcoe_rx_drop_pkt_cnt;
  940. };
  941. /*
  942. * FCoE RX statistics parameters section#1
  943. */
  944. struct fcoe_rx_stat_params_section1 {
  945. u32 fc_crc_cnt;
  946. u32 eofa_del_cnt;
  947. u32 miss_frame_cnt;
  948. u32 seq_timeout_cnt;
  949. u32 drop_seq_cnt;
  950. u32 fcoe_rx_drop_pkt_cnt;
  951. u32 fcp_rx_pkt_cnt;
  952. u32 reserved0;
  953. };
  954. /*
  955. * FCoE TX statistics parameters
  956. */
  957. struct fcoe_tx_stat_params {
  958. u32 fcoe_tx_pkt_cnt;
  959. u32 fcoe_tx_byte_cnt;
  960. u32 fcp_tx_pkt_cnt;
  961. u32 reserved0;
  962. };
  963. /*
  964. * FCoE statistics parameters
  965. */
  966. struct fcoe_statistics_params {
  967. struct fcoe_tx_stat_params tx_stat;
  968. struct fcoe_rx_stat_params_section0 rx_stat0;
  969. struct fcoe_rx_stat_params_section1 rx_stat1;
  970. };
  971. /*
  972. * FCoE t2 hash table entry (64 bytes)
  973. */
  974. struct fcoe_t2_hash_table_entry {
  975. struct fcoe_hash_table_entry data;
  976. struct regpair next;
  977. struct regpair reserved0[3];
  978. };
  979. /*
  980. * FCoE unsolicited CQE
  981. */
  982. struct fcoe_unsolicited_cqe {
  983. u16 wqe;
  984. #define FCOE_UNSOLICITED_CQE_SUBTYPE (0x3<<0)
  985. #define FCOE_UNSOLICITED_CQE_SUBTYPE_SHIFT 0
  986. #define FCOE_UNSOLICITED_CQE_PKT_LEN (0xFFF<<2)
  987. #define FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT 2
  988. #define FCOE_UNSOLICITED_CQE_CQE_TYPE (0x1<<14)
  989. #define FCOE_UNSOLICITED_CQE_CQE_TYPE_SHIFT 14
  990. #define FCOE_UNSOLICITED_CQE_TOGGLE_BIT (0x1<<15)
  991. #define FCOE_UNSOLICITED_CQE_TOGGLE_BIT_SHIFT 15
  992. };
  993. #endif /* __57XX_FCOE_HSI_LINUX_LE__ */