iwl3945-base.c 236 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/version.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/ieee80211_radiotap.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-3945-core.h"
  46. #include "iwl-3945.h"
  47. #include "iwl-helpers.h"
  48. #ifdef CONFIG_IWL3945_DEBUG
  49. u32 iwl3945_debug_level;
  50. #endif
  51. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  52. struct iwl3945_tx_queue *txq);
  53. /******************************************************************************
  54. *
  55. * module boiler plate
  56. *
  57. ******************************************************************************/
  58. /* module parameters */
  59. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  60. static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  61. static int iwl3945_param_disable; /* def: 0 = enable radio */
  62. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  63. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  64. static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
  65. int iwl3945_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  66. /*
  67. * module name, copyright, version, etc.
  68. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  69. */
  70. #define DRV_DESCRIPTION \
  71. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  72. #ifdef CONFIG_IWL3945_DEBUG
  73. #define VD "d"
  74. #else
  75. #define VD
  76. #endif
  77. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  78. #define VS "s"
  79. #else
  80. #define VS
  81. #endif
  82. #define IWLWIFI_VERSION "1.2.26k" VD VS
  83. #define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation"
  84. #define DRV_VERSION IWLWIFI_VERSION
  85. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86. MODULE_VERSION(DRV_VERSION);
  87. MODULE_AUTHOR(DRV_COPYRIGHT);
  88. MODULE_LICENSE("GPL");
  89. static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
  90. {
  91. u16 fc = le16_to_cpu(hdr->frame_control);
  92. int hdr_len = ieee80211_get_hdrlen(fc);
  93. if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
  94. return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
  95. return NULL;
  96. }
  97. static const struct ieee80211_supported_band *iwl3945_get_band(
  98. struct iwl3945_priv *priv, enum ieee80211_band band)
  99. {
  100. return priv->hw->wiphy->bands[band];
  101. }
  102. static int iwl3945_is_empty_essid(const char *essid, int essid_len)
  103. {
  104. /* Single white space is for Linksys APs */
  105. if (essid_len == 1 && essid[0] == ' ')
  106. return 1;
  107. /* Otherwise, if the entire essid is 0, we assume it is hidden */
  108. while (essid_len) {
  109. essid_len--;
  110. if (essid[essid_len] != '\0')
  111. return 0;
  112. }
  113. return 1;
  114. }
  115. static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
  116. {
  117. static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
  118. const char *s = essid;
  119. char *d = escaped;
  120. if (iwl3945_is_empty_essid(essid, essid_len)) {
  121. memcpy(escaped, "<hidden>", sizeof("<hidden>"));
  122. return escaped;
  123. }
  124. essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
  125. while (essid_len--) {
  126. if (*s == '\0') {
  127. *d++ = '\\';
  128. *d++ = '0';
  129. s++;
  130. } else
  131. *d++ = *s++;
  132. }
  133. *d = '\0';
  134. return escaped;
  135. }
  136. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  137. * DMA services
  138. *
  139. * Theory of operation
  140. *
  141. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  142. * of buffer descriptors, each of which points to one or more data buffers for
  143. * the device to read from or fill. Driver and device exchange status of each
  144. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  145. * entries in each circular buffer, to protect against confusing empty and full
  146. * queue states.
  147. *
  148. * The device reads or writes the data in the queues via the device's several
  149. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  150. *
  151. * For Tx queue, there are low mark and high mark limits. If, after queuing
  152. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  153. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  154. * Tx queue resumed.
  155. *
  156. * The 3945 operates with six queues: One receive queue, one transmit queue
  157. * (#4) for sending commands to the device firmware, and four transmit queues
  158. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  159. ***************************************************/
  160. int iwl3945_queue_space(const struct iwl3945_queue *q)
  161. {
  162. int s = q->read_ptr - q->write_ptr;
  163. if (q->read_ptr > q->write_ptr)
  164. s -= q->n_bd;
  165. if (s <= 0)
  166. s += q->n_window;
  167. /* keep some reserve to not confuse empty and full situations */
  168. s -= 2;
  169. if (s < 0)
  170. s = 0;
  171. return s;
  172. }
  173. int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
  174. {
  175. return q->write_ptr > q->read_ptr ?
  176. (i >= q->read_ptr && i < q->write_ptr) :
  177. !(i < q->read_ptr && i >= q->write_ptr);
  178. }
  179. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  180. {
  181. /* This is for scan command, the big buffer at end of command array */
  182. if (is_huge)
  183. return q->n_window; /* must be power of 2 */
  184. /* Otherwise, use normal size buffers */
  185. return index & (q->n_window - 1);
  186. }
  187. /**
  188. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  189. */
  190. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  191. int count, int slots_num, u32 id)
  192. {
  193. q->n_bd = count;
  194. q->n_window = slots_num;
  195. q->id = id;
  196. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  197. * and iwl_queue_dec_wrap are broken. */
  198. BUG_ON(!is_power_of_2(count));
  199. /* slots_num must be power-of-two size, otherwise
  200. * get_cmd_index is broken. */
  201. BUG_ON(!is_power_of_2(slots_num));
  202. q->low_mark = q->n_window / 4;
  203. if (q->low_mark < 4)
  204. q->low_mark = 4;
  205. q->high_mark = q->n_window / 8;
  206. if (q->high_mark < 2)
  207. q->high_mark = 2;
  208. q->write_ptr = q->read_ptr = 0;
  209. return 0;
  210. }
  211. /**
  212. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  213. */
  214. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  215. struct iwl3945_tx_queue *txq, u32 id)
  216. {
  217. struct pci_dev *dev = priv->pci_dev;
  218. /* Driver private data, only for Tx (not command) queues,
  219. * not shared with device. */
  220. if (id != IWL_CMD_QUEUE_NUM) {
  221. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  222. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  223. if (!txq->txb) {
  224. IWL_ERROR("kmalloc for auxiliary BD "
  225. "structures failed\n");
  226. goto error;
  227. }
  228. } else
  229. txq->txb = NULL;
  230. /* Circular buffer of transmit frame descriptors (TFDs),
  231. * shared with device */
  232. txq->bd = pci_alloc_consistent(dev,
  233. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  234. &txq->q.dma_addr);
  235. if (!txq->bd) {
  236. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  237. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  238. goto error;
  239. }
  240. txq->q.id = id;
  241. return 0;
  242. error:
  243. if (txq->txb) {
  244. kfree(txq->txb);
  245. txq->txb = NULL;
  246. }
  247. return -ENOMEM;
  248. }
  249. /**
  250. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  251. */
  252. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  253. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  254. {
  255. struct pci_dev *dev = priv->pci_dev;
  256. int len;
  257. int rc = 0;
  258. /*
  259. * Alloc buffer array for commands (Tx or other types of commands).
  260. * For the command queue (#4), allocate command space + one big
  261. * command for scan, since scan command is very huge; the system will
  262. * not have two scans at the same time, so only one is needed.
  263. * For data Tx queues (all other queues), no super-size command
  264. * space is needed.
  265. */
  266. len = sizeof(struct iwl3945_cmd) * slots_num;
  267. if (txq_id == IWL_CMD_QUEUE_NUM)
  268. len += IWL_MAX_SCAN_SIZE;
  269. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  270. if (!txq->cmd)
  271. return -ENOMEM;
  272. /* Alloc driver data array and TFD circular buffer */
  273. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  274. if (rc) {
  275. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  276. return -ENOMEM;
  277. }
  278. txq->need_update = 0;
  279. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  280. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  281. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  282. /* Initialize queue high/low-water, head/tail indexes */
  283. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  284. /* Tell device where to find queue, enable DMA channel. */
  285. iwl3945_hw_tx_queue_init(priv, txq);
  286. return 0;
  287. }
  288. /**
  289. * iwl3945_tx_queue_free - Deallocate DMA queue.
  290. * @txq: Transmit queue to deallocate.
  291. *
  292. * Empty queue by removing and destroying all BD's.
  293. * Free all buffers.
  294. * 0-fill, but do not free "txq" descriptor structure.
  295. */
  296. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  297. {
  298. struct iwl3945_queue *q = &txq->q;
  299. struct pci_dev *dev = priv->pci_dev;
  300. int len;
  301. if (q->n_bd == 0)
  302. return;
  303. /* first, empty all BD's */
  304. for (; q->write_ptr != q->read_ptr;
  305. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  306. iwl3945_hw_txq_free_tfd(priv, txq);
  307. len = sizeof(struct iwl3945_cmd) * q->n_window;
  308. if (q->id == IWL_CMD_QUEUE_NUM)
  309. len += IWL_MAX_SCAN_SIZE;
  310. /* De-alloc array of command/tx buffers */
  311. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  312. /* De-alloc circular buffer of TFDs */
  313. if (txq->q.n_bd)
  314. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  315. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  316. /* De-alloc array of per-TFD driver data */
  317. if (txq->txb) {
  318. kfree(txq->txb);
  319. txq->txb = NULL;
  320. }
  321. /* 0-fill queue descriptor structure */
  322. memset(txq, 0, sizeof(*txq));
  323. }
  324. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  325. /*************** STATION TABLE MANAGEMENT ****
  326. * mac80211 should be examined to determine if sta_info is duplicating
  327. * the functionality provided here
  328. */
  329. /**************************************************************/
  330. #if 0 /* temporary disable till we add real remove station */
  331. /**
  332. * iwl3945_remove_station - Remove driver's knowledge of station.
  333. *
  334. * NOTE: This does not remove station from device's station table.
  335. */
  336. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  337. {
  338. int index = IWL_INVALID_STATION;
  339. int i;
  340. unsigned long flags;
  341. spin_lock_irqsave(&priv->sta_lock, flags);
  342. if (is_ap)
  343. index = IWL_AP_ID;
  344. else if (is_broadcast_ether_addr(addr))
  345. index = priv->hw_setting.bcast_sta_id;
  346. else
  347. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  348. if (priv->stations[i].used &&
  349. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  350. addr)) {
  351. index = i;
  352. break;
  353. }
  354. if (unlikely(index == IWL_INVALID_STATION))
  355. goto out;
  356. if (priv->stations[index].used) {
  357. priv->stations[index].used = 0;
  358. priv->num_stations--;
  359. }
  360. BUG_ON(priv->num_stations < 0);
  361. out:
  362. spin_unlock_irqrestore(&priv->sta_lock, flags);
  363. return 0;
  364. }
  365. #endif
  366. /**
  367. * iwl3945_clear_stations_table - Clear the driver's station table
  368. *
  369. * NOTE: This does not clear or otherwise alter the device's station table.
  370. */
  371. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  372. {
  373. unsigned long flags;
  374. spin_lock_irqsave(&priv->sta_lock, flags);
  375. priv->num_stations = 0;
  376. memset(priv->stations, 0, sizeof(priv->stations));
  377. spin_unlock_irqrestore(&priv->sta_lock, flags);
  378. }
  379. /**
  380. * iwl3945_add_station - Add station to station tables in driver and device
  381. */
  382. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  383. {
  384. int i;
  385. int index = IWL_INVALID_STATION;
  386. struct iwl3945_station_entry *station;
  387. unsigned long flags_spin;
  388. DECLARE_MAC_BUF(mac);
  389. u8 rate;
  390. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  391. if (is_ap)
  392. index = IWL_AP_ID;
  393. else if (is_broadcast_ether_addr(addr))
  394. index = priv->hw_setting.bcast_sta_id;
  395. else
  396. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  397. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  398. addr)) {
  399. index = i;
  400. break;
  401. }
  402. if (!priv->stations[i].used &&
  403. index == IWL_INVALID_STATION)
  404. index = i;
  405. }
  406. /* These two conditions has the same outcome but keep them separate
  407. since they have different meaning */
  408. if (unlikely(index == IWL_INVALID_STATION)) {
  409. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  410. return index;
  411. }
  412. if (priv->stations[index].used &&
  413. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  414. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  415. return index;
  416. }
  417. IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
  418. station = &priv->stations[index];
  419. station->used = 1;
  420. priv->num_stations++;
  421. /* Set up the REPLY_ADD_STA command to send to device */
  422. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  423. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  424. station->sta.mode = 0;
  425. station->sta.sta.sta_id = index;
  426. station->sta.station_flags = 0;
  427. if (priv->band == IEEE80211_BAND_5GHZ)
  428. rate = IWL_RATE_6M_PLCP;
  429. else
  430. rate = IWL_RATE_1M_PLCP;
  431. /* Turn on both antennas for the station... */
  432. station->sta.rate_n_flags =
  433. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  434. station->current_rate.rate_n_flags =
  435. le16_to_cpu(station->sta.rate_n_flags);
  436. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  437. /* Add station to device's station table */
  438. iwl3945_send_add_station(priv, &station->sta, flags);
  439. return index;
  440. }
  441. /*************** DRIVER STATUS FUNCTIONS *****/
  442. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  443. {
  444. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  445. * set but EXIT_PENDING is not */
  446. return test_bit(STATUS_READY, &priv->status) &&
  447. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  448. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  449. }
  450. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  451. {
  452. return test_bit(STATUS_ALIVE, &priv->status);
  453. }
  454. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  455. {
  456. return test_bit(STATUS_INIT, &priv->status);
  457. }
  458. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  459. {
  460. return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
  461. test_bit(STATUS_RF_KILL_SW, &priv->status);
  462. }
  463. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  464. {
  465. if (iwl3945_is_rfkill(priv))
  466. return 0;
  467. return iwl3945_is_ready(priv);
  468. }
  469. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  470. #define IWL_CMD(x) case x : return #x
  471. static const char *get_cmd_string(u8 cmd)
  472. {
  473. switch (cmd) {
  474. IWL_CMD(REPLY_ALIVE);
  475. IWL_CMD(REPLY_ERROR);
  476. IWL_CMD(REPLY_RXON);
  477. IWL_CMD(REPLY_RXON_ASSOC);
  478. IWL_CMD(REPLY_QOS_PARAM);
  479. IWL_CMD(REPLY_RXON_TIMING);
  480. IWL_CMD(REPLY_ADD_STA);
  481. IWL_CMD(REPLY_REMOVE_STA);
  482. IWL_CMD(REPLY_REMOVE_ALL_STA);
  483. IWL_CMD(REPLY_3945_RX);
  484. IWL_CMD(REPLY_TX);
  485. IWL_CMD(REPLY_RATE_SCALE);
  486. IWL_CMD(REPLY_LEDS_CMD);
  487. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  488. IWL_CMD(RADAR_NOTIFICATION);
  489. IWL_CMD(REPLY_QUIET_CMD);
  490. IWL_CMD(REPLY_CHANNEL_SWITCH);
  491. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  492. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  493. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  494. IWL_CMD(POWER_TABLE_CMD);
  495. IWL_CMD(PM_SLEEP_NOTIFICATION);
  496. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  497. IWL_CMD(REPLY_SCAN_CMD);
  498. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  499. IWL_CMD(SCAN_START_NOTIFICATION);
  500. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  501. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  502. IWL_CMD(BEACON_NOTIFICATION);
  503. IWL_CMD(REPLY_TX_BEACON);
  504. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  505. IWL_CMD(QUIET_NOTIFICATION);
  506. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  507. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  508. IWL_CMD(REPLY_BT_CONFIG);
  509. IWL_CMD(REPLY_STATISTICS_CMD);
  510. IWL_CMD(STATISTICS_NOTIFICATION);
  511. IWL_CMD(REPLY_CARD_STATE_CMD);
  512. IWL_CMD(CARD_STATE_NOTIFICATION);
  513. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  514. default:
  515. return "UNKNOWN";
  516. }
  517. }
  518. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  519. /**
  520. * iwl3945_enqueue_hcmd - enqueue a uCode command
  521. * @priv: device private data point
  522. * @cmd: a point to the ucode command structure
  523. *
  524. * The function returns < 0 values to indicate the operation is
  525. * failed. On success, it turns the index (> 0) of command in the
  526. * command queue.
  527. */
  528. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  529. {
  530. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  531. struct iwl3945_queue *q = &txq->q;
  532. struct iwl3945_tfd_frame *tfd;
  533. u32 *control_flags;
  534. struct iwl3945_cmd *out_cmd;
  535. u32 idx;
  536. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  537. dma_addr_t phys_addr;
  538. int pad;
  539. u16 count;
  540. int ret;
  541. unsigned long flags;
  542. /* If any of the command structures end up being larger than
  543. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  544. * we will need to increase the size of the TFD entries */
  545. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  546. !(cmd->meta.flags & CMD_SIZE_HUGE));
  547. if (iwl3945_is_rfkill(priv)) {
  548. IWL_DEBUG_INFO("Not sending command - RF KILL");
  549. return -EIO;
  550. }
  551. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  552. IWL_ERROR("No space for Tx\n");
  553. return -ENOSPC;
  554. }
  555. spin_lock_irqsave(&priv->hcmd_lock, flags);
  556. tfd = &txq->bd[q->write_ptr];
  557. memset(tfd, 0, sizeof(*tfd));
  558. control_flags = (u32 *) tfd;
  559. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  560. out_cmd = &txq->cmd[idx];
  561. out_cmd->hdr.cmd = cmd->id;
  562. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  563. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  564. /* At this point, the out_cmd now has all of the incoming cmd
  565. * information */
  566. out_cmd->hdr.flags = 0;
  567. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  568. INDEX_TO_SEQ(q->write_ptr));
  569. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  570. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  571. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  572. offsetof(struct iwl3945_cmd, hdr);
  573. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  574. pad = U32_PAD(cmd->len);
  575. count = TFD_CTL_COUNT_GET(*control_flags);
  576. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  577. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  578. "%d bytes at %d[%d]:%d\n",
  579. get_cmd_string(out_cmd->hdr.cmd),
  580. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  581. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  582. txq->need_update = 1;
  583. /* Increment and update queue's write index */
  584. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  585. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  586. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  587. return ret ? ret : idx;
  588. }
  589. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  590. {
  591. int ret;
  592. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  593. /* An asynchronous command can not expect an SKB to be set. */
  594. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  595. /* An asynchronous command MUST have a callback. */
  596. BUG_ON(!cmd->meta.u.callback);
  597. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  598. return -EBUSY;
  599. ret = iwl3945_enqueue_hcmd(priv, cmd);
  600. if (ret < 0) {
  601. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  602. get_cmd_string(cmd->id), ret);
  603. return ret;
  604. }
  605. return 0;
  606. }
  607. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  608. {
  609. int cmd_idx;
  610. int ret;
  611. static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */
  612. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  613. /* A synchronous command can not have a callback set. */
  614. BUG_ON(cmd->meta.u.callback != NULL);
  615. if (atomic_xchg(&entry, 1)) {
  616. IWL_ERROR("Error sending %s: Already sending a host command\n",
  617. get_cmd_string(cmd->id));
  618. return -EBUSY;
  619. }
  620. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  621. if (cmd->meta.flags & CMD_WANT_SKB)
  622. cmd->meta.source = &cmd->meta;
  623. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  624. if (cmd_idx < 0) {
  625. ret = cmd_idx;
  626. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  627. get_cmd_string(cmd->id), ret);
  628. goto out;
  629. }
  630. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  631. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  632. HOST_COMPLETE_TIMEOUT);
  633. if (!ret) {
  634. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  635. IWL_ERROR("Error sending %s: time out after %dms.\n",
  636. get_cmd_string(cmd->id),
  637. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  638. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  639. ret = -ETIMEDOUT;
  640. goto cancel;
  641. }
  642. }
  643. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  644. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  645. get_cmd_string(cmd->id));
  646. ret = -ECANCELED;
  647. goto fail;
  648. }
  649. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  650. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  651. get_cmd_string(cmd->id));
  652. ret = -EIO;
  653. goto fail;
  654. }
  655. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  656. IWL_ERROR("Error: Response NULL in '%s'\n",
  657. get_cmd_string(cmd->id));
  658. ret = -EIO;
  659. goto out;
  660. }
  661. ret = 0;
  662. goto out;
  663. cancel:
  664. if (cmd->meta.flags & CMD_WANT_SKB) {
  665. struct iwl3945_cmd *qcmd;
  666. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  667. * TX cmd queue. Otherwise in case the cmd comes
  668. * in later, it will possibly set an invalid
  669. * address (cmd->meta.source). */
  670. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  671. qcmd->meta.flags &= ~CMD_WANT_SKB;
  672. }
  673. fail:
  674. if (cmd->meta.u.skb) {
  675. dev_kfree_skb_any(cmd->meta.u.skb);
  676. cmd->meta.u.skb = NULL;
  677. }
  678. out:
  679. atomic_set(&entry, 0);
  680. return ret;
  681. }
  682. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  683. {
  684. if (cmd->meta.flags & CMD_ASYNC)
  685. return iwl3945_send_cmd_async(priv, cmd);
  686. return iwl3945_send_cmd_sync(priv, cmd);
  687. }
  688. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  689. {
  690. struct iwl3945_host_cmd cmd = {
  691. .id = id,
  692. .len = len,
  693. .data = data,
  694. };
  695. return iwl3945_send_cmd_sync(priv, &cmd);
  696. }
  697. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  698. {
  699. struct iwl3945_host_cmd cmd = {
  700. .id = id,
  701. .len = sizeof(val),
  702. .data = &val,
  703. };
  704. return iwl3945_send_cmd_sync(priv, &cmd);
  705. }
  706. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  707. {
  708. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  709. }
  710. /**
  711. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  712. * @band: 2.4 or 5 GHz band
  713. * @channel: Any channel valid for the requested band
  714. * In addition to setting the staging RXON, priv->band is also set.
  715. *
  716. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  717. * in the staging RXON flag structure based on the band
  718. */
  719. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  720. enum ieee80211_band band,
  721. u16 channel)
  722. {
  723. if (!iwl3945_get_channel_info(priv, band, channel)) {
  724. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  725. channel, band);
  726. return -EINVAL;
  727. }
  728. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  729. (priv->band == band))
  730. return 0;
  731. priv->staging_rxon.channel = cpu_to_le16(channel);
  732. if (band == IEEE80211_BAND_5GHZ)
  733. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  734. else
  735. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  736. priv->band = band;
  737. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  738. return 0;
  739. }
  740. /**
  741. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  742. *
  743. * NOTE: This is really only useful during development and can eventually
  744. * be #ifdef'd out once the driver is stable and folks aren't actively
  745. * making changes
  746. */
  747. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  748. {
  749. int error = 0;
  750. int counter = 1;
  751. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  752. error |= le32_to_cpu(rxon->flags &
  753. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  754. RXON_FLG_RADAR_DETECT_MSK));
  755. if (error)
  756. IWL_WARNING("check 24G fields %d | %d\n",
  757. counter++, error);
  758. } else {
  759. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  760. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  761. if (error)
  762. IWL_WARNING("check 52 fields %d | %d\n",
  763. counter++, error);
  764. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  765. if (error)
  766. IWL_WARNING("check 52 CCK %d | %d\n",
  767. counter++, error);
  768. }
  769. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  770. if (error)
  771. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  772. /* make sure basic rates 6Mbps and 1Mbps are supported */
  773. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  774. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  775. if (error)
  776. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  777. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  778. if (error)
  779. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  780. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  781. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  782. if (error)
  783. IWL_WARNING("check CCK and short slot %d | %d\n",
  784. counter++, error);
  785. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  786. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  787. if (error)
  788. IWL_WARNING("check CCK & auto detect %d | %d\n",
  789. counter++, error);
  790. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  791. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  792. if (error)
  793. IWL_WARNING("check TGG and auto detect %d | %d\n",
  794. counter++, error);
  795. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  796. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  797. RXON_FLG_ANT_A_MSK)) == 0);
  798. if (error)
  799. IWL_WARNING("check antenna %d %d\n", counter++, error);
  800. if (error)
  801. IWL_WARNING("Tuning to channel %d\n",
  802. le16_to_cpu(rxon->channel));
  803. if (error) {
  804. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  805. return -1;
  806. }
  807. return 0;
  808. }
  809. /**
  810. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  811. * @priv: staging_rxon is compared to active_rxon
  812. *
  813. * If the RXON structure is changing enough to require a new tune,
  814. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  815. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  816. */
  817. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  818. {
  819. /* These items are only settable from the full RXON command */
  820. if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
  821. compare_ether_addr(priv->staging_rxon.bssid_addr,
  822. priv->active_rxon.bssid_addr) ||
  823. compare_ether_addr(priv->staging_rxon.node_addr,
  824. priv->active_rxon.node_addr) ||
  825. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  826. priv->active_rxon.wlap_bssid_addr) ||
  827. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  828. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  829. (priv->staging_rxon.air_propagation !=
  830. priv->active_rxon.air_propagation) ||
  831. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  832. return 1;
  833. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  834. * be updated with the RXON_ASSOC command -- however only some
  835. * flag transitions are allowed using RXON_ASSOC */
  836. /* Check if we are not switching bands */
  837. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  838. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  839. return 1;
  840. /* Check if we are switching association toggle */
  841. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  842. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  843. return 1;
  844. return 0;
  845. }
  846. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  847. {
  848. int rc = 0;
  849. struct iwl3945_rx_packet *res = NULL;
  850. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  851. struct iwl3945_host_cmd cmd = {
  852. .id = REPLY_RXON_ASSOC,
  853. .len = sizeof(rxon_assoc),
  854. .meta.flags = CMD_WANT_SKB,
  855. .data = &rxon_assoc,
  856. };
  857. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  858. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  859. if ((rxon1->flags == rxon2->flags) &&
  860. (rxon1->filter_flags == rxon2->filter_flags) &&
  861. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  862. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  863. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  864. return 0;
  865. }
  866. rxon_assoc.flags = priv->staging_rxon.flags;
  867. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  868. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  869. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  870. rxon_assoc.reserved = 0;
  871. rc = iwl3945_send_cmd_sync(priv, &cmd);
  872. if (rc)
  873. return rc;
  874. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  875. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  876. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  877. rc = -EIO;
  878. }
  879. priv->alloc_rxb_skb--;
  880. dev_kfree_skb_any(cmd.meta.u.skb);
  881. return rc;
  882. }
  883. /**
  884. * iwl3945_commit_rxon - commit staging_rxon to hardware
  885. *
  886. * The RXON command in staging_rxon is committed to the hardware and
  887. * the active_rxon structure is updated with the new data. This
  888. * function correctly transitions out of the RXON_ASSOC_MSK state if
  889. * a HW tune is required based on the RXON structure changes.
  890. */
  891. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  892. {
  893. /* cast away the const for active_rxon in this function */
  894. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  895. int rc = 0;
  896. DECLARE_MAC_BUF(mac);
  897. if (!iwl3945_is_alive(priv))
  898. return -1;
  899. /* always get timestamp with Rx frame */
  900. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  901. /* select antenna */
  902. priv->staging_rxon.flags &=
  903. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  904. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  905. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  906. if (rc) {
  907. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  908. return -EINVAL;
  909. }
  910. /* If we don't need to send a full RXON, we can use
  911. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  912. * and other flags for the current radio configuration. */
  913. if (!iwl3945_full_rxon_required(priv)) {
  914. rc = iwl3945_send_rxon_assoc(priv);
  915. if (rc) {
  916. IWL_ERROR("Error setting RXON_ASSOC "
  917. "configuration (%d).\n", rc);
  918. return rc;
  919. }
  920. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  921. return 0;
  922. }
  923. /* If we are currently associated and the new config requires
  924. * an RXON_ASSOC and the new config wants the associated mask enabled,
  925. * we must clear the associated from the active configuration
  926. * before we apply the new config */
  927. if (iwl3945_is_associated(priv) &&
  928. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  929. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  930. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  931. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  932. sizeof(struct iwl3945_rxon_cmd),
  933. &priv->active_rxon);
  934. /* If the mask clearing failed then we set
  935. * active_rxon back to what it was previously */
  936. if (rc) {
  937. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  938. IWL_ERROR("Error clearing ASSOC_MSK on current "
  939. "configuration (%d).\n", rc);
  940. return rc;
  941. }
  942. }
  943. IWL_DEBUG_INFO("Sending RXON\n"
  944. "* with%s RXON_FILTER_ASSOC_MSK\n"
  945. "* channel = %d\n"
  946. "* bssid = %s\n",
  947. ((priv->staging_rxon.filter_flags &
  948. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  949. le16_to_cpu(priv->staging_rxon.channel),
  950. print_mac(mac, priv->staging_rxon.bssid_addr));
  951. /* Apply the new configuration */
  952. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  953. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  954. if (rc) {
  955. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  956. return rc;
  957. }
  958. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  959. iwl3945_clear_stations_table(priv);
  960. /* If we issue a new RXON command which required a tune then we must
  961. * send a new TXPOWER command or we won't be able to Tx any frames */
  962. rc = iwl3945_hw_reg_send_txpower(priv);
  963. if (rc) {
  964. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  965. return rc;
  966. }
  967. /* Add the broadcast address so we can send broadcast frames */
  968. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  969. IWL_INVALID_STATION) {
  970. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  971. return -EIO;
  972. }
  973. /* If we have set the ASSOC_MSK and we are in BSS mode then
  974. * add the IWL_AP_ID to the station rate table */
  975. if (iwl3945_is_associated(priv) &&
  976. (priv->iw_mode == IEEE80211_IF_TYPE_STA))
  977. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  978. == IWL_INVALID_STATION) {
  979. IWL_ERROR("Error adding AP address for transmit.\n");
  980. return -EIO;
  981. }
  982. /* Init the hardware's rate fallback order based on the band */
  983. rc = iwl3945_init_hw_rate_table(priv);
  984. if (rc) {
  985. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  986. return -EIO;
  987. }
  988. return 0;
  989. }
  990. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  991. {
  992. struct iwl3945_bt_cmd bt_cmd = {
  993. .flags = 3,
  994. .lead_time = 0xAA,
  995. .max_kill = 1,
  996. .kill_ack_mask = 0,
  997. .kill_cts_mask = 0,
  998. };
  999. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1000. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  1001. }
  1002. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  1003. {
  1004. int rc = 0;
  1005. struct iwl3945_rx_packet *res;
  1006. struct iwl3945_host_cmd cmd = {
  1007. .id = REPLY_SCAN_ABORT_CMD,
  1008. .meta.flags = CMD_WANT_SKB,
  1009. };
  1010. /* If there isn't a scan actively going on in the hardware
  1011. * then we are in between scan bands and not actually
  1012. * actively scanning, so don't send the abort command */
  1013. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1014. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1015. return 0;
  1016. }
  1017. rc = iwl3945_send_cmd_sync(priv, &cmd);
  1018. if (rc) {
  1019. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1020. return rc;
  1021. }
  1022. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1023. if (res->u.status != CAN_ABORT_STATUS) {
  1024. /* The scan abort will return 1 for success or
  1025. * 2 for "failure". A failure condition can be
  1026. * due to simply not being in an active scan which
  1027. * can occur if we send the scan abort before we
  1028. * the microcode has notified us that a scan is
  1029. * completed. */
  1030. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  1031. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1032. clear_bit(STATUS_SCAN_HW, &priv->status);
  1033. }
  1034. dev_kfree_skb_any(cmd.meta.u.skb);
  1035. return rc;
  1036. }
  1037. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  1038. struct iwl3945_cmd *cmd,
  1039. struct sk_buff *skb)
  1040. {
  1041. return 1;
  1042. }
  1043. /*
  1044. * CARD_STATE_CMD
  1045. *
  1046. * Use: Sets the device's internal card state to enable, disable, or halt
  1047. *
  1048. * When in the 'enable' state the card operates as normal.
  1049. * When in the 'disable' state, the card enters into a low power mode.
  1050. * When in the 'halt' state, the card is shut down and must be fully
  1051. * restarted to come back on.
  1052. */
  1053. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1054. {
  1055. struct iwl3945_host_cmd cmd = {
  1056. .id = REPLY_CARD_STATE_CMD,
  1057. .len = sizeof(u32),
  1058. .data = &flags,
  1059. .meta.flags = meta_flag,
  1060. };
  1061. if (meta_flag & CMD_ASYNC)
  1062. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1063. return iwl3945_send_cmd(priv, &cmd);
  1064. }
  1065. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1066. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1067. {
  1068. struct iwl3945_rx_packet *res = NULL;
  1069. if (!skb) {
  1070. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1071. return 1;
  1072. }
  1073. res = (struct iwl3945_rx_packet *)skb->data;
  1074. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1075. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1076. res->hdr.flags);
  1077. return 1;
  1078. }
  1079. switch (res->u.add_sta.status) {
  1080. case ADD_STA_SUCCESS_MSK:
  1081. break;
  1082. default:
  1083. break;
  1084. }
  1085. /* We didn't cache the SKB; let the caller free it */
  1086. return 1;
  1087. }
  1088. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1089. struct iwl3945_addsta_cmd *sta, u8 flags)
  1090. {
  1091. struct iwl3945_rx_packet *res = NULL;
  1092. int rc = 0;
  1093. struct iwl3945_host_cmd cmd = {
  1094. .id = REPLY_ADD_STA,
  1095. .len = sizeof(struct iwl3945_addsta_cmd),
  1096. .meta.flags = flags,
  1097. .data = sta,
  1098. };
  1099. if (flags & CMD_ASYNC)
  1100. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1101. else
  1102. cmd.meta.flags |= CMD_WANT_SKB;
  1103. rc = iwl3945_send_cmd(priv, &cmd);
  1104. if (rc || (flags & CMD_ASYNC))
  1105. return rc;
  1106. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1107. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1108. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1109. res->hdr.flags);
  1110. rc = -EIO;
  1111. }
  1112. if (rc == 0) {
  1113. switch (res->u.add_sta.status) {
  1114. case ADD_STA_SUCCESS_MSK:
  1115. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1116. break;
  1117. default:
  1118. rc = -EIO;
  1119. IWL_WARNING("REPLY_ADD_STA failed\n");
  1120. break;
  1121. }
  1122. }
  1123. priv->alloc_rxb_skb--;
  1124. dev_kfree_skb_any(cmd.meta.u.skb);
  1125. return rc;
  1126. }
  1127. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1128. struct ieee80211_key_conf *keyconf,
  1129. u8 sta_id)
  1130. {
  1131. unsigned long flags;
  1132. __le16 key_flags = 0;
  1133. switch (keyconf->alg) {
  1134. case ALG_CCMP:
  1135. key_flags |= STA_KEY_FLG_CCMP;
  1136. key_flags |= cpu_to_le16(
  1137. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1138. key_flags &= ~STA_KEY_FLG_INVALID;
  1139. break;
  1140. case ALG_TKIP:
  1141. case ALG_WEP:
  1142. default:
  1143. return -EINVAL;
  1144. }
  1145. spin_lock_irqsave(&priv->sta_lock, flags);
  1146. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1147. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1148. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1149. keyconf->keylen);
  1150. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1151. keyconf->keylen);
  1152. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1153. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1154. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1155. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1156. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1157. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1158. return 0;
  1159. }
  1160. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1161. {
  1162. unsigned long flags;
  1163. spin_lock_irqsave(&priv->sta_lock, flags);
  1164. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1165. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1166. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1167. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1168. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1169. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1170. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1171. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1172. return 0;
  1173. }
  1174. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1175. {
  1176. struct list_head *element;
  1177. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1178. priv->frames_count);
  1179. while (!list_empty(&priv->free_frames)) {
  1180. element = priv->free_frames.next;
  1181. list_del(element);
  1182. kfree(list_entry(element, struct iwl3945_frame, list));
  1183. priv->frames_count--;
  1184. }
  1185. if (priv->frames_count) {
  1186. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1187. priv->frames_count);
  1188. priv->frames_count = 0;
  1189. }
  1190. }
  1191. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1192. {
  1193. struct iwl3945_frame *frame;
  1194. struct list_head *element;
  1195. if (list_empty(&priv->free_frames)) {
  1196. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1197. if (!frame) {
  1198. IWL_ERROR("Could not allocate frame!\n");
  1199. return NULL;
  1200. }
  1201. priv->frames_count++;
  1202. return frame;
  1203. }
  1204. element = priv->free_frames.next;
  1205. list_del(element);
  1206. return list_entry(element, struct iwl3945_frame, list);
  1207. }
  1208. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1209. {
  1210. memset(frame, 0, sizeof(*frame));
  1211. list_add(&frame->list, &priv->free_frames);
  1212. }
  1213. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1214. struct ieee80211_hdr *hdr,
  1215. const u8 *dest, int left)
  1216. {
  1217. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1218. ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
  1219. (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
  1220. return 0;
  1221. if (priv->ibss_beacon->len > left)
  1222. return 0;
  1223. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1224. return priv->ibss_beacon->len;
  1225. }
  1226. static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
  1227. {
  1228. u8 i;
  1229. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1230. i = iwl3945_rates[i].next_ieee) {
  1231. if (rate_mask & (1 << i))
  1232. return iwl3945_rates[i].plcp;
  1233. }
  1234. return IWL_RATE_INVALID;
  1235. }
  1236. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1237. {
  1238. struct iwl3945_frame *frame;
  1239. unsigned int frame_size;
  1240. int rc;
  1241. u8 rate;
  1242. frame = iwl3945_get_free_frame(priv);
  1243. if (!frame) {
  1244. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1245. "command.\n");
  1246. return -ENOMEM;
  1247. }
  1248. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1249. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
  1250. 0xFF0);
  1251. if (rate == IWL_INVALID_RATE)
  1252. rate = IWL_RATE_6M_PLCP;
  1253. } else {
  1254. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1255. if (rate == IWL_INVALID_RATE)
  1256. rate = IWL_RATE_1M_PLCP;
  1257. }
  1258. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1259. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1260. &frame->u.cmd[0]);
  1261. iwl3945_free_frame(priv, frame);
  1262. return rc;
  1263. }
  1264. /******************************************************************************
  1265. *
  1266. * EEPROM related functions
  1267. *
  1268. ******************************************************************************/
  1269. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1270. {
  1271. memcpy(mac, priv->eeprom.mac_address, 6);
  1272. }
  1273. /*
  1274. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1275. * embedded controller) as EEPROM reader; each read is a series of pulses
  1276. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1277. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1278. * simply claims ownership, which should be safe when this function is called
  1279. * (i.e. before loading uCode!).
  1280. */
  1281. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1282. {
  1283. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1284. return 0;
  1285. }
  1286. /**
  1287. * iwl3945_eeprom_init - read EEPROM contents
  1288. *
  1289. * Load the EEPROM contents from adapter into priv->eeprom
  1290. *
  1291. * NOTE: This routine uses the non-debug IO access functions.
  1292. */
  1293. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1294. {
  1295. u16 *e = (u16 *)&priv->eeprom;
  1296. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1297. u32 r;
  1298. int sz = sizeof(priv->eeprom);
  1299. int rc;
  1300. int i;
  1301. u16 addr;
  1302. /* The EEPROM structure has several padding buffers within it
  1303. * and when adding new EEPROM maps is subject to programmer errors
  1304. * which may be very difficult to identify without explicitly
  1305. * checking the resulting size of the eeprom map. */
  1306. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1307. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1308. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
  1309. return -ENOENT;
  1310. }
  1311. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1312. rc = iwl3945_eeprom_acquire_semaphore(priv);
  1313. if (rc < 0) {
  1314. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1315. return -ENOENT;
  1316. }
  1317. /* eeprom is an array of 16bit values */
  1318. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1319. _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
  1320. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1321. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1322. i += IWL_EEPROM_ACCESS_DELAY) {
  1323. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1324. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1325. break;
  1326. udelay(IWL_EEPROM_ACCESS_DELAY);
  1327. }
  1328. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1329. IWL_ERROR("Time out reading EEPROM[%d]", addr);
  1330. return -ETIMEDOUT;
  1331. }
  1332. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1333. }
  1334. return 0;
  1335. }
  1336. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1337. {
  1338. if (priv->hw_setting.shared_virt)
  1339. pci_free_consistent(priv->pci_dev,
  1340. sizeof(struct iwl3945_shared),
  1341. priv->hw_setting.shared_virt,
  1342. priv->hw_setting.shared_phys);
  1343. }
  1344. /**
  1345. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1346. *
  1347. * return : set the bit for each supported rate insert in ie
  1348. */
  1349. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1350. u16 basic_rate, int *left)
  1351. {
  1352. u16 ret_rates = 0, bit;
  1353. int i;
  1354. u8 *cnt = ie;
  1355. u8 *rates = ie + 1;
  1356. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1357. if (bit & supported_rate) {
  1358. ret_rates |= bit;
  1359. rates[*cnt] = iwl3945_rates[i].ieee |
  1360. ((bit & basic_rate) ? 0x80 : 0x00);
  1361. (*cnt)++;
  1362. (*left)--;
  1363. if ((*left <= 0) ||
  1364. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1365. break;
  1366. }
  1367. }
  1368. return ret_rates;
  1369. }
  1370. /**
  1371. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1372. */
  1373. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1374. struct ieee80211_mgmt *frame,
  1375. int left, int is_direct)
  1376. {
  1377. int len = 0;
  1378. u8 *pos = NULL;
  1379. u16 active_rates, ret_rates, cck_rates;
  1380. /* Make sure there is enough space for the probe request,
  1381. * two mandatory IEs and the data */
  1382. left -= 24;
  1383. if (left < 0)
  1384. return 0;
  1385. len += 24;
  1386. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1387. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1388. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1389. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1390. frame->seq_ctrl = 0;
  1391. /* fill in our indirect SSID IE */
  1392. /* ...next IE... */
  1393. left -= 2;
  1394. if (left < 0)
  1395. return 0;
  1396. len += 2;
  1397. pos = &(frame->u.probe_req.variable[0]);
  1398. *pos++ = WLAN_EID_SSID;
  1399. *pos++ = 0;
  1400. /* fill in our direct SSID IE... */
  1401. if (is_direct) {
  1402. /* ...next IE... */
  1403. left -= 2 + priv->essid_len;
  1404. if (left < 0)
  1405. return 0;
  1406. /* ... fill it in... */
  1407. *pos++ = WLAN_EID_SSID;
  1408. *pos++ = priv->essid_len;
  1409. memcpy(pos, priv->essid, priv->essid_len);
  1410. pos += priv->essid_len;
  1411. len += 2 + priv->essid_len;
  1412. }
  1413. /* fill in supported rate */
  1414. /* ...next IE... */
  1415. left -= 2;
  1416. if (left < 0)
  1417. return 0;
  1418. /* ... fill it in... */
  1419. *pos++ = WLAN_EID_SUPP_RATES;
  1420. *pos = 0;
  1421. priv->active_rate = priv->rates_mask;
  1422. active_rates = priv->active_rate;
  1423. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1424. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1425. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1426. priv->active_rate_basic, &left);
  1427. active_rates &= ~ret_rates;
  1428. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1429. priv->active_rate_basic, &left);
  1430. active_rates &= ~ret_rates;
  1431. len += 2 + *pos;
  1432. pos += (*pos) + 1;
  1433. if (active_rates == 0)
  1434. goto fill_end;
  1435. /* fill in supported extended rate */
  1436. /* ...next IE... */
  1437. left -= 2;
  1438. if (left < 0)
  1439. return 0;
  1440. /* ... fill it in... */
  1441. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1442. *pos = 0;
  1443. iwl3945_supported_rate_to_ie(pos, active_rates,
  1444. priv->active_rate_basic, &left);
  1445. if (*pos > 0)
  1446. len += 2 + *pos;
  1447. fill_end:
  1448. return (u16)len;
  1449. }
  1450. /*
  1451. * QoS support
  1452. */
  1453. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1454. struct iwl3945_qosparam_cmd *qos)
  1455. {
  1456. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1457. sizeof(struct iwl3945_qosparam_cmd), qos);
  1458. }
  1459. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1460. {
  1461. u16 cw_min = 15;
  1462. u16 cw_max = 1023;
  1463. u8 aifs = 2;
  1464. u8 is_legacy = 0;
  1465. unsigned long flags;
  1466. int i;
  1467. spin_lock_irqsave(&priv->lock, flags);
  1468. priv->qos_data.qos_active = 0;
  1469. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
  1470. if (priv->qos_data.qos_enable)
  1471. priv->qos_data.qos_active = 1;
  1472. if (!(priv->active_rate & 0xfff0)) {
  1473. cw_min = 31;
  1474. is_legacy = 1;
  1475. }
  1476. } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1477. if (priv->qos_data.qos_enable)
  1478. priv->qos_data.qos_active = 1;
  1479. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1480. cw_min = 31;
  1481. is_legacy = 1;
  1482. }
  1483. if (priv->qos_data.qos_active)
  1484. aifs = 3;
  1485. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1486. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1487. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1488. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1489. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1490. if (priv->qos_data.qos_active) {
  1491. i = 1;
  1492. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1493. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1494. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1495. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1496. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1497. i = 2;
  1498. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1499. cpu_to_le16((cw_min + 1) / 2 - 1);
  1500. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1501. cpu_to_le16(cw_max);
  1502. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1503. if (is_legacy)
  1504. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1505. cpu_to_le16(6016);
  1506. else
  1507. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1508. cpu_to_le16(3008);
  1509. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1510. i = 3;
  1511. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1512. cpu_to_le16((cw_min + 1) / 4 - 1);
  1513. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1514. cpu_to_le16((cw_max + 1) / 2 - 1);
  1515. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1516. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1517. if (is_legacy)
  1518. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1519. cpu_to_le16(3264);
  1520. else
  1521. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1522. cpu_to_le16(1504);
  1523. } else {
  1524. for (i = 1; i < 4; i++) {
  1525. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1526. cpu_to_le16(cw_min);
  1527. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1528. cpu_to_le16(cw_max);
  1529. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1530. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1531. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1532. }
  1533. }
  1534. IWL_DEBUG_QOS("set QoS to default \n");
  1535. spin_unlock_irqrestore(&priv->lock, flags);
  1536. }
  1537. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1538. {
  1539. unsigned long flags;
  1540. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1541. return;
  1542. if (!priv->qos_data.qos_enable)
  1543. return;
  1544. spin_lock_irqsave(&priv->lock, flags);
  1545. priv->qos_data.def_qos_parm.qos_flags = 0;
  1546. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1547. !priv->qos_data.qos_cap.q_AP.txop_request)
  1548. priv->qos_data.def_qos_parm.qos_flags |=
  1549. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1550. if (priv->qos_data.qos_active)
  1551. priv->qos_data.def_qos_parm.qos_flags |=
  1552. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1553. spin_unlock_irqrestore(&priv->lock, flags);
  1554. if (force || iwl3945_is_associated(priv)) {
  1555. IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
  1556. priv->qos_data.qos_active);
  1557. iwl3945_send_qos_params_command(priv,
  1558. &(priv->qos_data.def_qos_parm));
  1559. }
  1560. }
  1561. /*
  1562. * Power management (not Tx power!) functions
  1563. */
  1564. #define MSEC_TO_USEC 1024
  1565. #define NOSLP __constant_cpu_to_le32(0)
  1566. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1567. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1568. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1569. __constant_cpu_to_le32(X1), \
  1570. __constant_cpu_to_le32(X2), \
  1571. __constant_cpu_to_le32(X3), \
  1572. __constant_cpu_to_le32(X4)}
  1573. /* default power management (not Tx power) table values */
  1574. /* for tim 0-10 */
  1575. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1576. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1577. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1578. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1579. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1580. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1581. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1582. };
  1583. /* for tim > 10 */
  1584. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1585. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1586. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1587. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1588. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1589. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1590. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1591. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1592. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1593. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1594. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1595. };
  1596. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1597. {
  1598. int rc = 0, i;
  1599. struct iwl3945_power_mgr *pow_data;
  1600. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1601. u16 pci_pm;
  1602. IWL_DEBUG_POWER("Initialize power \n");
  1603. pow_data = &(priv->power_data);
  1604. memset(pow_data, 0, sizeof(*pow_data));
  1605. pow_data->active_index = IWL_POWER_RANGE_0;
  1606. pow_data->dtim_val = 0xffff;
  1607. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1608. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1609. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1610. if (rc != 0)
  1611. return 0;
  1612. else {
  1613. struct iwl3945_powertable_cmd *cmd;
  1614. IWL_DEBUG_POWER("adjust power command flags\n");
  1615. for (i = 0; i < IWL_POWER_AC; i++) {
  1616. cmd = &pow_data->pwr_range_0[i].cmd;
  1617. if (pci_pm & 0x1)
  1618. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1619. else
  1620. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1621. }
  1622. }
  1623. return rc;
  1624. }
  1625. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1626. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1627. {
  1628. int rc = 0, i;
  1629. u8 skip;
  1630. u32 max_sleep = 0;
  1631. struct iwl3945_power_vec_entry *range;
  1632. u8 period = 0;
  1633. struct iwl3945_power_mgr *pow_data;
  1634. if (mode > IWL_POWER_INDEX_5) {
  1635. IWL_DEBUG_POWER("Error invalid power mode \n");
  1636. return -1;
  1637. }
  1638. pow_data = &(priv->power_data);
  1639. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1640. range = &pow_data->pwr_range_0[0];
  1641. else
  1642. range = &pow_data->pwr_range_1[1];
  1643. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1644. #ifdef IWL_MAC80211_DISABLE
  1645. if (priv->assoc_network != NULL) {
  1646. unsigned long flags;
  1647. period = priv->assoc_network->tim.tim_period;
  1648. }
  1649. #endif /*IWL_MAC80211_DISABLE */
  1650. skip = range[mode].no_dtim;
  1651. if (period == 0) {
  1652. period = 1;
  1653. skip = 0;
  1654. }
  1655. if (skip == 0) {
  1656. max_sleep = period;
  1657. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1658. } else {
  1659. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1660. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1661. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1662. }
  1663. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1664. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1665. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1666. }
  1667. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1668. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1669. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1670. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1671. le32_to_cpu(cmd->sleep_interval[0]),
  1672. le32_to_cpu(cmd->sleep_interval[1]),
  1673. le32_to_cpu(cmd->sleep_interval[2]),
  1674. le32_to_cpu(cmd->sleep_interval[3]),
  1675. le32_to_cpu(cmd->sleep_interval[4]));
  1676. return rc;
  1677. }
  1678. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1679. {
  1680. u32 uninitialized_var(final_mode);
  1681. int rc;
  1682. struct iwl3945_powertable_cmd cmd;
  1683. /* If on battery, set to 3,
  1684. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1685. * else user level */
  1686. switch (mode) {
  1687. case IWL_POWER_BATTERY:
  1688. final_mode = IWL_POWER_INDEX_3;
  1689. break;
  1690. case IWL_POWER_AC:
  1691. final_mode = IWL_POWER_MODE_CAM;
  1692. break;
  1693. default:
  1694. final_mode = mode;
  1695. break;
  1696. }
  1697. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1698. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1699. if (final_mode == IWL_POWER_MODE_CAM)
  1700. clear_bit(STATUS_POWER_PMI, &priv->status);
  1701. else
  1702. set_bit(STATUS_POWER_PMI, &priv->status);
  1703. return rc;
  1704. }
  1705. int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  1706. {
  1707. /* Filter incoming packets to determine if they are targeted toward
  1708. * this network, discarding packets coming from ourselves */
  1709. switch (priv->iw_mode) {
  1710. case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
  1711. /* packets from our adapter are dropped (echo) */
  1712. if (!compare_ether_addr(header->addr2, priv->mac_addr))
  1713. return 0;
  1714. /* {broad,multi}cast packets to our IBSS go through */
  1715. if (is_multicast_ether_addr(header->addr1))
  1716. return !compare_ether_addr(header->addr3, priv->bssid);
  1717. /* packets to our adapter go through */
  1718. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1719. case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
  1720. /* packets from our adapter are dropped (echo) */
  1721. if (!compare_ether_addr(header->addr3, priv->mac_addr))
  1722. return 0;
  1723. /* {broad,multi}cast packets to our BSS go through */
  1724. if (is_multicast_ether_addr(header->addr1))
  1725. return !compare_ether_addr(header->addr2, priv->bssid);
  1726. /* packets to our adapter go through */
  1727. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1728. }
  1729. return 1;
  1730. }
  1731. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  1732. static const char *iwl3945_get_tx_fail_reason(u32 status)
  1733. {
  1734. switch (status & TX_STATUS_MSK) {
  1735. case TX_STATUS_SUCCESS:
  1736. return "SUCCESS";
  1737. TX_STATUS_ENTRY(SHORT_LIMIT);
  1738. TX_STATUS_ENTRY(LONG_LIMIT);
  1739. TX_STATUS_ENTRY(FIFO_UNDERRUN);
  1740. TX_STATUS_ENTRY(MGMNT_ABORT);
  1741. TX_STATUS_ENTRY(NEXT_FRAG);
  1742. TX_STATUS_ENTRY(LIFE_EXPIRE);
  1743. TX_STATUS_ENTRY(DEST_PS);
  1744. TX_STATUS_ENTRY(ABORTED);
  1745. TX_STATUS_ENTRY(BT_RETRY);
  1746. TX_STATUS_ENTRY(STA_INVALID);
  1747. TX_STATUS_ENTRY(FRAG_DROPPED);
  1748. TX_STATUS_ENTRY(TID_DISABLE);
  1749. TX_STATUS_ENTRY(FRAME_FLUSHED);
  1750. TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
  1751. TX_STATUS_ENTRY(TX_LOCKED);
  1752. TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
  1753. }
  1754. return "UNKNOWN";
  1755. }
  1756. /**
  1757. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1758. *
  1759. * NOTE: priv->mutex is not required before calling this function
  1760. */
  1761. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1762. {
  1763. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1764. clear_bit(STATUS_SCANNING, &priv->status);
  1765. return 0;
  1766. }
  1767. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1768. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1769. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1770. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1771. queue_work(priv->workqueue, &priv->abort_scan);
  1772. } else
  1773. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1774. return test_bit(STATUS_SCANNING, &priv->status);
  1775. }
  1776. return 0;
  1777. }
  1778. /**
  1779. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1780. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1781. *
  1782. * NOTE: priv->mutex must be held before calling this function
  1783. */
  1784. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1785. {
  1786. unsigned long now = jiffies;
  1787. int ret;
  1788. ret = iwl3945_scan_cancel(priv);
  1789. if (ret && ms) {
  1790. mutex_unlock(&priv->mutex);
  1791. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1792. test_bit(STATUS_SCANNING, &priv->status))
  1793. msleep(1);
  1794. mutex_lock(&priv->mutex);
  1795. return test_bit(STATUS_SCANNING, &priv->status);
  1796. }
  1797. return ret;
  1798. }
  1799. static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
  1800. {
  1801. /* Reset ieee stats */
  1802. /* We don't reset the net_device_stats (ieee->stats) on
  1803. * re-association */
  1804. priv->last_seq_num = -1;
  1805. priv->last_frag_num = -1;
  1806. priv->last_packet_time = 0;
  1807. iwl3945_scan_cancel(priv);
  1808. }
  1809. #define MAX_UCODE_BEACON_INTERVAL 1024
  1810. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1811. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1812. {
  1813. u16 new_val = 0;
  1814. u16 beacon_factor = 0;
  1815. beacon_factor =
  1816. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1817. / MAX_UCODE_BEACON_INTERVAL;
  1818. new_val = beacon_val / beacon_factor;
  1819. return cpu_to_le16(new_val);
  1820. }
  1821. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1822. {
  1823. u64 interval_tm_unit;
  1824. u64 tsf, result;
  1825. unsigned long flags;
  1826. struct ieee80211_conf *conf = NULL;
  1827. u16 beacon_int = 0;
  1828. conf = ieee80211_get_hw_conf(priv->hw);
  1829. spin_lock_irqsave(&priv->lock, flags);
  1830. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1831. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1832. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1833. tsf = priv->timestamp1;
  1834. tsf = ((tsf << 32) | priv->timestamp0);
  1835. beacon_int = priv->beacon_int;
  1836. spin_unlock_irqrestore(&priv->lock, flags);
  1837. if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
  1838. if (beacon_int == 0) {
  1839. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1840. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1841. } else {
  1842. priv->rxon_timing.beacon_interval =
  1843. cpu_to_le16(beacon_int);
  1844. priv->rxon_timing.beacon_interval =
  1845. iwl3945_adjust_beacon_interval(
  1846. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1847. }
  1848. priv->rxon_timing.atim_window = 0;
  1849. } else {
  1850. priv->rxon_timing.beacon_interval =
  1851. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1852. /* TODO: we need to get atim_window from upper stack
  1853. * for now we set to 0 */
  1854. priv->rxon_timing.atim_window = 0;
  1855. }
  1856. interval_tm_unit =
  1857. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1858. result = do_div(tsf, interval_tm_unit);
  1859. priv->rxon_timing.beacon_init_val =
  1860. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1861. IWL_DEBUG_ASSOC
  1862. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1863. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1864. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1865. le16_to_cpu(priv->rxon_timing.atim_window));
  1866. }
  1867. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1868. {
  1869. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1870. IWL_ERROR("APs don't scan.\n");
  1871. return 0;
  1872. }
  1873. if (!iwl3945_is_ready_rf(priv)) {
  1874. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1875. return -EIO;
  1876. }
  1877. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1878. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1879. return -EAGAIN;
  1880. }
  1881. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1882. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1883. "Queuing.\n");
  1884. return -EAGAIN;
  1885. }
  1886. IWL_DEBUG_INFO("Starting scan...\n");
  1887. priv->scan_bands = 2;
  1888. set_bit(STATUS_SCANNING, &priv->status);
  1889. priv->scan_start = jiffies;
  1890. priv->scan_pass_start = priv->scan_start;
  1891. queue_work(priv->workqueue, &priv->request_scan);
  1892. return 0;
  1893. }
  1894. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  1895. {
  1896. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  1897. if (hw_decrypt)
  1898. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1899. else
  1900. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1901. return 0;
  1902. }
  1903. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  1904. enum ieee80211_band band)
  1905. {
  1906. if (band == IEEE80211_BAND_5GHZ) {
  1907. priv->staging_rxon.flags &=
  1908. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1909. | RXON_FLG_CCK_MSK);
  1910. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1911. } else {
  1912. /* Copied from iwl3945_bg_post_associate() */
  1913. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1914. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1915. else
  1916. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1917. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  1918. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1919. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1920. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1921. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1922. }
  1923. }
  1924. /*
  1925. * initialize rxon structure with default values from eeprom
  1926. */
  1927. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
  1928. {
  1929. const struct iwl3945_channel_info *ch_info;
  1930. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1931. switch (priv->iw_mode) {
  1932. case IEEE80211_IF_TYPE_AP:
  1933. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1934. break;
  1935. case IEEE80211_IF_TYPE_STA:
  1936. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1937. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1938. break;
  1939. case IEEE80211_IF_TYPE_IBSS:
  1940. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1941. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1942. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1943. RXON_FILTER_ACCEPT_GRP_MSK;
  1944. break;
  1945. case IEEE80211_IF_TYPE_MNTR:
  1946. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1947. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1948. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1949. break;
  1950. }
  1951. #if 0
  1952. /* TODO: Figure out when short_preamble would be set and cache from
  1953. * that */
  1954. if (!hw_to_local(priv->hw)->short_preamble)
  1955. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1956. else
  1957. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1958. #endif
  1959. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1960. le16_to_cpu(priv->staging_rxon.channel));
  1961. if (!ch_info)
  1962. ch_info = &priv->channel_info[0];
  1963. /*
  1964. * in some case A channels are all non IBSS
  1965. * in this case force B/G channel
  1966. */
  1967. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  1968. !(is_channel_ibss(ch_info)))
  1969. ch_info = &priv->channel_info[0];
  1970. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1971. if (is_channel_a_band(ch_info))
  1972. priv->band = IEEE80211_BAND_5GHZ;
  1973. else
  1974. priv->band = IEEE80211_BAND_2GHZ;
  1975. iwl3945_set_flags_for_phymode(priv, priv->band);
  1976. priv->staging_rxon.ofdm_basic_rates =
  1977. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1978. priv->staging_rxon.cck_basic_rates =
  1979. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1980. }
  1981. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  1982. {
  1983. if (mode == IEEE80211_IF_TYPE_IBSS) {
  1984. const struct iwl3945_channel_info *ch_info;
  1985. ch_info = iwl3945_get_channel_info(priv,
  1986. priv->band,
  1987. le16_to_cpu(priv->staging_rxon.channel));
  1988. if (!ch_info || !is_channel_ibss(ch_info)) {
  1989. IWL_ERROR("channel %d not IBSS channel\n",
  1990. le16_to_cpu(priv->staging_rxon.channel));
  1991. return -EINVAL;
  1992. }
  1993. }
  1994. priv->iw_mode = mode;
  1995. iwl3945_connection_init_rx_config(priv);
  1996. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1997. iwl3945_clear_stations_table(priv);
  1998. /* dont commit rxon if rf-kill is on*/
  1999. if (!iwl3945_is_ready_rf(priv))
  2000. return -EAGAIN;
  2001. cancel_delayed_work(&priv->scan_check);
  2002. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  2003. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  2004. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  2005. return -EAGAIN;
  2006. }
  2007. iwl3945_commit_rxon(priv);
  2008. return 0;
  2009. }
  2010. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  2011. struct ieee80211_tx_control *ctl,
  2012. struct iwl3945_cmd *cmd,
  2013. struct sk_buff *skb_frag,
  2014. int last_frag)
  2015. {
  2016. struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
  2017. switch (keyinfo->alg) {
  2018. case ALG_CCMP:
  2019. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  2020. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  2021. IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
  2022. break;
  2023. case ALG_TKIP:
  2024. #if 0
  2025. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  2026. if (last_frag)
  2027. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  2028. 8);
  2029. else
  2030. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  2031. #endif
  2032. break;
  2033. case ALG_WEP:
  2034. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  2035. (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  2036. if (keyinfo->keylen == 13)
  2037. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  2038. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  2039. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  2040. "with key %d\n", ctl->key_idx);
  2041. break;
  2042. default:
  2043. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  2044. break;
  2045. }
  2046. }
  2047. /*
  2048. * handle build REPLY_TX command notification.
  2049. */
  2050. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  2051. struct iwl3945_cmd *cmd,
  2052. struct ieee80211_tx_control *ctrl,
  2053. struct ieee80211_hdr *hdr,
  2054. int is_unicast, u8 std_id)
  2055. {
  2056. __le16 *qc;
  2057. u16 fc = le16_to_cpu(hdr->frame_control);
  2058. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  2059. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2060. if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
  2061. tx_flags |= TX_CMD_FLG_ACK_MSK;
  2062. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
  2063. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2064. if (ieee80211_is_probe_response(fc) &&
  2065. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  2066. tx_flags |= TX_CMD_FLG_TSF_MSK;
  2067. } else {
  2068. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  2069. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2070. }
  2071. cmd->cmd.tx.sta_id = std_id;
  2072. if (ieee80211_get_morefrag(hdr))
  2073. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  2074. qc = ieee80211_get_qos_ctrl(hdr);
  2075. if (qc) {
  2076. cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
  2077. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  2078. } else
  2079. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2080. if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
  2081. tx_flags |= TX_CMD_FLG_RTS_MSK;
  2082. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  2083. } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
  2084. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2085. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2086. }
  2087. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  2088. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  2089. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  2090. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
  2091. if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
  2092. (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
  2093. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  2094. else
  2095. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  2096. } else
  2097. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  2098. cmd->cmd.tx.driver_txop = 0;
  2099. cmd->cmd.tx.tx_flags = tx_flags;
  2100. cmd->cmd.tx.next_frame_len = 0;
  2101. }
  2102. /**
  2103. * iwl3945_get_sta_id - Find station's index within station table
  2104. */
  2105. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2106. {
  2107. int sta_id;
  2108. u16 fc = le16_to_cpu(hdr->frame_control);
  2109. /* If this frame is broadcast or management, use broadcast station id */
  2110. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2111. is_multicast_ether_addr(hdr->addr1))
  2112. return priv->hw_setting.bcast_sta_id;
  2113. switch (priv->iw_mode) {
  2114. /* If we are a client station in a BSS network, use the special
  2115. * AP station entry (that's the only station we communicate with) */
  2116. case IEEE80211_IF_TYPE_STA:
  2117. return IWL_AP_ID;
  2118. /* If we are an AP, then find the station, or use BCAST */
  2119. case IEEE80211_IF_TYPE_AP:
  2120. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2121. if (sta_id != IWL_INVALID_STATION)
  2122. return sta_id;
  2123. return priv->hw_setting.bcast_sta_id;
  2124. /* If this frame is going out to an IBSS network, find the station,
  2125. * or create a new station table entry */
  2126. case IEEE80211_IF_TYPE_IBSS: {
  2127. DECLARE_MAC_BUF(mac);
  2128. /* Create new station table entry */
  2129. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2130. if (sta_id != IWL_INVALID_STATION)
  2131. return sta_id;
  2132. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2133. if (sta_id != IWL_INVALID_STATION)
  2134. return sta_id;
  2135. IWL_DEBUG_DROP("Station %s not in station map. "
  2136. "Defaulting to broadcast...\n",
  2137. print_mac(mac, hdr->addr1));
  2138. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2139. return priv->hw_setting.bcast_sta_id;
  2140. }
  2141. default:
  2142. IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
  2143. return priv->hw_setting.bcast_sta_id;
  2144. }
  2145. }
  2146. /*
  2147. * start REPLY_TX command process
  2148. */
  2149. static int iwl3945_tx_skb(struct iwl3945_priv *priv,
  2150. struct sk_buff *skb, struct ieee80211_tx_control *ctl)
  2151. {
  2152. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2153. struct iwl3945_tfd_frame *tfd;
  2154. u32 *control_flags;
  2155. int txq_id = ctl->queue;
  2156. struct iwl3945_tx_queue *txq = NULL;
  2157. struct iwl3945_queue *q = NULL;
  2158. dma_addr_t phys_addr;
  2159. dma_addr_t txcmd_phys;
  2160. struct iwl3945_cmd *out_cmd = NULL;
  2161. u16 len, idx, len_org;
  2162. u8 id, hdr_len, unicast;
  2163. u8 sta_id;
  2164. u16 seq_number = 0;
  2165. u16 fc;
  2166. __le16 *qc;
  2167. u8 wait_write_ptr = 0;
  2168. unsigned long flags;
  2169. int rc;
  2170. spin_lock_irqsave(&priv->lock, flags);
  2171. if (iwl3945_is_rfkill(priv)) {
  2172. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2173. goto drop_unlock;
  2174. }
  2175. if (!priv->vif) {
  2176. IWL_DEBUG_DROP("Dropping - !priv->vif\n");
  2177. goto drop_unlock;
  2178. }
  2179. if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2180. IWL_ERROR("ERROR: No TX rate available.\n");
  2181. goto drop_unlock;
  2182. }
  2183. unicast = !is_multicast_ether_addr(hdr->addr1);
  2184. id = 0;
  2185. fc = le16_to_cpu(hdr->frame_control);
  2186. #ifdef CONFIG_IWL3945_DEBUG
  2187. if (ieee80211_is_auth(fc))
  2188. IWL_DEBUG_TX("Sending AUTH frame\n");
  2189. else if (ieee80211_is_assoc_request(fc))
  2190. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2191. else if (ieee80211_is_reassoc_request(fc))
  2192. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2193. #endif
  2194. /* drop all data frame if we are not associated */
  2195. if ((!iwl3945_is_associated(priv) ||
  2196. ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) &&
  2197. ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
  2198. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2199. goto drop_unlock;
  2200. }
  2201. spin_unlock_irqrestore(&priv->lock, flags);
  2202. hdr_len = ieee80211_get_hdrlen(fc);
  2203. /* Find (or create) index into station table for destination station */
  2204. sta_id = iwl3945_get_sta_id(priv, hdr);
  2205. if (sta_id == IWL_INVALID_STATION) {
  2206. DECLARE_MAC_BUF(mac);
  2207. IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
  2208. print_mac(mac, hdr->addr1));
  2209. goto drop;
  2210. }
  2211. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2212. qc = ieee80211_get_qos_ctrl(hdr);
  2213. if (qc) {
  2214. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2215. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2216. IEEE80211_SCTL_SEQ;
  2217. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2218. (hdr->seq_ctrl &
  2219. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2220. seq_number += 0x10;
  2221. }
  2222. /* Descriptor for chosen Tx queue */
  2223. txq = &priv->txq[txq_id];
  2224. q = &txq->q;
  2225. spin_lock_irqsave(&priv->lock, flags);
  2226. /* Set up first empty TFD within this queue's circular TFD buffer */
  2227. tfd = &txq->bd[q->write_ptr];
  2228. memset(tfd, 0, sizeof(*tfd));
  2229. control_flags = (u32 *) tfd;
  2230. idx = get_cmd_index(q, q->write_ptr, 0);
  2231. /* Set up driver data for this TFD */
  2232. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2233. txq->txb[q->write_ptr].skb[0] = skb;
  2234. memcpy(&(txq->txb[q->write_ptr].status.control),
  2235. ctl, sizeof(struct ieee80211_tx_control));
  2236. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2237. out_cmd = &txq->cmd[idx];
  2238. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2239. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2240. /*
  2241. * Set up the Tx-command (not MAC!) header.
  2242. * Store the chosen Tx queue and TFD index within the sequence field;
  2243. * after Tx, uCode's Tx response will return this value so driver can
  2244. * locate the frame within the tx queue and do post-tx processing.
  2245. */
  2246. out_cmd->hdr.cmd = REPLY_TX;
  2247. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2248. INDEX_TO_SEQ(q->write_ptr)));
  2249. /* Copy MAC header from skb into command buffer */
  2250. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2251. /*
  2252. * Use the first empty entry in this queue's command buffer array
  2253. * to contain the Tx command and MAC header concatenated together
  2254. * (payload data will be in another buffer).
  2255. * Size of this varies, due to varying MAC header length.
  2256. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2257. * of the MAC header (device reads on dword boundaries).
  2258. * We'll tell device about this padding later.
  2259. */
  2260. len = priv->hw_setting.tx_cmd_len +
  2261. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2262. len_org = len;
  2263. len = (len + 3) & ~3;
  2264. if (len_org != len)
  2265. len_org = 1;
  2266. else
  2267. len_org = 0;
  2268. /* Physical address of this Tx command's header (not MAC header!),
  2269. * within command buffer array. */
  2270. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2271. offsetof(struct iwl3945_cmd, hdr);
  2272. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2273. * first entry */
  2274. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2275. if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
  2276. iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
  2277. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2278. * if any (802.11 null frames have no payload). */
  2279. len = skb->len - hdr_len;
  2280. if (len) {
  2281. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2282. len, PCI_DMA_TODEVICE);
  2283. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2284. }
  2285. if (!len)
  2286. /* If there is no payload, then we use only one Tx buffer */
  2287. *control_flags = TFD_CTL_COUNT_SET(1);
  2288. else
  2289. /* Else use 2 buffers.
  2290. * Tell 3945 about any padding after MAC header */
  2291. *control_flags = TFD_CTL_COUNT_SET(2) |
  2292. TFD_CTL_PAD_SET(U32_PAD(len));
  2293. /* Total # bytes to be transmitted */
  2294. len = (u16)skb->len;
  2295. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2296. /* TODO need this for burst mode later on */
  2297. iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
  2298. /* set is_hcca to 0; it probably will never be implemented */
  2299. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
  2300. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2301. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2302. if (!ieee80211_get_morefrag(hdr)) {
  2303. txq->need_update = 1;
  2304. if (qc) {
  2305. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2306. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2307. }
  2308. } else {
  2309. wait_write_ptr = 1;
  2310. txq->need_update = 0;
  2311. }
  2312. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2313. sizeof(out_cmd->cmd.tx));
  2314. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2315. ieee80211_get_hdrlen(fc));
  2316. /* Tell device the write index *just past* this latest filled TFD */
  2317. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2318. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2319. spin_unlock_irqrestore(&priv->lock, flags);
  2320. if (rc)
  2321. return rc;
  2322. if ((iwl3945_queue_space(q) < q->high_mark)
  2323. && priv->mac80211_registered) {
  2324. if (wait_write_ptr) {
  2325. spin_lock_irqsave(&priv->lock, flags);
  2326. txq->need_update = 1;
  2327. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2328. spin_unlock_irqrestore(&priv->lock, flags);
  2329. }
  2330. ieee80211_stop_queue(priv->hw, ctl->queue);
  2331. }
  2332. return 0;
  2333. drop_unlock:
  2334. spin_unlock_irqrestore(&priv->lock, flags);
  2335. drop:
  2336. return -1;
  2337. }
  2338. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2339. {
  2340. const struct ieee80211_supported_band *sband = NULL;
  2341. struct ieee80211_rate *rate;
  2342. int i;
  2343. sband = iwl3945_get_band(priv, priv->band);
  2344. if (!sband) {
  2345. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2346. return;
  2347. }
  2348. priv->active_rate = 0;
  2349. priv->active_rate_basic = 0;
  2350. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2351. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2352. for (i = 0; i < sband->n_bitrates; i++) {
  2353. rate = &sband->bitrates[i];
  2354. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2355. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2356. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2357. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2358. priv->active_rate |= (1 << rate->hw_value);
  2359. }
  2360. }
  2361. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2362. priv->active_rate, priv->active_rate_basic);
  2363. /*
  2364. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2365. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2366. * OFDM
  2367. */
  2368. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2369. priv->staging_rxon.cck_basic_rates =
  2370. ((priv->active_rate_basic &
  2371. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2372. else
  2373. priv->staging_rxon.cck_basic_rates =
  2374. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2375. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2376. priv->staging_rxon.ofdm_basic_rates =
  2377. ((priv->active_rate_basic &
  2378. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2379. IWL_FIRST_OFDM_RATE) & 0xFF;
  2380. else
  2381. priv->staging_rxon.ofdm_basic_rates =
  2382. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2383. }
  2384. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2385. {
  2386. unsigned long flags;
  2387. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2388. return;
  2389. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2390. disable_radio ? "OFF" : "ON");
  2391. if (disable_radio) {
  2392. iwl3945_scan_cancel(priv);
  2393. /* FIXME: This is a workaround for AP */
  2394. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  2395. spin_lock_irqsave(&priv->lock, flags);
  2396. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2397. CSR_UCODE_SW_BIT_RFKILL);
  2398. spin_unlock_irqrestore(&priv->lock, flags);
  2399. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2400. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2401. }
  2402. return;
  2403. }
  2404. spin_lock_irqsave(&priv->lock, flags);
  2405. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2406. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2407. spin_unlock_irqrestore(&priv->lock, flags);
  2408. /* wake up ucode */
  2409. msleep(10);
  2410. spin_lock_irqsave(&priv->lock, flags);
  2411. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2412. if (!iwl3945_grab_nic_access(priv))
  2413. iwl3945_release_nic_access(priv);
  2414. spin_unlock_irqrestore(&priv->lock, flags);
  2415. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2416. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2417. "disabled by HW switch\n");
  2418. return;
  2419. }
  2420. queue_work(priv->workqueue, &priv->restart);
  2421. return;
  2422. }
  2423. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2424. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2425. {
  2426. u16 fc =
  2427. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2428. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2429. return;
  2430. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2431. return;
  2432. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2433. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2434. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2435. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2436. RX_RES_STATUS_BAD_ICV_MIC)
  2437. stats->flag |= RX_FLAG_MMIC_ERROR;
  2438. case RX_RES_STATUS_SEC_TYPE_WEP:
  2439. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2440. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2441. RX_RES_STATUS_DECRYPT_OK) {
  2442. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2443. stats->flag |= RX_FLAG_DECRYPTED;
  2444. }
  2445. break;
  2446. default:
  2447. break;
  2448. }
  2449. }
  2450. #define IWL_PACKET_RETRY_TIME HZ
  2451. int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  2452. {
  2453. u16 sc = le16_to_cpu(header->seq_ctrl);
  2454. u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
  2455. u16 frag = sc & IEEE80211_SCTL_FRAG;
  2456. u16 *last_seq, *last_frag;
  2457. unsigned long *last_time;
  2458. switch (priv->iw_mode) {
  2459. case IEEE80211_IF_TYPE_IBSS:{
  2460. struct list_head *p;
  2461. struct iwl3945_ibss_seq *entry = NULL;
  2462. u8 *mac = header->addr2;
  2463. int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
  2464. __list_for_each(p, &priv->ibss_mac_hash[index]) {
  2465. entry = list_entry(p, struct iwl3945_ibss_seq, list);
  2466. if (!compare_ether_addr(entry->mac, mac))
  2467. break;
  2468. }
  2469. if (p == &priv->ibss_mac_hash[index]) {
  2470. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  2471. if (!entry) {
  2472. IWL_ERROR("Cannot malloc new mac entry\n");
  2473. return 0;
  2474. }
  2475. memcpy(entry->mac, mac, ETH_ALEN);
  2476. entry->seq_num = seq;
  2477. entry->frag_num = frag;
  2478. entry->packet_time = jiffies;
  2479. list_add(&entry->list, &priv->ibss_mac_hash[index]);
  2480. return 0;
  2481. }
  2482. last_seq = &entry->seq_num;
  2483. last_frag = &entry->frag_num;
  2484. last_time = &entry->packet_time;
  2485. break;
  2486. }
  2487. case IEEE80211_IF_TYPE_STA:
  2488. last_seq = &priv->last_seq_num;
  2489. last_frag = &priv->last_frag_num;
  2490. last_time = &priv->last_packet_time;
  2491. break;
  2492. default:
  2493. return 0;
  2494. }
  2495. if ((*last_seq == seq) &&
  2496. time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
  2497. if (*last_frag == frag)
  2498. goto drop;
  2499. if (*last_frag + 1 != frag)
  2500. /* out-of-order fragment */
  2501. goto drop;
  2502. } else
  2503. *last_seq = seq;
  2504. *last_frag = frag;
  2505. *last_time = jiffies;
  2506. return 0;
  2507. drop:
  2508. return 1;
  2509. }
  2510. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2511. #include "iwl-spectrum.h"
  2512. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2513. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2514. #define TIME_UNIT 1024
  2515. /*
  2516. * extended beacon time format
  2517. * time in usec will be changed into a 32-bit value in 8:24 format
  2518. * the high 1 byte is the beacon counts
  2519. * the lower 3 bytes is the time in usec within one beacon interval
  2520. */
  2521. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2522. {
  2523. u32 quot;
  2524. u32 rem;
  2525. u32 interval = beacon_interval * 1024;
  2526. if (!interval || !usec)
  2527. return 0;
  2528. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2529. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2530. return (quot << 24) + rem;
  2531. }
  2532. /* base is usually what we get from ucode with each received frame,
  2533. * the same as HW timer counter counting down
  2534. */
  2535. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2536. {
  2537. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2538. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2539. u32 interval = beacon_interval * TIME_UNIT;
  2540. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2541. (addon & BEACON_TIME_MASK_HIGH);
  2542. if (base_low > addon_low)
  2543. res += base_low - addon_low;
  2544. else if (base_low < addon_low) {
  2545. res += interval + base_low - addon_low;
  2546. res += (1 << 24);
  2547. } else
  2548. res += (1 << 24);
  2549. return cpu_to_le32(res);
  2550. }
  2551. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2552. struct ieee80211_measurement_params *params,
  2553. u8 type)
  2554. {
  2555. struct iwl3945_spectrum_cmd spectrum;
  2556. struct iwl3945_rx_packet *res;
  2557. struct iwl3945_host_cmd cmd = {
  2558. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2559. .data = (void *)&spectrum,
  2560. .meta.flags = CMD_WANT_SKB,
  2561. };
  2562. u32 add_time = le64_to_cpu(params->start_time);
  2563. int rc;
  2564. int spectrum_resp_status;
  2565. int duration = le16_to_cpu(params->duration);
  2566. if (iwl3945_is_associated(priv))
  2567. add_time =
  2568. iwl3945_usecs_to_beacons(
  2569. le64_to_cpu(params->start_time) - priv->last_tsf,
  2570. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2571. memset(&spectrum, 0, sizeof(spectrum));
  2572. spectrum.channel_count = cpu_to_le16(1);
  2573. spectrum.flags =
  2574. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2575. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2576. cmd.len = sizeof(spectrum);
  2577. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2578. if (iwl3945_is_associated(priv))
  2579. spectrum.start_time =
  2580. iwl3945_add_beacon_time(priv->last_beacon_time,
  2581. add_time,
  2582. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2583. else
  2584. spectrum.start_time = 0;
  2585. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2586. spectrum.channels[0].channel = params->channel;
  2587. spectrum.channels[0].type = type;
  2588. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2589. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2590. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2591. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2592. if (rc)
  2593. return rc;
  2594. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2595. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2596. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2597. rc = -EIO;
  2598. }
  2599. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2600. switch (spectrum_resp_status) {
  2601. case 0: /* Command will be handled */
  2602. if (res->u.spectrum.id != 0xff) {
  2603. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2604. res->u.spectrum.id);
  2605. priv->measurement_status &= ~MEASUREMENT_READY;
  2606. }
  2607. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2608. rc = 0;
  2609. break;
  2610. case 1: /* Command will not be handled */
  2611. rc = -EAGAIN;
  2612. break;
  2613. }
  2614. dev_kfree_skb_any(cmd.meta.u.skb);
  2615. return rc;
  2616. }
  2617. #endif
  2618. static void iwl3945_txstatus_to_ieee(struct iwl3945_priv *priv,
  2619. struct iwl3945_tx_info *tx_sta)
  2620. {
  2621. tx_sta->status.ack_signal = 0;
  2622. tx_sta->status.excessive_retries = 0;
  2623. tx_sta->status.queue_length = 0;
  2624. tx_sta->status.queue_number = 0;
  2625. if (in_interrupt())
  2626. ieee80211_tx_status_irqsafe(priv->hw,
  2627. tx_sta->skb[0], &(tx_sta->status));
  2628. else
  2629. ieee80211_tx_status(priv->hw,
  2630. tx_sta->skb[0], &(tx_sta->status));
  2631. tx_sta->skb[0] = NULL;
  2632. }
  2633. /**
  2634. * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
  2635. *
  2636. * When FW advances 'R' index, all entries between old and new 'R' index
  2637. * need to be reclaimed. As result, some free space forms. If there is
  2638. * enough free space (> low mark), wake the stack that feeds us.
  2639. */
  2640. static int iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv, int txq_id, int index)
  2641. {
  2642. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2643. struct iwl3945_queue *q = &txq->q;
  2644. int nfreed = 0;
  2645. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2646. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2647. "is out of range [0-%d] %d %d.\n", txq_id,
  2648. index, q->n_bd, q->write_ptr, q->read_ptr);
  2649. return 0;
  2650. }
  2651. for (index = iwl_queue_inc_wrap(index, q->n_bd);
  2652. q->read_ptr != index;
  2653. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2654. if (txq_id != IWL_CMD_QUEUE_NUM) {
  2655. iwl3945_txstatus_to_ieee(priv,
  2656. &(txq->txb[txq->q.read_ptr]));
  2657. iwl3945_hw_txq_free_tfd(priv, txq);
  2658. } else if (nfreed > 1) {
  2659. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2660. q->write_ptr, q->read_ptr);
  2661. queue_work(priv->workqueue, &priv->restart);
  2662. }
  2663. nfreed++;
  2664. }
  2665. if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
  2666. (txq_id != IWL_CMD_QUEUE_NUM) &&
  2667. priv->mac80211_registered)
  2668. ieee80211_wake_queue(priv->hw, txq_id);
  2669. return nfreed;
  2670. }
  2671. static int iwl3945_is_tx_success(u32 status)
  2672. {
  2673. return (status & 0xFF) == 0x1;
  2674. }
  2675. /******************************************************************************
  2676. *
  2677. * Generic RX handler implementations
  2678. *
  2679. ******************************************************************************/
  2680. /**
  2681. * iwl3945_rx_reply_tx - Handle Tx response
  2682. */
  2683. static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
  2684. struct iwl3945_rx_mem_buffer *rxb)
  2685. {
  2686. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2687. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2688. int txq_id = SEQ_TO_QUEUE(sequence);
  2689. int index = SEQ_TO_INDEX(sequence);
  2690. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2691. struct ieee80211_tx_status *tx_status;
  2692. struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  2693. u32 status = le32_to_cpu(tx_resp->status);
  2694. if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
  2695. IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
  2696. "is out of range [0-%d] %d %d\n", txq_id,
  2697. index, txq->q.n_bd, txq->q.write_ptr,
  2698. txq->q.read_ptr);
  2699. return;
  2700. }
  2701. tx_status = &(txq->txb[txq->q.read_ptr].status);
  2702. tx_status->retry_count = tx_resp->failure_frame;
  2703. tx_status->queue_number = status;
  2704. tx_status->queue_length = tx_resp->bt_kill_count;
  2705. tx_status->queue_length |= tx_resp->failure_rts;
  2706. tx_status->flags =
  2707. iwl3945_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
  2708. IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
  2709. txq_id, iwl3945_get_tx_fail_reason(status), status,
  2710. tx_resp->rate, tx_resp->failure_frame);
  2711. IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
  2712. if (index != -1)
  2713. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  2714. if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
  2715. IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
  2716. }
  2717. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2718. struct iwl3945_rx_mem_buffer *rxb)
  2719. {
  2720. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2721. struct iwl3945_alive_resp *palive;
  2722. struct delayed_work *pwork;
  2723. palive = &pkt->u.alive_frame;
  2724. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2725. "0x%01X 0x%01X\n",
  2726. palive->is_valid, palive->ver_type,
  2727. palive->ver_subtype);
  2728. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2729. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2730. memcpy(&priv->card_alive_init,
  2731. &pkt->u.alive_frame,
  2732. sizeof(struct iwl3945_init_alive_resp));
  2733. pwork = &priv->init_alive_start;
  2734. } else {
  2735. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2736. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2737. sizeof(struct iwl3945_alive_resp));
  2738. pwork = &priv->alive_start;
  2739. iwl3945_disable_events(priv);
  2740. }
  2741. /* We delay the ALIVE response by 5ms to
  2742. * give the HW RF Kill time to activate... */
  2743. if (palive->is_valid == UCODE_VALID_OK)
  2744. queue_delayed_work(priv->workqueue, pwork,
  2745. msecs_to_jiffies(5));
  2746. else
  2747. IWL_WARNING("uCode did not respond OK.\n");
  2748. }
  2749. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2750. struct iwl3945_rx_mem_buffer *rxb)
  2751. {
  2752. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2753. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2754. return;
  2755. }
  2756. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2757. struct iwl3945_rx_mem_buffer *rxb)
  2758. {
  2759. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2760. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2761. "seq 0x%04X ser 0x%08X\n",
  2762. le32_to_cpu(pkt->u.err_resp.error_type),
  2763. get_cmd_string(pkt->u.err_resp.cmd_id),
  2764. pkt->u.err_resp.cmd_id,
  2765. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2766. le32_to_cpu(pkt->u.err_resp.error_info));
  2767. }
  2768. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2769. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2770. {
  2771. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2772. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2773. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  2774. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2775. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2776. rxon->channel = csa->channel;
  2777. priv->staging_rxon.channel = csa->channel;
  2778. }
  2779. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2780. struct iwl3945_rx_mem_buffer *rxb)
  2781. {
  2782. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2783. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2784. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2785. if (!report->state) {
  2786. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2787. "Spectrum Measure Notification: Start\n");
  2788. return;
  2789. }
  2790. memcpy(&priv->measure_report, report, sizeof(*report));
  2791. priv->measurement_status |= MEASUREMENT_READY;
  2792. #endif
  2793. }
  2794. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2795. struct iwl3945_rx_mem_buffer *rxb)
  2796. {
  2797. #ifdef CONFIG_IWL3945_DEBUG
  2798. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2799. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2800. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2801. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2802. #endif
  2803. }
  2804. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2805. struct iwl3945_rx_mem_buffer *rxb)
  2806. {
  2807. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2808. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2809. "notification for %s:\n",
  2810. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2811. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2812. }
  2813. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2814. {
  2815. struct iwl3945_priv *priv =
  2816. container_of(work, struct iwl3945_priv, beacon_update);
  2817. struct sk_buff *beacon;
  2818. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2819. beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL);
  2820. if (!beacon) {
  2821. IWL_ERROR("update beacon failed\n");
  2822. return;
  2823. }
  2824. mutex_lock(&priv->mutex);
  2825. /* new beacon skb is allocated every time; dispose previous.*/
  2826. if (priv->ibss_beacon)
  2827. dev_kfree_skb(priv->ibss_beacon);
  2828. priv->ibss_beacon = beacon;
  2829. mutex_unlock(&priv->mutex);
  2830. iwl3945_send_beacon_cmd(priv);
  2831. }
  2832. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2833. struct iwl3945_rx_mem_buffer *rxb)
  2834. {
  2835. #ifdef CONFIG_IWL3945_DEBUG
  2836. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2837. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2838. u8 rate = beacon->beacon_notify_hdr.rate;
  2839. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2840. "tsf %d %d rate %d\n",
  2841. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2842. beacon->beacon_notify_hdr.failure_frame,
  2843. le32_to_cpu(beacon->ibss_mgr_status),
  2844. le32_to_cpu(beacon->high_tsf),
  2845. le32_to_cpu(beacon->low_tsf), rate);
  2846. #endif
  2847. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  2848. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2849. queue_work(priv->workqueue, &priv->beacon_update);
  2850. }
  2851. /* Service response to REPLY_SCAN_CMD (0x80) */
  2852. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  2853. struct iwl3945_rx_mem_buffer *rxb)
  2854. {
  2855. #ifdef CONFIG_IWL3945_DEBUG
  2856. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2857. struct iwl3945_scanreq_notification *notif =
  2858. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  2859. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2860. #endif
  2861. }
  2862. /* Service SCAN_START_NOTIFICATION (0x82) */
  2863. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  2864. struct iwl3945_rx_mem_buffer *rxb)
  2865. {
  2866. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2867. struct iwl3945_scanstart_notification *notif =
  2868. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  2869. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2870. IWL_DEBUG_SCAN("Scan start: "
  2871. "%d [802.11%s] "
  2872. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2873. notif->channel,
  2874. notif->band ? "bg" : "a",
  2875. notif->tsf_high,
  2876. notif->tsf_low, notif->status, notif->beacon_timer);
  2877. }
  2878. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2879. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  2880. struct iwl3945_rx_mem_buffer *rxb)
  2881. {
  2882. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2883. struct iwl3945_scanresults_notification *notif =
  2884. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  2885. IWL_DEBUG_SCAN("Scan ch.res: "
  2886. "%d [802.11%s] "
  2887. "(TSF: 0x%08X:%08X) - %d "
  2888. "elapsed=%lu usec (%dms since last)\n",
  2889. notif->channel,
  2890. notif->band ? "bg" : "a",
  2891. le32_to_cpu(notif->tsf_high),
  2892. le32_to_cpu(notif->tsf_low),
  2893. le32_to_cpu(notif->statistics[0]),
  2894. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2895. jiffies_to_msecs(elapsed_jiffies
  2896. (priv->last_scan_jiffies, jiffies)));
  2897. priv->last_scan_jiffies = jiffies;
  2898. priv->next_scan_jiffies = 0;
  2899. }
  2900. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2901. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  2902. struct iwl3945_rx_mem_buffer *rxb)
  2903. {
  2904. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2905. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2906. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2907. scan_notif->scanned_channels,
  2908. scan_notif->tsf_low,
  2909. scan_notif->tsf_high, scan_notif->status);
  2910. /* The HW is no longer scanning */
  2911. clear_bit(STATUS_SCAN_HW, &priv->status);
  2912. /* The scan completion notification came in, so kill that timer... */
  2913. cancel_delayed_work(&priv->scan_check);
  2914. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2915. (priv->scan_bands == 2) ? "2.4" : "5.2",
  2916. jiffies_to_msecs(elapsed_jiffies
  2917. (priv->scan_pass_start, jiffies)));
  2918. /* Remove this scanned band from the list
  2919. * of pending bands to scan */
  2920. priv->scan_bands--;
  2921. /* If a request to abort was given, or the scan did not succeed
  2922. * then we reset the scan state machine and terminate,
  2923. * re-queuing another scan if one has been requested */
  2924. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2925. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2926. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2927. } else {
  2928. /* If there are more bands on this scan pass reschedule */
  2929. if (priv->scan_bands > 0)
  2930. goto reschedule;
  2931. }
  2932. priv->last_scan_jiffies = jiffies;
  2933. priv->next_scan_jiffies = 0;
  2934. IWL_DEBUG_INFO("Setting scan to off\n");
  2935. clear_bit(STATUS_SCANNING, &priv->status);
  2936. IWL_DEBUG_INFO("Scan took %dms\n",
  2937. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2938. queue_work(priv->workqueue, &priv->scan_completed);
  2939. return;
  2940. reschedule:
  2941. priv->scan_pass_start = jiffies;
  2942. queue_work(priv->workqueue, &priv->request_scan);
  2943. }
  2944. /* Handle notification from uCode that card's power state is changing
  2945. * due to software, hardware, or critical temperature RFKILL */
  2946. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  2947. struct iwl3945_rx_mem_buffer *rxb)
  2948. {
  2949. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2950. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2951. unsigned long status = priv->status;
  2952. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2953. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2954. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2955. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2956. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2957. if (flags & HW_CARD_DISABLED)
  2958. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2959. else
  2960. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2961. if (flags & SW_CARD_DISABLED)
  2962. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2963. else
  2964. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2965. iwl3945_scan_cancel(priv);
  2966. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2967. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2968. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2969. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2970. queue_work(priv->workqueue, &priv->rf_kill);
  2971. else
  2972. wake_up_interruptible(&priv->wait_command_queue);
  2973. }
  2974. /**
  2975. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2976. *
  2977. * Setup the RX handlers for each of the reply types sent from the uCode
  2978. * to the host.
  2979. *
  2980. * This function chains into the hardware specific files for them to setup
  2981. * any hardware specific handlers as well.
  2982. */
  2983. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  2984. {
  2985. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2986. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2987. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2988. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2989. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2990. iwl3945_rx_spectrum_measure_notif;
  2991. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2992. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2993. iwl3945_rx_pm_debug_statistics_notif;
  2994. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2995. /*
  2996. * The same handler is used for both the REPLY to a discrete
  2997. * statistics request from the host as well as for the periodic
  2998. * statistics notifications (after received beacons) from the uCode.
  2999. */
  3000. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  3001. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  3002. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  3003. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  3004. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  3005. iwl3945_rx_scan_results_notif;
  3006. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  3007. iwl3945_rx_scan_complete_notif;
  3008. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  3009. priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
  3010. /* Set up hardware specific Rx handlers */
  3011. iwl3945_hw_rx_handler_setup(priv);
  3012. }
  3013. /**
  3014. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  3015. * @rxb: Rx buffer to reclaim
  3016. *
  3017. * If an Rx buffer has an async callback associated with it the callback
  3018. * will be executed. The attached skb (if present) will only be freed
  3019. * if the callback returns 1
  3020. */
  3021. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  3022. struct iwl3945_rx_mem_buffer *rxb)
  3023. {
  3024. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3025. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  3026. int txq_id = SEQ_TO_QUEUE(sequence);
  3027. int index = SEQ_TO_INDEX(sequence);
  3028. int huge = sequence & SEQ_HUGE_FRAME;
  3029. int cmd_index;
  3030. struct iwl3945_cmd *cmd;
  3031. /* If a Tx command is being handled and it isn't in the actual
  3032. * command queue then there a command routing bug has been introduced
  3033. * in the queue management code. */
  3034. if (txq_id != IWL_CMD_QUEUE_NUM)
  3035. IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
  3036. txq_id, pkt->hdr.cmd);
  3037. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  3038. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  3039. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  3040. /* Input error checking is done when commands are added to queue. */
  3041. if (cmd->meta.flags & CMD_WANT_SKB) {
  3042. cmd->meta.source->u.skb = rxb->skb;
  3043. rxb->skb = NULL;
  3044. } else if (cmd->meta.u.callback &&
  3045. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  3046. rxb->skb = NULL;
  3047. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  3048. if (!(cmd->meta.flags & CMD_ASYNC)) {
  3049. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3050. wake_up_interruptible(&priv->wait_command_queue);
  3051. }
  3052. }
  3053. /************************** RX-FUNCTIONS ****************************/
  3054. /*
  3055. * Rx theory of operation
  3056. *
  3057. * The host allocates 32 DMA target addresses and passes the host address
  3058. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  3059. * 0 to 31
  3060. *
  3061. * Rx Queue Indexes
  3062. * The host/firmware share two index registers for managing the Rx buffers.
  3063. *
  3064. * The READ index maps to the first position that the firmware may be writing
  3065. * to -- the driver can read up to (but not including) this position and get
  3066. * good data.
  3067. * The READ index is managed by the firmware once the card is enabled.
  3068. *
  3069. * The WRITE index maps to the last position the driver has read from -- the
  3070. * position preceding WRITE is the last slot the firmware can place a packet.
  3071. *
  3072. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  3073. * WRITE = READ.
  3074. *
  3075. * During initialization, the host sets up the READ queue position to the first
  3076. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  3077. *
  3078. * When the firmware places a packet in a buffer, it will advance the READ index
  3079. * and fire the RX interrupt. The driver can then query the READ index and
  3080. * process as many packets as possible, moving the WRITE index forward as it
  3081. * resets the Rx queue buffers with new memory.
  3082. *
  3083. * The management in the driver is as follows:
  3084. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  3085. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  3086. * to replenish the iwl->rxq->rx_free.
  3087. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  3088. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  3089. * 'processed' and 'read' driver indexes as well)
  3090. * + A received packet is processed and handed to the kernel network stack,
  3091. * detached from the iwl->rxq. The driver 'processed' index is updated.
  3092. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  3093. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  3094. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  3095. * were enough free buffers and RX_STALLED is set it is cleared.
  3096. *
  3097. *
  3098. * Driver sequence:
  3099. *
  3100. * iwl3945_rx_queue_alloc() Allocates rx_free
  3101. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  3102. * iwl3945_rx_queue_restock
  3103. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  3104. * queue, updates firmware pointers, and updates
  3105. * the WRITE index. If insufficient rx_free buffers
  3106. * are available, schedules iwl3945_rx_replenish
  3107. *
  3108. * -- enable interrupts --
  3109. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  3110. * READ INDEX, detaching the SKB from the pool.
  3111. * Moves the packet buffer from queue to rx_used.
  3112. * Calls iwl3945_rx_queue_restock to refill any empty
  3113. * slots.
  3114. * ...
  3115. *
  3116. */
  3117. /**
  3118. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  3119. */
  3120. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  3121. {
  3122. int s = q->read - q->write;
  3123. if (s <= 0)
  3124. s += RX_QUEUE_SIZE;
  3125. /* keep some buffer to not confuse full and empty queue */
  3126. s -= 2;
  3127. if (s < 0)
  3128. s = 0;
  3129. return s;
  3130. }
  3131. /**
  3132. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  3133. */
  3134. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  3135. {
  3136. u32 reg = 0;
  3137. int rc = 0;
  3138. unsigned long flags;
  3139. spin_lock_irqsave(&q->lock, flags);
  3140. if (q->need_update == 0)
  3141. goto exit_unlock;
  3142. /* If power-saving is in use, make sure device is awake */
  3143. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3144. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3145. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3146. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3147. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3148. goto exit_unlock;
  3149. }
  3150. rc = iwl3945_grab_nic_access(priv);
  3151. if (rc)
  3152. goto exit_unlock;
  3153. /* Device expects a multiple of 8 */
  3154. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  3155. q->write & ~0x7);
  3156. iwl3945_release_nic_access(priv);
  3157. /* Else device is assumed to be awake */
  3158. } else
  3159. /* Device expects a multiple of 8 */
  3160. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  3161. q->need_update = 0;
  3162. exit_unlock:
  3163. spin_unlock_irqrestore(&q->lock, flags);
  3164. return rc;
  3165. }
  3166. /**
  3167. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  3168. */
  3169. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  3170. dma_addr_t dma_addr)
  3171. {
  3172. return cpu_to_le32((u32)dma_addr);
  3173. }
  3174. /**
  3175. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  3176. *
  3177. * If there are slots in the RX queue that need to be restocked,
  3178. * and we have free pre-allocated buffers, fill the ranks as much
  3179. * as we can, pulling from rx_free.
  3180. *
  3181. * This moves the 'write' index forward to catch up with 'processed', and
  3182. * also updates the memory address in the firmware to reference the new
  3183. * target buffer.
  3184. */
  3185. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  3186. {
  3187. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3188. struct list_head *element;
  3189. struct iwl3945_rx_mem_buffer *rxb;
  3190. unsigned long flags;
  3191. int write, rc;
  3192. spin_lock_irqsave(&rxq->lock, flags);
  3193. write = rxq->write & ~0x7;
  3194. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  3195. /* Get next free Rx buffer, remove from free list */
  3196. element = rxq->rx_free.next;
  3197. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3198. list_del(element);
  3199. /* Point to Rx buffer via next RBD in circular buffer */
  3200. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  3201. rxq->queue[rxq->write] = rxb;
  3202. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  3203. rxq->free_count--;
  3204. }
  3205. spin_unlock_irqrestore(&rxq->lock, flags);
  3206. /* If the pre-allocated buffer pool is dropping low, schedule to
  3207. * refill it */
  3208. if (rxq->free_count <= RX_LOW_WATERMARK)
  3209. queue_work(priv->workqueue, &priv->rx_replenish);
  3210. /* If we've added more space for the firmware to place data, tell it.
  3211. * Increment device's write pointer in multiples of 8. */
  3212. if ((write != (rxq->write & ~0x7))
  3213. || (abs(rxq->write - rxq->read) > 7)) {
  3214. spin_lock_irqsave(&rxq->lock, flags);
  3215. rxq->need_update = 1;
  3216. spin_unlock_irqrestore(&rxq->lock, flags);
  3217. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  3218. if (rc)
  3219. return rc;
  3220. }
  3221. return 0;
  3222. }
  3223. /**
  3224. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  3225. *
  3226. * When moving to rx_free an SKB is allocated for the slot.
  3227. *
  3228. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  3229. * This is called as a scheduled work item (except for during initialization)
  3230. */
  3231. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  3232. {
  3233. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3234. struct list_head *element;
  3235. struct iwl3945_rx_mem_buffer *rxb;
  3236. unsigned long flags;
  3237. spin_lock_irqsave(&rxq->lock, flags);
  3238. while (!list_empty(&rxq->rx_used)) {
  3239. element = rxq->rx_used.next;
  3240. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3241. /* Alloc a new receive buffer */
  3242. rxb->skb =
  3243. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3244. if (!rxb->skb) {
  3245. if (net_ratelimit())
  3246. printk(KERN_CRIT DRV_NAME
  3247. ": Can not allocate SKB buffers\n");
  3248. /* We don't reschedule replenish work here -- we will
  3249. * call the restock method and if it still needs
  3250. * more buffers it will schedule replenish */
  3251. break;
  3252. }
  3253. /* If radiotap head is required, reserve some headroom here.
  3254. * The physical head count is a variable rx_stats->phy_count.
  3255. * We reserve 4 bytes here. Plus these extra bytes, the
  3256. * headroom of the physical head should be enough for the
  3257. * radiotap head that iwl3945 supported. See iwl3945_rt.
  3258. */
  3259. skb_reserve(rxb->skb, 4);
  3260. priv->alloc_rxb_skb++;
  3261. list_del(element);
  3262. /* Get physical address of RB/SKB */
  3263. rxb->dma_addr =
  3264. pci_map_single(priv->pci_dev, rxb->skb->data,
  3265. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3266. list_add_tail(&rxb->list, &rxq->rx_free);
  3267. rxq->free_count++;
  3268. }
  3269. spin_unlock_irqrestore(&rxq->lock, flags);
  3270. }
  3271. /*
  3272. * this should be called while priv->lock is locked
  3273. */
  3274. static void __iwl3945_rx_replenish(void *data)
  3275. {
  3276. struct iwl3945_priv *priv = data;
  3277. iwl3945_rx_allocate(priv);
  3278. iwl3945_rx_queue_restock(priv);
  3279. }
  3280. void iwl3945_rx_replenish(void *data)
  3281. {
  3282. struct iwl3945_priv *priv = data;
  3283. unsigned long flags;
  3284. iwl3945_rx_allocate(priv);
  3285. spin_lock_irqsave(&priv->lock, flags);
  3286. iwl3945_rx_queue_restock(priv);
  3287. spin_unlock_irqrestore(&priv->lock, flags);
  3288. }
  3289. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3290. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3291. * This free routine walks the list of POOL entries and if SKB is set to
  3292. * non NULL it is unmapped and freed
  3293. */
  3294. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3295. {
  3296. int i;
  3297. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3298. if (rxq->pool[i].skb != NULL) {
  3299. pci_unmap_single(priv->pci_dev,
  3300. rxq->pool[i].dma_addr,
  3301. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3302. dev_kfree_skb(rxq->pool[i].skb);
  3303. }
  3304. }
  3305. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3306. rxq->dma_addr);
  3307. rxq->bd = NULL;
  3308. }
  3309. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3310. {
  3311. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3312. struct pci_dev *dev = priv->pci_dev;
  3313. int i;
  3314. spin_lock_init(&rxq->lock);
  3315. INIT_LIST_HEAD(&rxq->rx_free);
  3316. INIT_LIST_HEAD(&rxq->rx_used);
  3317. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3318. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3319. if (!rxq->bd)
  3320. return -ENOMEM;
  3321. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3322. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3323. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3324. /* Set us so that we have processed and used all buffers, but have
  3325. * not restocked the Rx queue with fresh buffers */
  3326. rxq->read = rxq->write = 0;
  3327. rxq->free_count = 0;
  3328. rxq->need_update = 0;
  3329. return 0;
  3330. }
  3331. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3332. {
  3333. unsigned long flags;
  3334. int i;
  3335. spin_lock_irqsave(&rxq->lock, flags);
  3336. INIT_LIST_HEAD(&rxq->rx_free);
  3337. INIT_LIST_HEAD(&rxq->rx_used);
  3338. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3339. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3340. /* In the reset function, these buffers may have been allocated
  3341. * to an SKB, so we need to unmap and free potential storage */
  3342. if (rxq->pool[i].skb != NULL) {
  3343. pci_unmap_single(priv->pci_dev,
  3344. rxq->pool[i].dma_addr,
  3345. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3346. priv->alloc_rxb_skb--;
  3347. dev_kfree_skb(rxq->pool[i].skb);
  3348. rxq->pool[i].skb = NULL;
  3349. }
  3350. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3351. }
  3352. /* Set us so that we have processed and used all buffers, but have
  3353. * not restocked the Rx queue with fresh buffers */
  3354. rxq->read = rxq->write = 0;
  3355. rxq->free_count = 0;
  3356. spin_unlock_irqrestore(&rxq->lock, flags);
  3357. }
  3358. /* Convert linear signal-to-noise ratio into dB */
  3359. static u8 ratio2dB[100] = {
  3360. /* 0 1 2 3 4 5 6 7 8 9 */
  3361. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3362. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3363. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3364. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3365. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3366. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3367. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3368. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3369. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3370. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3371. };
  3372. /* Calculates a relative dB value from a ratio of linear
  3373. * (i.e. not dB) signal levels.
  3374. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3375. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3376. {
  3377. /* 1000:1 or higher just report as 60 dB */
  3378. if (sig_ratio >= 1000)
  3379. return 60;
  3380. /* 100:1 or higher, divide by 10 and use table,
  3381. * add 20 dB to make up for divide by 10 */
  3382. if (sig_ratio >= 100)
  3383. return (20 + (int)ratio2dB[sig_ratio/10]);
  3384. /* We shouldn't see this */
  3385. if (sig_ratio < 1)
  3386. return 0;
  3387. /* Use table for ratios 1:1 - 99:1 */
  3388. return (int)ratio2dB[sig_ratio];
  3389. }
  3390. #define PERFECT_RSSI (-20) /* dBm */
  3391. #define WORST_RSSI (-95) /* dBm */
  3392. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3393. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3394. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3395. * about formulas used below. */
  3396. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3397. {
  3398. int sig_qual;
  3399. int degradation = PERFECT_RSSI - rssi_dbm;
  3400. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3401. * as indicator; formula is (signal dbm - noise dbm).
  3402. * SNR at or above 40 is a great signal (100%).
  3403. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3404. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3405. if (noise_dbm) {
  3406. if (rssi_dbm - noise_dbm >= 40)
  3407. return 100;
  3408. else if (rssi_dbm < noise_dbm)
  3409. return 0;
  3410. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3411. /* Else use just the signal level.
  3412. * This formula is a least squares fit of data points collected and
  3413. * compared with a reference system that had a percentage (%) display
  3414. * for signal quality. */
  3415. } else
  3416. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3417. (15 * RSSI_RANGE + 62 * degradation)) /
  3418. (RSSI_RANGE * RSSI_RANGE);
  3419. if (sig_qual > 100)
  3420. sig_qual = 100;
  3421. else if (sig_qual < 1)
  3422. sig_qual = 0;
  3423. return sig_qual;
  3424. }
  3425. /**
  3426. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3427. *
  3428. * Uses the priv->rx_handlers callback function array to invoke
  3429. * the appropriate handlers, including command responses,
  3430. * frame-received notifications, and other notifications.
  3431. */
  3432. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3433. {
  3434. struct iwl3945_rx_mem_buffer *rxb;
  3435. struct iwl3945_rx_packet *pkt;
  3436. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3437. u32 r, i;
  3438. int reclaim;
  3439. unsigned long flags;
  3440. u8 fill_rx = 0;
  3441. u32 count = 8;
  3442. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3443. * buffer that the driver may process (last buffer filled by ucode). */
  3444. r = iwl3945_hw_get_rx_read(priv);
  3445. i = rxq->read;
  3446. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3447. fill_rx = 1;
  3448. /* Rx interrupt, but nothing sent from uCode */
  3449. if (i == r)
  3450. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3451. while (i != r) {
  3452. rxb = rxq->queue[i];
  3453. /* If an RXB doesn't have a Rx queue slot associated with it,
  3454. * then a bug has been introduced in the queue refilling
  3455. * routines -- catch it here */
  3456. BUG_ON(rxb == NULL);
  3457. rxq->queue[i] = NULL;
  3458. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3459. IWL_RX_BUF_SIZE,
  3460. PCI_DMA_FROMDEVICE);
  3461. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3462. /* Reclaim a command buffer only if this packet is a response
  3463. * to a (driver-originated) command.
  3464. * If the packet (e.g. Rx frame) originated from uCode,
  3465. * there is no command buffer to reclaim.
  3466. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3467. * but apparently a few don't get set; catch them here. */
  3468. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3469. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3470. (pkt->hdr.cmd != REPLY_TX);
  3471. /* Based on type of command response or notification,
  3472. * handle those that need handling via function in
  3473. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3474. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3475. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3476. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3477. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3478. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3479. } else {
  3480. /* No handling needed */
  3481. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3482. "r %d i %d No handler needed for %s, 0x%02x\n",
  3483. r, i, get_cmd_string(pkt->hdr.cmd),
  3484. pkt->hdr.cmd);
  3485. }
  3486. if (reclaim) {
  3487. /* Invoke any callbacks, transfer the skb to caller, and
  3488. * fire off the (possibly) blocking iwl3945_send_cmd()
  3489. * as we reclaim the driver command queue */
  3490. if (rxb && rxb->skb)
  3491. iwl3945_tx_cmd_complete(priv, rxb);
  3492. else
  3493. IWL_WARNING("Claim null rxb?\n");
  3494. }
  3495. /* For now we just don't re-use anything. We can tweak this
  3496. * later to try and re-use notification packets and SKBs that
  3497. * fail to Rx correctly */
  3498. if (rxb->skb != NULL) {
  3499. priv->alloc_rxb_skb--;
  3500. dev_kfree_skb_any(rxb->skb);
  3501. rxb->skb = NULL;
  3502. }
  3503. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3504. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3505. spin_lock_irqsave(&rxq->lock, flags);
  3506. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3507. spin_unlock_irqrestore(&rxq->lock, flags);
  3508. i = (i + 1) & RX_QUEUE_MASK;
  3509. /* If there are a lot of unused frames,
  3510. * restock the Rx queue so ucode won't assert. */
  3511. if (fill_rx) {
  3512. count++;
  3513. if (count >= 8) {
  3514. priv->rxq.read = i;
  3515. __iwl3945_rx_replenish(priv);
  3516. count = 0;
  3517. }
  3518. }
  3519. }
  3520. /* Backtrack one entry */
  3521. priv->rxq.read = i;
  3522. iwl3945_rx_queue_restock(priv);
  3523. }
  3524. /**
  3525. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3526. */
  3527. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3528. struct iwl3945_tx_queue *txq)
  3529. {
  3530. u32 reg = 0;
  3531. int rc = 0;
  3532. int txq_id = txq->q.id;
  3533. if (txq->need_update == 0)
  3534. return rc;
  3535. /* if we're trying to save power */
  3536. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3537. /* wake up nic if it's powered down ...
  3538. * uCode will wake up, and interrupt us again, so next
  3539. * time we'll skip this part. */
  3540. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3541. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3542. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3543. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3544. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3545. return rc;
  3546. }
  3547. /* restore this queue's parameters in nic hardware. */
  3548. rc = iwl3945_grab_nic_access(priv);
  3549. if (rc)
  3550. return rc;
  3551. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3552. txq->q.write_ptr | (txq_id << 8));
  3553. iwl3945_release_nic_access(priv);
  3554. /* else not in power-save mode, uCode will never sleep when we're
  3555. * trying to tx (during RFKILL, we're not trying to tx). */
  3556. } else
  3557. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3558. txq->q.write_ptr | (txq_id << 8));
  3559. txq->need_update = 0;
  3560. return rc;
  3561. }
  3562. #ifdef CONFIG_IWL3945_DEBUG
  3563. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3564. {
  3565. DECLARE_MAC_BUF(mac);
  3566. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3567. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3568. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3569. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3570. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3571. le32_to_cpu(rxon->filter_flags));
  3572. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3573. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3574. rxon->ofdm_basic_rates);
  3575. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3576. IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
  3577. print_mac(mac, rxon->node_addr));
  3578. IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
  3579. print_mac(mac, rxon->bssid_addr));
  3580. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3581. }
  3582. #endif
  3583. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3584. {
  3585. IWL_DEBUG_ISR("Enabling interrupts\n");
  3586. set_bit(STATUS_INT_ENABLED, &priv->status);
  3587. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3588. }
  3589. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3590. {
  3591. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3592. /* disable interrupts from uCode/NIC to host */
  3593. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3594. /* acknowledge/clear/reset any interrupts still pending
  3595. * from uCode or flow handler (Rx/Tx DMA) */
  3596. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3597. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3598. IWL_DEBUG_ISR("Disabled interrupts\n");
  3599. }
  3600. static const char *desc_lookup(int i)
  3601. {
  3602. switch (i) {
  3603. case 1:
  3604. return "FAIL";
  3605. case 2:
  3606. return "BAD_PARAM";
  3607. case 3:
  3608. return "BAD_CHECKSUM";
  3609. case 4:
  3610. return "NMI_INTERRUPT";
  3611. case 5:
  3612. return "SYSASSERT";
  3613. case 6:
  3614. return "FATAL_ERROR";
  3615. }
  3616. return "UNKNOWN";
  3617. }
  3618. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3619. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3620. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3621. {
  3622. u32 i;
  3623. u32 desc, time, count, base, data1;
  3624. u32 blink1, blink2, ilink1, ilink2;
  3625. int rc;
  3626. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3627. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3628. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3629. return;
  3630. }
  3631. rc = iwl3945_grab_nic_access(priv);
  3632. if (rc) {
  3633. IWL_WARNING("Can not read from adapter at this time.\n");
  3634. return;
  3635. }
  3636. count = iwl3945_read_targ_mem(priv, base);
  3637. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3638. IWL_ERROR("Start IWL Error Log Dump:\n");
  3639. IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
  3640. }
  3641. IWL_ERROR("Desc Time asrtPC blink2 "
  3642. "ilink1 nmiPC Line\n");
  3643. for (i = ERROR_START_OFFSET;
  3644. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3645. i += ERROR_ELEM_SIZE) {
  3646. desc = iwl3945_read_targ_mem(priv, base + i);
  3647. time =
  3648. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3649. blink1 =
  3650. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3651. blink2 =
  3652. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3653. ilink1 =
  3654. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3655. ilink2 =
  3656. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3657. data1 =
  3658. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3659. IWL_ERROR
  3660. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3661. desc_lookup(desc), desc, time, blink1, blink2,
  3662. ilink1, ilink2, data1);
  3663. }
  3664. iwl3945_release_nic_access(priv);
  3665. }
  3666. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3667. /**
  3668. * iwl3945_print_event_log - Dump error event log to syslog
  3669. *
  3670. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3671. */
  3672. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3673. u32 num_events, u32 mode)
  3674. {
  3675. u32 i;
  3676. u32 base; /* SRAM byte address of event log header */
  3677. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3678. u32 ptr; /* SRAM byte address of log data */
  3679. u32 ev, time, data; /* event log data */
  3680. if (num_events == 0)
  3681. return;
  3682. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3683. if (mode == 0)
  3684. event_size = 2 * sizeof(u32);
  3685. else
  3686. event_size = 3 * sizeof(u32);
  3687. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3688. /* "time" is actually "data" for mode 0 (no timestamp).
  3689. * place event id # at far right for easier visual parsing. */
  3690. for (i = 0; i < num_events; i++) {
  3691. ev = iwl3945_read_targ_mem(priv, ptr);
  3692. ptr += sizeof(u32);
  3693. time = iwl3945_read_targ_mem(priv, ptr);
  3694. ptr += sizeof(u32);
  3695. if (mode == 0)
  3696. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3697. else {
  3698. data = iwl3945_read_targ_mem(priv, ptr);
  3699. ptr += sizeof(u32);
  3700. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3701. }
  3702. }
  3703. }
  3704. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3705. {
  3706. int rc;
  3707. u32 base; /* SRAM byte address of event log header */
  3708. u32 capacity; /* event log capacity in # entries */
  3709. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3710. u32 num_wraps; /* # times uCode wrapped to top of log */
  3711. u32 next_entry; /* index of next entry to be written by uCode */
  3712. u32 size; /* # entries that we'll print */
  3713. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3714. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3715. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3716. return;
  3717. }
  3718. rc = iwl3945_grab_nic_access(priv);
  3719. if (rc) {
  3720. IWL_WARNING("Can not read from adapter at this time.\n");
  3721. return;
  3722. }
  3723. /* event log header */
  3724. capacity = iwl3945_read_targ_mem(priv, base);
  3725. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3726. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3727. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3728. size = num_wraps ? capacity : next_entry;
  3729. /* bail out if nothing in log */
  3730. if (size == 0) {
  3731. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3732. iwl3945_release_nic_access(priv);
  3733. return;
  3734. }
  3735. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3736. size, num_wraps);
  3737. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3738. * i.e the next one that uCode would fill. */
  3739. if (num_wraps)
  3740. iwl3945_print_event_log(priv, next_entry,
  3741. capacity - next_entry, mode);
  3742. /* (then/else) start at top of log */
  3743. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3744. iwl3945_release_nic_access(priv);
  3745. }
  3746. /**
  3747. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3748. */
  3749. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3750. {
  3751. /* Set the FW error flag -- cleared on iwl3945_down */
  3752. set_bit(STATUS_FW_ERROR, &priv->status);
  3753. /* Cancel currently queued command. */
  3754. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3755. #ifdef CONFIG_IWL3945_DEBUG
  3756. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3757. iwl3945_dump_nic_error_log(priv);
  3758. iwl3945_dump_nic_event_log(priv);
  3759. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3760. }
  3761. #endif
  3762. wake_up_interruptible(&priv->wait_command_queue);
  3763. /* Keep the restart process from trying to send host
  3764. * commands by clearing the INIT status bit */
  3765. clear_bit(STATUS_READY, &priv->status);
  3766. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3767. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3768. "Restarting adapter due to uCode error.\n");
  3769. if (iwl3945_is_associated(priv)) {
  3770. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3771. sizeof(priv->recovery_rxon));
  3772. priv->error_recovering = 1;
  3773. }
  3774. queue_work(priv->workqueue, &priv->restart);
  3775. }
  3776. }
  3777. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3778. {
  3779. unsigned long flags;
  3780. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3781. sizeof(priv->staging_rxon));
  3782. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3783. iwl3945_commit_rxon(priv);
  3784. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3785. spin_lock_irqsave(&priv->lock, flags);
  3786. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3787. priv->error_recovering = 0;
  3788. spin_unlock_irqrestore(&priv->lock, flags);
  3789. }
  3790. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3791. {
  3792. u32 inta, handled = 0;
  3793. u32 inta_fh;
  3794. unsigned long flags;
  3795. #ifdef CONFIG_IWL3945_DEBUG
  3796. u32 inta_mask;
  3797. #endif
  3798. spin_lock_irqsave(&priv->lock, flags);
  3799. /* Ack/clear/reset pending uCode interrupts.
  3800. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3801. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3802. inta = iwl3945_read32(priv, CSR_INT);
  3803. iwl3945_write32(priv, CSR_INT, inta);
  3804. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3805. * Any new interrupts that happen after this, either while we're
  3806. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3807. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3808. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3809. #ifdef CONFIG_IWL3945_DEBUG
  3810. if (iwl3945_debug_level & IWL_DL_ISR) {
  3811. /* just for debug */
  3812. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3813. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3814. inta, inta_mask, inta_fh);
  3815. }
  3816. #endif
  3817. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3818. * atomic, make sure that inta covers all the interrupts that
  3819. * we've discovered, even if FH interrupt came in just after
  3820. * reading CSR_INT. */
  3821. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3822. inta |= CSR_INT_BIT_FH_RX;
  3823. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3824. inta |= CSR_INT_BIT_FH_TX;
  3825. /* Now service all interrupt bits discovered above. */
  3826. if (inta & CSR_INT_BIT_HW_ERR) {
  3827. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3828. /* Tell the device to stop sending interrupts */
  3829. iwl3945_disable_interrupts(priv);
  3830. iwl3945_irq_handle_error(priv);
  3831. handled |= CSR_INT_BIT_HW_ERR;
  3832. spin_unlock_irqrestore(&priv->lock, flags);
  3833. return;
  3834. }
  3835. #ifdef CONFIG_IWL3945_DEBUG
  3836. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3837. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3838. if (inta & CSR_INT_BIT_SCD)
  3839. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3840. "the frame/frames.\n");
  3841. /* Alive notification via Rx interrupt will do the real work */
  3842. if (inta & CSR_INT_BIT_ALIVE)
  3843. IWL_DEBUG_ISR("Alive interrupt\n");
  3844. }
  3845. #endif
  3846. /* Safely ignore these bits for debug checks below */
  3847. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3848. /* HW RF KILL switch toggled (4965 only) */
  3849. if (inta & CSR_INT_BIT_RF_KILL) {
  3850. int hw_rf_kill = 0;
  3851. if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
  3852. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  3853. hw_rf_kill = 1;
  3854. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  3855. "RF_KILL bit toggled to %s.\n",
  3856. hw_rf_kill ? "disable radio":"enable radio");
  3857. /* Queue restart only if RF_KILL switch was set to "kill"
  3858. * when we loaded driver, and is now set to "enable".
  3859. * After we're Alive, RF_KILL gets handled by
  3860. * iwl3945_rx_card_state_notif() */
  3861. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  3862. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3863. queue_work(priv->workqueue, &priv->restart);
  3864. }
  3865. handled |= CSR_INT_BIT_RF_KILL;
  3866. }
  3867. /* Chip got too hot and stopped itself (4965 only) */
  3868. if (inta & CSR_INT_BIT_CT_KILL) {
  3869. IWL_ERROR("Microcode CT kill error detected.\n");
  3870. handled |= CSR_INT_BIT_CT_KILL;
  3871. }
  3872. /* Error detected by uCode */
  3873. if (inta & CSR_INT_BIT_SW_ERR) {
  3874. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3875. inta);
  3876. iwl3945_irq_handle_error(priv);
  3877. handled |= CSR_INT_BIT_SW_ERR;
  3878. }
  3879. /* uCode wakes up after power-down sleep */
  3880. if (inta & CSR_INT_BIT_WAKEUP) {
  3881. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3882. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3883. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3884. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3885. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3886. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3887. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3888. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3889. handled |= CSR_INT_BIT_WAKEUP;
  3890. }
  3891. /* All uCode command responses, including Tx command responses,
  3892. * Rx "responses" (frame-received notification), and other
  3893. * notifications from uCode come through here*/
  3894. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3895. iwl3945_rx_handle(priv);
  3896. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3897. }
  3898. if (inta & CSR_INT_BIT_FH_TX) {
  3899. IWL_DEBUG_ISR("Tx interrupt\n");
  3900. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3901. if (!iwl3945_grab_nic_access(priv)) {
  3902. iwl3945_write_direct32(priv,
  3903. FH_TCSR_CREDIT
  3904. (ALM_FH_SRVC_CHNL), 0x0);
  3905. iwl3945_release_nic_access(priv);
  3906. }
  3907. handled |= CSR_INT_BIT_FH_TX;
  3908. }
  3909. if (inta & ~handled)
  3910. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3911. if (inta & ~CSR_INI_SET_MASK) {
  3912. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  3913. inta & ~CSR_INI_SET_MASK);
  3914. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  3915. }
  3916. /* Re-enable all interrupts */
  3917. iwl3945_enable_interrupts(priv);
  3918. #ifdef CONFIG_IWL3945_DEBUG
  3919. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3920. inta = iwl3945_read32(priv, CSR_INT);
  3921. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3922. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3923. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3924. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3925. }
  3926. #endif
  3927. spin_unlock_irqrestore(&priv->lock, flags);
  3928. }
  3929. static irqreturn_t iwl3945_isr(int irq, void *data)
  3930. {
  3931. struct iwl3945_priv *priv = data;
  3932. u32 inta, inta_mask;
  3933. u32 inta_fh;
  3934. if (!priv)
  3935. return IRQ_NONE;
  3936. spin_lock(&priv->lock);
  3937. /* Disable (but don't clear!) interrupts here to avoid
  3938. * back-to-back ISRs and sporadic interrupts from our NIC.
  3939. * If we have something to service, the tasklet will re-enable ints.
  3940. * If we *don't* have something, we'll re-enable before leaving here. */
  3941. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  3942. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3943. /* Discover which interrupts are active/pending */
  3944. inta = iwl3945_read32(priv, CSR_INT);
  3945. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3946. /* Ignore interrupt if there's nothing in NIC to service.
  3947. * This may be due to IRQ shared with another device,
  3948. * or due to sporadic interrupts thrown from our NIC. */
  3949. if (!inta && !inta_fh) {
  3950. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3951. goto none;
  3952. }
  3953. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3954. /* Hardware disappeared */
  3955. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  3956. goto unplugged;
  3957. }
  3958. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3959. inta, inta_mask, inta_fh);
  3960. inta &= ~CSR_INT_BIT_SCD;
  3961. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3962. if (likely(inta || inta_fh))
  3963. tasklet_schedule(&priv->irq_tasklet);
  3964. unplugged:
  3965. spin_unlock(&priv->lock);
  3966. return IRQ_HANDLED;
  3967. none:
  3968. /* re-enable interrupts here since we don't have anything to service. */
  3969. iwl3945_enable_interrupts(priv);
  3970. spin_unlock(&priv->lock);
  3971. return IRQ_NONE;
  3972. }
  3973. /************************** EEPROM BANDS ****************************
  3974. *
  3975. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3976. * EEPROM contents to the specific channel number supported for each
  3977. * band.
  3978. *
  3979. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  3980. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3981. * The specific geography and calibration information for that channel
  3982. * is contained in the eeprom map itself.
  3983. *
  3984. * During init, we copy the eeprom information and channel map
  3985. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3986. *
  3987. * channel_map_24/52 provides the index in the channel_info array for a
  3988. * given channel. We have to have two separate maps as there is channel
  3989. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3990. * band_2
  3991. *
  3992. * A value of 0xff stored in the channel_map indicates that the channel
  3993. * is not supported by the hardware at all.
  3994. *
  3995. * A value of 0xfe in the channel_map indicates that the channel is not
  3996. * valid for Tx with the current hardware. This means that
  3997. * while the system can tune and receive on a given channel, it may not
  3998. * be able to associate or transmit any frames on that
  3999. * channel. There is no corresponding channel information for that
  4000. * entry.
  4001. *
  4002. *********************************************************************/
  4003. /* 2.4 GHz */
  4004. static const u8 iwl3945_eeprom_band_1[14] = {
  4005. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  4006. };
  4007. /* 5.2 GHz bands */
  4008. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  4009. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  4010. };
  4011. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  4012. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  4013. };
  4014. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  4015. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  4016. };
  4017. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  4018. 145, 149, 153, 157, 161, 165
  4019. };
  4020. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  4021. int *eeprom_ch_count,
  4022. const struct iwl3945_eeprom_channel
  4023. **eeprom_ch_info,
  4024. const u8 **eeprom_ch_index)
  4025. {
  4026. switch (band) {
  4027. case 1: /* 2.4GHz band */
  4028. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  4029. *eeprom_ch_info = priv->eeprom.band_1_channels;
  4030. *eeprom_ch_index = iwl3945_eeprom_band_1;
  4031. break;
  4032. case 2: /* 4.9GHz band */
  4033. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  4034. *eeprom_ch_info = priv->eeprom.band_2_channels;
  4035. *eeprom_ch_index = iwl3945_eeprom_band_2;
  4036. break;
  4037. case 3: /* 5.2GHz band */
  4038. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  4039. *eeprom_ch_info = priv->eeprom.band_3_channels;
  4040. *eeprom_ch_index = iwl3945_eeprom_band_3;
  4041. break;
  4042. case 4: /* 5.5GHz band */
  4043. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  4044. *eeprom_ch_info = priv->eeprom.band_4_channels;
  4045. *eeprom_ch_index = iwl3945_eeprom_band_4;
  4046. break;
  4047. case 5: /* 5.7GHz band */
  4048. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  4049. *eeprom_ch_info = priv->eeprom.band_5_channels;
  4050. *eeprom_ch_index = iwl3945_eeprom_band_5;
  4051. break;
  4052. default:
  4053. BUG();
  4054. return;
  4055. }
  4056. }
  4057. /**
  4058. * iwl3945_get_channel_info - Find driver's private channel info
  4059. *
  4060. * Based on band and channel number.
  4061. */
  4062. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  4063. enum ieee80211_band band, u16 channel)
  4064. {
  4065. int i;
  4066. switch (band) {
  4067. case IEEE80211_BAND_5GHZ:
  4068. for (i = 14; i < priv->channel_count; i++) {
  4069. if (priv->channel_info[i].channel == channel)
  4070. return &priv->channel_info[i];
  4071. }
  4072. break;
  4073. case IEEE80211_BAND_2GHZ:
  4074. if (channel >= 1 && channel <= 14)
  4075. return &priv->channel_info[channel - 1];
  4076. break;
  4077. case IEEE80211_NUM_BANDS:
  4078. WARN_ON(1);
  4079. }
  4080. return NULL;
  4081. }
  4082. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  4083. ? # x " " : "")
  4084. /**
  4085. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  4086. */
  4087. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  4088. {
  4089. int eeprom_ch_count = 0;
  4090. const u8 *eeprom_ch_index = NULL;
  4091. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  4092. int band, ch;
  4093. struct iwl3945_channel_info *ch_info;
  4094. if (priv->channel_count) {
  4095. IWL_DEBUG_INFO("Channel map already initialized.\n");
  4096. return 0;
  4097. }
  4098. if (priv->eeprom.version < 0x2f) {
  4099. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  4100. priv->eeprom.version);
  4101. return -EINVAL;
  4102. }
  4103. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  4104. priv->channel_count =
  4105. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  4106. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  4107. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  4108. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  4109. ARRAY_SIZE(iwl3945_eeprom_band_5);
  4110. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  4111. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  4112. priv->channel_count, GFP_KERNEL);
  4113. if (!priv->channel_info) {
  4114. IWL_ERROR("Could not allocate channel_info\n");
  4115. priv->channel_count = 0;
  4116. return -ENOMEM;
  4117. }
  4118. ch_info = priv->channel_info;
  4119. /* Loop through the 5 EEPROM bands adding them in order to the
  4120. * channel map we maintain (that contains additional information than
  4121. * what just in the EEPROM) */
  4122. for (band = 1; band <= 5; band++) {
  4123. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  4124. &eeprom_ch_info, &eeprom_ch_index);
  4125. /* Loop through each band adding each of the channels */
  4126. for (ch = 0; ch < eeprom_ch_count; ch++) {
  4127. ch_info->channel = eeprom_ch_index[ch];
  4128. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  4129. IEEE80211_BAND_5GHZ;
  4130. /* permanently store EEPROM's channel regulatory flags
  4131. * and max power in channel info database. */
  4132. ch_info->eeprom = eeprom_ch_info[ch];
  4133. /* Copy the run-time flags so they are there even on
  4134. * invalid channels */
  4135. ch_info->flags = eeprom_ch_info[ch].flags;
  4136. if (!(is_channel_valid(ch_info))) {
  4137. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  4138. "No traffic\n",
  4139. ch_info->channel,
  4140. ch_info->flags,
  4141. is_channel_a_band(ch_info) ?
  4142. "5.2" : "2.4");
  4143. ch_info++;
  4144. continue;
  4145. }
  4146. /* Initialize regulatory-based run-time data */
  4147. ch_info->max_power_avg = ch_info->curr_txpow =
  4148. eeprom_ch_info[ch].max_power_avg;
  4149. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  4150. ch_info->min_power = 0;
  4151. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x"
  4152. " %ddBm): Ad-Hoc %ssupported\n",
  4153. ch_info->channel,
  4154. is_channel_a_band(ch_info) ?
  4155. "5.2" : "2.4",
  4156. CHECK_AND_PRINT(VALID),
  4157. CHECK_AND_PRINT(IBSS),
  4158. CHECK_AND_PRINT(ACTIVE),
  4159. CHECK_AND_PRINT(RADAR),
  4160. CHECK_AND_PRINT(WIDE),
  4161. CHECK_AND_PRINT(NARROW),
  4162. CHECK_AND_PRINT(DFS),
  4163. eeprom_ch_info[ch].flags,
  4164. eeprom_ch_info[ch].max_power_avg,
  4165. ((eeprom_ch_info[ch].
  4166. flags & EEPROM_CHANNEL_IBSS)
  4167. && !(eeprom_ch_info[ch].
  4168. flags & EEPROM_CHANNEL_RADAR))
  4169. ? "" : "not ");
  4170. /* Set the user_txpower_limit to the highest power
  4171. * supported by any channel */
  4172. if (eeprom_ch_info[ch].max_power_avg >
  4173. priv->user_txpower_limit)
  4174. priv->user_txpower_limit =
  4175. eeprom_ch_info[ch].max_power_avg;
  4176. ch_info++;
  4177. }
  4178. }
  4179. /* Set up txpower settings in driver for all channels */
  4180. if (iwl3945_txpower_set_from_eeprom(priv))
  4181. return -EIO;
  4182. return 0;
  4183. }
  4184. /*
  4185. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  4186. */
  4187. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  4188. {
  4189. kfree(priv->channel_info);
  4190. priv->channel_count = 0;
  4191. }
  4192. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  4193. * sending probe req. This should be set long enough to hear probe responses
  4194. * from more than one AP. */
  4195. #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
  4196. #define IWL_ACTIVE_DWELL_TIME_52 (10)
  4197. /* For faster active scanning, scan will move to the next channel if fewer than
  4198. * PLCP_QUIET_THRESH packets are heard on this channel within
  4199. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  4200. * time if it's a quiet channel (nothing responded to our probe, and there's
  4201. * no other traffic).
  4202. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  4203. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  4204. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
  4205. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  4206. * Must be set longer than active dwell time.
  4207. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  4208. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  4209. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  4210. #define IWL_PASSIVE_DWELL_BASE (100)
  4211. #define IWL_CHANNEL_TUNE_TIME 5
  4212. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  4213. enum ieee80211_band band)
  4214. {
  4215. if (band == IEEE80211_BAND_5GHZ)
  4216. return IWL_ACTIVE_DWELL_TIME_52;
  4217. else
  4218. return IWL_ACTIVE_DWELL_TIME_24;
  4219. }
  4220. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  4221. enum ieee80211_band band)
  4222. {
  4223. u16 active = iwl3945_get_active_dwell_time(priv, band);
  4224. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  4225. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4226. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4227. if (iwl3945_is_associated(priv)) {
  4228. /* If we're associated, we clamp the maximum passive
  4229. * dwell time to be 98% of the beacon interval (minus
  4230. * 2 * channel tune time) */
  4231. passive = priv->beacon_int;
  4232. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4233. passive = IWL_PASSIVE_DWELL_BASE;
  4234. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4235. }
  4236. if (passive <= active)
  4237. passive = active + 1;
  4238. return passive;
  4239. }
  4240. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  4241. enum ieee80211_band band,
  4242. u8 is_active, u8 direct_mask,
  4243. struct iwl3945_scan_channel *scan_ch)
  4244. {
  4245. const struct ieee80211_channel *channels = NULL;
  4246. const struct ieee80211_supported_band *sband;
  4247. const struct iwl3945_channel_info *ch_info;
  4248. u16 passive_dwell = 0;
  4249. u16 active_dwell = 0;
  4250. int added, i;
  4251. sband = iwl3945_get_band(priv, band);
  4252. if (!sband)
  4253. return 0;
  4254. channels = sband->channels;
  4255. active_dwell = iwl3945_get_active_dwell_time(priv, band);
  4256. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  4257. for (i = 0, added = 0; i < sband->n_channels; i++) {
  4258. if (channels[i].hw_value ==
  4259. le16_to_cpu(priv->active_rxon.channel)) {
  4260. if (iwl3945_is_associated(priv)) {
  4261. IWL_DEBUG_SCAN
  4262. ("Skipping current channel %d\n",
  4263. le16_to_cpu(priv->active_rxon.channel));
  4264. continue;
  4265. }
  4266. } else if (priv->only_active_channel)
  4267. continue;
  4268. scan_ch->channel = channels[i].hw_value;
  4269. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  4270. if (!is_channel_valid(ch_info)) {
  4271. IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
  4272. scan_ch->channel);
  4273. continue;
  4274. }
  4275. if (!is_active || is_channel_passive(ch_info) ||
  4276. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
  4277. scan_ch->type = 0; /* passive */
  4278. else
  4279. scan_ch->type = 1; /* active */
  4280. if (scan_ch->type & 1)
  4281. scan_ch->type |= (direct_mask << 1);
  4282. if (is_channel_narrow(ch_info))
  4283. scan_ch->type |= (1 << 7);
  4284. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4285. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4286. /* Set txpower levels to defaults */
  4287. scan_ch->tpc.dsp_atten = 110;
  4288. /* scan_pwr_info->tpc.dsp_atten; */
  4289. /*scan_pwr_info->tpc.tx_gain; */
  4290. if (band == IEEE80211_BAND_5GHZ)
  4291. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4292. else {
  4293. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4294. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4295. * power level:
  4296. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  4297. */
  4298. }
  4299. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4300. scan_ch->channel,
  4301. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4302. (scan_ch->type & 1) ?
  4303. active_dwell : passive_dwell);
  4304. scan_ch++;
  4305. added++;
  4306. }
  4307. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4308. return added;
  4309. }
  4310. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4311. struct ieee80211_rate *rates)
  4312. {
  4313. int i;
  4314. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4315. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  4316. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4317. rates[i].hw_value_short = i;
  4318. rates[i].flags = 0;
  4319. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4320. /*
  4321. * If CCK != 1M then set short preamble rate flag.
  4322. */
  4323. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4324. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4325. }
  4326. }
  4327. }
  4328. /**
  4329. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4330. */
  4331. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4332. {
  4333. struct iwl3945_channel_info *ch;
  4334. struct ieee80211_supported_band *sband;
  4335. struct ieee80211_channel *channels;
  4336. struct ieee80211_channel *geo_ch;
  4337. struct ieee80211_rate *rates;
  4338. int i = 0;
  4339. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4340. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4341. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4342. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4343. return 0;
  4344. }
  4345. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4346. priv->channel_count, GFP_KERNEL);
  4347. if (!channels)
  4348. return -ENOMEM;
  4349. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  4350. GFP_KERNEL);
  4351. if (!rates) {
  4352. kfree(channels);
  4353. return -ENOMEM;
  4354. }
  4355. /* 5.2GHz channels start after the 2.4GHz channels */
  4356. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4357. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4358. /* just OFDM */
  4359. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  4360. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  4361. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4362. sband->channels = channels;
  4363. /* OFDM & CCK */
  4364. sband->bitrates = rates;
  4365. sband->n_bitrates = IWL_RATE_COUNT;
  4366. priv->ieee_channels = channels;
  4367. priv->ieee_rates = rates;
  4368. iwl3945_init_hw_rates(priv, rates);
  4369. for (i = 0; i < priv->channel_count; i++) {
  4370. ch = &priv->channel_info[i];
  4371. /* FIXME: might be removed if scan is OK*/
  4372. if (!is_channel_valid(ch))
  4373. continue;
  4374. if (is_channel_a_band(ch))
  4375. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4376. else
  4377. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4378. geo_ch = &sband->channels[sband->n_channels++];
  4379. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  4380. geo_ch->max_power = ch->max_power_avg;
  4381. geo_ch->max_antenna_gain = 0xff;
  4382. geo_ch->hw_value = ch->channel;
  4383. if (is_channel_valid(ch)) {
  4384. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4385. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4386. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4387. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4388. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4389. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4390. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4391. priv->max_channel_txpower_limit =
  4392. ch->max_power_avg;
  4393. } else {
  4394. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4395. }
  4396. /* Save flags for reg domain usage */
  4397. geo_ch->orig_flags = geo_ch->flags;
  4398. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  4399. ch->channel, geo_ch->center_freq,
  4400. is_channel_a_band(ch) ? "5.2" : "2.4",
  4401. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  4402. "restricted" : "valid",
  4403. geo_ch->flags);
  4404. }
  4405. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  4406. priv->cfg->sku & IWL_SKU_A) {
  4407. printk(KERN_INFO DRV_NAME
  4408. ": Incorrectly detected BG card as ABG. Please send "
  4409. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4410. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4411. priv->cfg->sku &= ~IWL_SKU_A;
  4412. }
  4413. printk(KERN_INFO DRV_NAME
  4414. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4415. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4416. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4417. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->bands[IEEE80211_BAND_2GHZ];
  4418. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->bands[IEEE80211_BAND_5GHZ];
  4419. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4420. return 0;
  4421. }
  4422. /*
  4423. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4424. */
  4425. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4426. {
  4427. kfree(priv->ieee_channels);
  4428. kfree(priv->ieee_rates);
  4429. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4430. }
  4431. /******************************************************************************
  4432. *
  4433. * uCode download functions
  4434. *
  4435. ******************************************************************************/
  4436. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4437. {
  4438. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4439. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4440. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4441. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4442. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4443. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4444. }
  4445. /**
  4446. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4447. * looking at all data.
  4448. */
  4449. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
  4450. {
  4451. u32 val;
  4452. u32 save_len = len;
  4453. int rc = 0;
  4454. u32 errcnt;
  4455. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4456. rc = iwl3945_grab_nic_access(priv);
  4457. if (rc)
  4458. return rc;
  4459. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4460. errcnt = 0;
  4461. for (; len > 0; len -= sizeof(u32), image++) {
  4462. /* read data comes through single port, auto-incr addr */
  4463. /* NOTE: Use the debugless read so we don't flood kernel log
  4464. * if IWL_DL_IO is set */
  4465. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4466. if (val != le32_to_cpu(*image)) {
  4467. IWL_ERROR("uCode INST section is invalid at "
  4468. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4469. save_len - len, val, le32_to_cpu(*image));
  4470. rc = -EIO;
  4471. errcnt++;
  4472. if (errcnt >= 20)
  4473. break;
  4474. }
  4475. }
  4476. iwl3945_release_nic_access(priv);
  4477. if (!errcnt)
  4478. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4479. return rc;
  4480. }
  4481. /**
  4482. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4483. * using sample data 100 bytes apart. If these sample points are good,
  4484. * it's a pretty good bet that everything between them is good, too.
  4485. */
  4486. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4487. {
  4488. u32 val;
  4489. int rc = 0;
  4490. u32 errcnt = 0;
  4491. u32 i;
  4492. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4493. rc = iwl3945_grab_nic_access(priv);
  4494. if (rc)
  4495. return rc;
  4496. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4497. /* read data comes through single port, auto-incr addr */
  4498. /* NOTE: Use the debugless read so we don't flood kernel log
  4499. * if IWL_DL_IO is set */
  4500. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4501. i + RTC_INST_LOWER_BOUND);
  4502. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4503. if (val != le32_to_cpu(*image)) {
  4504. #if 0 /* Enable this if you want to see details */
  4505. IWL_ERROR("uCode INST section is invalid at "
  4506. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4507. i, val, *image);
  4508. #endif
  4509. rc = -EIO;
  4510. errcnt++;
  4511. if (errcnt >= 3)
  4512. break;
  4513. }
  4514. }
  4515. iwl3945_release_nic_access(priv);
  4516. return rc;
  4517. }
  4518. /**
  4519. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4520. * and verify its contents
  4521. */
  4522. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4523. {
  4524. __le32 *image;
  4525. u32 len;
  4526. int rc = 0;
  4527. /* Try bootstrap */
  4528. image = (__le32 *)priv->ucode_boot.v_addr;
  4529. len = priv->ucode_boot.len;
  4530. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4531. if (rc == 0) {
  4532. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4533. return 0;
  4534. }
  4535. /* Try initialize */
  4536. image = (__le32 *)priv->ucode_init.v_addr;
  4537. len = priv->ucode_init.len;
  4538. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4539. if (rc == 0) {
  4540. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4541. return 0;
  4542. }
  4543. /* Try runtime/protocol */
  4544. image = (__le32 *)priv->ucode_code.v_addr;
  4545. len = priv->ucode_code.len;
  4546. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4547. if (rc == 0) {
  4548. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4549. return 0;
  4550. }
  4551. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4552. /* Since nothing seems to match, show first several data entries in
  4553. * instruction SRAM, so maybe visual inspection will give a clue.
  4554. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4555. image = (__le32 *)priv->ucode_boot.v_addr;
  4556. len = priv->ucode_boot.len;
  4557. rc = iwl3945_verify_inst_full(priv, image, len);
  4558. return rc;
  4559. }
  4560. /* check contents of special bootstrap uCode SRAM */
  4561. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4562. {
  4563. __le32 *image = priv->ucode_boot.v_addr;
  4564. u32 len = priv->ucode_boot.len;
  4565. u32 reg;
  4566. u32 val;
  4567. IWL_DEBUG_INFO("Begin verify bsm\n");
  4568. /* verify BSM SRAM contents */
  4569. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4570. for (reg = BSM_SRAM_LOWER_BOUND;
  4571. reg < BSM_SRAM_LOWER_BOUND + len;
  4572. reg += sizeof(u32), image ++) {
  4573. val = iwl3945_read_prph(priv, reg);
  4574. if (val != le32_to_cpu(*image)) {
  4575. IWL_ERROR("BSM uCode verification failed at "
  4576. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4577. BSM_SRAM_LOWER_BOUND,
  4578. reg - BSM_SRAM_LOWER_BOUND, len,
  4579. val, le32_to_cpu(*image));
  4580. return -EIO;
  4581. }
  4582. }
  4583. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4584. return 0;
  4585. }
  4586. /**
  4587. * iwl3945_load_bsm - Load bootstrap instructions
  4588. *
  4589. * BSM operation:
  4590. *
  4591. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4592. * in special SRAM that does not power down during RFKILL. When powering back
  4593. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4594. * the bootstrap program into the on-board processor, and starts it.
  4595. *
  4596. * The bootstrap program loads (via DMA) instructions and data for a new
  4597. * program from host DRAM locations indicated by the host driver in the
  4598. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4599. * automatically.
  4600. *
  4601. * When initializing the NIC, the host driver points the BSM to the
  4602. * "initialize" uCode image. This uCode sets up some internal data, then
  4603. * notifies host via "initialize alive" that it is complete.
  4604. *
  4605. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4606. * normal runtime uCode instructions and a backup uCode data cache buffer
  4607. * (filled initially with starting data values for the on-board processor),
  4608. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4609. * which begins normal operation.
  4610. *
  4611. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4612. * the backup data cache in DRAM before SRAM is powered down.
  4613. *
  4614. * When powering back up, the BSM loads the bootstrap program. This reloads
  4615. * the runtime uCode instructions and the backup data cache into SRAM,
  4616. * and re-launches the runtime uCode from where it left off.
  4617. */
  4618. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4619. {
  4620. __le32 *image = priv->ucode_boot.v_addr;
  4621. u32 len = priv->ucode_boot.len;
  4622. dma_addr_t pinst;
  4623. dma_addr_t pdata;
  4624. u32 inst_len;
  4625. u32 data_len;
  4626. int rc;
  4627. int i;
  4628. u32 done;
  4629. u32 reg_offset;
  4630. IWL_DEBUG_INFO("Begin load bsm\n");
  4631. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4632. if (len > IWL_MAX_BSM_SIZE)
  4633. return -EINVAL;
  4634. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4635. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4636. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4637. * after the "initialize" uCode has run, to point to
  4638. * runtime/protocol instructions and backup data cache. */
  4639. pinst = priv->ucode_init.p_addr;
  4640. pdata = priv->ucode_init_data.p_addr;
  4641. inst_len = priv->ucode_init.len;
  4642. data_len = priv->ucode_init_data.len;
  4643. rc = iwl3945_grab_nic_access(priv);
  4644. if (rc)
  4645. return rc;
  4646. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4647. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4648. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4649. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4650. /* Fill BSM memory with bootstrap instructions */
  4651. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4652. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4653. reg_offset += sizeof(u32), image++)
  4654. _iwl3945_write_prph(priv, reg_offset,
  4655. le32_to_cpu(*image));
  4656. rc = iwl3945_verify_bsm(priv);
  4657. if (rc) {
  4658. iwl3945_release_nic_access(priv);
  4659. return rc;
  4660. }
  4661. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4662. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4663. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4664. RTC_INST_LOWER_BOUND);
  4665. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4666. /* Load bootstrap code into instruction SRAM now,
  4667. * to prepare to load "initialize" uCode */
  4668. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4669. BSM_WR_CTRL_REG_BIT_START);
  4670. /* Wait for load of bootstrap uCode to finish */
  4671. for (i = 0; i < 100; i++) {
  4672. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4673. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4674. break;
  4675. udelay(10);
  4676. }
  4677. if (i < 100)
  4678. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4679. else {
  4680. IWL_ERROR("BSM write did not complete!\n");
  4681. return -EIO;
  4682. }
  4683. /* Enable future boot loads whenever power management unit triggers it
  4684. * (e.g. when powering back up after power-save shutdown) */
  4685. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4686. BSM_WR_CTRL_REG_BIT_START_EN);
  4687. iwl3945_release_nic_access(priv);
  4688. return 0;
  4689. }
  4690. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4691. {
  4692. /* Remove all resets to allow NIC to operate */
  4693. iwl3945_write32(priv, CSR_RESET, 0);
  4694. }
  4695. /**
  4696. * iwl3945_read_ucode - Read uCode images from disk file.
  4697. *
  4698. * Copy into buffers for card to fetch via bus-mastering
  4699. */
  4700. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4701. {
  4702. struct iwl3945_ucode *ucode;
  4703. int ret = 0;
  4704. const struct firmware *ucode_raw;
  4705. /* firmware file name contains uCode/driver compatibility version */
  4706. const char *name = priv->cfg->fw_name;
  4707. u8 *src;
  4708. size_t len;
  4709. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4710. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4711. * request_firmware() is synchronous, file is in memory on return. */
  4712. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  4713. if (ret < 0) {
  4714. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4715. name, ret);
  4716. goto error;
  4717. }
  4718. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4719. name, ucode_raw->size);
  4720. /* Make sure that we got at least our header! */
  4721. if (ucode_raw->size < sizeof(*ucode)) {
  4722. IWL_ERROR("File size way too small!\n");
  4723. ret = -EINVAL;
  4724. goto err_release;
  4725. }
  4726. /* Data from ucode file: header followed by uCode images */
  4727. ucode = (void *)ucode_raw->data;
  4728. ver = le32_to_cpu(ucode->ver);
  4729. inst_size = le32_to_cpu(ucode->inst_size);
  4730. data_size = le32_to_cpu(ucode->data_size);
  4731. init_size = le32_to_cpu(ucode->init_size);
  4732. init_data_size = le32_to_cpu(ucode->init_data_size);
  4733. boot_size = le32_to_cpu(ucode->boot_size);
  4734. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  4735. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4736. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4737. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4738. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4739. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4740. /* Verify size of file vs. image size info in file's header */
  4741. if (ucode_raw->size < sizeof(*ucode) +
  4742. inst_size + data_size + init_size +
  4743. init_data_size + boot_size) {
  4744. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4745. (int)ucode_raw->size);
  4746. ret = -EINVAL;
  4747. goto err_release;
  4748. }
  4749. /* Verify that uCode images will fit in card's SRAM */
  4750. if (inst_size > IWL_MAX_INST_SIZE) {
  4751. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4752. inst_size);
  4753. ret = -EINVAL;
  4754. goto err_release;
  4755. }
  4756. if (data_size > IWL_MAX_DATA_SIZE) {
  4757. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4758. data_size);
  4759. ret = -EINVAL;
  4760. goto err_release;
  4761. }
  4762. if (init_size > IWL_MAX_INST_SIZE) {
  4763. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4764. init_size);
  4765. ret = -EINVAL;
  4766. goto err_release;
  4767. }
  4768. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4769. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4770. init_data_size);
  4771. ret = -EINVAL;
  4772. goto err_release;
  4773. }
  4774. if (boot_size > IWL_MAX_BSM_SIZE) {
  4775. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4776. boot_size);
  4777. ret = -EINVAL;
  4778. goto err_release;
  4779. }
  4780. /* Allocate ucode buffers for card's bus-master loading ... */
  4781. /* Runtime instructions and 2 copies of data:
  4782. * 1) unmodified from disk
  4783. * 2) backup cache for save/restore during power-downs */
  4784. priv->ucode_code.len = inst_size;
  4785. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4786. priv->ucode_data.len = data_size;
  4787. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4788. priv->ucode_data_backup.len = data_size;
  4789. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4790. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4791. !priv->ucode_data_backup.v_addr)
  4792. goto err_pci_alloc;
  4793. /* Initialization instructions and data */
  4794. if (init_size && init_data_size) {
  4795. priv->ucode_init.len = init_size;
  4796. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4797. priv->ucode_init_data.len = init_data_size;
  4798. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4799. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4800. goto err_pci_alloc;
  4801. }
  4802. /* Bootstrap (instructions only, no data) */
  4803. if (boot_size) {
  4804. priv->ucode_boot.len = boot_size;
  4805. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4806. if (!priv->ucode_boot.v_addr)
  4807. goto err_pci_alloc;
  4808. }
  4809. /* Copy images into buffers for card's bus-master reads ... */
  4810. /* Runtime instructions (first block of data in file) */
  4811. src = &ucode->data[0];
  4812. len = priv->ucode_code.len;
  4813. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4814. memcpy(priv->ucode_code.v_addr, src, len);
  4815. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4816. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4817. /* Runtime data (2nd block)
  4818. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4819. src = &ucode->data[inst_size];
  4820. len = priv->ucode_data.len;
  4821. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4822. memcpy(priv->ucode_data.v_addr, src, len);
  4823. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4824. /* Initialization instructions (3rd block) */
  4825. if (init_size) {
  4826. src = &ucode->data[inst_size + data_size];
  4827. len = priv->ucode_init.len;
  4828. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4829. len);
  4830. memcpy(priv->ucode_init.v_addr, src, len);
  4831. }
  4832. /* Initialization data (4th block) */
  4833. if (init_data_size) {
  4834. src = &ucode->data[inst_size + data_size + init_size];
  4835. len = priv->ucode_init_data.len;
  4836. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4837. (int)len);
  4838. memcpy(priv->ucode_init_data.v_addr, src, len);
  4839. }
  4840. /* Bootstrap instructions (5th block) */
  4841. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4842. len = priv->ucode_boot.len;
  4843. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4844. (int)len);
  4845. memcpy(priv->ucode_boot.v_addr, src, len);
  4846. /* We have our copies now, allow OS release its copies */
  4847. release_firmware(ucode_raw);
  4848. return 0;
  4849. err_pci_alloc:
  4850. IWL_ERROR("failed to allocate pci memory\n");
  4851. ret = -ENOMEM;
  4852. iwl3945_dealloc_ucode_pci(priv);
  4853. err_release:
  4854. release_firmware(ucode_raw);
  4855. error:
  4856. return ret;
  4857. }
  4858. /**
  4859. * iwl3945_set_ucode_ptrs - Set uCode address location
  4860. *
  4861. * Tell initialization uCode where to find runtime uCode.
  4862. *
  4863. * BSM registers initially contain pointers to initialization uCode.
  4864. * We need to replace them to load runtime uCode inst and data,
  4865. * and to save runtime data when powering down.
  4866. */
  4867. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  4868. {
  4869. dma_addr_t pinst;
  4870. dma_addr_t pdata;
  4871. int rc = 0;
  4872. unsigned long flags;
  4873. /* bits 31:0 for 3945 */
  4874. pinst = priv->ucode_code.p_addr;
  4875. pdata = priv->ucode_data_backup.p_addr;
  4876. spin_lock_irqsave(&priv->lock, flags);
  4877. rc = iwl3945_grab_nic_access(priv);
  4878. if (rc) {
  4879. spin_unlock_irqrestore(&priv->lock, flags);
  4880. return rc;
  4881. }
  4882. /* Tell bootstrap uCode where to find image to load */
  4883. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4884. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4885. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4886. priv->ucode_data.len);
  4887. /* Inst bytecount must be last to set up, bit 31 signals uCode
  4888. * that all new ptr/size info is in place */
  4889. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4890. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4891. iwl3945_release_nic_access(priv);
  4892. spin_unlock_irqrestore(&priv->lock, flags);
  4893. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4894. return rc;
  4895. }
  4896. /**
  4897. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4898. *
  4899. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4900. *
  4901. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4902. */
  4903. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  4904. {
  4905. /* Check alive response for "valid" sign from uCode */
  4906. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4907. /* We had an error bringing up the hardware, so take it
  4908. * all the way back down so we can try again */
  4909. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4910. goto restart;
  4911. }
  4912. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4913. * This is a paranoid check, because we would not have gotten the
  4914. * "initialize" alive if code weren't properly loaded. */
  4915. if (iwl3945_verify_ucode(priv)) {
  4916. /* Runtime instruction load was bad;
  4917. * take it all the way back down so we can try again */
  4918. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4919. goto restart;
  4920. }
  4921. /* Send pointers to protocol/runtime uCode image ... init code will
  4922. * load and launch runtime uCode, which will send us another "Alive"
  4923. * notification. */
  4924. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4925. if (iwl3945_set_ucode_ptrs(priv)) {
  4926. /* Runtime instruction load won't happen;
  4927. * take it all the way back down so we can try again */
  4928. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4929. goto restart;
  4930. }
  4931. return;
  4932. restart:
  4933. queue_work(priv->workqueue, &priv->restart);
  4934. }
  4935. /**
  4936. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4937. * from protocol/runtime uCode (initialization uCode's
  4938. * Alive gets handled by iwl3945_init_alive_start()).
  4939. */
  4940. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  4941. {
  4942. int rc = 0;
  4943. int thermal_spin = 0;
  4944. u32 rfkill;
  4945. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4946. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4947. /* We had an error bringing up the hardware, so take it
  4948. * all the way back down so we can try again */
  4949. IWL_DEBUG_INFO("Alive failed.\n");
  4950. goto restart;
  4951. }
  4952. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4953. * This is a paranoid check, because we would not have gotten the
  4954. * "runtime" alive if code weren't properly loaded. */
  4955. if (iwl3945_verify_ucode(priv)) {
  4956. /* Runtime instruction load was bad;
  4957. * take it all the way back down so we can try again */
  4958. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4959. goto restart;
  4960. }
  4961. iwl3945_clear_stations_table(priv);
  4962. rc = iwl3945_grab_nic_access(priv);
  4963. if (rc) {
  4964. IWL_WARNING("Can not read rfkill status from adapter\n");
  4965. return;
  4966. }
  4967. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  4968. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4969. iwl3945_release_nic_access(priv);
  4970. if (rfkill & 0x1) {
  4971. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4972. /* if rfkill is not on, then wait for thermal
  4973. * sensor in adapter to kick in */
  4974. while (iwl3945_hw_get_temperature(priv) == 0) {
  4975. thermal_spin++;
  4976. udelay(10);
  4977. }
  4978. if (thermal_spin)
  4979. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4980. thermal_spin * 10);
  4981. } else
  4982. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4983. /* After the ALIVE response, we can send commands to 3945 uCode */
  4984. set_bit(STATUS_ALIVE, &priv->status);
  4985. /* Clear out the uCode error bit if it is set */
  4986. clear_bit(STATUS_FW_ERROR, &priv->status);
  4987. if (iwl3945_is_rfkill(priv))
  4988. return;
  4989. ieee80211_start_queues(priv->hw);
  4990. priv->active_rate = priv->rates_mask;
  4991. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4992. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4993. if (iwl3945_is_associated(priv)) {
  4994. struct iwl3945_rxon_cmd *active_rxon =
  4995. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  4996. memcpy(&priv->staging_rxon, &priv->active_rxon,
  4997. sizeof(priv->staging_rxon));
  4998. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4999. } else {
  5000. /* Initialize our rx_config data */
  5001. iwl3945_connection_init_rx_config(priv);
  5002. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  5003. }
  5004. /* Configure Bluetooth device coexistence support */
  5005. iwl3945_send_bt_config(priv);
  5006. /* Configure the adapter for unassociated operation */
  5007. iwl3945_commit_rxon(priv);
  5008. /* At this point, the NIC is initialized and operational */
  5009. priv->notif_missed_beacons = 0;
  5010. set_bit(STATUS_READY, &priv->status);
  5011. iwl3945_reg_txpower_periodic(priv);
  5012. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  5013. wake_up_interruptible(&priv->wait_command_queue);
  5014. if (priv->error_recovering)
  5015. iwl3945_error_recovery(priv);
  5016. return;
  5017. restart:
  5018. queue_work(priv->workqueue, &priv->restart);
  5019. }
  5020. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  5021. static void __iwl3945_down(struct iwl3945_priv *priv)
  5022. {
  5023. unsigned long flags;
  5024. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  5025. struct ieee80211_conf *conf = NULL;
  5026. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  5027. conf = ieee80211_get_hw_conf(priv->hw);
  5028. if (!exit_pending)
  5029. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5030. iwl3945_clear_stations_table(priv);
  5031. /* Unblock any waiting calls */
  5032. wake_up_interruptible_all(&priv->wait_command_queue);
  5033. /* Wipe out the EXIT_PENDING status bit if we are not actually
  5034. * exiting the module */
  5035. if (!exit_pending)
  5036. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  5037. /* stop and reset the on-board processor */
  5038. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  5039. /* tell the device to stop sending interrupts */
  5040. iwl3945_disable_interrupts(priv);
  5041. if (priv->mac80211_registered)
  5042. ieee80211_stop_queues(priv->hw);
  5043. /* If we have not previously called iwl3945_init() then
  5044. * clear all bits but the RF Kill and SUSPEND bits and return */
  5045. if (!iwl3945_is_init(priv)) {
  5046. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5047. STATUS_RF_KILL_HW |
  5048. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5049. STATUS_RF_KILL_SW |
  5050. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  5051. STATUS_GEO_CONFIGURED |
  5052. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5053. STATUS_IN_SUSPEND;
  5054. goto exit;
  5055. }
  5056. /* ...otherwise clear out all the status bits but the RF Kill and
  5057. * SUSPEND bits and continue taking the NIC down. */
  5058. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5059. STATUS_RF_KILL_HW |
  5060. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5061. STATUS_RF_KILL_SW |
  5062. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  5063. STATUS_GEO_CONFIGURED |
  5064. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5065. STATUS_IN_SUSPEND |
  5066. test_bit(STATUS_FW_ERROR, &priv->status) <<
  5067. STATUS_FW_ERROR;
  5068. spin_lock_irqsave(&priv->lock, flags);
  5069. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  5070. spin_unlock_irqrestore(&priv->lock, flags);
  5071. iwl3945_hw_txq_ctx_stop(priv);
  5072. iwl3945_hw_rxq_stop(priv);
  5073. spin_lock_irqsave(&priv->lock, flags);
  5074. if (!iwl3945_grab_nic_access(priv)) {
  5075. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  5076. APMG_CLK_VAL_DMA_CLK_RQT);
  5077. iwl3945_release_nic_access(priv);
  5078. }
  5079. spin_unlock_irqrestore(&priv->lock, flags);
  5080. udelay(5);
  5081. iwl3945_hw_nic_stop_master(priv);
  5082. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  5083. iwl3945_hw_nic_reset(priv);
  5084. exit:
  5085. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  5086. if (priv->ibss_beacon)
  5087. dev_kfree_skb(priv->ibss_beacon);
  5088. priv->ibss_beacon = NULL;
  5089. /* clear out any free frames */
  5090. iwl3945_clear_free_frames(priv);
  5091. }
  5092. static void iwl3945_down(struct iwl3945_priv *priv)
  5093. {
  5094. mutex_lock(&priv->mutex);
  5095. __iwl3945_down(priv);
  5096. mutex_unlock(&priv->mutex);
  5097. iwl3945_cancel_deferred_work(priv);
  5098. }
  5099. #define MAX_HW_RESTARTS 5
  5100. static int __iwl3945_up(struct iwl3945_priv *priv)
  5101. {
  5102. int rc, i;
  5103. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5104. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  5105. return -EIO;
  5106. }
  5107. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  5108. IWL_WARNING("Radio disabled by SW RF kill (module "
  5109. "parameter)\n");
  5110. return -ENODEV;
  5111. }
  5112. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  5113. IWL_ERROR("ucode not available for device bringup\n");
  5114. return -EIO;
  5115. }
  5116. /* If platform's RF_KILL switch is NOT set to KILL */
  5117. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  5118. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  5119. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  5120. else {
  5121. set_bit(STATUS_RF_KILL_HW, &priv->status);
  5122. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  5123. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  5124. return -ENODEV;
  5125. }
  5126. }
  5127. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5128. rc = iwl3945_hw_nic_init(priv);
  5129. if (rc) {
  5130. IWL_ERROR("Unable to int nic\n");
  5131. return rc;
  5132. }
  5133. /* make sure rfkill handshake bits are cleared */
  5134. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5135. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  5136. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  5137. /* clear (again), then enable host interrupts */
  5138. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5139. iwl3945_enable_interrupts(priv);
  5140. /* really make sure rfkill handshake bits are cleared */
  5141. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5142. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5143. /* Copy original ucode data image from disk into backup cache.
  5144. * This will be used to initialize the on-board processor's
  5145. * data SRAM for a clean start when the runtime program first loads. */
  5146. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  5147. priv->ucode_data.len);
  5148. /* We return success when we resume from suspend and rf_kill is on. */
  5149. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  5150. return 0;
  5151. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  5152. iwl3945_clear_stations_table(priv);
  5153. /* load bootstrap state machine,
  5154. * load bootstrap program into processor's memory,
  5155. * prepare to load the "initialize" uCode */
  5156. rc = iwl3945_load_bsm(priv);
  5157. if (rc) {
  5158. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  5159. continue;
  5160. }
  5161. /* start card; "initialize" will load runtime ucode */
  5162. iwl3945_nic_start(priv);
  5163. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  5164. return 0;
  5165. }
  5166. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5167. __iwl3945_down(priv);
  5168. /* tried to restart and config the device for as long as our
  5169. * patience could withstand */
  5170. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  5171. return -EIO;
  5172. }
  5173. /*****************************************************************************
  5174. *
  5175. * Workqueue callbacks
  5176. *
  5177. *****************************************************************************/
  5178. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  5179. {
  5180. struct iwl3945_priv *priv =
  5181. container_of(data, struct iwl3945_priv, init_alive_start.work);
  5182. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5183. return;
  5184. mutex_lock(&priv->mutex);
  5185. iwl3945_init_alive_start(priv);
  5186. mutex_unlock(&priv->mutex);
  5187. }
  5188. static void iwl3945_bg_alive_start(struct work_struct *data)
  5189. {
  5190. struct iwl3945_priv *priv =
  5191. container_of(data, struct iwl3945_priv, alive_start.work);
  5192. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5193. return;
  5194. mutex_lock(&priv->mutex);
  5195. iwl3945_alive_start(priv);
  5196. mutex_unlock(&priv->mutex);
  5197. }
  5198. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5199. {
  5200. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5201. wake_up_interruptible(&priv->wait_command_queue);
  5202. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5203. return;
  5204. mutex_lock(&priv->mutex);
  5205. if (!iwl3945_is_rfkill(priv)) {
  5206. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5207. "HW and/or SW RF Kill no longer active, restarting "
  5208. "device\n");
  5209. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5210. queue_work(priv->workqueue, &priv->restart);
  5211. } else {
  5212. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5213. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5214. "disabled by SW switch\n");
  5215. else
  5216. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5217. "Kill switch must be turned off for "
  5218. "wireless networking to work.\n");
  5219. }
  5220. mutex_unlock(&priv->mutex);
  5221. }
  5222. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5223. static void iwl3945_bg_scan_check(struct work_struct *data)
  5224. {
  5225. struct iwl3945_priv *priv =
  5226. container_of(data, struct iwl3945_priv, scan_check.work);
  5227. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5228. return;
  5229. mutex_lock(&priv->mutex);
  5230. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5231. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5232. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5233. "Scan completion watchdog resetting adapter (%dms)\n",
  5234. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5235. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5236. iwl3945_send_scan_abort(priv);
  5237. }
  5238. mutex_unlock(&priv->mutex);
  5239. }
  5240. static void iwl3945_bg_request_scan(struct work_struct *data)
  5241. {
  5242. struct iwl3945_priv *priv =
  5243. container_of(data, struct iwl3945_priv, request_scan);
  5244. struct iwl3945_host_cmd cmd = {
  5245. .id = REPLY_SCAN_CMD,
  5246. .len = sizeof(struct iwl3945_scan_cmd),
  5247. .meta.flags = CMD_SIZE_HUGE,
  5248. };
  5249. int rc = 0;
  5250. struct iwl3945_scan_cmd *scan;
  5251. struct ieee80211_conf *conf = NULL;
  5252. u8 direct_mask;
  5253. enum ieee80211_band band;
  5254. conf = ieee80211_get_hw_conf(priv->hw);
  5255. mutex_lock(&priv->mutex);
  5256. if (!iwl3945_is_ready(priv)) {
  5257. IWL_WARNING("request scan called when driver not ready.\n");
  5258. goto done;
  5259. }
  5260. /* Make sure the scan wasn't cancelled before this queued work
  5261. * was given the chance to run... */
  5262. if (!test_bit(STATUS_SCANNING, &priv->status))
  5263. goto done;
  5264. /* This should never be called or scheduled if there is currently
  5265. * a scan active in the hardware. */
  5266. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5267. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5268. "Ignoring second request.\n");
  5269. rc = -EIO;
  5270. goto done;
  5271. }
  5272. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5273. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5274. goto done;
  5275. }
  5276. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5277. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5278. goto done;
  5279. }
  5280. if (iwl3945_is_rfkill(priv)) {
  5281. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5282. goto done;
  5283. }
  5284. if (!test_bit(STATUS_READY, &priv->status)) {
  5285. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5286. goto done;
  5287. }
  5288. if (!priv->scan_bands) {
  5289. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5290. goto done;
  5291. }
  5292. if (!priv->scan) {
  5293. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5294. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5295. if (!priv->scan) {
  5296. rc = -ENOMEM;
  5297. goto done;
  5298. }
  5299. }
  5300. scan = priv->scan;
  5301. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5302. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5303. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5304. if (iwl3945_is_associated(priv)) {
  5305. u16 interval = 0;
  5306. u32 extra;
  5307. u32 suspend_time = 100;
  5308. u32 scan_suspend_time = 100;
  5309. unsigned long flags;
  5310. IWL_DEBUG_INFO("Scanning while associated...\n");
  5311. spin_lock_irqsave(&priv->lock, flags);
  5312. interval = priv->beacon_int;
  5313. spin_unlock_irqrestore(&priv->lock, flags);
  5314. scan->suspend_time = 0;
  5315. scan->max_out_time = cpu_to_le32(200 * 1024);
  5316. if (!interval)
  5317. interval = suspend_time;
  5318. /*
  5319. * suspend time format:
  5320. * 0-19: beacon interval in usec (time before exec.)
  5321. * 20-23: 0
  5322. * 24-31: number of beacons (suspend between channels)
  5323. */
  5324. extra = (suspend_time / interval) << 24;
  5325. scan_suspend_time = 0xFF0FFFFF &
  5326. (extra | ((suspend_time % interval) * 1024));
  5327. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5328. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5329. scan_suspend_time, interval);
  5330. }
  5331. /* We should add the ability for user to lock to PASSIVE ONLY */
  5332. if (priv->one_direct_scan) {
  5333. IWL_DEBUG_SCAN
  5334. ("Kicking off one direct scan for '%s'\n",
  5335. iwl3945_escape_essid(priv->direct_ssid,
  5336. priv->direct_ssid_len));
  5337. scan->direct_scan[0].id = WLAN_EID_SSID;
  5338. scan->direct_scan[0].len = priv->direct_ssid_len;
  5339. memcpy(scan->direct_scan[0].ssid,
  5340. priv->direct_ssid, priv->direct_ssid_len);
  5341. direct_mask = 1;
  5342. } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
  5343. scan->direct_scan[0].id = WLAN_EID_SSID;
  5344. scan->direct_scan[0].len = priv->essid_len;
  5345. memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
  5346. direct_mask = 1;
  5347. } else
  5348. direct_mask = 0;
  5349. /* We don't build a direct scan probe request; the uCode will do
  5350. * that based on the direct_mask added to each channel entry */
  5351. scan->tx_cmd.len = cpu_to_le16(
  5352. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5353. IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
  5354. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5355. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5356. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5357. /* flags + rate selection */
  5358. switch (priv->scan_bands) {
  5359. case 2:
  5360. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5361. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5362. scan->good_CRC_th = 0;
  5363. band = IEEE80211_BAND_2GHZ;
  5364. break;
  5365. case 1:
  5366. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5367. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5368. band = IEEE80211_BAND_5GHZ;
  5369. break;
  5370. default:
  5371. IWL_WARNING("Invalid scan band count\n");
  5372. goto done;
  5373. }
  5374. /* select Rx antennas */
  5375. scan->flags |= iwl3945_get_antenna_flags(priv);
  5376. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
  5377. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5378. if (direct_mask)
  5379. IWL_DEBUG_SCAN
  5380. ("Initiating direct scan for %s.\n",
  5381. iwl3945_escape_essid(priv->essid, priv->essid_len));
  5382. else
  5383. IWL_DEBUG_SCAN("Initiating indirect scan.\n");
  5384. scan->channel_count =
  5385. iwl3945_get_channels_for_scan(
  5386. priv, band, 1, /* active */
  5387. direct_mask,
  5388. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5389. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5390. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5391. cmd.data = scan;
  5392. scan->len = cpu_to_le16(cmd.len);
  5393. set_bit(STATUS_SCAN_HW, &priv->status);
  5394. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5395. if (rc)
  5396. goto done;
  5397. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5398. IWL_SCAN_CHECK_WATCHDOG);
  5399. mutex_unlock(&priv->mutex);
  5400. return;
  5401. done:
  5402. /* inform mac80211 scan aborted */
  5403. queue_work(priv->workqueue, &priv->scan_completed);
  5404. mutex_unlock(&priv->mutex);
  5405. }
  5406. static void iwl3945_bg_up(struct work_struct *data)
  5407. {
  5408. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5409. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5410. return;
  5411. mutex_lock(&priv->mutex);
  5412. __iwl3945_up(priv);
  5413. mutex_unlock(&priv->mutex);
  5414. }
  5415. static void iwl3945_bg_restart(struct work_struct *data)
  5416. {
  5417. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5418. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5419. return;
  5420. iwl3945_down(priv);
  5421. queue_work(priv->workqueue, &priv->up);
  5422. }
  5423. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5424. {
  5425. struct iwl3945_priv *priv =
  5426. container_of(data, struct iwl3945_priv, rx_replenish);
  5427. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5428. return;
  5429. mutex_lock(&priv->mutex);
  5430. iwl3945_rx_replenish(priv);
  5431. mutex_unlock(&priv->mutex);
  5432. }
  5433. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5434. static void iwl3945_bg_post_associate(struct work_struct *data)
  5435. {
  5436. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
  5437. post_associate.work);
  5438. int rc = 0;
  5439. struct ieee80211_conf *conf = NULL;
  5440. DECLARE_MAC_BUF(mac);
  5441. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5442. IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
  5443. return;
  5444. }
  5445. IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
  5446. priv->assoc_id,
  5447. print_mac(mac, priv->active_rxon.bssid_addr));
  5448. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5449. return;
  5450. mutex_lock(&priv->mutex);
  5451. if (!priv->vif || !priv->is_open) {
  5452. mutex_unlock(&priv->mutex);
  5453. return;
  5454. }
  5455. iwl3945_scan_cancel_timeout(priv, 200);
  5456. conf = ieee80211_get_hw_conf(priv->hw);
  5457. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5458. iwl3945_commit_rxon(priv);
  5459. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5460. iwl3945_setup_rxon_timing(priv);
  5461. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5462. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5463. if (rc)
  5464. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5465. "Attempting to continue.\n");
  5466. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5467. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5468. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5469. priv->assoc_id, priv->beacon_int);
  5470. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5471. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5472. else
  5473. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5474. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5475. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5476. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5477. else
  5478. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5479. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5480. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5481. }
  5482. iwl3945_commit_rxon(priv);
  5483. switch (priv->iw_mode) {
  5484. case IEEE80211_IF_TYPE_STA:
  5485. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5486. break;
  5487. case IEEE80211_IF_TYPE_IBSS:
  5488. /* clear out the station table */
  5489. iwl3945_clear_stations_table(priv);
  5490. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5491. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5492. iwl3945_sync_sta(priv, IWL_STA_ID,
  5493. (priv->band == IEEE80211_BAND_5GHZ) ?
  5494. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5495. CMD_ASYNC);
  5496. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5497. iwl3945_send_beacon_cmd(priv);
  5498. break;
  5499. default:
  5500. IWL_ERROR("%s Should not be called in %d mode\n",
  5501. __FUNCTION__, priv->iw_mode);
  5502. break;
  5503. }
  5504. iwl3945_sequence_reset(priv);
  5505. iwl3945_activate_qos(priv, 0);
  5506. /* we have just associated, don't start scan too early */
  5507. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5508. mutex_unlock(&priv->mutex);
  5509. }
  5510. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5511. {
  5512. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5513. if (!iwl3945_is_ready(priv))
  5514. return;
  5515. mutex_lock(&priv->mutex);
  5516. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5517. iwl3945_send_scan_abort(priv);
  5518. mutex_unlock(&priv->mutex);
  5519. }
  5520. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
  5521. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5522. {
  5523. struct iwl3945_priv *priv =
  5524. container_of(work, struct iwl3945_priv, scan_completed);
  5525. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5526. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5527. return;
  5528. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5529. iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
  5530. ieee80211_scan_completed(priv->hw);
  5531. /* Since setting the TXPOWER may have been deferred while
  5532. * performing the scan, fire one off */
  5533. mutex_lock(&priv->mutex);
  5534. iwl3945_hw_reg_send_txpower(priv);
  5535. mutex_unlock(&priv->mutex);
  5536. }
  5537. /*****************************************************************************
  5538. *
  5539. * mac80211 entry point functions
  5540. *
  5541. *****************************************************************************/
  5542. #define UCODE_READY_TIMEOUT (2 * HZ)
  5543. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5544. {
  5545. struct iwl3945_priv *priv = hw->priv;
  5546. int ret;
  5547. IWL_DEBUG_MAC80211("enter\n");
  5548. if (pci_enable_device(priv->pci_dev)) {
  5549. IWL_ERROR("Fail to pci_enable_device\n");
  5550. return -ENODEV;
  5551. }
  5552. pci_restore_state(priv->pci_dev);
  5553. pci_enable_msi(priv->pci_dev);
  5554. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5555. DRV_NAME, priv);
  5556. if (ret) {
  5557. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5558. goto out_disable_msi;
  5559. }
  5560. /* we should be verifying the device is ready to be opened */
  5561. mutex_lock(&priv->mutex);
  5562. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5563. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5564. * ucode filename and max sizes are card-specific. */
  5565. if (!priv->ucode_code.len) {
  5566. ret = iwl3945_read_ucode(priv);
  5567. if (ret) {
  5568. IWL_ERROR("Could not read microcode: %d\n", ret);
  5569. mutex_unlock(&priv->mutex);
  5570. goto out_release_irq;
  5571. }
  5572. }
  5573. ret = __iwl3945_up(priv);
  5574. mutex_unlock(&priv->mutex);
  5575. if (ret)
  5576. goto out_release_irq;
  5577. IWL_DEBUG_INFO("Start UP work.\n");
  5578. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5579. return 0;
  5580. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5581. * mac80211 will not be run successfully. */
  5582. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5583. test_bit(STATUS_READY, &priv->status),
  5584. UCODE_READY_TIMEOUT);
  5585. if (!ret) {
  5586. if (!test_bit(STATUS_READY, &priv->status)) {
  5587. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5588. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5589. ret = -ETIMEDOUT;
  5590. goto out_release_irq;
  5591. }
  5592. }
  5593. priv->is_open = 1;
  5594. IWL_DEBUG_MAC80211("leave\n");
  5595. return 0;
  5596. out_release_irq:
  5597. free_irq(priv->pci_dev->irq, priv);
  5598. out_disable_msi:
  5599. pci_disable_msi(priv->pci_dev);
  5600. pci_disable_device(priv->pci_dev);
  5601. priv->is_open = 0;
  5602. IWL_DEBUG_MAC80211("leave - failed\n");
  5603. return ret;
  5604. }
  5605. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5606. {
  5607. struct iwl3945_priv *priv = hw->priv;
  5608. IWL_DEBUG_MAC80211("enter\n");
  5609. if (!priv->is_open) {
  5610. IWL_DEBUG_MAC80211("leave - skip\n");
  5611. return;
  5612. }
  5613. priv->is_open = 0;
  5614. if (iwl3945_is_ready_rf(priv)) {
  5615. /* stop mac, cancel any scan request and clear
  5616. * RXON_FILTER_ASSOC_MSK BIT
  5617. */
  5618. mutex_lock(&priv->mutex);
  5619. iwl3945_scan_cancel_timeout(priv, 100);
  5620. cancel_delayed_work(&priv->post_associate);
  5621. mutex_unlock(&priv->mutex);
  5622. }
  5623. iwl3945_down(priv);
  5624. flush_workqueue(priv->workqueue);
  5625. free_irq(priv->pci_dev->irq, priv);
  5626. pci_disable_msi(priv->pci_dev);
  5627. pci_save_state(priv->pci_dev);
  5628. pci_disable_device(priv->pci_dev);
  5629. IWL_DEBUG_MAC80211("leave\n");
  5630. }
  5631. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
  5632. struct ieee80211_tx_control *ctl)
  5633. {
  5634. struct iwl3945_priv *priv = hw->priv;
  5635. IWL_DEBUG_MAC80211("enter\n");
  5636. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  5637. IWL_DEBUG_MAC80211("leave - monitor\n");
  5638. return -1;
  5639. }
  5640. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5641. ctl->tx_rate->bitrate);
  5642. if (iwl3945_tx_skb(priv, skb, ctl))
  5643. dev_kfree_skb_any(skb);
  5644. IWL_DEBUG_MAC80211("leave\n");
  5645. return 0;
  5646. }
  5647. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5648. struct ieee80211_if_init_conf *conf)
  5649. {
  5650. struct iwl3945_priv *priv = hw->priv;
  5651. unsigned long flags;
  5652. DECLARE_MAC_BUF(mac);
  5653. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5654. if (priv->vif) {
  5655. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5656. return -EOPNOTSUPP;
  5657. }
  5658. spin_lock_irqsave(&priv->lock, flags);
  5659. priv->vif = conf->vif;
  5660. spin_unlock_irqrestore(&priv->lock, flags);
  5661. mutex_lock(&priv->mutex);
  5662. if (conf->mac_addr) {
  5663. IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
  5664. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5665. }
  5666. if (iwl3945_is_ready(priv))
  5667. iwl3945_set_mode(priv, conf->type);
  5668. mutex_unlock(&priv->mutex);
  5669. IWL_DEBUG_MAC80211("leave\n");
  5670. return 0;
  5671. }
  5672. /**
  5673. * iwl3945_mac_config - mac80211 config callback
  5674. *
  5675. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5676. * be set inappropriately and the driver currently sets the hardware up to
  5677. * use it whenever needed.
  5678. */
  5679. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  5680. {
  5681. struct iwl3945_priv *priv = hw->priv;
  5682. const struct iwl3945_channel_info *ch_info;
  5683. unsigned long flags;
  5684. int ret = 0;
  5685. mutex_lock(&priv->mutex);
  5686. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5687. priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
  5688. if (!iwl3945_is_ready(priv)) {
  5689. IWL_DEBUG_MAC80211("leave - not ready\n");
  5690. ret = -EIO;
  5691. goto out;
  5692. }
  5693. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5694. test_bit(STATUS_SCANNING, &priv->status))) {
  5695. IWL_DEBUG_MAC80211("leave - scanning\n");
  5696. set_bit(STATUS_CONF_PENDING, &priv->status);
  5697. mutex_unlock(&priv->mutex);
  5698. return 0;
  5699. }
  5700. spin_lock_irqsave(&priv->lock, flags);
  5701. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5702. conf->channel->hw_value);
  5703. if (!is_channel_valid(ch_info)) {
  5704. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
  5705. conf->channel->hw_value, conf->channel->band);
  5706. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5707. spin_unlock_irqrestore(&priv->lock, flags);
  5708. ret = -EINVAL;
  5709. goto out;
  5710. }
  5711. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5712. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5713. /* The list of supported rates and rate mask can be different
  5714. * for each phymode; since the phymode may have changed, reset
  5715. * the rate mask to what mac80211 lists */
  5716. iwl3945_set_rate(priv);
  5717. spin_unlock_irqrestore(&priv->lock, flags);
  5718. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5719. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5720. iwl3945_hw_channel_switch(priv, conf->channel);
  5721. goto out;
  5722. }
  5723. #endif
  5724. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5725. if (!conf->radio_enabled) {
  5726. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5727. goto out;
  5728. }
  5729. if (iwl3945_is_rfkill(priv)) {
  5730. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5731. ret = -EIO;
  5732. goto out;
  5733. }
  5734. iwl3945_set_rate(priv);
  5735. if (memcmp(&priv->active_rxon,
  5736. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5737. iwl3945_commit_rxon(priv);
  5738. else
  5739. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5740. IWL_DEBUG_MAC80211("leave\n");
  5741. out:
  5742. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5743. mutex_unlock(&priv->mutex);
  5744. return ret;
  5745. }
  5746. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5747. {
  5748. int rc = 0;
  5749. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5750. return;
  5751. /* The following should be done only at AP bring up */
  5752. if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
  5753. /* RXON - unassoc (to set timing command) */
  5754. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5755. iwl3945_commit_rxon(priv);
  5756. /* RXON Timing */
  5757. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5758. iwl3945_setup_rxon_timing(priv);
  5759. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5760. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5761. if (rc)
  5762. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5763. "Attempting to continue.\n");
  5764. /* FIXME: what should be the assoc_id for AP? */
  5765. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5766. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5767. priv->staging_rxon.flags |=
  5768. RXON_FLG_SHORT_PREAMBLE_MSK;
  5769. else
  5770. priv->staging_rxon.flags &=
  5771. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5772. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5773. if (priv->assoc_capability &
  5774. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5775. priv->staging_rxon.flags |=
  5776. RXON_FLG_SHORT_SLOT_MSK;
  5777. else
  5778. priv->staging_rxon.flags &=
  5779. ~RXON_FLG_SHORT_SLOT_MSK;
  5780. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5781. priv->staging_rxon.flags &=
  5782. ~RXON_FLG_SHORT_SLOT_MSK;
  5783. }
  5784. /* restore RXON assoc */
  5785. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5786. iwl3945_commit_rxon(priv);
  5787. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5788. }
  5789. iwl3945_send_beacon_cmd(priv);
  5790. /* FIXME - we need to add code here to detect a totally new
  5791. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5792. * clear sta table, add BCAST sta... */
  5793. }
  5794. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5795. struct ieee80211_vif *vif,
  5796. struct ieee80211_if_conf *conf)
  5797. {
  5798. struct iwl3945_priv *priv = hw->priv;
  5799. DECLARE_MAC_BUF(mac);
  5800. unsigned long flags;
  5801. int rc;
  5802. if (conf == NULL)
  5803. return -EIO;
  5804. if (priv->vif != vif) {
  5805. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5806. mutex_unlock(&priv->mutex);
  5807. return 0;
  5808. }
  5809. /* XXX: this MUST use conf->mac_addr */
  5810. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  5811. (!conf->beacon || !conf->ssid_len)) {
  5812. IWL_DEBUG_MAC80211
  5813. ("Leaving in AP mode because HostAPD is not ready.\n");
  5814. return 0;
  5815. }
  5816. if (!iwl3945_is_alive(priv))
  5817. return -EAGAIN;
  5818. mutex_lock(&priv->mutex);
  5819. if (conf->bssid)
  5820. IWL_DEBUG_MAC80211("bssid: %s\n",
  5821. print_mac(mac, conf->bssid));
  5822. /*
  5823. * very dubious code was here; the probe filtering flag is never set:
  5824. *
  5825. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5826. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5827. */
  5828. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5829. if (!conf->bssid) {
  5830. conf->bssid = priv->mac_addr;
  5831. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5832. IWL_DEBUG_MAC80211("bssid was set to: %s\n",
  5833. print_mac(mac, conf->bssid));
  5834. }
  5835. if (priv->ibss_beacon)
  5836. dev_kfree_skb(priv->ibss_beacon);
  5837. priv->ibss_beacon = conf->beacon;
  5838. }
  5839. if (iwl3945_is_rfkill(priv))
  5840. goto done;
  5841. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5842. !is_multicast_ether_addr(conf->bssid)) {
  5843. /* If there is currently a HW scan going on in the background
  5844. * then we need to cancel it else the RXON below will fail. */
  5845. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5846. IWL_WARNING("Aborted scan still in progress "
  5847. "after 100ms\n");
  5848. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5849. mutex_unlock(&priv->mutex);
  5850. return -EAGAIN;
  5851. }
  5852. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5853. /* TODO: Audit driver for usage of these members and see
  5854. * if mac80211 deprecates them (priv->bssid looks like it
  5855. * shouldn't be there, but I haven't scanned the IBSS code
  5856. * to verify) - jpk */
  5857. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5858. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  5859. iwl3945_config_ap(priv);
  5860. else {
  5861. rc = iwl3945_commit_rxon(priv);
  5862. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
  5863. iwl3945_add_station(priv,
  5864. priv->active_rxon.bssid_addr, 1, 0);
  5865. }
  5866. } else {
  5867. iwl3945_scan_cancel_timeout(priv, 100);
  5868. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5869. iwl3945_commit_rxon(priv);
  5870. }
  5871. done:
  5872. spin_lock_irqsave(&priv->lock, flags);
  5873. if (!conf->ssid_len)
  5874. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5875. else
  5876. memcpy(priv->essid, conf->ssid, conf->ssid_len);
  5877. priv->essid_len = conf->ssid_len;
  5878. spin_unlock_irqrestore(&priv->lock, flags);
  5879. IWL_DEBUG_MAC80211("leave\n");
  5880. mutex_unlock(&priv->mutex);
  5881. return 0;
  5882. }
  5883. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5884. unsigned int changed_flags,
  5885. unsigned int *total_flags,
  5886. int mc_count, struct dev_addr_list *mc_list)
  5887. {
  5888. /*
  5889. * XXX: dummy
  5890. * see also iwl3945_connection_init_rx_config
  5891. */
  5892. *total_flags = 0;
  5893. }
  5894. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5895. struct ieee80211_if_init_conf *conf)
  5896. {
  5897. struct iwl3945_priv *priv = hw->priv;
  5898. IWL_DEBUG_MAC80211("enter\n");
  5899. mutex_lock(&priv->mutex);
  5900. if (iwl3945_is_ready_rf(priv)) {
  5901. iwl3945_scan_cancel_timeout(priv, 100);
  5902. cancel_delayed_work(&priv->post_associate);
  5903. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5904. iwl3945_commit_rxon(priv);
  5905. }
  5906. if (priv->vif == conf->vif) {
  5907. priv->vif = NULL;
  5908. memset(priv->bssid, 0, ETH_ALEN);
  5909. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5910. priv->essid_len = 0;
  5911. }
  5912. mutex_unlock(&priv->mutex);
  5913. IWL_DEBUG_MAC80211("leave\n");
  5914. }
  5915. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5916. {
  5917. int rc = 0;
  5918. unsigned long flags;
  5919. struct iwl3945_priv *priv = hw->priv;
  5920. IWL_DEBUG_MAC80211("enter\n");
  5921. mutex_lock(&priv->mutex);
  5922. spin_lock_irqsave(&priv->lock, flags);
  5923. if (!iwl3945_is_ready_rf(priv)) {
  5924. rc = -EIO;
  5925. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5926. goto out_unlock;
  5927. }
  5928. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
  5929. rc = -EIO;
  5930. IWL_ERROR("ERROR: APs don't scan\n");
  5931. goto out_unlock;
  5932. }
  5933. /* we don't schedule scan within next_scan_jiffies period */
  5934. if (priv->next_scan_jiffies &&
  5935. time_after(priv->next_scan_jiffies, jiffies)) {
  5936. rc = -EAGAIN;
  5937. goto out_unlock;
  5938. }
  5939. /* if we just finished scan ask for delay */
  5940. if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
  5941. IWL_DELAY_NEXT_SCAN, jiffies)) {
  5942. rc = -EAGAIN;
  5943. goto out_unlock;
  5944. }
  5945. if (len) {
  5946. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5947. iwl3945_escape_essid(ssid, len), (int)len);
  5948. priv->one_direct_scan = 1;
  5949. priv->direct_ssid_len = (u8)
  5950. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5951. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5952. } else
  5953. priv->one_direct_scan = 0;
  5954. rc = iwl3945_scan_initiate(priv);
  5955. IWL_DEBUG_MAC80211("leave\n");
  5956. out_unlock:
  5957. spin_unlock_irqrestore(&priv->lock, flags);
  5958. mutex_unlock(&priv->mutex);
  5959. return rc;
  5960. }
  5961. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5962. const u8 *local_addr, const u8 *addr,
  5963. struct ieee80211_key_conf *key)
  5964. {
  5965. struct iwl3945_priv *priv = hw->priv;
  5966. int rc = 0;
  5967. u8 sta_id;
  5968. IWL_DEBUG_MAC80211("enter\n");
  5969. if (!iwl3945_param_hwcrypto) {
  5970. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5971. return -EOPNOTSUPP;
  5972. }
  5973. if (is_zero_ether_addr(addr))
  5974. /* only support pairwise keys */
  5975. return -EOPNOTSUPP;
  5976. sta_id = iwl3945_hw_find_station(priv, addr);
  5977. if (sta_id == IWL_INVALID_STATION) {
  5978. DECLARE_MAC_BUF(mac);
  5979. IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
  5980. print_mac(mac, addr));
  5981. return -EINVAL;
  5982. }
  5983. mutex_lock(&priv->mutex);
  5984. iwl3945_scan_cancel_timeout(priv, 100);
  5985. switch (cmd) {
  5986. case SET_KEY:
  5987. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5988. if (!rc) {
  5989. iwl3945_set_rxon_hwcrypto(priv, 1);
  5990. iwl3945_commit_rxon(priv);
  5991. key->hw_key_idx = sta_id;
  5992. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5993. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5994. }
  5995. break;
  5996. case DISABLE_KEY:
  5997. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5998. if (!rc) {
  5999. iwl3945_set_rxon_hwcrypto(priv, 0);
  6000. iwl3945_commit_rxon(priv);
  6001. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  6002. }
  6003. break;
  6004. default:
  6005. rc = -EINVAL;
  6006. }
  6007. IWL_DEBUG_MAC80211("leave\n");
  6008. mutex_unlock(&priv->mutex);
  6009. return rc;
  6010. }
  6011. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue,
  6012. const struct ieee80211_tx_queue_params *params)
  6013. {
  6014. struct iwl3945_priv *priv = hw->priv;
  6015. unsigned long flags;
  6016. int q;
  6017. IWL_DEBUG_MAC80211("enter\n");
  6018. if (!iwl3945_is_ready_rf(priv)) {
  6019. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6020. return -EIO;
  6021. }
  6022. if (queue >= AC_NUM) {
  6023. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  6024. return 0;
  6025. }
  6026. if (!priv->qos_data.qos_enable) {
  6027. priv->qos_data.qos_active = 0;
  6028. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  6029. return 0;
  6030. }
  6031. q = AC_NUM - 1 - queue;
  6032. spin_lock_irqsave(&priv->lock, flags);
  6033. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  6034. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  6035. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  6036. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  6037. cpu_to_le16((params->txop * 32));
  6038. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  6039. priv->qos_data.qos_active = 1;
  6040. spin_unlock_irqrestore(&priv->lock, flags);
  6041. mutex_lock(&priv->mutex);
  6042. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  6043. iwl3945_activate_qos(priv, 1);
  6044. else if (priv->assoc_id && iwl3945_is_associated(priv))
  6045. iwl3945_activate_qos(priv, 0);
  6046. mutex_unlock(&priv->mutex);
  6047. IWL_DEBUG_MAC80211("leave\n");
  6048. return 0;
  6049. }
  6050. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  6051. struct ieee80211_tx_queue_stats *stats)
  6052. {
  6053. struct iwl3945_priv *priv = hw->priv;
  6054. int i, avail;
  6055. struct iwl3945_tx_queue *txq;
  6056. struct iwl3945_queue *q;
  6057. unsigned long flags;
  6058. IWL_DEBUG_MAC80211("enter\n");
  6059. if (!iwl3945_is_ready_rf(priv)) {
  6060. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6061. return -EIO;
  6062. }
  6063. spin_lock_irqsave(&priv->lock, flags);
  6064. for (i = 0; i < AC_NUM; i++) {
  6065. txq = &priv->txq[i];
  6066. q = &txq->q;
  6067. avail = iwl3945_queue_space(q);
  6068. stats->data[i].len = q->n_window - avail;
  6069. stats->data[i].limit = q->n_window - q->high_mark;
  6070. stats->data[i].count = q->n_window;
  6071. }
  6072. spin_unlock_irqrestore(&priv->lock, flags);
  6073. IWL_DEBUG_MAC80211("leave\n");
  6074. return 0;
  6075. }
  6076. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  6077. struct ieee80211_low_level_stats *stats)
  6078. {
  6079. IWL_DEBUG_MAC80211("enter\n");
  6080. IWL_DEBUG_MAC80211("leave\n");
  6081. return 0;
  6082. }
  6083. static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
  6084. {
  6085. IWL_DEBUG_MAC80211("enter\n");
  6086. IWL_DEBUG_MAC80211("leave\n");
  6087. return 0;
  6088. }
  6089. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  6090. {
  6091. struct iwl3945_priv *priv = hw->priv;
  6092. unsigned long flags;
  6093. mutex_lock(&priv->mutex);
  6094. IWL_DEBUG_MAC80211("enter\n");
  6095. iwl3945_reset_qos(priv);
  6096. cancel_delayed_work(&priv->post_associate);
  6097. spin_lock_irqsave(&priv->lock, flags);
  6098. priv->assoc_id = 0;
  6099. priv->assoc_capability = 0;
  6100. priv->call_post_assoc_from_beacon = 0;
  6101. /* new association get rid of ibss beacon skb */
  6102. if (priv->ibss_beacon)
  6103. dev_kfree_skb(priv->ibss_beacon);
  6104. priv->ibss_beacon = NULL;
  6105. priv->beacon_int = priv->hw->conf.beacon_int;
  6106. priv->timestamp1 = 0;
  6107. priv->timestamp0 = 0;
  6108. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
  6109. priv->beacon_int = 0;
  6110. spin_unlock_irqrestore(&priv->lock, flags);
  6111. if (!iwl3945_is_ready_rf(priv)) {
  6112. IWL_DEBUG_MAC80211("leave - not ready\n");
  6113. mutex_unlock(&priv->mutex);
  6114. return;
  6115. }
  6116. /* we are restarting association process
  6117. * clear RXON_FILTER_ASSOC_MSK bit
  6118. */
  6119. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  6120. iwl3945_scan_cancel_timeout(priv, 100);
  6121. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6122. iwl3945_commit_rxon(priv);
  6123. }
  6124. /* Per mac80211.h: This is only used in IBSS mode... */
  6125. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6126. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  6127. mutex_unlock(&priv->mutex);
  6128. return;
  6129. }
  6130. priv->only_active_channel = 0;
  6131. iwl3945_set_rate(priv);
  6132. mutex_unlock(&priv->mutex);
  6133. IWL_DEBUG_MAC80211("leave\n");
  6134. }
  6135. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
  6136. struct ieee80211_tx_control *control)
  6137. {
  6138. struct iwl3945_priv *priv = hw->priv;
  6139. unsigned long flags;
  6140. mutex_lock(&priv->mutex);
  6141. IWL_DEBUG_MAC80211("enter\n");
  6142. if (!iwl3945_is_ready_rf(priv)) {
  6143. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6144. mutex_unlock(&priv->mutex);
  6145. return -EIO;
  6146. }
  6147. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6148. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  6149. mutex_unlock(&priv->mutex);
  6150. return -EIO;
  6151. }
  6152. spin_lock_irqsave(&priv->lock, flags);
  6153. if (priv->ibss_beacon)
  6154. dev_kfree_skb(priv->ibss_beacon);
  6155. priv->ibss_beacon = skb;
  6156. priv->assoc_id = 0;
  6157. IWL_DEBUG_MAC80211("leave\n");
  6158. spin_unlock_irqrestore(&priv->lock, flags);
  6159. iwl3945_reset_qos(priv);
  6160. queue_work(priv->workqueue, &priv->post_associate.work);
  6161. mutex_unlock(&priv->mutex);
  6162. return 0;
  6163. }
  6164. /*****************************************************************************
  6165. *
  6166. * sysfs attributes
  6167. *
  6168. *****************************************************************************/
  6169. #ifdef CONFIG_IWL3945_DEBUG
  6170. /*
  6171. * The following adds a new attribute to the sysfs representation
  6172. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6173. * used for controlling the debug level.
  6174. *
  6175. * See the level definitions in iwl for details.
  6176. */
  6177. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6178. {
  6179. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6180. }
  6181. static ssize_t store_debug_level(struct device_driver *d,
  6182. const char *buf, size_t count)
  6183. {
  6184. char *p = (char *)buf;
  6185. u32 val;
  6186. val = simple_strtoul(p, &p, 0);
  6187. if (p == buf)
  6188. printk(KERN_INFO DRV_NAME
  6189. ": %s is not in hex or decimal form.\n", buf);
  6190. else
  6191. iwl3945_debug_level = val;
  6192. return strnlen(buf, count);
  6193. }
  6194. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6195. show_debug_level, store_debug_level);
  6196. #endif /* CONFIG_IWL3945_DEBUG */
  6197. static ssize_t show_rf_kill(struct device *d,
  6198. struct device_attribute *attr, char *buf)
  6199. {
  6200. /*
  6201. * 0 - RF kill not enabled
  6202. * 1 - SW based RF kill active (sysfs)
  6203. * 2 - HW based RF kill active
  6204. * 3 - Both HW and SW based RF kill active
  6205. */
  6206. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6207. int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
  6208. (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
  6209. return sprintf(buf, "%i\n", val);
  6210. }
  6211. static ssize_t store_rf_kill(struct device *d,
  6212. struct device_attribute *attr,
  6213. const char *buf, size_t count)
  6214. {
  6215. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6216. mutex_lock(&priv->mutex);
  6217. iwl3945_radio_kill_sw(priv, buf[0] == '1');
  6218. mutex_unlock(&priv->mutex);
  6219. return count;
  6220. }
  6221. static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
  6222. static ssize_t show_temperature(struct device *d,
  6223. struct device_attribute *attr, char *buf)
  6224. {
  6225. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6226. if (!iwl3945_is_alive(priv))
  6227. return -EAGAIN;
  6228. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6229. }
  6230. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6231. static ssize_t show_rs_window(struct device *d,
  6232. struct device_attribute *attr,
  6233. char *buf)
  6234. {
  6235. struct iwl3945_priv *priv = d->driver_data;
  6236. return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
  6237. }
  6238. static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
  6239. static ssize_t show_tx_power(struct device *d,
  6240. struct device_attribute *attr, char *buf)
  6241. {
  6242. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6243. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6244. }
  6245. static ssize_t store_tx_power(struct device *d,
  6246. struct device_attribute *attr,
  6247. const char *buf, size_t count)
  6248. {
  6249. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6250. char *p = (char *)buf;
  6251. u32 val;
  6252. val = simple_strtoul(p, &p, 10);
  6253. if (p == buf)
  6254. printk(KERN_INFO DRV_NAME
  6255. ": %s is not in decimal form.\n", buf);
  6256. else
  6257. iwl3945_hw_reg_set_txpower(priv, val);
  6258. return count;
  6259. }
  6260. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6261. static ssize_t show_flags(struct device *d,
  6262. struct device_attribute *attr, char *buf)
  6263. {
  6264. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6265. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6266. }
  6267. static ssize_t store_flags(struct device *d,
  6268. struct device_attribute *attr,
  6269. const char *buf, size_t count)
  6270. {
  6271. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6272. u32 flags = simple_strtoul(buf, NULL, 0);
  6273. mutex_lock(&priv->mutex);
  6274. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6275. /* Cancel any currently running scans... */
  6276. if (iwl3945_scan_cancel_timeout(priv, 100))
  6277. IWL_WARNING("Could not cancel scan.\n");
  6278. else {
  6279. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6280. flags);
  6281. priv->staging_rxon.flags = cpu_to_le32(flags);
  6282. iwl3945_commit_rxon(priv);
  6283. }
  6284. }
  6285. mutex_unlock(&priv->mutex);
  6286. return count;
  6287. }
  6288. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6289. static ssize_t show_filter_flags(struct device *d,
  6290. struct device_attribute *attr, char *buf)
  6291. {
  6292. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6293. return sprintf(buf, "0x%04X\n",
  6294. le32_to_cpu(priv->active_rxon.filter_flags));
  6295. }
  6296. static ssize_t store_filter_flags(struct device *d,
  6297. struct device_attribute *attr,
  6298. const char *buf, size_t count)
  6299. {
  6300. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6301. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6302. mutex_lock(&priv->mutex);
  6303. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6304. /* Cancel any currently running scans... */
  6305. if (iwl3945_scan_cancel_timeout(priv, 100))
  6306. IWL_WARNING("Could not cancel scan.\n");
  6307. else {
  6308. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6309. "0x%04X\n", filter_flags);
  6310. priv->staging_rxon.filter_flags =
  6311. cpu_to_le32(filter_flags);
  6312. iwl3945_commit_rxon(priv);
  6313. }
  6314. }
  6315. mutex_unlock(&priv->mutex);
  6316. return count;
  6317. }
  6318. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6319. store_filter_flags);
  6320. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6321. static ssize_t show_measurement(struct device *d,
  6322. struct device_attribute *attr, char *buf)
  6323. {
  6324. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6325. struct iwl3945_spectrum_notification measure_report;
  6326. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6327. u8 *data = (u8 *) & measure_report;
  6328. unsigned long flags;
  6329. spin_lock_irqsave(&priv->lock, flags);
  6330. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6331. spin_unlock_irqrestore(&priv->lock, flags);
  6332. return 0;
  6333. }
  6334. memcpy(&measure_report, &priv->measure_report, size);
  6335. priv->measurement_status = 0;
  6336. spin_unlock_irqrestore(&priv->lock, flags);
  6337. while (size && (PAGE_SIZE - len)) {
  6338. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6339. PAGE_SIZE - len, 1);
  6340. len = strlen(buf);
  6341. if (PAGE_SIZE - len)
  6342. buf[len++] = '\n';
  6343. ofs += 16;
  6344. size -= min(size, 16U);
  6345. }
  6346. return len;
  6347. }
  6348. static ssize_t store_measurement(struct device *d,
  6349. struct device_attribute *attr,
  6350. const char *buf, size_t count)
  6351. {
  6352. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6353. struct ieee80211_measurement_params params = {
  6354. .channel = le16_to_cpu(priv->active_rxon.channel),
  6355. .start_time = cpu_to_le64(priv->last_tsf),
  6356. .duration = cpu_to_le16(1),
  6357. };
  6358. u8 type = IWL_MEASURE_BASIC;
  6359. u8 buffer[32];
  6360. u8 channel;
  6361. if (count) {
  6362. char *p = buffer;
  6363. strncpy(buffer, buf, min(sizeof(buffer), count));
  6364. channel = simple_strtoul(p, NULL, 0);
  6365. if (channel)
  6366. params.channel = channel;
  6367. p = buffer;
  6368. while (*p && *p != ' ')
  6369. p++;
  6370. if (*p)
  6371. type = simple_strtoul(p + 1, NULL, 0);
  6372. }
  6373. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6374. "channel %d (for '%s')\n", type, params.channel, buf);
  6375. iwl3945_get_measurement(priv, &params, type);
  6376. return count;
  6377. }
  6378. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6379. show_measurement, store_measurement);
  6380. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6381. static ssize_t store_retry_rate(struct device *d,
  6382. struct device_attribute *attr,
  6383. const char *buf, size_t count)
  6384. {
  6385. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6386. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6387. if (priv->retry_rate <= 0)
  6388. priv->retry_rate = 1;
  6389. return count;
  6390. }
  6391. static ssize_t show_retry_rate(struct device *d,
  6392. struct device_attribute *attr, char *buf)
  6393. {
  6394. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6395. return sprintf(buf, "%d", priv->retry_rate);
  6396. }
  6397. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6398. store_retry_rate);
  6399. static ssize_t store_power_level(struct device *d,
  6400. struct device_attribute *attr,
  6401. const char *buf, size_t count)
  6402. {
  6403. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6404. int rc;
  6405. int mode;
  6406. mode = simple_strtoul(buf, NULL, 0);
  6407. mutex_lock(&priv->mutex);
  6408. if (!iwl3945_is_ready(priv)) {
  6409. rc = -EAGAIN;
  6410. goto out;
  6411. }
  6412. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6413. mode = IWL_POWER_AC;
  6414. else
  6415. mode |= IWL_POWER_ENABLED;
  6416. if (mode != priv->power_mode) {
  6417. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6418. if (rc) {
  6419. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6420. goto out;
  6421. }
  6422. priv->power_mode = mode;
  6423. }
  6424. rc = count;
  6425. out:
  6426. mutex_unlock(&priv->mutex);
  6427. return rc;
  6428. }
  6429. #define MAX_WX_STRING 80
  6430. /* Values are in microsecond */
  6431. static const s32 timeout_duration[] = {
  6432. 350000,
  6433. 250000,
  6434. 75000,
  6435. 37000,
  6436. 25000,
  6437. };
  6438. static const s32 period_duration[] = {
  6439. 400000,
  6440. 700000,
  6441. 1000000,
  6442. 1000000,
  6443. 1000000
  6444. };
  6445. static ssize_t show_power_level(struct device *d,
  6446. struct device_attribute *attr, char *buf)
  6447. {
  6448. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6449. int level = IWL_POWER_LEVEL(priv->power_mode);
  6450. char *p = buf;
  6451. p += sprintf(p, "%d ", level);
  6452. switch (level) {
  6453. case IWL_POWER_MODE_CAM:
  6454. case IWL_POWER_AC:
  6455. p += sprintf(p, "(AC)");
  6456. break;
  6457. case IWL_POWER_BATTERY:
  6458. p += sprintf(p, "(BATTERY)");
  6459. break;
  6460. default:
  6461. p += sprintf(p,
  6462. "(Timeout %dms, Period %dms)",
  6463. timeout_duration[level - 1] / 1000,
  6464. period_duration[level - 1] / 1000);
  6465. }
  6466. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6467. p += sprintf(p, " OFF\n");
  6468. else
  6469. p += sprintf(p, " \n");
  6470. return (p - buf + 1);
  6471. }
  6472. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6473. store_power_level);
  6474. static ssize_t show_channels(struct device *d,
  6475. struct device_attribute *attr, char *buf)
  6476. {
  6477. /* all this shit doesn't belong into sysfs anyway */
  6478. return 0;
  6479. }
  6480. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6481. static ssize_t show_statistics(struct device *d,
  6482. struct device_attribute *attr, char *buf)
  6483. {
  6484. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6485. u32 size = sizeof(struct iwl3945_notif_statistics);
  6486. u32 len = 0, ofs = 0;
  6487. u8 *data = (u8 *) & priv->statistics;
  6488. int rc = 0;
  6489. if (!iwl3945_is_alive(priv))
  6490. return -EAGAIN;
  6491. mutex_lock(&priv->mutex);
  6492. rc = iwl3945_send_statistics_request(priv);
  6493. mutex_unlock(&priv->mutex);
  6494. if (rc) {
  6495. len = sprintf(buf,
  6496. "Error sending statistics request: 0x%08X\n", rc);
  6497. return len;
  6498. }
  6499. while (size && (PAGE_SIZE - len)) {
  6500. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6501. PAGE_SIZE - len, 1);
  6502. len = strlen(buf);
  6503. if (PAGE_SIZE - len)
  6504. buf[len++] = '\n';
  6505. ofs += 16;
  6506. size -= min(size, 16U);
  6507. }
  6508. return len;
  6509. }
  6510. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6511. static ssize_t show_antenna(struct device *d,
  6512. struct device_attribute *attr, char *buf)
  6513. {
  6514. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6515. if (!iwl3945_is_alive(priv))
  6516. return -EAGAIN;
  6517. return sprintf(buf, "%d\n", priv->antenna);
  6518. }
  6519. static ssize_t store_antenna(struct device *d,
  6520. struct device_attribute *attr,
  6521. const char *buf, size_t count)
  6522. {
  6523. int ant;
  6524. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6525. if (count == 0)
  6526. return 0;
  6527. if (sscanf(buf, "%1i", &ant) != 1) {
  6528. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6529. return count;
  6530. }
  6531. if ((ant >= 0) && (ant <= 2)) {
  6532. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6533. priv->antenna = (enum iwl3945_antenna)ant;
  6534. } else
  6535. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6536. return count;
  6537. }
  6538. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6539. static ssize_t show_status(struct device *d,
  6540. struct device_attribute *attr, char *buf)
  6541. {
  6542. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6543. if (!iwl3945_is_alive(priv))
  6544. return -EAGAIN;
  6545. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6546. }
  6547. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6548. static ssize_t dump_error_log(struct device *d,
  6549. struct device_attribute *attr,
  6550. const char *buf, size_t count)
  6551. {
  6552. char *p = (char *)buf;
  6553. if (p[0] == '1')
  6554. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6555. return strnlen(buf, count);
  6556. }
  6557. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6558. static ssize_t dump_event_log(struct device *d,
  6559. struct device_attribute *attr,
  6560. const char *buf, size_t count)
  6561. {
  6562. char *p = (char *)buf;
  6563. if (p[0] == '1')
  6564. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6565. return strnlen(buf, count);
  6566. }
  6567. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6568. /*****************************************************************************
  6569. *
  6570. * driver setup and teardown
  6571. *
  6572. *****************************************************************************/
  6573. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6574. {
  6575. priv->workqueue = create_workqueue(DRV_NAME);
  6576. init_waitqueue_head(&priv->wait_command_queue);
  6577. INIT_WORK(&priv->up, iwl3945_bg_up);
  6578. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6579. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6580. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6581. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6582. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6583. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6584. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6585. INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
  6586. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6587. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6588. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6589. iwl3945_hw_setup_deferred_work(priv);
  6590. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6591. iwl3945_irq_tasklet, (unsigned long)priv);
  6592. }
  6593. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6594. {
  6595. iwl3945_hw_cancel_deferred_work(priv);
  6596. cancel_delayed_work_sync(&priv->init_alive_start);
  6597. cancel_delayed_work(&priv->scan_check);
  6598. cancel_delayed_work(&priv->alive_start);
  6599. cancel_delayed_work(&priv->post_associate);
  6600. cancel_work_sync(&priv->beacon_update);
  6601. }
  6602. static struct attribute *iwl3945_sysfs_entries[] = {
  6603. &dev_attr_antenna.attr,
  6604. &dev_attr_channels.attr,
  6605. &dev_attr_dump_errors.attr,
  6606. &dev_attr_dump_events.attr,
  6607. &dev_attr_flags.attr,
  6608. &dev_attr_filter_flags.attr,
  6609. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6610. &dev_attr_measurement.attr,
  6611. #endif
  6612. &dev_attr_power_level.attr,
  6613. &dev_attr_retry_rate.attr,
  6614. &dev_attr_rf_kill.attr,
  6615. &dev_attr_rs_window.attr,
  6616. &dev_attr_statistics.attr,
  6617. &dev_attr_status.attr,
  6618. &dev_attr_temperature.attr,
  6619. &dev_attr_tx_power.attr,
  6620. NULL
  6621. };
  6622. static struct attribute_group iwl3945_attribute_group = {
  6623. .name = NULL, /* put in device directory */
  6624. .attrs = iwl3945_sysfs_entries,
  6625. };
  6626. static struct ieee80211_ops iwl3945_hw_ops = {
  6627. .tx = iwl3945_mac_tx,
  6628. .start = iwl3945_mac_start,
  6629. .stop = iwl3945_mac_stop,
  6630. .add_interface = iwl3945_mac_add_interface,
  6631. .remove_interface = iwl3945_mac_remove_interface,
  6632. .config = iwl3945_mac_config,
  6633. .config_interface = iwl3945_mac_config_interface,
  6634. .configure_filter = iwl3945_configure_filter,
  6635. .set_key = iwl3945_mac_set_key,
  6636. .get_stats = iwl3945_mac_get_stats,
  6637. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6638. .conf_tx = iwl3945_mac_conf_tx,
  6639. .get_tsf = iwl3945_mac_get_tsf,
  6640. .reset_tsf = iwl3945_mac_reset_tsf,
  6641. .beacon_update = iwl3945_mac_beacon_update,
  6642. .hw_scan = iwl3945_mac_hw_scan
  6643. };
  6644. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6645. {
  6646. int err = 0;
  6647. struct iwl3945_priv *priv;
  6648. struct ieee80211_hw *hw;
  6649. struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
  6650. int i;
  6651. DECLARE_MAC_BUF(mac);
  6652. /* Disabling hardware scan means that mac80211 will perform scans
  6653. * "the hard way", rather than using device's scan. */
  6654. if (iwl3945_param_disable_hw_scan) {
  6655. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6656. iwl3945_hw_ops.hw_scan = NULL;
  6657. }
  6658. if ((iwl3945_param_queues_num > IWL_MAX_NUM_QUEUES) ||
  6659. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6660. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6661. IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
  6662. err = -EINVAL;
  6663. goto out;
  6664. }
  6665. /* mac80211 allocates memory for this device instance, including
  6666. * space for this driver's private structure */
  6667. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6668. if (hw == NULL) {
  6669. IWL_ERROR("Can not allocate network device\n");
  6670. err = -ENOMEM;
  6671. goto out;
  6672. }
  6673. SET_IEEE80211_DEV(hw, &pdev->dev);
  6674. hw->rate_control_algorithm = "iwl-3945-rs";
  6675. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6676. priv = hw->priv;
  6677. priv->hw = hw;
  6678. priv->pci_dev = pdev;
  6679. priv->cfg = cfg;
  6680. /* Select antenna (may be helpful if only one antenna is connected) */
  6681. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6682. #ifdef CONFIG_IWL3945_DEBUG
  6683. iwl3945_debug_level = iwl3945_param_debug;
  6684. atomic_set(&priv->restrict_refcnt, 0);
  6685. #endif
  6686. priv->retry_rate = 1;
  6687. priv->ibss_beacon = NULL;
  6688. /* Tell mac80211 and its clients (e.g. Wireless Extensions)
  6689. * the range of signal quality values that we'll provide.
  6690. * Negative values for level/noise indicate that we'll provide dBm.
  6691. * For WE, at least, non-0 values here *enable* display of values
  6692. * in app (iwconfig). */
  6693. hw->max_rssi = -20; /* signal level, negative indicates dBm */
  6694. hw->max_noise = -20; /* noise level, negative indicates dBm */
  6695. hw->max_signal = 100; /* link quality indication (%) */
  6696. /* Tell mac80211 our Tx characteristics */
  6697. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
  6698. /* 4 EDCA QOS priorities */
  6699. hw->queues = 4;
  6700. spin_lock_init(&priv->lock);
  6701. spin_lock_init(&priv->power_data.lock);
  6702. spin_lock_init(&priv->sta_lock);
  6703. spin_lock_init(&priv->hcmd_lock);
  6704. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
  6705. INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
  6706. INIT_LIST_HEAD(&priv->free_frames);
  6707. mutex_init(&priv->mutex);
  6708. if (pci_enable_device(pdev)) {
  6709. err = -ENODEV;
  6710. goto out_ieee80211_free_hw;
  6711. }
  6712. pci_set_master(pdev);
  6713. /* Clear the driver's (not device's) station table */
  6714. iwl3945_clear_stations_table(priv);
  6715. priv->data_retry_limit = -1;
  6716. priv->ieee_channels = NULL;
  6717. priv->ieee_rates = NULL;
  6718. priv->band = IEEE80211_BAND_2GHZ;
  6719. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6720. if (!err)
  6721. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6722. if (err) {
  6723. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6724. goto out_pci_disable_device;
  6725. }
  6726. pci_set_drvdata(pdev, priv);
  6727. err = pci_request_regions(pdev, DRV_NAME);
  6728. if (err)
  6729. goto out_pci_disable_device;
  6730. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6731. * PCI Tx retries from interfering with C3 CPU state */
  6732. pci_write_config_byte(pdev, 0x41, 0x00);
  6733. priv->hw_base = pci_iomap(pdev, 0, 0);
  6734. if (!priv->hw_base) {
  6735. err = -ENODEV;
  6736. goto out_pci_release_regions;
  6737. }
  6738. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6739. (unsigned long long) pci_resource_len(pdev, 0));
  6740. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6741. /* Initialize module parameter values here */
  6742. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6743. if (iwl3945_param_disable) {
  6744. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6745. IWL_DEBUG_INFO("Radio disabled.\n");
  6746. }
  6747. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  6748. printk(KERN_INFO DRV_NAME
  6749. ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
  6750. /* Device-specific setup */
  6751. if (iwl3945_hw_set_hw_setting(priv)) {
  6752. IWL_ERROR("failed to set hw settings\n");
  6753. goto out_iounmap;
  6754. }
  6755. if (iwl3945_param_qos_enable)
  6756. priv->qos_data.qos_enable = 1;
  6757. iwl3945_reset_qos(priv);
  6758. priv->qos_data.qos_active = 0;
  6759. priv->qos_data.qos_cap.val = 0;
  6760. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6761. iwl3945_setup_deferred_work(priv);
  6762. iwl3945_setup_rx_handlers(priv);
  6763. priv->rates_mask = IWL_RATES_MASK;
  6764. /* If power management is turned on, default to AC mode */
  6765. priv->power_mode = IWL_POWER_AC;
  6766. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6767. iwl3945_disable_interrupts(priv);
  6768. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6769. if (err) {
  6770. IWL_ERROR("failed to create sysfs device attributes\n");
  6771. goto out_release_irq;
  6772. }
  6773. /* nic init */
  6774. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6775. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6776. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6777. err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
  6778. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  6779. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6780. if (err < 0) {
  6781. IWL_DEBUG_INFO("Failed to init the card\n");
  6782. goto out_remove_sysfs;
  6783. }
  6784. /* Read the EEPROM */
  6785. err = iwl3945_eeprom_init(priv);
  6786. if (err) {
  6787. IWL_ERROR("Unable to init EEPROM\n");
  6788. goto out_remove_sysfs;
  6789. }
  6790. /* MAC Address location in EEPROM same for 3945/4965 */
  6791. get_eeprom_mac(priv, priv->mac_addr);
  6792. IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
  6793. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6794. err = iwl3945_init_channel_map(priv);
  6795. if (err) {
  6796. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6797. goto out_remove_sysfs;
  6798. }
  6799. err = iwl3945_init_geos(priv);
  6800. if (err) {
  6801. IWL_ERROR("initializing geos failed: %d\n", err);
  6802. goto out_free_channel_map;
  6803. }
  6804. iwl3945_rate_control_register(priv->hw);
  6805. err = ieee80211_register_hw(priv->hw);
  6806. if (err) {
  6807. IWL_ERROR("Failed to register network device (error %d)\n", err);
  6808. goto out_free_geos;
  6809. }
  6810. priv->hw->conf.beacon_int = 100;
  6811. priv->mac80211_registered = 1;
  6812. pci_save_state(pdev);
  6813. pci_disable_device(pdev);
  6814. return 0;
  6815. out_free_geos:
  6816. iwl3945_free_geos(priv);
  6817. out_free_channel_map:
  6818. iwl3945_free_channel_map(priv);
  6819. out_remove_sysfs:
  6820. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6821. out_release_irq:
  6822. destroy_workqueue(priv->workqueue);
  6823. priv->workqueue = NULL;
  6824. iwl3945_unset_hw_setting(priv);
  6825. out_iounmap:
  6826. pci_iounmap(pdev, priv->hw_base);
  6827. out_pci_release_regions:
  6828. pci_release_regions(pdev);
  6829. out_pci_disable_device:
  6830. pci_disable_device(pdev);
  6831. pci_set_drvdata(pdev, NULL);
  6832. out_ieee80211_free_hw:
  6833. ieee80211_free_hw(priv->hw);
  6834. out:
  6835. return err;
  6836. }
  6837. static void iwl3945_pci_remove(struct pci_dev *pdev)
  6838. {
  6839. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6840. struct list_head *p, *q;
  6841. int i;
  6842. if (!priv)
  6843. return;
  6844. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6845. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6846. iwl3945_down(priv);
  6847. /* Free MAC hash list for ADHOC */
  6848. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
  6849. list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
  6850. list_del(p);
  6851. kfree(list_entry(p, struct iwl3945_ibss_seq, list));
  6852. }
  6853. }
  6854. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6855. iwl3945_dealloc_ucode_pci(priv);
  6856. if (priv->rxq.bd)
  6857. iwl3945_rx_queue_free(priv, &priv->rxq);
  6858. iwl3945_hw_txq_ctx_free(priv);
  6859. iwl3945_unset_hw_setting(priv);
  6860. iwl3945_clear_stations_table(priv);
  6861. if (priv->mac80211_registered) {
  6862. ieee80211_unregister_hw(priv->hw);
  6863. iwl3945_rate_control_unregister(priv->hw);
  6864. }
  6865. /*netif_stop_queue(dev); */
  6866. flush_workqueue(priv->workqueue);
  6867. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6868. * priv->workqueue... so we can't take down the workqueue
  6869. * until now... */
  6870. destroy_workqueue(priv->workqueue);
  6871. priv->workqueue = NULL;
  6872. pci_iounmap(pdev, priv->hw_base);
  6873. pci_release_regions(pdev);
  6874. pci_disable_device(pdev);
  6875. pci_set_drvdata(pdev, NULL);
  6876. iwl3945_free_channel_map(priv);
  6877. iwl3945_free_geos(priv);
  6878. if (priv->ibss_beacon)
  6879. dev_kfree_skb(priv->ibss_beacon);
  6880. ieee80211_free_hw(priv->hw);
  6881. }
  6882. #ifdef CONFIG_PM
  6883. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6884. {
  6885. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6886. if (priv->is_open) {
  6887. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6888. iwl3945_mac_stop(priv->hw);
  6889. priv->is_open = 1;
  6890. }
  6891. pci_set_power_state(pdev, PCI_D3hot);
  6892. return 0;
  6893. }
  6894. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6895. {
  6896. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6897. pci_set_power_state(pdev, PCI_D0);
  6898. if (priv->is_open)
  6899. iwl3945_mac_start(priv->hw);
  6900. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6901. return 0;
  6902. }
  6903. #endif /* CONFIG_PM */
  6904. /*****************************************************************************
  6905. *
  6906. * driver and module entry point
  6907. *
  6908. *****************************************************************************/
  6909. static struct pci_driver iwl3945_driver = {
  6910. .name = DRV_NAME,
  6911. .id_table = iwl3945_hw_card_ids,
  6912. .probe = iwl3945_pci_probe,
  6913. .remove = __devexit_p(iwl3945_pci_remove),
  6914. #ifdef CONFIG_PM
  6915. .suspend = iwl3945_pci_suspend,
  6916. .resume = iwl3945_pci_resume,
  6917. #endif
  6918. };
  6919. static int __init iwl3945_init(void)
  6920. {
  6921. int ret;
  6922. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6923. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6924. ret = pci_register_driver(&iwl3945_driver);
  6925. if (ret) {
  6926. IWL_ERROR("Unable to initialize PCI module\n");
  6927. return ret;
  6928. }
  6929. #ifdef CONFIG_IWL3945_DEBUG
  6930. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6931. if (ret) {
  6932. IWL_ERROR("Unable to create driver sysfs file\n");
  6933. pci_unregister_driver(&iwl3945_driver);
  6934. return ret;
  6935. }
  6936. #endif
  6937. return ret;
  6938. }
  6939. static void __exit iwl3945_exit(void)
  6940. {
  6941. #ifdef CONFIG_IWL3945_DEBUG
  6942. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6943. #endif
  6944. pci_unregister_driver(&iwl3945_driver);
  6945. }
  6946. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  6947. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6948. module_param_named(disable, iwl3945_param_disable, int, 0444);
  6949. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6950. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  6951. MODULE_PARM_DESC(hwcrypto,
  6952. "using hardware crypto engine (default 0 [software])\n");
  6953. module_param_named(debug, iwl3945_param_debug, int, 0444);
  6954. MODULE_PARM_DESC(debug, "debug output mask");
  6955. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  6956. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6957. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  6958. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6959. /* QoS */
  6960. module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
  6961. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  6962. module_exit(iwl3945_exit);
  6963. module_init(iwl3945_init);