paging_tmpl.h 15 KB

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  1. /*
  2. * Kernel-based Virtual Machine driver for Linux
  3. *
  4. * This module enables machines with Intel VT-x extensions to run virtual
  5. * machines without emulation or binary translation.
  6. *
  7. * MMU support
  8. *
  9. * Copyright (C) 2006 Qumranet, Inc.
  10. *
  11. * Authors:
  12. * Yaniv Kamay <yaniv@qumranet.com>
  13. * Avi Kivity <avi@qumranet.com>
  14. *
  15. * This work is licensed under the terms of the GNU GPL, version 2. See
  16. * the COPYING file in the top-level directory.
  17. *
  18. */
  19. /*
  20. * We need the mmu code to access both 32-bit and 64-bit guest ptes,
  21. * so the code in this file is compiled twice, once per pte size.
  22. */
  23. #if PTTYPE == 64
  24. #define pt_element_t u64
  25. #define guest_walker guest_walker64
  26. #define FNAME(name) paging##64_##name
  27. #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
  28. #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
  29. #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
  30. #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
  31. #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
  32. #define PT_LEVEL_BITS PT64_LEVEL_BITS
  33. #ifdef CONFIG_X86_64
  34. #define PT_MAX_FULL_LEVELS 4
  35. #else
  36. #define PT_MAX_FULL_LEVELS 2
  37. #endif
  38. #elif PTTYPE == 32
  39. #define pt_element_t u32
  40. #define guest_walker guest_walker32
  41. #define FNAME(name) paging##32_##name
  42. #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
  43. #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
  44. #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
  45. #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
  46. #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
  47. #define PT_LEVEL_BITS PT32_LEVEL_BITS
  48. #define PT_MAX_FULL_LEVELS 2
  49. #else
  50. #error Invalid PTTYPE value
  51. #endif
  52. /*
  53. * The guest_walker structure emulates the behavior of the hardware page
  54. * table walker.
  55. */
  56. struct guest_walker {
  57. int level;
  58. gfn_t table_gfn[PT_MAX_FULL_LEVELS];
  59. pt_element_t *table;
  60. pt_element_t pte;
  61. pt_element_t *ptep;
  62. struct page *page;
  63. int index;
  64. pt_element_t inherited_ar;
  65. gfn_t gfn;
  66. u32 error_code;
  67. };
  68. static void FNAME(update_dirty_bit)(struct kvm_vcpu *vcpu,
  69. int write_fault,
  70. pt_element_t *ptep,
  71. gfn_t table_gfn)
  72. {
  73. gpa_t pte_gpa;
  74. if (write_fault && !is_dirty_pte(*ptep)) {
  75. mark_page_dirty(vcpu->kvm, table_gfn);
  76. *ptep |= PT_DIRTY_MASK;
  77. pte_gpa = ((gpa_t)table_gfn << PAGE_SHIFT);
  78. pte_gpa += offset_in_page(ptep);
  79. kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)ptep, sizeof(*ptep));
  80. }
  81. }
  82. /*
  83. * Fetch a guest pte for a guest virtual address
  84. */
  85. static int FNAME(walk_addr)(struct guest_walker *walker,
  86. struct kvm_vcpu *vcpu, gva_t addr,
  87. int write_fault, int user_fault, int fetch_fault)
  88. {
  89. hpa_t hpa;
  90. struct kvm_memory_slot *slot;
  91. pt_element_t *ptep;
  92. pt_element_t root;
  93. gfn_t table_gfn;
  94. pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
  95. walker->level = vcpu->mmu.root_level;
  96. walker->table = NULL;
  97. walker->page = NULL;
  98. walker->ptep = NULL;
  99. root = vcpu->cr3;
  100. #if PTTYPE == 64
  101. if (!is_long_mode(vcpu)) {
  102. walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3];
  103. root = *walker->ptep;
  104. walker->pte = root;
  105. if (!(root & PT_PRESENT_MASK))
  106. goto not_present;
  107. --walker->level;
  108. }
  109. #endif
  110. table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
  111. walker->table_gfn[walker->level - 1] = table_gfn;
  112. pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
  113. walker->level - 1, table_gfn);
  114. slot = gfn_to_memslot(vcpu->kvm, table_gfn);
  115. hpa = safe_gpa_to_hpa(vcpu->kvm, root & PT64_BASE_ADDR_MASK);
  116. walker->page = pfn_to_page(hpa >> PAGE_SHIFT);
  117. walker->table = kmap_atomic(walker->page, KM_USER0);
  118. ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
  119. (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
  120. walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;
  121. for (;;) {
  122. int index = PT_INDEX(addr, walker->level);
  123. hpa_t paddr;
  124. ptep = &walker->table[index];
  125. walker->index = index;
  126. ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
  127. ((unsigned long)ptep & PAGE_MASK));
  128. if (!is_present_pte(*ptep))
  129. goto not_present;
  130. if (write_fault && !is_writeble_pte(*ptep))
  131. if (user_fault || is_write_protection(vcpu))
  132. goto access_error;
  133. if (user_fault && !(*ptep & PT_USER_MASK))
  134. goto access_error;
  135. #if PTTYPE == 64
  136. if (fetch_fault && is_nx(vcpu) && (*ptep & PT64_NX_MASK))
  137. goto access_error;
  138. #endif
  139. if (!(*ptep & PT_ACCESSED_MASK)) {
  140. mark_page_dirty(vcpu->kvm, table_gfn);
  141. *ptep |= PT_ACCESSED_MASK;
  142. }
  143. if (walker->level == PT_PAGE_TABLE_LEVEL) {
  144. walker->gfn = (*ptep & PT_BASE_ADDR_MASK)
  145. >> PAGE_SHIFT;
  146. FNAME(update_dirty_bit)(vcpu, write_fault, ptep,
  147. table_gfn);
  148. break;
  149. }
  150. if (walker->level == PT_DIRECTORY_LEVEL
  151. && (*ptep & PT_PAGE_SIZE_MASK)
  152. && (PTTYPE == 64 || is_pse(vcpu))) {
  153. walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK)
  154. >> PAGE_SHIFT;
  155. walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
  156. FNAME(update_dirty_bit)(vcpu, write_fault, ptep,
  157. table_gfn);
  158. break;
  159. }
  160. walker->inherited_ar &= walker->table[index];
  161. table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
  162. kunmap_atomic(walker->table, KM_USER0);
  163. paddr = safe_gpa_to_hpa(vcpu->kvm, table_gfn << PAGE_SHIFT);
  164. walker->page = pfn_to_page(paddr >> PAGE_SHIFT);
  165. walker->table = kmap_atomic(walker->page, KM_USER0);
  166. --walker->level;
  167. walker->table_gfn[walker->level - 1] = table_gfn;
  168. pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
  169. walker->level - 1, table_gfn);
  170. }
  171. walker->pte = *ptep;
  172. if (walker->page)
  173. walker->ptep = NULL;
  174. if (walker->table)
  175. kunmap_atomic(walker->table, KM_USER0);
  176. pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep);
  177. return 1;
  178. not_present:
  179. walker->error_code = 0;
  180. goto err;
  181. access_error:
  182. walker->error_code = PFERR_PRESENT_MASK;
  183. err:
  184. if (write_fault)
  185. walker->error_code |= PFERR_WRITE_MASK;
  186. if (user_fault)
  187. walker->error_code |= PFERR_USER_MASK;
  188. if (fetch_fault)
  189. walker->error_code |= PFERR_FETCH_MASK;
  190. if (walker->table)
  191. kunmap_atomic(walker->table, KM_USER0);
  192. return 0;
  193. }
  194. static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
  195. u64 *shadow_pte,
  196. gpa_t gaddr,
  197. pt_element_t gpte,
  198. u64 access_bits,
  199. int user_fault,
  200. int write_fault,
  201. int *ptwrite,
  202. struct guest_walker *walker,
  203. gfn_t gfn)
  204. {
  205. hpa_t paddr;
  206. int dirty = gpte & PT_DIRTY_MASK;
  207. u64 spte;
  208. int was_rmapped = is_rmap_pte(*shadow_pte);
  209. pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
  210. " user_fault %d gfn %lx\n",
  211. __FUNCTION__, *shadow_pte, (u64)gpte, access_bits,
  212. write_fault, user_fault, gfn);
  213. /*
  214. * We don't set the accessed bit, since we sometimes want to see
  215. * whether the guest actually used the pte (in order to detect
  216. * demand paging).
  217. */
  218. spte = PT_PRESENT_MASK | PT_DIRTY_MASK;
  219. spte |= gpte & PT64_NX_MASK;
  220. if (!dirty)
  221. access_bits &= ~PT_WRITABLE_MASK;
  222. paddr = gpa_to_hpa(vcpu->kvm, gaddr & PT64_BASE_ADDR_MASK);
  223. spte |= PT_PRESENT_MASK;
  224. if (access_bits & PT_USER_MASK)
  225. spte |= PT_USER_MASK;
  226. if (is_error_hpa(paddr)) {
  227. set_shadow_pte(shadow_pte,
  228. shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK);
  229. return;
  230. }
  231. spte |= paddr;
  232. if ((access_bits & PT_WRITABLE_MASK)
  233. || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
  234. struct kvm_mmu_page *shadow;
  235. spte |= PT_WRITABLE_MASK;
  236. if (user_fault) {
  237. mmu_unshadow(vcpu->kvm, gfn);
  238. goto unshadowed;
  239. }
  240. shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
  241. if (shadow) {
  242. pgprintk("%s: found shadow page for %lx, marking ro\n",
  243. __FUNCTION__, gfn);
  244. access_bits &= ~PT_WRITABLE_MASK;
  245. if (is_writeble_pte(spte)) {
  246. spte &= ~PT_WRITABLE_MASK;
  247. kvm_x86_ops->tlb_flush(vcpu);
  248. }
  249. if (write_fault)
  250. *ptwrite = 1;
  251. }
  252. }
  253. unshadowed:
  254. if (access_bits & PT_WRITABLE_MASK)
  255. mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);
  256. pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte);
  257. set_shadow_pte(shadow_pte, spte);
  258. page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
  259. if (!was_rmapped)
  260. rmap_add(vcpu, shadow_pte, (gaddr & PT64_BASE_ADDR_MASK)
  261. >> PAGE_SHIFT);
  262. if (!ptwrite || !*ptwrite)
  263. vcpu->last_pte_updated = shadow_pte;
  264. }
  265. static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
  266. u64 *shadow_pte, u64 access_bits,
  267. int user_fault, int write_fault, int *ptwrite,
  268. struct guest_walker *walker, gfn_t gfn)
  269. {
  270. access_bits &= gpte;
  271. FNAME(set_pte_common)(vcpu, shadow_pte, gpte & PT_BASE_ADDR_MASK,
  272. gpte, access_bits, user_fault, write_fault,
  273. ptwrite, walker, gfn);
  274. }
  275. static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
  276. u64 *spte, const void *pte, int bytes,
  277. int offset_in_pte)
  278. {
  279. pt_element_t gpte;
  280. gpte = *(const pt_element_t *)pte;
  281. if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
  282. if (!offset_in_pte && !is_present_pte(gpte))
  283. set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
  284. return;
  285. }
  286. if (bytes < sizeof(pt_element_t))
  287. return;
  288. pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
  289. FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0,
  290. 0, NULL, NULL,
  291. (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT);
  292. }
  293. static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t gpde,
  294. u64 *shadow_pte, u64 access_bits,
  295. int user_fault, int write_fault, int *ptwrite,
  296. struct guest_walker *walker, gfn_t gfn)
  297. {
  298. gpa_t gaddr;
  299. access_bits &= gpde;
  300. gaddr = (gpa_t)gfn << PAGE_SHIFT;
  301. if (PTTYPE == 32 && is_cpuid_PSE36())
  302. gaddr |= (gpde & PT32_DIR_PSE36_MASK) <<
  303. (32 - PT32_DIR_PSE36_SHIFT);
  304. FNAME(set_pte_common)(vcpu, shadow_pte, gaddr,
  305. gpde, access_bits, user_fault, write_fault,
  306. ptwrite, walker, gfn);
  307. }
  308. /*
  309. * Fetch a shadow pte for a specific level in the paging hierarchy.
  310. */
  311. static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
  312. struct guest_walker *walker,
  313. int user_fault, int write_fault, int *ptwrite)
  314. {
  315. hpa_t shadow_addr;
  316. int level;
  317. u64 *shadow_ent;
  318. u64 *prev_shadow_ent = NULL;
  319. if (!is_present_pte(walker->pte))
  320. return NULL;
  321. shadow_addr = vcpu->mmu.root_hpa;
  322. level = vcpu->mmu.shadow_root_level;
  323. if (level == PT32E_ROOT_LEVEL) {
  324. shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
  325. shadow_addr &= PT64_BASE_ADDR_MASK;
  326. --level;
  327. }
  328. for (; ; level--) {
  329. u32 index = SHADOW_PT_INDEX(addr, level);
  330. struct kvm_mmu_page *shadow_page;
  331. u64 shadow_pte;
  332. int metaphysical;
  333. gfn_t table_gfn;
  334. unsigned hugepage_access = 0;
  335. shadow_ent = ((u64 *)__va(shadow_addr)) + index;
  336. if (is_shadow_present_pte(*shadow_ent)) {
  337. if (level == PT_PAGE_TABLE_LEVEL)
  338. break;
  339. shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
  340. prev_shadow_ent = shadow_ent;
  341. continue;
  342. }
  343. if (level == PT_PAGE_TABLE_LEVEL)
  344. break;
  345. if (level - 1 == PT_PAGE_TABLE_LEVEL
  346. && walker->level == PT_DIRECTORY_LEVEL) {
  347. metaphysical = 1;
  348. hugepage_access = walker->pte;
  349. hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK;
  350. if (!is_dirty_pte(walker->pte))
  351. hugepage_access &= ~PT_WRITABLE_MASK;
  352. hugepage_access >>= PT_WRITABLE_SHIFT;
  353. if (walker->pte & PT64_NX_MASK)
  354. hugepage_access |= (1 << 2);
  355. table_gfn = (walker->pte & PT_BASE_ADDR_MASK)
  356. >> PAGE_SHIFT;
  357. } else {
  358. metaphysical = 0;
  359. table_gfn = walker->table_gfn[level - 2];
  360. }
  361. shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
  362. metaphysical, hugepage_access,
  363. shadow_ent);
  364. shadow_addr = __pa(shadow_page->spt);
  365. shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
  366. | PT_WRITABLE_MASK | PT_USER_MASK;
  367. *shadow_ent = shadow_pte;
  368. prev_shadow_ent = shadow_ent;
  369. }
  370. if (walker->level == PT_DIRECTORY_LEVEL) {
  371. FNAME(set_pde)(vcpu, walker->pte, shadow_ent,
  372. walker->inherited_ar, user_fault, write_fault,
  373. ptwrite, walker, walker->gfn);
  374. } else {
  375. ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
  376. FNAME(set_pte)(vcpu, walker->pte, shadow_ent,
  377. walker->inherited_ar, user_fault, write_fault,
  378. ptwrite, walker, walker->gfn);
  379. }
  380. return shadow_ent;
  381. }
  382. /*
  383. * Page fault handler. There are several causes for a page fault:
  384. * - there is no shadow pte for the guest pte
  385. * - write access through a shadow pte marked read only so that we can set
  386. * the dirty bit
  387. * - write access to a shadow pte marked read only so we can update the page
  388. * dirty bitmap, when userspace requests it
  389. * - mmio access; in this case we will never install a present shadow pte
  390. * - normal guest page fault due to the guest pte marked not present, not
  391. * writable, or not executable
  392. *
  393. * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
  394. * a negative value on error.
  395. */
  396. static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
  397. u32 error_code)
  398. {
  399. int write_fault = error_code & PFERR_WRITE_MASK;
  400. int user_fault = error_code & PFERR_USER_MASK;
  401. int fetch_fault = error_code & PFERR_FETCH_MASK;
  402. struct guest_walker walker;
  403. u64 *shadow_pte;
  404. int write_pt = 0;
  405. int r;
  406. pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
  407. kvm_mmu_audit(vcpu, "pre page fault");
  408. r = mmu_topup_memory_caches(vcpu);
  409. if (r)
  410. return r;
  411. /*
  412. * Look up the shadow pte for the faulting address.
  413. */
  414. r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
  415. fetch_fault);
  416. /*
  417. * The page is not mapped by the guest. Let the guest handle it.
  418. */
  419. if (!r) {
  420. pgprintk("%s: guest page fault\n", __FUNCTION__);
  421. inject_page_fault(vcpu, addr, walker.error_code);
  422. vcpu->last_pt_write_count = 0; /* reset fork detector */
  423. return 0;
  424. }
  425. shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
  426. &write_pt);
  427. pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
  428. shadow_pte, *shadow_pte, write_pt);
  429. if (!write_pt)
  430. vcpu->last_pt_write_count = 0; /* reset fork detector */
  431. /*
  432. * mmio: emulate if accessible, otherwise its a guest fault.
  433. */
  434. if (is_io_pte(*shadow_pte))
  435. return 1;
  436. ++vcpu->stat.pf_fixed;
  437. kvm_mmu_audit(vcpu, "post page fault (fixed)");
  438. return write_pt;
  439. }
  440. static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
  441. {
  442. struct guest_walker walker;
  443. gpa_t gpa = UNMAPPED_GVA;
  444. int r;
  445. r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
  446. if (r) {
  447. gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
  448. gpa |= vaddr & ~PAGE_MASK;
  449. }
  450. return gpa;
  451. }
  452. static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
  453. struct kvm_mmu_page *sp)
  454. {
  455. int i;
  456. pt_element_t *gpt;
  457. if (sp->role.metaphysical || PTTYPE == 32) {
  458. nonpaging_prefetch_page(vcpu, sp);
  459. return;
  460. }
  461. gpt = kmap_atomic(gfn_to_page(vcpu->kvm, sp->gfn), KM_USER0);
  462. for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
  463. if (is_present_pte(gpt[i]))
  464. sp->spt[i] = shadow_trap_nonpresent_pte;
  465. else
  466. sp->spt[i] = shadow_notrap_nonpresent_pte;
  467. kunmap_atomic(gpt, KM_USER0);
  468. }
  469. #undef pt_element_t
  470. #undef guest_walker
  471. #undef FNAME
  472. #undef PT_BASE_ADDR_MASK
  473. #undef PT_INDEX
  474. #undef SHADOW_PT_INDEX
  475. #undef PT_LEVEL_MASK
  476. #undef PT_DIR_BASE_ADDR_MASK
  477. #undef PT_LEVEL_BITS
  478. #undef PT_MAX_FULL_LEVELS