mci.c 18 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/dma-mapping.h>
  17. #include <linux/slab.h>
  18. #include "ath9k.h"
  19. #include "mci.h"
  20. u8 ath_mci_duty_cycle[] = { 0, 50, 60, 70, 80, 85, 90, 95, 98 };
  21. static struct ath_mci_profile_info*
  22. ath_mci_find_profile(struct ath_mci_profile *mci,
  23. struct ath_mci_profile_info *info)
  24. {
  25. struct ath_mci_profile_info *entry;
  26. list_for_each_entry(entry, &mci->info, list) {
  27. if (entry->conn_handle == info->conn_handle)
  28. break;
  29. }
  30. return entry;
  31. }
  32. static bool ath_mci_add_profile(struct ath_common *common,
  33. struct ath_mci_profile *mci,
  34. struct ath_mci_profile_info *info)
  35. {
  36. struct ath_mci_profile_info *entry;
  37. if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
  38. (info->type == MCI_GPM_COEX_PROFILE_VOICE)) {
  39. ath_dbg(common, ATH_DBG_MCI,
  40. "Too many SCO profile, failed to add new profile\n");
  41. return false;
  42. }
  43. if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
  44. (info->type != MCI_GPM_COEX_PROFILE_VOICE)) {
  45. ath_dbg(common, ATH_DBG_MCI,
  46. "Too many ACL profile, failed to add new profile\n");
  47. return false;
  48. }
  49. entry = ath_mci_find_profile(mci, info);
  50. if (entry)
  51. memcpy(entry, info, 10);
  52. else {
  53. entry = kzalloc(sizeof(*entry), GFP_KERNEL);
  54. if (!entry)
  55. return false;
  56. memcpy(entry, info, 10);
  57. INC_PROF(mci, info);
  58. list_add_tail(&info->list, &mci->info);
  59. }
  60. return true;
  61. }
  62. static void ath_mci_del_profile(struct ath_common *common,
  63. struct ath_mci_profile *mci,
  64. struct ath_mci_profile_info *info)
  65. {
  66. struct ath_mci_profile_info *entry;
  67. entry = ath_mci_find_profile(mci, info);
  68. if (!entry) {
  69. ath_dbg(common, ATH_DBG_MCI,
  70. "Profile to be deleted not found\n");
  71. return;
  72. }
  73. DEC_PROF(mci, entry);
  74. list_del(&entry->list);
  75. kfree(entry);
  76. }
  77. void ath_mci_flush_profile(struct ath_mci_profile *mci)
  78. {
  79. struct ath_mci_profile_info *info, *tinfo;
  80. list_for_each_entry_safe(info, tinfo, &mci->info, list) {
  81. list_del(&info->list);
  82. DEC_PROF(mci, info);
  83. kfree(info);
  84. }
  85. mci->aggr_limit = 0;
  86. }
  87. static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
  88. {
  89. struct ath_mci_profile *mci = &btcoex->mci;
  90. u32 wlan_airtime = btcoex->btcoex_period *
  91. (100 - btcoex->duty_cycle) / 100;
  92. /*
  93. * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
  94. * When wlan_airtime is less than 4ms, aggregation limit has to be
  95. * adjusted half of wlan_airtime to ensure that the aggregation can fit
  96. * without collision with BT traffic.
  97. */
  98. if ((wlan_airtime <= 4) &&
  99. (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime))))
  100. mci->aggr_limit = 2 * wlan_airtime;
  101. }
  102. static void ath_mci_update_scheme(struct ath_softc *sc)
  103. {
  104. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  105. struct ath_btcoex *btcoex = &sc->btcoex;
  106. struct ath_mci_profile *mci = &btcoex->mci;
  107. struct ath_mci_profile_info *info;
  108. u32 num_profile = NUM_PROF(mci);
  109. if (num_profile == 1) {
  110. info = list_first_entry(&mci->info,
  111. struct ath_mci_profile_info,
  112. list);
  113. if (mci->num_sco && info->T == 12) {
  114. mci->aggr_limit = 8;
  115. ath_dbg(common, ATH_DBG_MCI,
  116. "Single SCO, aggregation limit 2 ms\n");
  117. } else if ((info->type == MCI_GPM_COEX_PROFILE_BNEP) &&
  118. !info->master) {
  119. btcoex->btcoex_period = 60;
  120. ath_dbg(common, ATH_DBG_MCI,
  121. "Single slave PAN/FTP, bt period 60 ms\n");
  122. } else if ((info->type == MCI_GPM_COEX_PROFILE_HID) &&
  123. (info->T > 0 && info->T < 50) &&
  124. (info->A > 1 || info->W > 1)) {
  125. btcoex->duty_cycle = 30;
  126. mci->aggr_limit = 8;
  127. ath_dbg(common, ATH_DBG_MCI,
  128. "Multiple attempt/timeout single HID "
  129. "aggregation limit 2 ms dutycycle 30%%\n");
  130. }
  131. } else if ((num_profile == 2) && (mci->num_hid == 2)) {
  132. btcoex->duty_cycle = 30;
  133. mci->aggr_limit = 8;
  134. ath_dbg(common, ATH_DBG_MCI,
  135. "Two HIDs aggregation limit 2 ms dutycycle 30%%\n");
  136. } else if (num_profile > 3) {
  137. mci->aggr_limit = 6;
  138. ath_dbg(common, ATH_DBG_MCI,
  139. "Three or more profiles aggregation limit 1.5 ms\n");
  140. }
  141. if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
  142. if (IS_CHAN_HT(sc->sc_ah->curchan))
  143. ath_mci_adjust_aggr_limit(btcoex);
  144. else
  145. btcoex->btcoex_period >>= 1;
  146. }
  147. ath9k_hw_btcoex_disable(sc->sc_ah);
  148. ath9k_btcoex_timer_pause(sc);
  149. if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
  150. return;
  151. btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_MAX_DUTY_CYCLE : 0);
  152. if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
  153. btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
  154. btcoex->btcoex_period *= 1000;
  155. btcoex->btcoex_no_stomp = btcoex->btcoex_period *
  156. (100 - btcoex->duty_cycle) / 100;
  157. ath9k_hw_btcoex_enable(sc->sc_ah);
  158. ath9k_btcoex_timer_resume(sc);
  159. }
  160. static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  161. {
  162. struct ath_hw *ah = sc->sc_ah;
  163. struct ath_common *common = ath9k_hw_common(ah);
  164. u32 payload[4] = {0, 0, 0, 0};
  165. switch (opcode) {
  166. case MCI_GPM_BT_CAL_REQ:
  167. ath_dbg(common, ATH_DBG_MCI, "MCI received BT_CAL_REQ\n");
  168. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) {
  169. ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START, NULL);
  170. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  171. } else
  172. ath_dbg(common, ATH_DBG_MCI,
  173. "MCI State mismatches: %d\n",
  174. ar9003_mci_state(ah, MCI_STATE_BT, NULL));
  175. break;
  176. case MCI_GPM_BT_CAL_DONE:
  177. ath_dbg(common, ATH_DBG_MCI, "MCI received BT_CAL_DONE\n");
  178. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_CAL)
  179. ath_dbg(common, ATH_DBG_MCI, "MCI error illegal!\n");
  180. else
  181. ath_dbg(common, ATH_DBG_MCI, "MCI BT not in CAL state\n");
  182. break;
  183. case MCI_GPM_BT_CAL_GRANT:
  184. ath_dbg(common, ATH_DBG_MCI, "MCI received BT_CAL_GRANT\n");
  185. /* Send WLAN_CAL_DONE for now */
  186. ath_dbg(common, ATH_DBG_MCI, "MCI send WLAN_CAL_DONE\n");
  187. MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
  188. ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
  189. 16, false, true);
  190. break;
  191. default:
  192. ath_dbg(common, ATH_DBG_MCI, "MCI Unknown GPM CAL message\n");
  193. break;
  194. }
  195. }
  196. void ath_mci_process_profile(struct ath_softc *sc,
  197. struct ath_mci_profile_info *info)
  198. {
  199. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  200. struct ath_btcoex *btcoex = &sc->btcoex;
  201. struct ath_mci_profile *mci = &btcoex->mci;
  202. if (info->start) {
  203. if (!ath_mci_add_profile(common, mci, info))
  204. return;
  205. } else
  206. ath_mci_del_profile(common, mci, info);
  207. btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
  208. mci->aggr_limit = mci->num_sco ? 6 : 0;
  209. if (NUM_PROF(mci)) {
  210. btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
  211. btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)];
  212. } else {
  213. btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
  214. ATH_BTCOEX_STOMP_LOW;
  215. btcoex->duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE;
  216. }
  217. ath_mci_update_scheme(sc);
  218. }
  219. void ath_mci_process_status(struct ath_softc *sc,
  220. struct ath_mci_profile_status *status)
  221. {
  222. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  223. struct ath_btcoex *btcoex = &sc->btcoex;
  224. struct ath_mci_profile *mci = &btcoex->mci;
  225. struct ath_mci_profile_info info;
  226. int i = 0, old_num_mgmt = mci->num_mgmt;
  227. /* Link status type are not handled */
  228. if (status->is_link) {
  229. ath_dbg(common, ATH_DBG_MCI,
  230. "Skip link type status update\n");
  231. return;
  232. }
  233. memset(&info, 0, sizeof(struct ath_mci_profile_info));
  234. info.conn_handle = status->conn_handle;
  235. if (ath_mci_find_profile(mci, &info)) {
  236. ath_dbg(common, ATH_DBG_MCI,
  237. "Skip non link state update for existing profile %d\n",
  238. status->conn_handle);
  239. return;
  240. }
  241. if (status->conn_handle >= ATH_MCI_MAX_PROFILE) {
  242. ath_dbg(common, ATH_DBG_MCI,
  243. "Ignore too many non-link update\n");
  244. return;
  245. }
  246. if (status->is_critical)
  247. __set_bit(status->conn_handle, mci->status);
  248. else
  249. __clear_bit(status->conn_handle, mci->status);
  250. mci->num_mgmt = 0;
  251. do {
  252. if (test_bit(i, mci->status))
  253. mci->num_mgmt++;
  254. } while (++i < ATH_MCI_MAX_PROFILE);
  255. if (old_num_mgmt != mci->num_mgmt)
  256. ath_mci_update_scheme(sc);
  257. }
  258. static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  259. {
  260. struct ath_hw *ah = sc->sc_ah;
  261. struct ath_mci_profile_info profile_info;
  262. struct ath_mci_profile_status profile_status;
  263. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  264. u32 version;
  265. u8 major;
  266. u8 minor;
  267. u32 seq_num;
  268. switch (opcode) {
  269. case MCI_GPM_COEX_VERSION_QUERY:
  270. ath_dbg(common, ATH_DBG_MCI,
  271. "MCI Recv GPM COEX Version Query.\n");
  272. version = ar9003_mci_state(ah,
  273. MCI_STATE_SEND_WLAN_COEX_VERSION, NULL);
  274. break;
  275. case MCI_GPM_COEX_VERSION_RESPONSE:
  276. ath_dbg(common, ATH_DBG_MCI,
  277. "MCI Recv GPM COEX Version Response.\n");
  278. major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
  279. minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
  280. ath_dbg(common, ATH_DBG_MCI,
  281. "MCI BT Coex version: %d.%d\n", major, minor);
  282. version = (major << 8) + minor;
  283. version = ar9003_mci_state(ah,
  284. MCI_STATE_SET_BT_COEX_VERSION, &version);
  285. break;
  286. case MCI_GPM_COEX_STATUS_QUERY:
  287. ath_dbg(common, ATH_DBG_MCI,
  288. "MCI Recv GPM COEX Status Query = 0x%02x.\n",
  289. *(rx_payload + MCI_GPM_COEX_B_WLAN_BITMAP));
  290. ar9003_mci_state(ah,
  291. MCI_STATE_SEND_WLAN_CHANNELS, NULL);
  292. break;
  293. case MCI_GPM_COEX_BT_PROFILE_INFO:
  294. ath_dbg(common, ATH_DBG_MCI,
  295. "MCI Recv GPM Coex BT profile info\n");
  296. memcpy(&profile_info,
  297. (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
  298. if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN)
  299. || (profile_info.type >=
  300. MCI_GPM_COEX_PROFILE_MAX)) {
  301. ath_dbg(common, ATH_DBG_MCI,
  302. "illegal profile type = %d,"
  303. "state = %d\n", profile_info.type,
  304. profile_info.start);
  305. break;
  306. }
  307. ath_mci_process_profile(sc, &profile_info);
  308. break;
  309. case MCI_GPM_COEX_BT_STATUS_UPDATE:
  310. profile_status.is_link = *(rx_payload +
  311. MCI_GPM_COEX_B_STATUS_TYPE);
  312. profile_status.conn_handle = *(rx_payload +
  313. MCI_GPM_COEX_B_STATUS_LINKID);
  314. profile_status.is_critical = *(rx_payload +
  315. MCI_GPM_COEX_B_STATUS_STATE);
  316. seq_num = *((u32 *)(rx_payload + 12));
  317. ath_dbg(common, ATH_DBG_MCI,
  318. "MCI Recv GPM COEX BT_Status_Update: "
  319. "is_link=%d, linkId=%d, state=%d, SEQ=%d\n",
  320. profile_status.is_link, profile_status.conn_handle,
  321. profile_status.is_critical, seq_num);
  322. ath_mci_process_status(sc, &profile_status);
  323. break;
  324. default:
  325. ath_dbg(common, ATH_DBG_MCI,
  326. "MCI Unknown GPM COEX message = 0x%02x\n", opcode);
  327. break;
  328. }
  329. }
  330. static int ath_mci_buf_alloc(struct ath_softc *sc, struct ath_mci_buf *buf)
  331. {
  332. int error = 0;
  333. buf->bf_addr = dma_alloc_coherent(sc->dev, buf->bf_len,
  334. &buf->bf_paddr, GFP_KERNEL);
  335. if (buf->bf_addr == NULL) {
  336. error = -ENOMEM;
  337. goto fail;
  338. }
  339. return 0;
  340. fail:
  341. memset(buf, 0, sizeof(*buf));
  342. return error;
  343. }
  344. static void ath_mci_buf_free(struct ath_softc *sc, struct ath_mci_buf *buf)
  345. {
  346. if (buf->bf_addr) {
  347. dma_free_coherent(sc->dev, buf->bf_len, buf->bf_addr,
  348. buf->bf_paddr);
  349. memset(buf, 0, sizeof(*buf));
  350. }
  351. }
  352. int ath_mci_setup(struct ath_softc *sc)
  353. {
  354. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  355. struct ath_mci_coex *mci = &sc->mci_coex;
  356. int error = 0;
  357. mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE;
  358. if (ath_mci_buf_alloc(sc, &mci->sched_buf)) {
  359. ath_dbg(common, ATH_DBG_FATAL, "MCI buffer alloc failed\n");
  360. error = -ENOMEM;
  361. goto fail;
  362. }
  363. mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
  364. memset(mci->sched_buf.bf_addr, MCI_GPM_RSVD_PATTERN,
  365. mci->sched_buf.bf_len);
  366. mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
  367. mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr +
  368. mci->sched_buf.bf_len;
  369. mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
  370. /* initialize the buffer */
  371. memset(mci->gpm_buf.bf_addr, MCI_GPM_RSVD_PATTERN, mci->gpm_buf.bf_len);
  372. ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
  373. mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
  374. mci->sched_buf.bf_paddr);
  375. fail:
  376. return error;
  377. }
  378. void ath_mci_cleanup(struct ath_softc *sc)
  379. {
  380. struct ath_hw *ah = sc->sc_ah;
  381. struct ath_mci_coex *mci = &sc->mci_coex;
  382. /*
  383. * both schedule and gpm buffers will be released
  384. */
  385. ath_mci_buf_free(sc, &mci->sched_buf);
  386. ar9003_mci_cleanup(ah);
  387. }
  388. void ath_mci_intr(struct ath_softc *sc)
  389. {
  390. struct ath_mci_coex *mci = &sc->mci_coex;
  391. struct ath_hw *ah = sc->sc_ah;
  392. struct ath_common *common = ath9k_hw_common(ah);
  393. u32 mci_int, mci_int_rxmsg;
  394. u32 offset, subtype, opcode;
  395. u32 *pgpm;
  396. u32 more_data = MCI_GPM_MORE;
  397. bool skip_gpm = false;
  398. ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
  399. if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) == 0) {
  400. ar9003_mci_state(sc->sc_ah, MCI_STATE_INIT_GPM_OFFSET, NULL);
  401. ath_dbg(common, ATH_DBG_MCI,
  402. "MCI interrupt but MCI disabled\n");
  403. ath_dbg(common, ATH_DBG_MCI,
  404. "MCI interrupt: intr = 0x%x, intr_rxmsg = 0x%x\n",
  405. mci_int, mci_int_rxmsg);
  406. return;
  407. }
  408. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
  409. u32 payload[4] = { 0xffffffff, 0xffffffff,
  410. 0xffffffff, 0xffffff00};
  411. /*
  412. * The following REMOTE_RESET and SYS_WAKING used to sent
  413. * only when BT wake up. Now they are always sent, as a
  414. * recovery method to reset BT MCI's RX alignment.
  415. */
  416. ath_dbg(common, ATH_DBG_MCI, "MCI interrupt send REMOTE_RESET\n");
  417. ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
  418. payload, 16, true, false);
  419. ath_dbg(common, ATH_DBG_MCI, "MCI interrupt send SYS_WAKING\n");
  420. ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
  421. NULL, 0, true, false);
  422. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
  423. ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE, NULL);
  424. /*
  425. * always do this for recovery and 2G/5G toggling and LNA_TRANS
  426. */
  427. ath_dbg(common, ATH_DBG_MCI, "MCI Set BT state to AWAKE.\n");
  428. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, NULL);
  429. }
  430. /* Processing SYS_WAKING/SYS_SLEEPING */
  431. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
  432. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
  433. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_SLEEP) {
  434. if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL)
  435. == MCI_BT_SLEEP)
  436. ath_dbg(common, ATH_DBG_MCI,
  437. "MCI BT stays in sleep mode\n");
  438. else {
  439. ath_dbg(common, ATH_DBG_MCI,
  440. "MCI Set BT state to AWAKE.\n");
  441. ar9003_mci_state(ah,
  442. MCI_STATE_SET_BT_AWAKE, NULL);
  443. }
  444. } else
  445. ath_dbg(common, ATH_DBG_MCI,
  446. "MCI BT stays in AWAKE mode.\n");
  447. }
  448. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
  449. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
  450. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) {
  451. if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL)
  452. == MCI_BT_AWAKE)
  453. ath_dbg(common, ATH_DBG_MCI,
  454. "MCI BT stays in AWAKE mode.\n");
  455. else {
  456. ath_dbg(common, ATH_DBG_MCI,
  457. "MCI SetBT state to SLEEP\n");
  458. ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP,
  459. NULL);
  460. }
  461. } else
  462. ath_dbg(common, ATH_DBG_MCI,
  463. "MCI BT stays in SLEEP mode\n");
  464. }
  465. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  466. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
  467. ath_dbg(common, ATH_DBG_MCI, "MCI RX broken, skip GPM msgs\n");
  468. ar9003_mci_state(ah, MCI_STATE_RECOVER_RX, NULL);
  469. skip_gpm = true;
  470. }
  471. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
  472. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
  473. offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET,
  474. NULL);
  475. }
  476. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
  477. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
  478. while (more_data == MCI_GPM_MORE) {
  479. pgpm = mci->gpm_buf.bf_addr;
  480. offset = ar9003_mci_state(ah,
  481. MCI_STATE_NEXT_GPM_OFFSET, &more_data);
  482. if (offset == MCI_GPM_INVALID)
  483. break;
  484. pgpm += (offset >> 2);
  485. /*
  486. * The first dword is timer.
  487. * The real data starts from 2nd dword.
  488. */
  489. subtype = MCI_GPM_TYPE(pgpm);
  490. opcode = MCI_GPM_OPCODE(pgpm);
  491. if (!skip_gpm) {
  492. if (MCI_GPM_IS_CAL_TYPE(subtype))
  493. ath_mci_cal_msg(sc, subtype,
  494. (u8 *) pgpm);
  495. else {
  496. switch (subtype) {
  497. case MCI_GPM_COEX_AGENT:
  498. ath_mci_msg(sc, opcode,
  499. (u8 *) pgpm);
  500. break;
  501. default:
  502. break;
  503. }
  504. }
  505. }
  506. MCI_GPM_RECYCLE(pgpm);
  507. }
  508. }
  509. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
  510. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
  511. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
  512. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO) {
  513. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
  514. ath_dbg(common, ATH_DBG_MCI, "MCI LNA_INFO\n");
  515. }
  516. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
  517. int value_dbm = ar9003_mci_state(ah,
  518. MCI_STATE_CONT_RSSI_POWER, NULL);
  519. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
  520. if (ar9003_mci_state(ah, MCI_STATE_CONT_TXRX, NULL))
  521. ath_dbg(common, ATH_DBG_MCI,
  522. "MCI CONT_INFO: "
  523. "(tx) pri = %d, pwr = %d dBm\n",
  524. ar9003_mci_state(ah,
  525. MCI_STATE_CONT_PRIORITY, NULL),
  526. value_dbm);
  527. else
  528. ath_dbg(common, ATH_DBG_MCI,
  529. "MCI CONT_INFO:"
  530. "(rx) pri = %d,pwr = %d dBm\n",
  531. ar9003_mci_state(ah,
  532. MCI_STATE_CONT_PRIORITY, NULL),
  533. value_dbm);
  534. }
  535. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK) {
  536. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
  537. ath_dbg(common, ATH_DBG_MCI, "MCI CONT_NACK\n");
  538. }
  539. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST) {
  540. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
  541. ath_dbg(common, ATH_DBG_MCI, "MCI CONT_RST\n");
  542. }
  543. }
  544. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  545. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT))
  546. mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
  547. AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
  548. if (mci_int_rxmsg & 0xfffffffe)
  549. ath_dbg(common, ATH_DBG_MCI,
  550. "MCI not processed mci_int_rxmsg = 0x%x\n",
  551. mci_int_rxmsg);
  552. }