cm2xxx_3xxx.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403
  1. /*
  2. * OMAP2/3 CM module functions
  3. *
  4. * Copyright (C) 2009 Nokia Corporation
  5. * Paul Walmsley
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/types.h>
  13. #include <linux/delay.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/list.h>
  16. #include <linux/errno.h>
  17. #include <linux/err.h>
  18. #include <linux/io.h>
  19. #include <plat/common.h>
  20. #include "cm.h"
  21. #include "cm2xxx_3xxx.h"
  22. #include "cm-regbits-24xx.h"
  23. #include "cm-regbits-34xx.h"
  24. static const u8 cm_idlest_offs[] = {
  25. CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
  26. };
  27. u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
  28. {
  29. return __raw_readl(cm_base + module + idx);
  30. }
  31. void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
  32. {
  33. __raw_writel(val, cm_base + module + idx);
  34. }
  35. /* Read-modify-write a register in a CM module. Caller must lock */
  36. u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
  37. {
  38. u32 v;
  39. v = omap2_cm_read_mod_reg(module, idx);
  40. v &= ~mask;
  41. v |= bits;
  42. omap2_cm_write_mod_reg(v, module, idx);
  43. return v;
  44. }
  45. u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
  46. {
  47. return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
  48. }
  49. u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
  50. {
  51. return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
  52. }
  53. /**
  54. * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
  55. * @prcm_mod: PRCM module offset
  56. * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
  57. * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
  58. *
  59. * XXX document
  60. */
  61. int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
  62. {
  63. int ena = 0, i = 0;
  64. u8 cm_idlest_reg;
  65. u32 mask;
  66. if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
  67. return -EINVAL;
  68. cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
  69. mask = 1 << idlest_shift;
  70. if (cpu_is_omap24xx())
  71. ena = mask;
  72. else if (cpu_is_omap34xx())
  73. ena = 0;
  74. else
  75. BUG();
  76. omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
  77. MAX_MODULE_READY_TIME, i);
  78. return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
  79. }
  80. /*
  81. * Context save/restore code - OMAP3 only
  82. */
  83. #ifdef CONFIG_ARCH_OMAP3
  84. struct omap3_cm_regs {
  85. u32 iva2_cm_clksel1;
  86. u32 iva2_cm_clksel2;
  87. u32 cm_sysconfig;
  88. u32 sgx_cm_clksel;
  89. u32 dss_cm_clksel;
  90. u32 cam_cm_clksel;
  91. u32 per_cm_clksel;
  92. u32 emu_cm_clksel;
  93. u32 emu_cm_clkstctrl;
  94. u32 pll_cm_autoidle2;
  95. u32 pll_cm_clksel4;
  96. u32 pll_cm_clksel5;
  97. u32 pll_cm_clken2;
  98. u32 cm_polctrl;
  99. u32 iva2_cm_fclken;
  100. u32 iva2_cm_clken_pll;
  101. u32 core_cm_fclken1;
  102. u32 core_cm_fclken3;
  103. u32 sgx_cm_fclken;
  104. u32 wkup_cm_fclken;
  105. u32 dss_cm_fclken;
  106. u32 cam_cm_fclken;
  107. u32 per_cm_fclken;
  108. u32 usbhost_cm_fclken;
  109. u32 core_cm_iclken1;
  110. u32 core_cm_iclken2;
  111. u32 core_cm_iclken3;
  112. u32 sgx_cm_iclken;
  113. u32 wkup_cm_iclken;
  114. u32 dss_cm_iclken;
  115. u32 cam_cm_iclken;
  116. u32 per_cm_iclken;
  117. u32 usbhost_cm_iclken;
  118. u32 iva2_cm_autoidle2;
  119. u32 mpu_cm_autoidle2;
  120. u32 iva2_cm_clkstctrl;
  121. u32 mpu_cm_clkstctrl;
  122. u32 core_cm_clkstctrl;
  123. u32 sgx_cm_clkstctrl;
  124. u32 dss_cm_clkstctrl;
  125. u32 cam_cm_clkstctrl;
  126. u32 per_cm_clkstctrl;
  127. u32 neon_cm_clkstctrl;
  128. u32 usbhost_cm_clkstctrl;
  129. u32 core_cm_autoidle1;
  130. u32 core_cm_autoidle2;
  131. u32 core_cm_autoidle3;
  132. u32 wkup_cm_autoidle;
  133. u32 dss_cm_autoidle;
  134. u32 cam_cm_autoidle;
  135. u32 per_cm_autoidle;
  136. u32 usbhost_cm_autoidle;
  137. u32 sgx_cm_sleepdep;
  138. u32 dss_cm_sleepdep;
  139. u32 cam_cm_sleepdep;
  140. u32 per_cm_sleepdep;
  141. u32 usbhost_cm_sleepdep;
  142. u32 cm_clkout_ctrl;
  143. };
  144. static struct omap3_cm_regs cm_context;
  145. void omap3_cm_save_context(void)
  146. {
  147. cm_context.iva2_cm_clksel1 =
  148. omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
  149. cm_context.iva2_cm_clksel2 =
  150. omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
  151. cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
  152. cm_context.sgx_cm_clksel =
  153. omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
  154. cm_context.dss_cm_clksel =
  155. omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
  156. cm_context.cam_cm_clksel =
  157. omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
  158. cm_context.per_cm_clksel =
  159. omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
  160. cm_context.emu_cm_clksel =
  161. omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
  162. cm_context.emu_cm_clkstctrl =
  163. omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
  164. cm_context.pll_cm_autoidle2 =
  165. omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
  166. cm_context.pll_cm_clksel4 =
  167. omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
  168. cm_context.pll_cm_clksel5 =
  169. omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
  170. cm_context.pll_cm_clken2 =
  171. omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
  172. cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
  173. cm_context.iva2_cm_fclken =
  174. omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
  175. cm_context.iva2_cm_clken_pll =
  176. omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
  177. cm_context.core_cm_fclken1 =
  178. omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  179. cm_context.core_cm_fclken3 =
  180. omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
  181. cm_context.sgx_cm_fclken =
  182. omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
  183. cm_context.wkup_cm_fclken =
  184. omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
  185. cm_context.dss_cm_fclken =
  186. omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
  187. cm_context.cam_cm_fclken =
  188. omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
  189. cm_context.per_cm_fclken =
  190. omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
  191. cm_context.usbhost_cm_fclken =
  192. omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
  193. cm_context.core_cm_iclken1 =
  194. omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
  195. cm_context.core_cm_iclken2 =
  196. omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
  197. cm_context.core_cm_iclken3 =
  198. omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
  199. cm_context.sgx_cm_iclken =
  200. omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
  201. cm_context.wkup_cm_iclken =
  202. omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
  203. cm_context.dss_cm_iclken =
  204. omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
  205. cm_context.cam_cm_iclken =
  206. omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
  207. cm_context.per_cm_iclken =
  208. omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
  209. cm_context.usbhost_cm_iclken =
  210. omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
  211. cm_context.iva2_cm_autoidle2 =
  212. omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
  213. cm_context.mpu_cm_autoidle2 =
  214. omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
  215. cm_context.iva2_cm_clkstctrl =
  216. omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
  217. cm_context.mpu_cm_clkstctrl =
  218. omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
  219. cm_context.core_cm_clkstctrl =
  220. omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
  221. cm_context.sgx_cm_clkstctrl =
  222. omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
  223. cm_context.dss_cm_clkstctrl =
  224. omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
  225. cm_context.cam_cm_clkstctrl =
  226. omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
  227. cm_context.per_cm_clkstctrl =
  228. omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
  229. cm_context.neon_cm_clkstctrl =
  230. omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
  231. cm_context.usbhost_cm_clkstctrl =
  232. omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
  233. OMAP2_CM_CLKSTCTRL);
  234. cm_context.core_cm_autoidle1 =
  235. omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
  236. cm_context.core_cm_autoidle2 =
  237. omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
  238. cm_context.core_cm_autoidle3 =
  239. omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
  240. cm_context.wkup_cm_autoidle =
  241. omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
  242. cm_context.dss_cm_autoidle =
  243. omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
  244. cm_context.cam_cm_autoidle =
  245. omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
  246. cm_context.per_cm_autoidle =
  247. omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
  248. cm_context.usbhost_cm_autoidle =
  249. omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
  250. cm_context.sgx_cm_sleepdep =
  251. omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
  252. OMAP3430_CM_SLEEPDEP);
  253. cm_context.dss_cm_sleepdep =
  254. omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
  255. cm_context.cam_cm_sleepdep =
  256. omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
  257. cm_context.per_cm_sleepdep =
  258. omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
  259. cm_context.usbhost_cm_sleepdep =
  260. omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
  261. OMAP3430_CM_SLEEPDEP);
  262. cm_context.cm_clkout_ctrl =
  263. omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
  264. OMAP3_CM_CLKOUT_CTRL_OFFSET);
  265. }
  266. void omap3_cm_restore_context(void)
  267. {
  268. omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
  269. CM_CLKSEL1);
  270. omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
  271. CM_CLKSEL2);
  272. __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
  273. omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
  274. CM_CLKSEL);
  275. omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
  276. CM_CLKSEL);
  277. omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
  278. CM_CLKSEL);
  279. omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
  280. CM_CLKSEL);
  281. omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
  282. CM_CLKSEL1);
  283. omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
  284. OMAP2_CM_CLKSTCTRL);
  285. omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
  286. CM_AUTOIDLE2);
  287. omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
  288. OMAP3430ES2_CM_CLKSEL4);
  289. omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
  290. OMAP3430ES2_CM_CLKSEL5);
  291. omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
  292. OMAP3430ES2_CM_CLKEN2);
  293. __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
  294. omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
  295. CM_FCLKEN);
  296. omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
  297. OMAP3430_CM_CLKEN_PLL);
  298. omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
  299. CM_FCLKEN1);
  300. omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
  301. OMAP3430ES2_CM_FCLKEN3);
  302. omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
  303. CM_FCLKEN);
  304. omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
  305. omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
  306. CM_FCLKEN);
  307. omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
  308. CM_FCLKEN);
  309. omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
  310. CM_FCLKEN);
  311. omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
  312. OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
  313. omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
  314. CM_ICLKEN1);
  315. omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
  316. CM_ICLKEN2);
  317. omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
  318. CM_ICLKEN3);
  319. omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
  320. CM_ICLKEN);
  321. omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
  322. omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
  323. CM_ICLKEN);
  324. omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
  325. CM_ICLKEN);
  326. omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
  327. CM_ICLKEN);
  328. omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
  329. OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
  330. omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
  331. CM_AUTOIDLE2);
  332. omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
  333. CM_AUTOIDLE2);
  334. omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
  335. OMAP2_CM_CLKSTCTRL);
  336. omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
  337. OMAP2_CM_CLKSTCTRL);
  338. omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
  339. OMAP2_CM_CLKSTCTRL);
  340. omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
  341. OMAP2_CM_CLKSTCTRL);
  342. omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
  343. OMAP2_CM_CLKSTCTRL);
  344. omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
  345. OMAP2_CM_CLKSTCTRL);
  346. omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
  347. OMAP2_CM_CLKSTCTRL);
  348. omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
  349. OMAP2_CM_CLKSTCTRL);
  350. omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
  351. OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
  352. omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
  353. CM_AUTOIDLE1);
  354. omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
  355. CM_AUTOIDLE2);
  356. omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
  357. CM_AUTOIDLE3);
  358. omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
  359. CM_AUTOIDLE);
  360. omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
  361. CM_AUTOIDLE);
  362. omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
  363. CM_AUTOIDLE);
  364. omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
  365. CM_AUTOIDLE);
  366. omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
  367. OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
  368. omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
  369. OMAP3430_CM_SLEEPDEP);
  370. omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
  371. OMAP3430_CM_SLEEPDEP);
  372. omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
  373. OMAP3430_CM_SLEEPDEP);
  374. omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
  375. OMAP3430_CM_SLEEPDEP);
  376. omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
  377. OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
  378. omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
  379. OMAP3_CM_CLKOUT_CTRL_OFFSET);
  380. }
  381. #endif