dmaengine.c 29 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  47. #include <linux/dma-mapping.h>
  48. #include <linux/init.h>
  49. #include <linux/module.h>
  50. #include <linux/mm.h>
  51. #include <linux/device.h>
  52. #include <linux/dmaengine.h>
  53. #include <linux/hardirq.h>
  54. #include <linux/spinlock.h>
  55. #include <linux/percpu.h>
  56. #include <linux/rcupdate.h>
  57. #include <linux/mutex.h>
  58. #include <linux/jiffies.h>
  59. #include <linux/rculist.h>
  60. #include <linux/idr.h>
  61. #include <linux/slab.h>
  62. #include <linux/acpi.h>
  63. #include <linux/acpi_dma.h>
  64. #include <linux/of_dma.h>
  65. static DEFINE_MUTEX(dma_list_mutex);
  66. static DEFINE_IDR(dma_idr);
  67. static LIST_HEAD(dma_device_list);
  68. static long dmaengine_ref_count;
  69. /* --- sysfs implementation --- */
  70. /**
  71. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  72. * @dev - device node
  73. *
  74. * Must be called under dma_list_mutex
  75. */
  76. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  77. {
  78. struct dma_chan_dev *chan_dev;
  79. chan_dev = container_of(dev, typeof(*chan_dev), device);
  80. return chan_dev->chan;
  81. }
  82. static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
  83. {
  84. struct dma_chan *chan;
  85. unsigned long count = 0;
  86. int i;
  87. int err;
  88. mutex_lock(&dma_list_mutex);
  89. chan = dev_to_dma_chan(dev);
  90. if (chan) {
  91. for_each_possible_cpu(i)
  92. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  93. err = sprintf(buf, "%lu\n", count);
  94. } else
  95. err = -ENODEV;
  96. mutex_unlock(&dma_list_mutex);
  97. return err;
  98. }
  99. static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
  100. char *buf)
  101. {
  102. struct dma_chan *chan;
  103. unsigned long count = 0;
  104. int i;
  105. int err;
  106. mutex_lock(&dma_list_mutex);
  107. chan = dev_to_dma_chan(dev);
  108. if (chan) {
  109. for_each_possible_cpu(i)
  110. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  111. err = sprintf(buf, "%lu\n", count);
  112. } else
  113. err = -ENODEV;
  114. mutex_unlock(&dma_list_mutex);
  115. return err;
  116. }
  117. static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
  118. {
  119. struct dma_chan *chan;
  120. int err;
  121. mutex_lock(&dma_list_mutex);
  122. chan = dev_to_dma_chan(dev);
  123. if (chan)
  124. err = sprintf(buf, "%d\n", chan->client_count);
  125. else
  126. err = -ENODEV;
  127. mutex_unlock(&dma_list_mutex);
  128. return err;
  129. }
  130. static struct device_attribute dma_attrs[] = {
  131. __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
  132. __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
  133. __ATTR(in_use, S_IRUGO, show_in_use, NULL),
  134. __ATTR_NULL
  135. };
  136. static void chan_dev_release(struct device *dev)
  137. {
  138. struct dma_chan_dev *chan_dev;
  139. chan_dev = container_of(dev, typeof(*chan_dev), device);
  140. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  141. mutex_lock(&dma_list_mutex);
  142. idr_remove(&dma_idr, chan_dev->dev_id);
  143. mutex_unlock(&dma_list_mutex);
  144. kfree(chan_dev->idr_ref);
  145. }
  146. kfree(chan_dev);
  147. }
  148. static struct class dma_devclass = {
  149. .name = "dma",
  150. .dev_attrs = dma_attrs,
  151. .dev_release = chan_dev_release,
  152. };
  153. /* --- client and device registration --- */
  154. #define dma_device_satisfies_mask(device, mask) \
  155. __dma_device_satisfies_mask((device), &(mask))
  156. static int
  157. __dma_device_satisfies_mask(struct dma_device *device,
  158. const dma_cap_mask_t *want)
  159. {
  160. dma_cap_mask_t has;
  161. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  162. DMA_TX_TYPE_END);
  163. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  164. }
  165. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  166. {
  167. return chan->device->dev->driver->owner;
  168. }
  169. /**
  170. * balance_ref_count - catch up the channel reference count
  171. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  172. *
  173. * balance_ref_count must be called under dma_list_mutex
  174. */
  175. static void balance_ref_count(struct dma_chan *chan)
  176. {
  177. struct module *owner = dma_chan_to_owner(chan);
  178. while (chan->client_count < dmaengine_ref_count) {
  179. __module_get(owner);
  180. chan->client_count++;
  181. }
  182. }
  183. /**
  184. * dma_chan_get - try to grab a dma channel's parent driver module
  185. * @chan - channel to grab
  186. *
  187. * Must be called under dma_list_mutex
  188. */
  189. static int dma_chan_get(struct dma_chan *chan)
  190. {
  191. int err = -ENODEV;
  192. struct module *owner = dma_chan_to_owner(chan);
  193. if (chan->client_count) {
  194. __module_get(owner);
  195. err = 0;
  196. } else if (try_module_get(owner))
  197. err = 0;
  198. if (err == 0)
  199. chan->client_count++;
  200. /* allocate upon first client reference */
  201. if (chan->client_count == 1 && err == 0) {
  202. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  203. if (desc_cnt < 0) {
  204. err = desc_cnt;
  205. chan->client_count = 0;
  206. module_put(owner);
  207. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  208. balance_ref_count(chan);
  209. }
  210. return err;
  211. }
  212. /**
  213. * dma_chan_put - drop a reference to a dma channel's parent driver module
  214. * @chan - channel to release
  215. *
  216. * Must be called under dma_list_mutex
  217. */
  218. static void dma_chan_put(struct dma_chan *chan)
  219. {
  220. if (!chan->client_count)
  221. return; /* this channel failed alloc_chan_resources */
  222. chan->client_count--;
  223. module_put(dma_chan_to_owner(chan));
  224. if (chan->client_count == 0)
  225. chan->device->device_free_chan_resources(chan);
  226. }
  227. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  228. {
  229. enum dma_status status;
  230. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  231. dma_async_issue_pending(chan);
  232. do {
  233. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  234. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  235. pr_err("%s: timeout!\n", __func__);
  236. return DMA_ERROR;
  237. }
  238. if (status != DMA_IN_PROGRESS)
  239. break;
  240. cpu_relax();
  241. } while (1);
  242. return status;
  243. }
  244. EXPORT_SYMBOL(dma_sync_wait);
  245. /**
  246. * dma_cap_mask_all - enable iteration over all operation types
  247. */
  248. static dma_cap_mask_t dma_cap_mask_all;
  249. /**
  250. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  251. * @chan - associated channel for this entry
  252. */
  253. struct dma_chan_tbl_ent {
  254. struct dma_chan *chan;
  255. };
  256. /**
  257. * channel_table - percpu lookup table for memory-to-memory offload providers
  258. */
  259. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  260. static int __init dma_channel_table_init(void)
  261. {
  262. enum dma_transaction_type cap;
  263. int err = 0;
  264. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  265. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  266. * but are not associated with an operation so they do not need
  267. * an entry in the channel_table
  268. */
  269. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  270. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  271. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  272. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  273. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  274. if (!channel_table[cap]) {
  275. err = -ENOMEM;
  276. break;
  277. }
  278. }
  279. if (err) {
  280. pr_err("initialization failure\n");
  281. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  282. if (channel_table[cap])
  283. free_percpu(channel_table[cap]);
  284. }
  285. return err;
  286. }
  287. arch_initcall(dma_channel_table_init);
  288. /**
  289. * dma_find_channel - find a channel to carry out the operation
  290. * @tx_type: transaction type
  291. */
  292. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  293. {
  294. return this_cpu_read(channel_table[tx_type]->chan);
  295. }
  296. EXPORT_SYMBOL(dma_find_channel);
  297. /*
  298. * net_dma_find_channel - find a channel for net_dma
  299. * net_dma has alignment requirements
  300. */
  301. struct dma_chan *net_dma_find_channel(void)
  302. {
  303. struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
  304. if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
  305. return NULL;
  306. return chan;
  307. }
  308. EXPORT_SYMBOL(net_dma_find_channel);
  309. /**
  310. * dma_issue_pending_all - flush all pending operations across all channels
  311. */
  312. void dma_issue_pending_all(void)
  313. {
  314. struct dma_device *device;
  315. struct dma_chan *chan;
  316. rcu_read_lock();
  317. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  318. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  319. continue;
  320. list_for_each_entry(chan, &device->channels, device_node)
  321. if (chan->client_count)
  322. device->device_issue_pending(chan);
  323. }
  324. rcu_read_unlock();
  325. }
  326. EXPORT_SYMBOL(dma_issue_pending_all);
  327. /**
  328. * dma_chan_is_local - returns true if the channel is in the same numa-node as the cpu
  329. */
  330. static bool dma_chan_is_local(struct dma_chan *chan, int cpu)
  331. {
  332. int node = dev_to_node(chan->device->dev);
  333. return node == -1 || cpumask_test_cpu(cpu, cpumask_of_node(node));
  334. }
  335. /**
  336. * min_chan - returns the channel with min count and in the same numa-node as the cpu
  337. * @cap: capability to match
  338. * @cpu: cpu index which the channel should be close to
  339. *
  340. * If some channels are close to the given cpu, the one with the lowest
  341. * reference count is returned. Otherwise, cpu is ignored and only the
  342. * reference count is taken into account.
  343. * Must be called under dma_list_mutex.
  344. */
  345. static struct dma_chan *min_chan(enum dma_transaction_type cap, int cpu)
  346. {
  347. struct dma_device *device;
  348. struct dma_chan *chan;
  349. struct dma_chan *min = NULL;
  350. struct dma_chan *localmin = NULL;
  351. list_for_each_entry(device, &dma_device_list, global_node) {
  352. if (!dma_has_cap(cap, device->cap_mask) ||
  353. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  354. continue;
  355. list_for_each_entry(chan, &device->channels, device_node) {
  356. if (!chan->client_count)
  357. continue;
  358. if (!min || chan->table_count < min->table_count)
  359. min = chan;
  360. if (dma_chan_is_local(chan, cpu))
  361. if (!localmin ||
  362. chan->table_count < localmin->table_count)
  363. localmin = chan;
  364. }
  365. }
  366. chan = localmin ? localmin : min;
  367. if (chan)
  368. chan->table_count++;
  369. return chan;
  370. }
  371. /**
  372. * dma_channel_rebalance - redistribute the available channels
  373. *
  374. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  375. * operation type) in the SMP case, and operation isolation (avoid
  376. * multi-tasking channels) in the non-SMP case. Must be called under
  377. * dma_list_mutex.
  378. */
  379. static void dma_channel_rebalance(void)
  380. {
  381. struct dma_chan *chan;
  382. struct dma_device *device;
  383. int cpu;
  384. int cap;
  385. /* undo the last distribution */
  386. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  387. for_each_possible_cpu(cpu)
  388. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  389. list_for_each_entry(device, &dma_device_list, global_node) {
  390. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  391. continue;
  392. list_for_each_entry(chan, &device->channels, device_node)
  393. chan->table_count = 0;
  394. }
  395. /* don't populate the channel_table if no clients are available */
  396. if (!dmaengine_ref_count)
  397. return;
  398. /* redistribute available channels */
  399. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  400. for_each_online_cpu(cpu) {
  401. chan = min_chan(cap, cpu);
  402. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  403. }
  404. }
  405. static struct dma_chan *private_candidate(const dma_cap_mask_t *mask,
  406. struct dma_device *dev,
  407. dma_filter_fn fn, void *fn_param)
  408. {
  409. struct dma_chan *chan;
  410. if (!__dma_device_satisfies_mask(dev, mask)) {
  411. pr_debug("%s: wrong capabilities\n", __func__);
  412. return NULL;
  413. }
  414. /* devices with multiple channels need special handling as we need to
  415. * ensure that all channels are either private or public.
  416. */
  417. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  418. list_for_each_entry(chan, &dev->channels, device_node) {
  419. /* some channels are already publicly allocated */
  420. if (chan->client_count)
  421. return NULL;
  422. }
  423. list_for_each_entry(chan, &dev->channels, device_node) {
  424. if (chan->client_count) {
  425. pr_debug("%s: %s busy\n",
  426. __func__, dma_chan_name(chan));
  427. continue;
  428. }
  429. if (fn && !fn(chan, fn_param)) {
  430. pr_debug("%s: %s filter said false\n",
  431. __func__, dma_chan_name(chan));
  432. continue;
  433. }
  434. return chan;
  435. }
  436. return NULL;
  437. }
  438. /**
  439. * dma_request_channel - try to allocate an exclusive channel
  440. * @mask: capabilities that the channel must satisfy
  441. * @fn: optional callback to disposition available channels
  442. * @fn_param: opaque parameter to pass to dma_filter_fn
  443. */
  444. struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
  445. dma_filter_fn fn, void *fn_param)
  446. {
  447. struct dma_device *device, *_d;
  448. struct dma_chan *chan = NULL;
  449. int err;
  450. /* Find a channel */
  451. mutex_lock(&dma_list_mutex);
  452. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  453. chan = private_candidate(mask, device, fn, fn_param);
  454. if (chan) {
  455. /* Found a suitable channel, try to grab, prep, and
  456. * return it. We first set DMA_PRIVATE to disable
  457. * balance_ref_count as this channel will not be
  458. * published in the general-purpose allocator
  459. */
  460. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  461. device->privatecnt++;
  462. err = dma_chan_get(chan);
  463. if (err == -ENODEV) {
  464. pr_debug("%s: %s module removed\n",
  465. __func__, dma_chan_name(chan));
  466. list_del_rcu(&device->global_node);
  467. } else if (err)
  468. pr_debug("%s: failed to get %s: (%d)\n",
  469. __func__, dma_chan_name(chan), err);
  470. else
  471. break;
  472. if (--device->privatecnt == 0)
  473. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  474. chan = NULL;
  475. }
  476. }
  477. mutex_unlock(&dma_list_mutex);
  478. pr_debug("%s: %s (%s)\n",
  479. __func__,
  480. chan ? "success" : "fail",
  481. chan ? dma_chan_name(chan) : NULL);
  482. return chan;
  483. }
  484. EXPORT_SYMBOL_GPL(__dma_request_channel);
  485. /**
  486. * dma_request_slave_channel - try to allocate an exclusive slave channel
  487. * @dev: pointer to client device structure
  488. * @name: slave channel name
  489. */
  490. struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name)
  491. {
  492. /* If device-tree is present get slave info from here */
  493. if (dev->of_node)
  494. return of_dma_request_slave_channel(dev->of_node, name);
  495. /* If device was enumerated by ACPI get slave info from here */
  496. if (ACPI_HANDLE(dev))
  497. return acpi_dma_request_slave_chan_by_name(dev, name);
  498. return NULL;
  499. }
  500. EXPORT_SYMBOL_GPL(dma_request_slave_channel);
  501. void dma_release_channel(struct dma_chan *chan)
  502. {
  503. mutex_lock(&dma_list_mutex);
  504. WARN_ONCE(chan->client_count != 1,
  505. "chan reference count %d != 1\n", chan->client_count);
  506. dma_chan_put(chan);
  507. /* drop PRIVATE cap enabled by __dma_request_channel() */
  508. if (--chan->device->privatecnt == 0)
  509. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  510. mutex_unlock(&dma_list_mutex);
  511. }
  512. EXPORT_SYMBOL_GPL(dma_release_channel);
  513. /**
  514. * dmaengine_get - register interest in dma_channels
  515. */
  516. void dmaengine_get(void)
  517. {
  518. struct dma_device *device, *_d;
  519. struct dma_chan *chan;
  520. int err;
  521. mutex_lock(&dma_list_mutex);
  522. dmaengine_ref_count++;
  523. /* try to grab channels */
  524. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  525. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  526. continue;
  527. list_for_each_entry(chan, &device->channels, device_node) {
  528. err = dma_chan_get(chan);
  529. if (err == -ENODEV) {
  530. /* module removed before we could use it */
  531. list_del_rcu(&device->global_node);
  532. break;
  533. } else if (err)
  534. pr_debug("%s: failed to get %s: (%d)\n",
  535. __func__, dma_chan_name(chan), err);
  536. }
  537. }
  538. /* if this is the first reference and there were channels
  539. * waiting we need to rebalance to get those channels
  540. * incorporated into the channel table
  541. */
  542. if (dmaengine_ref_count == 1)
  543. dma_channel_rebalance();
  544. mutex_unlock(&dma_list_mutex);
  545. }
  546. EXPORT_SYMBOL(dmaengine_get);
  547. /**
  548. * dmaengine_put - let dma drivers be removed when ref_count == 0
  549. */
  550. void dmaengine_put(void)
  551. {
  552. struct dma_device *device;
  553. struct dma_chan *chan;
  554. mutex_lock(&dma_list_mutex);
  555. dmaengine_ref_count--;
  556. BUG_ON(dmaengine_ref_count < 0);
  557. /* drop channel references */
  558. list_for_each_entry(device, &dma_device_list, global_node) {
  559. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  560. continue;
  561. list_for_each_entry(chan, &device->channels, device_node)
  562. dma_chan_put(chan);
  563. }
  564. mutex_unlock(&dma_list_mutex);
  565. }
  566. EXPORT_SYMBOL(dmaengine_put);
  567. static bool device_has_all_tx_types(struct dma_device *device)
  568. {
  569. /* A device that satisfies this test has channels that will never cause
  570. * an async_tx channel switch event as all possible operation types can
  571. * be handled.
  572. */
  573. #ifdef CONFIG_ASYNC_TX_DMA
  574. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  575. return false;
  576. #endif
  577. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  578. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  579. return false;
  580. #endif
  581. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  582. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  583. return false;
  584. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  585. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  586. return false;
  587. #endif
  588. #endif
  589. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  590. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  591. return false;
  592. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  593. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  594. return false;
  595. #endif
  596. #endif
  597. return true;
  598. }
  599. static int get_dma_id(struct dma_device *device)
  600. {
  601. int rc;
  602. mutex_lock(&dma_list_mutex);
  603. rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
  604. if (rc >= 0)
  605. device->dev_id = rc;
  606. mutex_unlock(&dma_list_mutex);
  607. return rc < 0 ? rc : 0;
  608. }
  609. /**
  610. * dma_async_device_register - registers DMA devices found
  611. * @device: &dma_device
  612. */
  613. int dma_async_device_register(struct dma_device *device)
  614. {
  615. int chancnt = 0, rc;
  616. struct dma_chan* chan;
  617. atomic_t *idr_ref;
  618. if (!device)
  619. return -ENODEV;
  620. /* validate device routines */
  621. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  622. !device->device_prep_dma_memcpy);
  623. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  624. !device->device_prep_dma_xor);
  625. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  626. !device->device_prep_dma_xor_val);
  627. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  628. !device->device_prep_dma_pq);
  629. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  630. !device->device_prep_dma_pq_val);
  631. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  632. !device->device_prep_dma_interrupt);
  633. BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
  634. !device->device_prep_dma_sg);
  635. BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
  636. !device->device_prep_dma_cyclic);
  637. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  638. !device->device_control);
  639. BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
  640. !device->device_prep_interleaved_dma);
  641. BUG_ON(!device->device_alloc_chan_resources);
  642. BUG_ON(!device->device_free_chan_resources);
  643. BUG_ON(!device->device_tx_status);
  644. BUG_ON(!device->device_issue_pending);
  645. BUG_ON(!device->dev);
  646. /* note: this only matters in the
  647. * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
  648. */
  649. if (device_has_all_tx_types(device))
  650. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  651. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  652. if (!idr_ref)
  653. return -ENOMEM;
  654. rc = get_dma_id(device);
  655. if (rc != 0) {
  656. kfree(idr_ref);
  657. return rc;
  658. }
  659. atomic_set(idr_ref, 0);
  660. /* represent channels in sysfs. Probably want devs too */
  661. list_for_each_entry(chan, &device->channels, device_node) {
  662. rc = -ENOMEM;
  663. chan->local = alloc_percpu(typeof(*chan->local));
  664. if (chan->local == NULL)
  665. goto err_out;
  666. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  667. if (chan->dev == NULL) {
  668. free_percpu(chan->local);
  669. chan->local = NULL;
  670. goto err_out;
  671. }
  672. chan->chan_id = chancnt++;
  673. chan->dev->device.class = &dma_devclass;
  674. chan->dev->device.parent = device->dev;
  675. chan->dev->chan = chan;
  676. chan->dev->idr_ref = idr_ref;
  677. chan->dev->dev_id = device->dev_id;
  678. atomic_inc(idr_ref);
  679. dev_set_name(&chan->dev->device, "dma%dchan%d",
  680. device->dev_id, chan->chan_id);
  681. rc = device_register(&chan->dev->device);
  682. if (rc) {
  683. free_percpu(chan->local);
  684. chan->local = NULL;
  685. kfree(chan->dev);
  686. atomic_dec(idr_ref);
  687. goto err_out;
  688. }
  689. chan->client_count = 0;
  690. }
  691. device->chancnt = chancnt;
  692. mutex_lock(&dma_list_mutex);
  693. /* take references on public channels */
  694. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  695. list_for_each_entry(chan, &device->channels, device_node) {
  696. /* if clients are already waiting for channels we need
  697. * to take references on their behalf
  698. */
  699. if (dma_chan_get(chan) == -ENODEV) {
  700. /* note we can only get here for the first
  701. * channel as the remaining channels are
  702. * guaranteed to get a reference
  703. */
  704. rc = -ENODEV;
  705. mutex_unlock(&dma_list_mutex);
  706. goto err_out;
  707. }
  708. }
  709. list_add_tail_rcu(&device->global_node, &dma_device_list);
  710. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  711. device->privatecnt++; /* Always private */
  712. dma_channel_rebalance();
  713. mutex_unlock(&dma_list_mutex);
  714. return 0;
  715. err_out:
  716. /* if we never registered a channel just release the idr */
  717. if (atomic_read(idr_ref) == 0) {
  718. mutex_lock(&dma_list_mutex);
  719. idr_remove(&dma_idr, device->dev_id);
  720. mutex_unlock(&dma_list_mutex);
  721. kfree(idr_ref);
  722. return rc;
  723. }
  724. list_for_each_entry(chan, &device->channels, device_node) {
  725. if (chan->local == NULL)
  726. continue;
  727. mutex_lock(&dma_list_mutex);
  728. chan->dev->chan = NULL;
  729. mutex_unlock(&dma_list_mutex);
  730. device_unregister(&chan->dev->device);
  731. free_percpu(chan->local);
  732. }
  733. return rc;
  734. }
  735. EXPORT_SYMBOL(dma_async_device_register);
  736. /**
  737. * dma_async_device_unregister - unregister a DMA device
  738. * @device: &dma_device
  739. *
  740. * This routine is called by dma driver exit routines, dmaengine holds module
  741. * references to prevent it being called while channels are in use.
  742. */
  743. void dma_async_device_unregister(struct dma_device *device)
  744. {
  745. struct dma_chan *chan;
  746. mutex_lock(&dma_list_mutex);
  747. list_del_rcu(&device->global_node);
  748. dma_channel_rebalance();
  749. mutex_unlock(&dma_list_mutex);
  750. list_for_each_entry(chan, &device->channels, device_node) {
  751. WARN_ONCE(chan->client_count,
  752. "%s called while %d clients hold a reference\n",
  753. __func__, chan->client_count);
  754. mutex_lock(&dma_list_mutex);
  755. chan->dev->chan = NULL;
  756. mutex_unlock(&dma_list_mutex);
  757. device_unregister(&chan->dev->device);
  758. free_percpu(chan->local);
  759. }
  760. }
  761. EXPORT_SYMBOL(dma_async_device_unregister);
  762. /**
  763. * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
  764. * @chan: DMA channel to offload copy to
  765. * @dest: destination address (virtual)
  766. * @src: source address (virtual)
  767. * @len: length
  768. *
  769. * Both @dest and @src must be mappable to a bus address according to the
  770. * DMA mapping API rules for streaming mappings.
  771. * Both @dest and @src must stay memory resident (kernel memory or locked
  772. * user space pages).
  773. */
  774. dma_cookie_t
  775. dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
  776. void *src, size_t len)
  777. {
  778. struct dma_device *dev = chan->device;
  779. struct dma_async_tx_descriptor *tx;
  780. dma_addr_t dma_dest, dma_src;
  781. dma_cookie_t cookie;
  782. unsigned long flags;
  783. dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
  784. dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
  785. flags = DMA_CTRL_ACK |
  786. DMA_COMPL_SRC_UNMAP_SINGLE |
  787. DMA_COMPL_DEST_UNMAP_SINGLE;
  788. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  789. if (!tx) {
  790. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  791. dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  792. return -ENOMEM;
  793. }
  794. tx->callback = NULL;
  795. cookie = tx->tx_submit(tx);
  796. preempt_disable();
  797. __this_cpu_add(chan->local->bytes_transferred, len);
  798. __this_cpu_inc(chan->local->memcpy_count);
  799. preempt_enable();
  800. return cookie;
  801. }
  802. EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
  803. /**
  804. * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
  805. * @chan: DMA channel to offload copy to
  806. * @page: destination page
  807. * @offset: offset in page to copy to
  808. * @kdata: source address (virtual)
  809. * @len: length
  810. *
  811. * Both @page/@offset and @kdata must be mappable to a bus address according
  812. * to the DMA mapping API rules for streaming mappings.
  813. * Both @page/@offset and @kdata must stay memory resident (kernel memory or
  814. * locked user space pages)
  815. */
  816. dma_cookie_t
  817. dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
  818. unsigned int offset, void *kdata, size_t len)
  819. {
  820. struct dma_device *dev = chan->device;
  821. struct dma_async_tx_descriptor *tx;
  822. dma_addr_t dma_dest, dma_src;
  823. dma_cookie_t cookie;
  824. unsigned long flags;
  825. dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
  826. dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
  827. flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
  828. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  829. if (!tx) {
  830. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  831. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  832. return -ENOMEM;
  833. }
  834. tx->callback = NULL;
  835. cookie = tx->tx_submit(tx);
  836. preempt_disable();
  837. __this_cpu_add(chan->local->bytes_transferred, len);
  838. __this_cpu_inc(chan->local->memcpy_count);
  839. preempt_enable();
  840. return cookie;
  841. }
  842. EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
  843. /**
  844. * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
  845. * @chan: DMA channel to offload copy to
  846. * @dest_pg: destination page
  847. * @dest_off: offset in page to copy to
  848. * @src_pg: source page
  849. * @src_off: offset in page to copy from
  850. * @len: length
  851. *
  852. * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
  853. * address according to the DMA mapping API rules for streaming mappings.
  854. * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
  855. * (kernel memory or locked user space pages).
  856. */
  857. dma_cookie_t
  858. dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
  859. unsigned int dest_off, struct page *src_pg, unsigned int src_off,
  860. size_t len)
  861. {
  862. struct dma_device *dev = chan->device;
  863. struct dma_async_tx_descriptor *tx;
  864. dma_addr_t dma_dest, dma_src;
  865. dma_cookie_t cookie;
  866. unsigned long flags;
  867. dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
  868. dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
  869. DMA_FROM_DEVICE);
  870. flags = DMA_CTRL_ACK;
  871. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  872. if (!tx) {
  873. dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
  874. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  875. return -ENOMEM;
  876. }
  877. tx->callback = NULL;
  878. cookie = tx->tx_submit(tx);
  879. preempt_disable();
  880. __this_cpu_add(chan->local->bytes_transferred, len);
  881. __this_cpu_inc(chan->local->memcpy_count);
  882. preempt_enable();
  883. return cookie;
  884. }
  885. EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
  886. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  887. struct dma_chan *chan)
  888. {
  889. tx->chan = chan;
  890. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  891. spin_lock_init(&tx->lock);
  892. #endif
  893. }
  894. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  895. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  896. * @tx: in-flight transaction to wait on
  897. */
  898. enum dma_status
  899. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  900. {
  901. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  902. if (!tx)
  903. return DMA_SUCCESS;
  904. while (tx->cookie == -EBUSY) {
  905. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  906. pr_err("%s timeout waiting for descriptor submission\n",
  907. __func__);
  908. return DMA_ERROR;
  909. }
  910. cpu_relax();
  911. }
  912. return dma_sync_wait(tx->chan, tx->cookie);
  913. }
  914. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  915. /* dma_run_dependencies - helper routine for dma drivers to process
  916. * (start) dependent operations on their target channel
  917. * @tx: transaction with dependencies
  918. */
  919. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  920. {
  921. struct dma_async_tx_descriptor *dep = txd_next(tx);
  922. struct dma_async_tx_descriptor *dep_next;
  923. struct dma_chan *chan;
  924. if (!dep)
  925. return;
  926. /* we'll submit tx->next now, so clear the link */
  927. txd_clear_next(tx);
  928. chan = dep->chan;
  929. /* keep submitting up until a channel switch is detected
  930. * in that case we will be called again as a result of
  931. * processing the interrupt from async_tx_channel_switch
  932. */
  933. for (; dep; dep = dep_next) {
  934. txd_lock(dep);
  935. txd_clear_parent(dep);
  936. dep_next = txd_next(dep);
  937. if (dep_next && dep_next->chan == chan)
  938. txd_clear_next(dep); /* ->next will be submitted */
  939. else
  940. dep_next = NULL; /* submit current dep and terminate */
  941. txd_unlock(dep);
  942. dep->tx_submit(dep);
  943. }
  944. chan->device->device_issue_pending(chan);
  945. }
  946. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  947. static int __init dma_bus_init(void)
  948. {
  949. return class_register(&dma_devclass);
  950. }
  951. arch_initcall(dma_bus_init);