sky2.c 85 KB

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  1. /*
  2. * New driver for Marvell Yukon 2 chipset.
  3. * Based on earlier sk98lin, and skge driver.
  4. *
  5. * This driver intentionally does not support all the features
  6. * of the original driver such as link fail-over and link management because
  7. * those should be done at higher levels.
  8. *
  9. * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24. */
  25. /*
  26. * TOTEST
  27. * - speed setting
  28. * - suspend/resume
  29. */
  30. #include <linux/config.h>
  31. #include <linux/crc32.h>
  32. #include <linux/kernel.h>
  33. #include <linux/version.h>
  34. #include <linux/module.h>
  35. #include <linux/netdevice.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/etherdevice.h>
  38. #include <linux/ethtool.h>
  39. #include <linux/pci.h>
  40. #include <linux/ip.h>
  41. #include <linux/tcp.h>
  42. #include <linux/in.h>
  43. #include <linux/delay.h>
  44. #include <linux/workqueue.h>
  45. #include <linux/if_vlan.h>
  46. #include <linux/prefetch.h>
  47. #include <linux/mii.h>
  48. #include <asm/irq.h>
  49. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  50. #define SKY2_VLAN_TAG_USED 1
  51. #endif
  52. #include "sky2.h"
  53. #define DRV_NAME "sky2"
  54. #define DRV_VERSION "0.11"
  55. #define PFX DRV_NAME " "
  56. /*
  57. * The Yukon II chipset takes 64 bit command blocks (called list elements)
  58. * that are organized into three (receive, transmit, status) different rings
  59. * similar to Tigon3. A transmit can require several elements;
  60. * a receive requires one (or two if using 64 bit dma).
  61. */
  62. #define is_ec_a1(hw) \
  63. unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
  64. (hw)->chip_rev == CHIP_REV_YU_EC_A1)
  65. #define RX_LE_SIZE 512
  66. #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
  67. #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
  68. #define RX_DEF_PENDING RX_MAX_PENDING
  69. #define TX_RING_SIZE 512
  70. #define TX_DEF_PENDING (TX_RING_SIZE - 1)
  71. #define TX_MIN_PENDING 64
  72. #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
  73. #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
  74. #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
  75. #define ETH_JUMBO_MTU 9000
  76. #define TX_WATCHDOG (5 * HZ)
  77. #define NAPI_WEIGHT 64
  78. #define PHY_RETRIES 1000
  79. static const u32 default_msg =
  80. NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  81. | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
  82. | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
  83. static int debug = -1; /* defaults above */
  84. module_param(debug, int, 0);
  85. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  86. static int copybreak __read_mostly = 256;
  87. module_param(copybreak, int, 0);
  88. MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  89. static const struct pci_device_id sky2_id_table[] = {
  90. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
  91. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
  92. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
  93. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
  94. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
  95. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
  96. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
  97. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
  98. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
  99. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
  100. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
  101. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
  102. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
  103. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
  104. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
  105. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
  106. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
  107. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
  108. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
  109. { 0 }
  110. };
  111. MODULE_DEVICE_TABLE(pci, sky2_id_table);
  112. /* Avoid conditionals by using array */
  113. static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
  114. static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
  115. /* This driver supports yukon2 chipset only */
  116. static const char *yukon2_name[] = {
  117. "XL", /* 0xb3 */
  118. "EC Ultra", /* 0xb4 */
  119. "UNKNOWN", /* 0xb5 */
  120. "EC", /* 0xb6 */
  121. "FE", /* 0xb7 */
  122. };
  123. /* Access to external PHY */
  124. static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
  125. {
  126. int i;
  127. gma_write16(hw, port, GM_SMI_DATA, val);
  128. gma_write16(hw, port, GM_SMI_CTRL,
  129. GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
  130. for (i = 0; i < PHY_RETRIES; i++) {
  131. if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
  132. return 0;
  133. udelay(1);
  134. }
  135. printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
  136. return -ETIMEDOUT;
  137. }
  138. static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
  139. {
  140. int i;
  141. gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
  142. | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
  143. for (i = 0; i < PHY_RETRIES; i++) {
  144. if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
  145. *val = gma_read16(hw, port, GM_SMI_DATA);
  146. return 0;
  147. }
  148. udelay(1);
  149. }
  150. return -ETIMEDOUT;
  151. }
  152. static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
  153. {
  154. u16 v;
  155. if (__gm_phy_read(hw, port, reg, &v) != 0)
  156. printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
  157. return v;
  158. }
  159. static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
  160. {
  161. u16 power_control;
  162. u32 reg1;
  163. int vaux;
  164. int ret = 0;
  165. pr_debug("sky2_set_power_state %d\n", state);
  166. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  167. pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
  168. vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
  169. (power_control & PCI_PM_CAP_PME_D3cold);
  170. pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
  171. power_control |= PCI_PM_CTRL_PME_STATUS;
  172. power_control &= ~(PCI_PM_CTRL_STATE_MASK);
  173. switch (state) {
  174. case PCI_D0:
  175. /* switch power to VCC (WA for VAUX problem) */
  176. sky2_write8(hw, B0_POWER_CTRL,
  177. PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
  178. /* disable Core Clock Division, */
  179. sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
  180. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
  181. /* enable bits are inverted */
  182. sky2_write8(hw, B2_Y2_CLK_GATE,
  183. Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
  184. Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
  185. Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
  186. else
  187. sky2_write8(hw, B2_Y2_CLK_GATE, 0);
  188. /* Turn off phy power saving */
  189. pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
  190. reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
  191. /* looks like this XL is back asswards .. */
  192. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
  193. reg1 |= PCI_Y2_PHY1_COMA;
  194. if (hw->ports > 1)
  195. reg1 |= PCI_Y2_PHY2_COMA;
  196. }
  197. pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
  198. break;
  199. case PCI_D3hot:
  200. case PCI_D3cold:
  201. /* Turn on phy power saving */
  202. pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
  203. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
  204. reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
  205. else
  206. reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
  207. pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
  208. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
  209. sky2_write8(hw, B2_Y2_CLK_GATE, 0);
  210. else
  211. /* enable bits are inverted */
  212. sky2_write8(hw, B2_Y2_CLK_GATE,
  213. Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
  214. Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
  215. Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
  216. /* switch power to VAUX */
  217. if (vaux && state != PCI_D3cold)
  218. sky2_write8(hw, B0_POWER_CTRL,
  219. (PC_VAUX_ENA | PC_VCC_ENA |
  220. PC_VAUX_ON | PC_VCC_OFF));
  221. break;
  222. default:
  223. printk(KERN_ERR PFX "Unknown power state %d\n", state);
  224. ret = -1;
  225. }
  226. pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
  227. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  228. return ret;
  229. }
  230. static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
  231. {
  232. u16 reg;
  233. /* disable all GMAC IRQ's */
  234. sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
  235. /* disable PHY IRQs */
  236. gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
  237. gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
  238. gma_write16(hw, port, GM_MC_ADDR_H2, 0);
  239. gma_write16(hw, port, GM_MC_ADDR_H3, 0);
  240. gma_write16(hw, port, GM_MC_ADDR_H4, 0);
  241. reg = gma_read16(hw, port, GM_RX_CTRL);
  242. reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
  243. gma_write16(hw, port, GM_RX_CTRL, reg);
  244. }
  245. static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
  246. {
  247. struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
  248. u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
  249. if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
  250. u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
  251. ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
  252. PHY_M_EC_MAC_S_MSK);
  253. ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
  254. if (hw->chip_id == CHIP_ID_YUKON_EC)
  255. ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
  256. else
  257. ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
  258. gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
  259. }
  260. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  261. if (hw->copper) {
  262. if (hw->chip_id == CHIP_ID_YUKON_FE) {
  263. /* enable automatic crossover */
  264. ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
  265. } else {
  266. /* disable energy detect */
  267. ctrl &= ~PHY_M_PC_EN_DET_MSK;
  268. /* enable automatic crossover */
  269. ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
  270. if (sky2->autoneg == AUTONEG_ENABLE &&
  271. hw->chip_id == CHIP_ID_YUKON_XL) {
  272. ctrl &= ~PHY_M_PC_DSC_MSK;
  273. ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
  274. }
  275. }
  276. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  277. } else {
  278. /* workaround for deviation #4.88 (CRC errors) */
  279. /* disable Automatic Crossover */
  280. ctrl &= ~PHY_M_PC_MDIX_MSK;
  281. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  282. if (hw->chip_id == CHIP_ID_YUKON_XL) {
  283. /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
  284. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
  285. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  286. ctrl &= ~PHY_M_MAC_MD_MSK;
  287. ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
  288. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  289. /* select page 1 to access Fiber registers */
  290. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
  291. }
  292. }
  293. ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
  294. if (sky2->autoneg == AUTONEG_DISABLE)
  295. ctrl &= ~PHY_CT_ANE;
  296. else
  297. ctrl |= PHY_CT_ANE;
  298. ctrl |= PHY_CT_RESET;
  299. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  300. ctrl = 0;
  301. ct1000 = 0;
  302. adv = PHY_AN_CSMA;
  303. if (sky2->autoneg == AUTONEG_ENABLE) {
  304. if (hw->copper) {
  305. if (sky2->advertising & ADVERTISED_1000baseT_Full)
  306. ct1000 |= PHY_M_1000C_AFD;
  307. if (sky2->advertising & ADVERTISED_1000baseT_Half)
  308. ct1000 |= PHY_M_1000C_AHD;
  309. if (sky2->advertising & ADVERTISED_100baseT_Full)
  310. adv |= PHY_M_AN_100_FD;
  311. if (sky2->advertising & ADVERTISED_100baseT_Half)
  312. adv |= PHY_M_AN_100_HD;
  313. if (sky2->advertising & ADVERTISED_10baseT_Full)
  314. adv |= PHY_M_AN_10_FD;
  315. if (sky2->advertising & ADVERTISED_10baseT_Half)
  316. adv |= PHY_M_AN_10_HD;
  317. } else /* special defines for FIBER (88E1011S only) */
  318. adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
  319. /* Set Flow-control capabilities */
  320. if (sky2->tx_pause && sky2->rx_pause)
  321. adv |= PHY_AN_PAUSE_CAP; /* symmetric */
  322. else if (sky2->rx_pause && !sky2->tx_pause)
  323. adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
  324. else if (!sky2->rx_pause && sky2->tx_pause)
  325. adv |= PHY_AN_PAUSE_ASYM; /* local */
  326. /* Restart Auto-negotiation */
  327. ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
  328. } else {
  329. /* forced speed/duplex settings */
  330. ct1000 = PHY_M_1000C_MSE;
  331. if (sky2->duplex == DUPLEX_FULL)
  332. ctrl |= PHY_CT_DUP_MD;
  333. switch (sky2->speed) {
  334. case SPEED_1000:
  335. ctrl |= PHY_CT_SP1000;
  336. break;
  337. case SPEED_100:
  338. ctrl |= PHY_CT_SP100;
  339. break;
  340. }
  341. ctrl |= PHY_CT_RESET;
  342. }
  343. if (hw->chip_id != CHIP_ID_YUKON_FE)
  344. gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
  345. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
  346. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  347. /* Setup Phy LED's */
  348. ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
  349. ledover = 0;
  350. switch (hw->chip_id) {
  351. case CHIP_ID_YUKON_FE:
  352. /* on 88E3082 these bits are at 11..9 (shifted left) */
  353. ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
  354. ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
  355. /* delete ACT LED control bits */
  356. ctrl &= ~PHY_M_FELP_LED1_MSK;
  357. /* change ACT LED control to blink mode */
  358. ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
  359. gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
  360. break;
  361. case CHIP_ID_YUKON_XL:
  362. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  363. /* select page 3 to access LED control register */
  364. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  365. /* set LED Function Control register */
  366. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
  367. PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
  368. PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
  369. PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
  370. /* set Polarity Control register */
  371. gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
  372. (PHY_M_POLC_LS1_P_MIX(4) |
  373. PHY_M_POLC_IS0_P_MIX(4) |
  374. PHY_M_POLC_LOS_CTRL(2) |
  375. PHY_M_POLC_INIT_CTRL(2) |
  376. PHY_M_POLC_STA1_CTRL(2) |
  377. PHY_M_POLC_STA0_CTRL(2)));
  378. /* restore page register */
  379. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  380. break;
  381. default:
  382. /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
  383. ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
  384. /* turn off the Rx LED (LED_RX) */
  385. ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
  386. }
  387. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
  388. if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
  389. /* turn on 100 Mbps LED (LED_LINK100) */
  390. ledover |= PHY_M_LED_MO_100(MO_LED_ON);
  391. }
  392. if (ledover)
  393. gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
  394. /* Enable phy interrupt on auto-negotiation complete (or link up) */
  395. if (sky2->autoneg == AUTONEG_ENABLE)
  396. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
  397. else
  398. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
  399. }
  400. /* Force a renegotiation */
  401. static void sky2_phy_reinit(struct sky2_port *sky2)
  402. {
  403. down(&sky2->phy_sema);
  404. sky2_phy_init(sky2->hw, sky2->port);
  405. up(&sky2->phy_sema);
  406. }
  407. static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
  408. {
  409. struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
  410. u16 reg;
  411. int i;
  412. const u8 *addr = hw->dev[port]->dev_addr;
  413. sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  414. sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
  415. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
  416. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
  417. /* WA DEV_472 -- looks like crossed wires on port 2 */
  418. /* clear GMAC 1 Control reset */
  419. sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
  420. do {
  421. sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
  422. sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
  423. } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
  424. gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
  425. gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
  426. }
  427. if (sky2->autoneg == AUTONEG_DISABLE) {
  428. reg = gma_read16(hw, port, GM_GP_CTRL);
  429. reg |= GM_GPCR_AU_ALL_DIS;
  430. gma_write16(hw, port, GM_GP_CTRL, reg);
  431. gma_read16(hw, port, GM_GP_CTRL);
  432. switch (sky2->speed) {
  433. case SPEED_1000:
  434. reg |= GM_GPCR_SPEED_1000;
  435. /* fallthru */
  436. case SPEED_100:
  437. reg |= GM_GPCR_SPEED_100;
  438. }
  439. if (sky2->duplex == DUPLEX_FULL)
  440. reg |= GM_GPCR_DUP_FULL;
  441. } else
  442. reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
  443. if (!sky2->tx_pause && !sky2->rx_pause) {
  444. sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  445. reg |=
  446. GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
  447. } else if (sky2->tx_pause && !sky2->rx_pause) {
  448. /* disable Rx flow-control */
  449. reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
  450. }
  451. gma_write16(hw, port, GM_GP_CTRL, reg);
  452. sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
  453. down(&sky2->phy_sema);
  454. sky2_phy_init(hw, port);
  455. up(&sky2->phy_sema);
  456. /* MIB clear */
  457. reg = gma_read16(hw, port, GM_PHY_ADDR);
  458. gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
  459. for (i = 0; i < GM_MIB_CNT_SIZE; i++)
  460. gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
  461. gma_write16(hw, port, GM_PHY_ADDR, reg);
  462. /* transmit control */
  463. gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
  464. /* receive control reg: unicast + multicast + no FCS */
  465. gma_write16(hw, port, GM_RX_CTRL,
  466. GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
  467. /* transmit flow control */
  468. gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
  469. /* transmit parameter */
  470. gma_write16(hw, port, GM_TX_PARAM,
  471. TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
  472. TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
  473. TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
  474. TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
  475. /* serial mode register */
  476. reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
  477. GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
  478. if (hw->dev[port]->mtu > ETH_DATA_LEN)
  479. reg |= GM_SMOD_JUMBO_ENA;
  480. gma_write16(hw, port, GM_SERIAL_MODE, reg);
  481. /* virtual address for data */
  482. gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
  483. /* physical address: used for pause frames */
  484. gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
  485. /* ignore counter overflows */
  486. gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
  487. gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
  488. gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
  489. /* Configure Rx MAC FIFO */
  490. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
  491. sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
  492. GMF_RX_CTRL_DEF);
  493. /* Flush Rx MAC FIFO on any flow control or error */
  494. sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
  495. /* Set threshold to 0xa (64 bytes)
  496. * ASF disabled so no need to do WA dev #4.30
  497. */
  498. sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
  499. /* Configure Tx MAC FIFO */
  500. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
  501. sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
  502. if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
  503. sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
  504. sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
  505. if (hw->dev[port]->mtu > ETH_DATA_LEN) {
  506. /* set Tx GMAC FIFO Almost Empty Threshold */
  507. sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
  508. /* Disable Store & Forward mode for TX */
  509. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
  510. }
  511. }
  512. }
  513. static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
  514. {
  515. u32 end;
  516. start /= 8;
  517. len /= 8;
  518. end = start + len - 1;
  519. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
  520. sky2_write32(hw, RB_ADDR(q, RB_START), start);
  521. sky2_write32(hw, RB_ADDR(q, RB_END), end);
  522. sky2_write32(hw, RB_ADDR(q, RB_WP), start);
  523. sky2_write32(hw, RB_ADDR(q, RB_RP), start);
  524. if (q == Q_R1 || q == Q_R2) {
  525. u32 rxup, rxlo;
  526. rxlo = len/2;
  527. rxup = rxlo + len/4;
  528. /* Set thresholds on receive queue's */
  529. sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
  530. sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
  531. } else {
  532. /* Enable store & forward on Tx queue's because
  533. * Tx FIFO is only 1K on Yukon
  534. */
  535. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
  536. }
  537. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
  538. sky2_read8(hw, RB_ADDR(q, RB_CTRL));
  539. }
  540. /* Setup Bus Memory Interface */
  541. static void sky2_qset(struct sky2_hw *hw, u16 q)
  542. {
  543. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
  544. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
  545. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
  546. sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
  547. }
  548. /* Setup prefetch unit registers. This is the interface between
  549. * hardware and driver list elements
  550. */
  551. static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
  552. u64 addr, u32 last)
  553. {
  554. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
  555. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
  556. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
  557. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
  558. sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
  559. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
  560. sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
  561. }
  562. static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
  563. {
  564. struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
  565. sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
  566. return le;
  567. }
  568. /*
  569. * This is a workaround code taken from SysKonnect sk98lin driver
  570. * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
  571. */
  572. static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
  573. u16 idx, u16 *last, u16 size)
  574. {
  575. if (is_ec_a1(hw) && idx < *last) {
  576. u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
  577. if (hwget == 0) {
  578. /* Start prefetching again */
  579. sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
  580. goto setnew;
  581. }
  582. if (hwget == size - 1) {
  583. /* set watermark to one list element */
  584. sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
  585. /* set put index to first list element */
  586. sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
  587. } else /* have hardware go to end of list */
  588. sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
  589. size - 1);
  590. } else {
  591. setnew:
  592. sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
  593. }
  594. *last = idx;
  595. }
  596. static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
  597. {
  598. struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
  599. sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
  600. return le;
  601. }
  602. /* Return high part of DMA address (could be 32 or 64 bit) */
  603. static inline u32 high32(dma_addr_t a)
  604. {
  605. return (a >> 16) >> 16;
  606. }
  607. /* Build description to hardware about buffer */
  608. static inline void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
  609. {
  610. struct sky2_rx_le *le;
  611. u32 hi = high32(map);
  612. u16 len = sky2->rx_bufsize;
  613. if (sky2->rx_addr64 != hi) {
  614. le = sky2_next_rx(sky2);
  615. le->addr = cpu_to_le32(hi);
  616. le->ctrl = 0;
  617. le->opcode = OP_ADDR64 | HW_OWNER;
  618. sky2->rx_addr64 = high32(map + len);
  619. }
  620. le = sky2_next_rx(sky2);
  621. le->addr = cpu_to_le32((u32) map);
  622. le->length = cpu_to_le16(len);
  623. le->ctrl = 0;
  624. le->opcode = OP_PACKET | HW_OWNER;
  625. }
  626. /* Tell chip where to start receive checksum.
  627. * Actually has two checksums, but set both same to avoid possible byte
  628. * order problems.
  629. */
  630. static void rx_set_checksum(struct sky2_port *sky2)
  631. {
  632. struct sky2_rx_le *le;
  633. le = sky2_next_rx(sky2);
  634. le->addr = (ETH_HLEN << 16) | ETH_HLEN;
  635. le->ctrl = 0;
  636. le->opcode = OP_TCPSTART | HW_OWNER;
  637. sky2_write32(sky2->hw,
  638. Q_ADDR(rxqaddr[sky2->port], Q_CSR),
  639. sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
  640. }
  641. /*
  642. * The RX Stop command will not work for Yukon-2 if the BMU does not
  643. * reach the end of packet and since we can't make sure that we have
  644. * incoming data, we must reset the BMU while it is not doing a DMA
  645. * transfer. Since it is possible that the RX path is still active,
  646. * the RX RAM buffer will be stopped first, so any possible incoming
  647. * data will not trigger a DMA. After the RAM buffer is stopped, the
  648. * BMU is polled until any DMA in progress is ended and only then it
  649. * will be reset.
  650. */
  651. static void sky2_rx_stop(struct sky2_port *sky2)
  652. {
  653. struct sky2_hw *hw = sky2->hw;
  654. unsigned rxq = rxqaddr[sky2->port];
  655. int i;
  656. /* disable the RAM Buffer receive queue */
  657. sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
  658. for (i = 0; i < 0xffff; i++)
  659. if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
  660. == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
  661. goto stopped;
  662. printk(KERN_WARNING PFX "%s: receiver stop failed\n",
  663. sky2->netdev->name);
  664. stopped:
  665. sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
  666. /* reset the Rx prefetch unit */
  667. sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
  668. }
  669. /* Clean out receive buffer area, assumes receiver hardware stopped */
  670. static void sky2_rx_clean(struct sky2_port *sky2)
  671. {
  672. unsigned i;
  673. memset(sky2->rx_le, 0, RX_LE_BYTES);
  674. for (i = 0; i < sky2->rx_pending; i++) {
  675. struct ring_info *re = sky2->rx_ring + i;
  676. if (re->skb) {
  677. pci_unmap_single(sky2->hw->pdev,
  678. re->mapaddr, sky2->rx_bufsize,
  679. PCI_DMA_FROMDEVICE);
  680. kfree_skb(re->skb);
  681. re->skb = NULL;
  682. }
  683. }
  684. }
  685. /* Basic MII support */
  686. static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  687. {
  688. struct mii_ioctl_data *data = if_mii(ifr);
  689. struct sky2_port *sky2 = netdev_priv(dev);
  690. struct sky2_hw *hw = sky2->hw;
  691. int err = -EOPNOTSUPP;
  692. if (!netif_running(dev))
  693. return -ENODEV; /* Phy still in reset */
  694. switch(cmd) {
  695. case SIOCGMIIPHY:
  696. data->phy_id = PHY_ADDR_MARV;
  697. /* fallthru */
  698. case SIOCGMIIREG: {
  699. u16 val = 0;
  700. down(&sky2->phy_sema);
  701. err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
  702. up(&sky2->phy_sema);
  703. data->val_out = val;
  704. break;
  705. }
  706. case SIOCSMIIREG:
  707. if (!capable(CAP_NET_ADMIN))
  708. return -EPERM;
  709. down(&sky2->phy_sema);
  710. err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
  711. data->val_in);
  712. up(&sky2->phy_sema);
  713. break;
  714. }
  715. return err;
  716. }
  717. #ifdef SKY2_VLAN_TAG_USED
  718. static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  719. {
  720. struct sky2_port *sky2 = netdev_priv(dev);
  721. struct sky2_hw *hw = sky2->hw;
  722. u16 port = sky2->port;
  723. spin_lock(&sky2->tx_lock);
  724. sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
  725. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
  726. sky2->vlgrp = grp;
  727. spin_unlock(&sky2->tx_lock);
  728. }
  729. static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
  730. {
  731. struct sky2_port *sky2 = netdev_priv(dev);
  732. struct sky2_hw *hw = sky2->hw;
  733. u16 port = sky2->port;
  734. spin_lock(&sky2->tx_lock);
  735. sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
  736. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
  737. if (sky2->vlgrp)
  738. sky2->vlgrp->vlan_devices[vid] = NULL;
  739. spin_unlock(&sky2->tx_lock);
  740. }
  741. #endif
  742. /*
  743. * Allocate and setup receiver buffer pool.
  744. * In case of 64 bit dma, there are 2X as many list elements
  745. * available as ring entries
  746. * and need to reserve one list element so we don't wrap around.
  747. *
  748. * It appears the hardware has a bug in the FIFO logic that
  749. * cause it to hang if the FIFO gets overrun and the receive buffer
  750. * is not aligned. This means we can't use skb_reserve to align
  751. * the IP header.
  752. */
  753. static int sky2_rx_start(struct sky2_port *sky2)
  754. {
  755. struct sky2_hw *hw = sky2->hw;
  756. unsigned rxq = rxqaddr[sky2->port];
  757. int i;
  758. sky2->rx_put = sky2->rx_next = 0;
  759. sky2_qset(hw, rxq);
  760. sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
  761. rx_set_checksum(sky2);
  762. for (i = 0; i < sky2->rx_pending; i++) {
  763. struct ring_info *re = sky2->rx_ring + i;
  764. re->skb = dev_alloc_skb(sky2->rx_bufsize);
  765. if (!re->skb)
  766. goto nomem;
  767. re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
  768. sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
  769. sky2_rx_add(sky2, re->mapaddr);
  770. }
  771. /* Tell chip about available buffers */
  772. sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
  773. sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
  774. return 0;
  775. nomem:
  776. sky2_rx_clean(sky2);
  777. return -ENOMEM;
  778. }
  779. /* Bring up network interface. */
  780. static int sky2_up(struct net_device *dev)
  781. {
  782. struct sky2_port *sky2 = netdev_priv(dev);
  783. struct sky2_hw *hw = sky2->hw;
  784. unsigned port = sky2->port;
  785. u32 ramsize, rxspace;
  786. int err = -ENOMEM;
  787. if (netif_msg_ifup(sky2))
  788. printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
  789. /* must be power of 2 */
  790. sky2->tx_le = pci_alloc_consistent(hw->pdev,
  791. TX_RING_SIZE *
  792. sizeof(struct sky2_tx_le),
  793. &sky2->tx_le_map);
  794. if (!sky2->tx_le)
  795. goto err_out;
  796. sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
  797. GFP_KERNEL);
  798. if (!sky2->tx_ring)
  799. goto err_out;
  800. sky2->tx_prod = sky2->tx_cons = 0;
  801. sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
  802. &sky2->rx_le_map);
  803. if (!sky2->rx_le)
  804. goto err_out;
  805. memset(sky2->rx_le, 0, RX_LE_BYTES);
  806. sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
  807. GFP_KERNEL);
  808. if (!sky2->rx_ring)
  809. goto err_out;
  810. sky2_mac_init(hw, port);
  811. /* Configure RAM buffers */
  812. if (hw->chip_id == CHIP_ID_YUKON_FE ||
  813. (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
  814. ramsize = 4096;
  815. else {
  816. u8 e0 = sky2_read8(hw, B2_E_0);
  817. ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
  818. }
  819. /* 2/3 for Rx */
  820. rxspace = (2 * ramsize) / 3;
  821. sky2_ramset(hw, rxqaddr[port], 0, rxspace);
  822. sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
  823. /* Make sure SyncQ is disabled */
  824. sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
  825. RB_RST_SET);
  826. sky2_qset(hw, txqaddr[port]);
  827. if (hw->chip_id == CHIP_ID_YUKON_EC_U)
  828. sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
  829. sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
  830. TX_RING_SIZE - 1);
  831. err = sky2_rx_start(sky2);
  832. if (err)
  833. goto err_out;
  834. /* Enable interrupts from phy/mac for port */
  835. hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
  836. sky2_write32(hw, B0_IMSK, hw->intr_mask);
  837. return 0;
  838. err_out:
  839. if (sky2->rx_le) {
  840. pci_free_consistent(hw->pdev, RX_LE_BYTES,
  841. sky2->rx_le, sky2->rx_le_map);
  842. sky2->rx_le = NULL;
  843. }
  844. if (sky2->tx_le) {
  845. pci_free_consistent(hw->pdev,
  846. TX_RING_SIZE * sizeof(struct sky2_tx_le),
  847. sky2->tx_le, sky2->tx_le_map);
  848. sky2->tx_le = NULL;
  849. }
  850. kfree(sky2->tx_ring);
  851. kfree(sky2->rx_ring);
  852. sky2->tx_ring = NULL;
  853. sky2->rx_ring = NULL;
  854. return err;
  855. }
  856. /* Modular subtraction in ring */
  857. static inline int tx_dist(unsigned tail, unsigned head)
  858. {
  859. return (head - tail) % TX_RING_SIZE;
  860. }
  861. /* Number of list elements available for next tx */
  862. static inline int tx_avail(const struct sky2_port *sky2)
  863. {
  864. return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
  865. }
  866. /* Estimate of number of transmit list elements required */
  867. static inline unsigned tx_le_req(const struct sk_buff *skb)
  868. {
  869. unsigned count;
  870. count = sizeof(dma_addr_t) / sizeof(u32);
  871. count += skb_shinfo(skb)->nr_frags * count;
  872. if (skb_shinfo(skb)->tso_size)
  873. ++count;
  874. if (skb->ip_summed == CHECKSUM_HW)
  875. ++count;
  876. return count;
  877. }
  878. /*
  879. * Put one packet in ring for transmit.
  880. * A single packet can generate multiple list elements, and
  881. * the number of ring elements will probably be less than the number
  882. * of list elements used.
  883. *
  884. * No BH disabling for tx_lock here (like tg3)
  885. */
  886. static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
  887. {
  888. struct sky2_port *sky2 = netdev_priv(dev);
  889. struct sky2_hw *hw = sky2->hw;
  890. struct sky2_tx_le *le = NULL;
  891. struct tx_ring_info *re;
  892. unsigned i, len;
  893. dma_addr_t mapping;
  894. u32 addr64;
  895. u16 mss;
  896. u8 ctrl;
  897. if (!spin_trylock(&sky2->tx_lock))
  898. return NETDEV_TX_LOCKED;
  899. if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
  900. /* There is a known but harmless race with lockless tx
  901. * and netif_stop_queue.
  902. */
  903. if (!netif_queue_stopped(dev)) {
  904. netif_stop_queue(dev);
  905. printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
  906. dev->name);
  907. }
  908. spin_unlock(&sky2->tx_lock);
  909. return NETDEV_TX_BUSY;
  910. }
  911. if (unlikely(netif_msg_tx_queued(sky2)))
  912. printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
  913. dev->name, sky2->tx_prod, skb->len);
  914. len = skb_headlen(skb);
  915. mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
  916. addr64 = high32(mapping);
  917. re = sky2->tx_ring + sky2->tx_prod;
  918. /* Send high bits if changed or crosses boundary */
  919. if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
  920. le = get_tx_le(sky2);
  921. le->tx.addr = cpu_to_le32(addr64);
  922. le->ctrl = 0;
  923. le->opcode = OP_ADDR64 | HW_OWNER;
  924. sky2->tx_addr64 = high32(mapping + len);
  925. }
  926. /* Check for TCP Segmentation Offload */
  927. mss = skb_shinfo(skb)->tso_size;
  928. if (mss != 0) {
  929. /* just drop the packet if non-linear expansion fails */
  930. if (skb_header_cloned(skb) &&
  931. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  932. dev_kfree_skb_any(skb);
  933. goto out_unlock;
  934. }
  935. mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
  936. mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
  937. mss += ETH_HLEN;
  938. }
  939. if (mss != sky2->tx_last_mss) {
  940. le = get_tx_le(sky2);
  941. le->tx.tso.size = cpu_to_le16(mss);
  942. le->tx.tso.rsvd = 0;
  943. le->opcode = OP_LRGLEN | HW_OWNER;
  944. le->ctrl = 0;
  945. sky2->tx_last_mss = mss;
  946. }
  947. ctrl = 0;
  948. #ifdef SKY2_VLAN_TAG_USED
  949. /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
  950. if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
  951. if (!le) {
  952. le = get_tx_le(sky2);
  953. le->tx.addr = 0;
  954. le->opcode = OP_VLAN|HW_OWNER;
  955. le->ctrl = 0;
  956. } else
  957. le->opcode |= OP_VLAN;
  958. le->length = cpu_to_be16(vlan_tx_tag_get(skb));
  959. ctrl |= INS_VLAN;
  960. }
  961. #endif
  962. /* Handle TCP checksum offload */
  963. if (skb->ip_summed == CHECKSUM_HW) {
  964. u16 hdr = skb->h.raw - skb->data;
  965. u16 offset = hdr + skb->csum;
  966. ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
  967. if (skb->nh.iph->protocol == IPPROTO_UDP)
  968. ctrl |= UDPTCP;
  969. le = get_tx_le(sky2);
  970. le->tx.csum.start = cpu_to_le16(hdr);
  971. le->tx.csum.offset = cpu_to_le16(offset);
  972. le->length = 0; /* initial checksum value */
  973. le->ctrl = 1; /* one packet */
  974. le->opcode = OP_TCPLISW | HW_OWNER;
  975. }
  976. le = get_tx_le(sky2);
  977. le->tx.addr = cpu_to_le32((u32) mapping);
  978. le->length = cpu_to_le16(len);
  979. le->ctrl = ctrl;
  980. le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
  981. /* Record the transmit mapping info */
  982. re->skb = skb;
  983. pci_unmap_addr_set(re, mapaddr, mapping);
  984. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  985. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  986. struct tx_ring_info *fre;
  987. mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
  988. frag->size, PCI_DMA_TODEVICE);
  989. addr64 = (mapping >> 16) >> 16;
  990. if (addr64 != sky2->tx_addr64) {
  991. le = get_tx_le(sky2);
  992. le->tx.addr = cpu_to_le32(addr64);
  993. le->ctrl = 0;
  994. le->opcode = OP_ADDR64 | HW_OWNER;
  995. sky2->tx_addr64 = addr64;
  996. }
  997. le = get_tx_le(sky2);
  998. le->tx.addr = cpu_to_le32((u32) mapping);
  999. le->length = cpu_to_le16(frag->size);
  1000. le->ctrl = ctrl;
  1001. le->opcode = OP_BUFFER | HW_OWNER;
  1002. fre = sky2->tx_ring
  1003. + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
  1004. pci_unmap_addr_set(fre, mapaddr, mapping);
  1005. }
  1006. re->idx = sky2->tx_prod;
  1007. le->ctrl |= EOP;
  1008. sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
  1009. &sky2->tx_last_put, TX_RING_SIZE);
  1010. if (tx_avail(sky2) <= MAX_SKB_TX_LE)
  1011. netif_stop_queue(dev);
  1012. out_unlock:
  1013. mmiowb();
  1014. spin_unlock(&sky2->tx_lock);
  1015. dev->trans_start = jiffies;
  1016. return NETDEV_TX_OK;
  1017. }
  1018. /*
  1019. * Free ring elements from starting at tx_cons until "done"
  1020. *
  1021. * NB: the hardware will tell us about partial completion of multi-part
  1022. * buffers; these are deferred until completion.
  1023. */
  1024. static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
  1025. {
  1026. struct net_device *dev = sky2->netdev;
  1027. struct pci_dev *pdev = sky2->hw->pdev;
  1028. u16 nxt, put;
  1029. unsigned i;
  1030. BUG_ON(done >= TX_RING_SIZE);
  1031. if (unlikely(netif_msg_tx_done(sky2)))
  1032. printk(KERN_DEBUG "%s: tx done, up to %u\n",
  1033. dev->name, done);
  1034. for (put = sky2->tx_cons; put != done; put = nxt) {
  1035. struct tx_ring_info *re = sky2->tx_ring + put;
  1036. struct sk_buff *skb = re->skb;
  1037. nxt = re->idx;
  1038. BUG_ON(nxt >= TX_RING_SIZE);
  1039. prefetch(sky2->tx_ring + nxt);
  1040. /* Check for partial status */
  1041. if (tx_dist(put, done) < tx_dist(put, nxt))
  1042. break;
  1043. skb = re->skb;
  1044. pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
  1045. skb_headlen(skb), PCI_DMA_TODEVICE);
  1046. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  1047. struct tx_ring_info *fre;
  1048. fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
  1049. pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
  1050. skb_shinfo(skb)->frags[i].size,
  1051. PCI_DMA_TODEVICE);
  1052. }
  1053. dev_kfree_skb_any(skb);
  1054. }
  1055. spin_lock(&sky2->tx_lock);
  1056. sky2->tx_cons = put;
  1057. if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
  1058. netif_wake_queue(dev);
  1059. spin_unlock(&sky2->tx_lock);
  1060. }
  1061. /* Cleanup all untransmitted buffers, assume transmitter not running */
  1062. static void sky2_tx_clean(struct sky2_port *sky2)
  1063. {
  1064. sky2_tx_complete(sky2, sky2->tx_prod);
  1065. }
  1066. /* Network shutdown */
  1067. static int sky2_down(struct net_device *dev)
  1068. {
  1069. struct sky2_port *sky2 = netdev_priv(dev);
  1070. struct sky2_hw *hw = sky2->hw;
  1071. unsigned port = sky2->port;
  1072. u16 ctrl;
  1073. /* Never really got started! */
  1074. if (!sky2->tx_le)
  1075. return 0;
  1076. if (netif_msg_ifdown(sky2))
  1077. printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
  1078. /* Stop more packets from being queued */
  1079. netif_stop_queue(dev);
  1080. /* Disable port IRQ */
  1081. local_irq_disable();
  1082. hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
  1083. sky2_write32(hw, B0_IMSK, hw->intr_mask);
  1084. local_irq_enable();
  1085. flush_scheduled_work();
  1086. sky2_phy_reset(hw, port);
  1087. /* Stop transmitter */
  1088. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
  1089. sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
  1090. sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
  1091. RB_RST_SET | RB_DIS_OP_MD);
  1092. ctrl = gma_read16(hw, port, GM_GP_CTRL);
  1093. ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
  1094. gma_write16(hw, port, GM_GP_CTRL, ctrl);
  1095. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  1096. /* Workaround shared GMAC reset */
  1097. if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
  1098. && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
  1099. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
  1100. /* Disable Force Sync bit and Enable Alloc bit */
  1101. sky2_write8(hw, SK_REG(port, TXA_CTRL),
  1102. TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
  1103. /* Stop Interval Timer and Limit Counter of Tx Arbiter */
  1104. sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
  1105. sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
  1106. /* Reset the PCI FIFO of the async Tx queue */
  1107. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
  1108. BMU_RST_SET | BMU_FIFO_RST);
  1109. /* Reset the Tx prefetch units */
  1110. sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
  1111. PREF_UNIT_RST_SET);
  1112. sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
  1113. sky2_rx_stop(sky2);
  1114. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
  1115. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  1116. /* turn off LED's */
  1117. sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
  1118. synchronize_irq(hw->pdev->irq);
  1119. sky2_tx_clean(sky2);
  1120. sky2_rx_clean(sky2);
  1121. pci_free_consistent(hw->pdev, RX_LE_BYTES,
  1122. sky2->rx_le, sky2->rx_le_map);
  1123. kfree(sky2->rx_ring);
  1124. pci_free_consistent(hw->pdev,
  1125. TX_RING_SIZE * sizeof(struct sky2_tx_le),
  1126. sky2->tx_le, sky2->tx_le_map);
  1127. kfree(sky2->tx_ring);
  1128. sky2->tx_le = NULL;
  1129. sky2->rx_le = NULL;
  1130. sky2->rx_ring = NULL;
  1131. sky2->tx_ring = NULL;
  1132. return 0;
  1133. }
  1134. static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
  1135. {
  1136. if (!hw->copper)
  1137. return SPEED_1000;
  1138. if (hw->chip_id == CHIP_ID_YUKON_FE)
  1139. return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
  1140. switch (aux & PHY_M_PS_SPEED_MSK) {
  1141. case PHY_M_PS_SPEED_1000:
  1142. return SPEED_1000;
  1143. case PHY_M_PS_SPEED_100:
  1144. return SPEED_100;
  1145. default:
  1146. return SPEED_10;
  1147. }
  1148. }
  1149. static void sky2_link_up(struct sky2_port *sky2)
  1150. {
  1151. struct sky2_hw *hw = sky2->hw;
  1152. unsigned port = sky2->port;
  1153. u16 reg;
  1154. /* Enable Transmit FIFO Underrun */
  1155. sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
  1156. reg = gma_read16(hw, port, GM_GP_CTRL);
  1157. if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
  1158. reg |= GM_GPCR_DUP_FULL;
  1159. /* enable Rx/Tx */
  1160. reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
  1161. gma_write16(hw, port, GM_GP_CTRL, reg);
  1162. gma_read16(hw, port, GM_GP_CTRL);
  1163. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
  1164. netif_carrier_on(sky2->netdev);
  1165. netif_wake_queue(sky2->netdev);
  1166. /* Turn on link LED */
  1167. sky2_write8(hw, SK_REG(port, LNK_LED_REG),
  1168. LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
  1169. if (hw->chip_id == CHIP_ID_YUKON_XL) {
  1170. u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  1171. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  1172. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
  1173. PHY_M_LEDC_INIT_CTRL(sky2->speed ==
  1174. SPEED_10 ? 7 : 0) |
  1175. PHY_M_LEDC_STA1_CTRL(sky2->speed ==
  1176. SPEED_100 ? 7 : 0) |
  1177. PHY_M_LEDC_STA0_CTRL(sky2->speed ==
  1178. SPEED_1000 ? 7 : 0));
  1179. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  1180. }
  1181. if (netif_msg_link(sky2))
  1182. printk(KERN_INFO PFX
  1183. "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
  1184. sky2->netdev->name, sky2->speed,
  1185. sky2->duplex == DUPLEX_FULL ? "full" : "half",
  1186. (sky2->tx_pause && sky2->rx_pause) ? "both" :
  1187. sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
  1188. }
  1189. static void sky2_link_down(struct sky2_port *sky2)
  1190. {
  1191. struct sky2_hw *hw = sky2->hw;
  1192. unsigned port = sky2->port;
  1193. u16 reg;
  1194. gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
  1195. reg = gma_read16(hw, port, GM_GP_CTRL);
  1196. reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  1197. gma_write16(hw, port, GM_GP_CTRL, reg);
  1198. gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
  1199. if (sky2->rx_pause && !sky2->tx_pause) {
  1200. /* restore Asymmetric Pause bit */
  1201. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
  1202. gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
  1203. | PHY_M_AN_ASP);
  1204. }
  1205. netif_carrier_off(sky2->netdev);
  1206. netif_stop_queue(sky2->netdev);
  1207. /* Turn on link LED */
  1208. sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
  1209. if (netif_msg_link(sky2))
  1210. printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
  1211. sky2_phy_init(hw, port);
  1212. }
  1213. static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
  1214. {
  1215. struct sky2_hw *hw = sky2->hw;
  1216. unsigned port = sky2->port;
  1217. u16 lpa;
  1218. lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
  1219. if (lpa & PHY_M_AN_RF) {
  1220. printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
  1221. return -1;
  1222. }
  1223. if (hw->chip_id != CHIP_ID_YUKON_FE &&
  1224. gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
  1225. printk(KERN_ERR PFX "%s: master/slave fault",
  1226. sky2->netdev->name);
  1227. return -1;
  1228. }
  1229. if (!(aux & PHY_M_PS_SPDUP_RES)) {
  1230. printk(KERN_ERR PFX "%s: speed/duplex mismatch",
  1231. sky2->netdev->name);
  1232. return -1;
  1233. }
  1234. sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
  1235. sky2->speed = sky2_phy_speed(hw, aux);
  1236. /* Pause bits are offset (9..8) */
  1237. if (hw->chip_id == CHIP_ID_YUKON_XL)
  1238. aux >>= 6;
  1239. sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
  1240. sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
  1241. if ((sky2->tx_pause || sky2->rx_pause)
  1242. && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
  1243. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
  1244. else
  1245. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  1246. return 0;
  1247. }
  1248. /*
  1249. * Interrupt from PHY are handled outside of interrupt context
  1250. * because accessing phy registers requires spin wait which might
  1251. * cause excess interrupt latency.
  1252. */
  1253. static void sky2_phy_task(void *arg)
  1254. {
  1255. struct sky2_port *sky2 = arg;
  1256. struct sky2_hw *hw = sky2->hw;
  1257. u16 istatus, phystat;
  1258. down(&sky2->phy_sema);
  1259. istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
  1260. phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
  1261. if (netif_msg_intr(sky2))
  1262. printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
  1263. sky2->netdev->name, istatus, phystat);
  1264. if (istatus & PHY_M_IS_AN_COMPL) {
  1265. if (sky2_autoneg_done(sky2, phystat) == 0)
  1266. sky2_link_up(sky2);
  1267. goto out;
  1268. }
  1269. if (istatus & PHY_M_IS_LSP_CHANGE)
  1270. sky2->speed = sky2_phy_speed(hw, phystat);
  1271. if (istatus & PHY_M_IS_DUP_CHANGE)
  1272. sky2->duplex =
  1273. (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
  1274. if (istatus & PHY_M_IS_LST_CHANGE) {
  1275. if (phystat & PHY_M_PS_LINK_UP)
  1276. sky2_link_up(sky2);
  1277. else
  1278. sky2_link_down(sky2);
  1279. }
  1280. out:
  1281. up(&sky2->phy_sema);
  1282. local_irq_disable();
  1283. hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
  1284. sky2_write32(hw, B0_IMSK, hw->intr_mask);
  1285. local_irq_enable();
  1286. }
  1287. static void sky2_tx_timeout(struct net_device *dev)
  1288. {
  1289. struct sky2_port *sky2 = netdev_priv(dev);
  1290. struct sky2_hw *hw = sky2->hw;
  1291. unsigned txq = txqaddr[sky2->port];
  1292. if (netif_msg_timer(sky2))
  1293. printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
  1294. netif_stop_queue(dev);
  1295. sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
  1296. sky2_read32(hw, Q_ADDR(txq, Q_CSR));
  1297. sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
  1298. sky2_tx_clean(sky2);
  1299. sky2_qset(hw, txq);
  1300. sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
  1301. netif_wake_queue(dev);
  1302. }
  1303. #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
  1304. /* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
  1305. static inline unsigned sky2_buf_size(int mtu)
  1306. {
  1307. return roundup(mtu + ETH_HLEN + 4, 8);
  1308. }
  1309. static int sky2_change_mtu(struct net_device *dev, int new_mtu)
  1310. {
  1311. struct sky2_port *sky2 = netdev_priv(dev);
  1312. struct sky2_hw *hw = sky2->hw;
  1313. int err;
  1314. u16 ctl, mode;
  1315. if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
  1316. return -EINVAL;
  1317. if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
  1318. return -EINVAL;
  1319. if (!netif_running(dev)) {
  1320. dev->mtu = new_mtu;
  1321. return 0;
  1322. }
  1323. sky2_write32(hw, B0_IMSK, 0);
  1324. dev->trans_start = jiffies; /* prevent tx timeout */
  1325. netif_stop_queue(dev);
  1326. netif_poll_disable(hw->dev[0]);
  1327. ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
  1328. gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
  1329. sky2_rx_stop(sky2);
  1330. sky2_rx_clean(sky2);
  1331. dev->mtu = new_mtu;
  1332. sky2->rx_bufsize = sky2_buf_size(new_mtu);
  1333. mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
  1334. GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
  1335. if (dev->mtu > ETH_DATA_LEN)
  1336. mode |= GM_SMOD_JUMBO_ENA;
  1337. gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
  1338. sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
  1339. err = sky2_rx_start(sky2);
  1340. sky2_write32(hw, B0_IMSK, hw->intr_mask);
  1341. if (err)
  1342. dev_close(dev);
  1343. else {
  1344. gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
  1345. netif_poll_enable(hw->dev[0]);
  1346. netif_wake_queue(dev);
  1347. }
  1348. return err;
  1349. }
  1350. /*
  1351. * Receive one packet.
  1352. * For small packets or errors, just reuse existing skb.
  1353. * For larger packets, get new buffer.
  1354. */
  1355. static struct sk_buff *sky2_receive(struct sky2_port *sky2,
  1356. u16 length, u32 status)
  1357. {
  1358. struct ring_info *re = sky2->rx_ring + sky2->rx_next;
  1359. struct sk_buff *skb = NULL;
  1360. if (unlikely(netif_msg_rx_status(sky2)))
  1361. printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
  1362. sky2->netdev->name, sky2->rx_next, status, length);
  1363. sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
  1364. prefetch(sky2->rx_ring + sky2->rx_next);
  1365. if (status & GMR_FS_ANY_ERR)
  1366. goto error;
  1367. if (!(status & GMR_FS_RX_OK))
  1368. goto resubmit;
  1369. if ((status >> 16) != length || length > sky2->rx_bufsize)
  1370. goto oversize;
  1371. if (length < copybreak) {
  1372. skb = alloc_skb(length + 2, GFP_ATOMIC);
  1373. if (!skb)
  1374. goto resubmit;
  1375. skb_reserve(skb, 2);
  1376. pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
  1377. length, PCI_DMA_FROMDEVICE);
  1378. memcpy(skb->data, re->skb->data, length);
  1379. skb->ip_summed = re->skb->ip_summed;
  1380. skb->csum = re->skb->csum;
  1381. pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
  1382. length, PCI_DMA_FROMDEVICE);
  1383. } else {
  1384. struct sk_buff *nskb;
  1385. nskb = dev_alloc_skb(sky2->rx_bufsize);
  1386. if (!nskb)
  1387. goto resubmit;
  1388. skb = re->skb;
  1389. re->skb = nskb;
  1390. pci_unmap_single(sky2->hw->pdev, re->mapaddr,
  1391. sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
  1392. prefetch(skb->data);
  1393. re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
  1394. sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
  1395. }
  1396. skb_put(skb, length);
  1397. resubmit:
  1398. re->skb->ip_summed = CHECKSUM_NONE;
  1399. sky2_rx_add(sky2, re->mapaddr);
  1400. /* Tell receiver about new buffers. */
  1401. sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
  1402. &sky2->rx_last_put, RX_LE_SIZE);
  1403. return skb;
  1404. oversize:
  1405. ++sky2->net_stats.rx_over_errors;
  1406. goto resubmit;
  1407. error:
  1408. ++sky2->net_stats.rx_errors;
  1409. if (netif_msg_rx_err(sky2))
  1410. printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
  1411. sky2->netdev->name, status, length);
  1412. if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
  1413. sky2->net_stats.rx_length_errors++;
  1414. if (status & GMR_FS_FRAGMENT)
  1415. sky2->net_stats.rx_frame_errors++;
  1416. if (status & GMR_FS_CRC_ERR)
  1417. sky2->net_stats.rx_crc_errors++;
  1418. if (status & GMR_FS_RX_FF_OV)
  1419. sky2->net_stats.rx_fifo_errors++;
  1420. goto resubmit;
  1421. }
  1422. /*
  1423. * Check for transmit complete
  1424. */
  1425. #define TX_NO_STATUS 0xffff
  1426. static inline void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
  1427. {
  1428. if (last != TX_NO_STATUS) {
  1429. struct net_device *dev = hw->dev[port];
  1430. if (dev && netif_running(dev)) {
  1431. struct sky2_port *sky2 = netdev_priv(dev);
  1432. sky2_tx_complete(sky2, last);
  1433. }
  1434. }
  1435. }
  1436. /*
  1437. * Both ports share the same status interrupt, therefore there is only
  1438. * one poll routine.
  1439. */
  1440. static int sky2_poll(struct net_device *dev0, int *budget)
  1441. {
  1442. struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
  1443. unsigned int to_do = min(dev0->quota, *budget);
  1444. unsigned int work_done = 0;
  1445. u16 hwidx;
  1446. u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
  1447. hwidx = sky2_read16(hw, STAT_PUT_IDX);
  1448. BUG_ON(hwidx >= STATUS_RING_SIZE);
  1449. rmb();
  1450. while (hwidx != hw->st_idx) {
  1451. struct sky2_status_le *le = hw->st_le + hw->st_idx;
  1452. struct net_device *dev;
  1453. struct sky2_port *sky2;
  1454. struct sk_buff *skb;
  1455. u32 status;
  1456. u16 length;
  1457. u8 op;
  1458. le = hw->st_le + hw->st_idx;
  1459. hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
  1460. prefetch(hw->st_le + hw->st_idx);
  1461. BUG_ON(le->link >= 2);
  1462. dev = hw->dev[le->link];
  1463. if (dev == NULL || !netif_running(dev))
  1464. continue;
  1465. sky2 = netdev_priv(dev);
  1466. status = le32_to_cpu(le->status);
  1467. length = le16_to_cpu(le->length);
  1468. op = le->opcode & ~HW_OWNER;
  1469. le->opcode = 0;
  1470. switch (op) {
  1471. case OP_RXSTAT:
  1472. skb = sky2_receive(sky2, length, status);
  1473. if (!skb)
  1474. break;
  1475. skb->dev = dev;
  1476. skb->protocol = eth_type_trans(skb, dev);
  1477. dev->last_rx = jiffies;
  1478. #ifdef SKY2_VLAN_TAG_USED
  1479. if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
  1480. vlan_hwaccel_receive_skb(skb,
  1481. sky2->vlgrp,
  1482. be16_to_cpu(sky2->rx_tag));
  1483. } else
  1484. #endif
  1485. netif_receive_skb(skb);
  1486. if (++work_done >= to_do)
  1487. goto exit_loop;
  1488. break;
  1489. #ifdef SKY2_VLAN_TAG_USED
  1490. case OP_RXVLAN:
  1491. sky2->rx_tag = length;
  1492. break;
  1493. case OP_RXCHKSVLAN:
  1494. sky2->rx_tag = length;
  1495. /* fall through */
  1496. #endif
  1497. case OP_RXCHKS:
  1498. skb = sky2->rx_ring[sky2->rx_next].skb;
  1499. skb->ip_summed = CHECKSUM_HW;
  1500. skb->csum = le16_to_cpu(status);
  1501. break;
  1502. case OP_TXINDEXLE:
  1503. /* TX index reports status for both ports */
  1504. tx_done[0] = status & 0xffff;
  1505. tx_done[1] = ((status >> 24) & 0xff)
  1506. | (u16)(length & 0xf) << 8;
  1507. break;
  1508. default:
  1509. if (net_ratelimit())
  1510. printk(KERN_WARNING PFX
  1511. "unknown status opcode 0x%x\n", op);
  1512. break;
  1513. }
  1514. }
  1515. exit_loop:
  1516. sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
  1517. mmiowb();
  1518. sky2_tx_check(hw, 0, tx_done[0]);
  1519. sky2_tx_check(hw, 1, tx_done[1]);
  1520. if (sky2_read16(hw, STAT_PUT_IDX) == hw->st_idx) {
  1521. /* need to restart TX timer */
  1522. if (is_ec_a1(hw)) {
  1523. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
  1524. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
  1525. }
  1526. netif_rx_complete(dev0);
  1527. hw->intr_mask |= Y2_IS_STAT_BMU;
  1528. sky2_write32(hw, B0_IMSK, hw->intr_mask);
  1529. mmiowb();
  1530. return 0;
  1531. } else {
  1532. *budget -= work_done;
  1533. dev0->quota -= work_done;
  1534. return 1;
  1535. }
  1536. }
  1537. static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
  1538. {
  1539. struct net_device *dev = hw->dev[port];
  1540. printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
  1541. dev->name, status);
  1542. if (status & Y2_IS_PAR_RD1) {
  1543. printk(KERN_ERR PFX "%s: ram data read parity error\n",
  1544. dev->name);
  1545. /* Clear IRQ */
  1546. sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
  1547. }
  1548. if (status & Y2_IS_PAR_WR1) {
  1549. printk(KERN_ERR PFX "%s: ram data write parity error\n",
  1550. dev->name);
  1551. sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
  1552. }
  1553. if (status & Y2_IS_PAR_MAC1) {
  1554. printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
  1555. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
  1556. }
  1557. if (status & Y2_IS_PAR_RX1) {
  1558. printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
  1559. sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
  1560. }
  1561. if (status & Y2_IS_TCP_TXA1) {
  1562. printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
  1563. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
  1564. }
  1565. }
  1566. static void sky2_hw_intr(struct sky2_hw *hw)
  1567. {
  1568. u32 status = sky2_read32(hw, B0_HWE_ISRC);
  1569. if (status & Y2_IS_TIST_OV)
  1570. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  1571. if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
  1572. u16 pci_err;
  1573. pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
  1574. printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
  1575. pci_name(hw->pdev), pci_err);
  1576. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  1577. pci_write_config_word(hw->pdev, PCI_STATUS,
  1578. pci_err | PCI_STATUS_ERROR_BITS);
  1579. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  1580. }
  1581. if (status & Y2_IS_PCI_EXP) {
  1582. /* PCI-Express uncorrectable Error occurred */
  1583. u32 pex_err;
  1584. pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
  1585. printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
  1586. pci_name(hw->pdev), pex_err);
  1587. /* clear the interrupt */
  1588. sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  1589. pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
  1590. 0xffffffffUL);
  1591. sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  1592. if (pex_err & PEX_FATAL_ERRORS) {
  1593. u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
  1594. hwmsk &= ~Y2_IS_PCI_EXP;
  1595. sky2_write32(hw, B0_HWE_IMSK, hwmsk);
  1596. }
  1597. }
  1598. if (status & Y2_HWE_L1_MASK)
  1599. sky2_hw_error(hw, 0, status);
  1600. status >>= 8;
  1601. if (status & Y2_HWE_L1_MASK)
  1602. sky2_hw_error(hw, 1, status);
  1603. }
  1604. static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
  1605. {
  1606. struct net_device *dev = hw->dev[port];
  1607. struct sky2_port *sky2 = netdev_priv(dev);
  1608. u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
  1609. if (netif_msg_intr(sky2))
  1610. printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
  1611. dev->name, status);
  1612. if (status & GM_IS_RX_FF_OR) {
  1613. ++sky2->net_stats.rx_fifo_errors;
  1614. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
  1615. }
  1616. if (status & GM_IS_TX_FF_UR) {
  1617. ++sky2->net_stats.tx_fifo_errors;
  1618. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
  1619. }
  1620. }
  1621. static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
  1622. {
  1623. struct net_device *dev = hw->dev[port];
  1624. struct sky2_port *sky2 = netdev_priv(dev);
  1625. hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
  1626. sky2_write32(hw, B0_IMSK, hw->intr_mask);
  1627. schedule_work(&sky2->phy_task);
  1628. }
  1629. static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
  1630. {
  1631. struct sky2_hw *hw = dev_id;
  1632. struct net_device *dev0 = hw->dev[0];
  1633. u32 status;
  1634. status = sky2_read32(hw, B0_Y2_SP_ISRC2);
  1635. if (status == 0 || status == ~0)
  1636. return IRQ_NONE;
  1637. if (status & Y2_IS_HW_ERR)
  1638. sky2_hw_intr(hw);
  1639. /* Do NAPI for Rx and Tx status */
  1640. if (status & Y2_IS_STAT_BMU) {
  1641. hw->intr_mask &= ~Y2_IS_STAT_BMU;
  1642. sky2_write32(hw, B0_IMSK, hw->intr_mask);
  1643. if (likely(__netif_rx_schedule_prep(dev0))) {
  1644. prefetch(&hw->st_le[hw->st_idx]);
  1645. __netif_rx_schedule(dev0);
  1646. }
  1647. }
  1648. if (status & Y2_IS_IRQ_PHY1)
  1649. sky2_phy_intr(hw, 0);
  1650. if (status & Y2_IS_IRQ_PHY2)
  1651. sky2_phy_intr(hw, 1);
  1652. if (status & Y2_IS_IRQ_MAC1)
  1653. sky2_mac_intr(hw, 0);
  1654. if (status & Y2_IS_IRQ_MAC2)
  1655. sky2_mac_intr(hw, 1);
  1656. sky2_write32(hw, B0_Y2_SP_ICR, 2);
  1657. sky2_read32(hw, B0_IMSK);
  1658. return IRQ_HANDLED;
  1659. }
  1660. #ifdef CONFIG_NET_POLL_CONTROLLER
  1661. static void sky2_netpoll(struct net_device *dev)
  1662. {
  1663. struct sky2_port *sky2 = netdev_priv(dev);
  1664. sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
  1665. }
  1666. #endif
  1667. /* Chip internal frequency for clock calculations */
  1668. static inline u32 sky2_mhz(const struct sky2_hw *hw)
  1669. {
  1670. switch (hw->chip_id) {
  1671. case CHIP_ID_YUKON_EC:
  1672. case CHIP_ID_YUKON_EC_U:
  1673. return 125; /* 125 Mhz */
  1674. case CHIP_ID_YUKON_FE:
  1675. return 100; /* 100 Mhz */
  1676. default: /* YUKON_XL */
  1677. return 156; /* 156 Mhz */
  1678. }
  1679. }
  1680. static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
  1681. {
  1682. return sky2_mhz(hw) * us;
  1683. }
  1684. static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
  1685. {
  1686. return clk / sky2_mhz(hw);
  1687. }
  1688. static int sky2_reset(struct sky2_hw *hw)
  1689. {
  1690. u32 ctst;
  1691. u16 status;
  1692. u8 t8, pmd_type;
  1693. int i;
  1694. ctst = sky2_read32(hw, B0_CTST);
  1695. sky2_write8(hw, B0_CTST, CS_RST_CLR);
  1696. hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
  1697. if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
  1698. printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
  1699. pci_name(hw->pdev), hw->chip_id);
  1700. return -EOPNOTSUPP;
  1701. }
  1702. /* ring for status responses */
  1703. hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
  1704. &hw->st_dma);
  1705. if (!hw->st_le)
  1706. return -ENOMEM;
  1707. /* disable ASF */
  1708. if (hw->chip_id <= CHIP_ID_YUKON_EC) {
  1709. sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
  1710. sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
  1711. }
  1712. /* do a SW reset */
  1713. sky2_write8(hw, B0_CTST, CS_RST_SET);
  1714. sky2_write8(hw, B0_CTST, CS_RST_CLR);
  1715. /* clear PCI errors, if any */
  1716. pci_read_config_word(hw->pdev, PCI_STATUS, &status);
  1717. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  1718. pci_write_config_word(hw->pdev, PCI_STATUS,
  1719. status | PCI_STATUS_ERROR_BITS);
  1720. sky2_write8(hw, B0_CTST, CS_MRST_CLR);
  1721. /* clear any PEX errors */
  1722. if (is_pciex(hw)) {
  1723. u16 lstat;
  1724. pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
  1725. 0xffffffffUL);
  1726. pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
  1727. }
  1728. pmd_type = sky2_read8(hw, B2_PMD_TYP);
  1729. hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
  1730. hw->ports = 1;
  1731. t8 = sky2_read8(hw, B2_Y2_HW_RES);
  1732. if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
  1733. if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
  1734. ++hw->ports;
  1735. }
  1736. hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
  1737. sky2_set_power_state(hw, PCI_D0);
  1738. for (i = 0; i < hw->ports; i++) {
  1739. sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
  1740. sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
  1741. }
  1742. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  1743. /* Clear I2C IRQ noise */
  1744. sky2_write32(hw, B2_I2C_IRQ, 1);
  1745. /* turn off hardware timer (unused) */
  1746. sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
  1747. sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
  1748. sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
  1749. /* Turn off descriptor polling */
  1750. sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
  1751. /* Turn off receive timestamp */
  1752. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
  1753. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  1754. /* enable the Tx Arbiters */
  1755. for (i = 0; i < hw->ports; i++)
  1756. sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
  1757. /* Initialize ram interface */
  1758. for (i = 0; i < hw->ports; i++) {
  1759. sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
  1760. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
  1761. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
  1762. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
  1763. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
  1764. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
  1765. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
  1766. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
  1767. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
  1768. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
  1769. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
  1770. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
  1771. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
  1772. }
  1773. sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
  1774. for (i = 0; i < hw->ports; i++)
  1775. sky2_phy_reset(hw, i);
  1776. memset(hw->st_le, 0, STATUS_LE_BYTES);
  1777. hw->st_idx = 0;
  1778. sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
  1779. sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
  1780. sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
  1781. sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
  1782. /* Set the list last index */
  1783. sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
  1784. /* These status setup values are copied from SysKonnect's driver */
  1785. if (is_ec_a1(hw)) {
  1786. /* WA for dev. #4.3 */
  1787. sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
  1788. /* set Status-FIFO watermark */
  1789. sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
  1790. /* set Status-FIFO ISR watermark */
  1791. sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
  1792. sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
  1793. } else {
  1794. sky2_write16(hw, STAT_TX_IDX_TH, 10);
  1795. sky2_write8(hw, STAT_FIFO_WM, 16);
  1796. /* set Status-FIFO ISR watermark */
  1797. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
  1798. sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
  1799. else
  1800. sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
  1801. sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
  1802. sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
  1803. sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
  1804. }
  1805. /* enable status unit */
  1806. sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
  1807. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
  1808. sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
  1809. sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
  1810. return 0;
  1811. }
  1812. static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
  1813. {
  1814. u32 modes;
  1815. if (hw->copper) {
  1816. modes = SUPPORTED_10baseT_Half
  1817. | SUPPORTED_10baseT_Full
  1818. | SUPPORTED_100baseT_Half
  1819. | SUPPORTED_100baseT_Full
  1820. | SUPPORTED_Autoneg | SUPPORTED_TP;
  1821. if (hw->chip_id != CHIP_ID_YUKON_FE)
  1822. modes |= SUPPORTED_1000baseT_Half
  1823. | SUPPORTED_1000baseT_Full;
  1824. } else
  1825. modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
  1826. | SUPPORTED_Autoneg;
  1827. return modes;
  1828. }
  1829. static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  1830. {
  1831. struct sky2_port *sky2 = netdev_priv(dev);
  1832. struct sky2_hw *hw = sky2->hw;
  1833. ecmd->transceiver = XCVR_INTERNAL;
  1834. ecmd->supported = sky2_supported_modes(hw);
  1835. ecmd->phy_address = PHY_ADDR_MARV;
  1836. if (hw->copper) {
  1837. ecmd->supported = SUPPORTED_10baseT_Half
  1838. | SUPPORTED_10baseT_Full
  1839. | SUPPORTED_100baseT_Half
  1840. | SUPPORTED_100baseT_Full
  1841. | SUPPORTED_1000baseT_Half
  1842. | SUPPORTED_1000baseT_Full
  1843. | SUPPORTED_Autoneg | SUPPORTED_TP;
  1844. ecmd->port = PORT_TP;
  1845. } else
  1846. ecmd->port = PORT_FIBRE;
  1847. ecmd->advertising = sky2->advertising;
  1848. ecmd->autoneg = sky2->autoneg;
  1849. ecmd->speed = sky2->speed;
  1850. ecmd->duplex = sky2->duplex;
  1851. return 0;
  1852. }
  1853. static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  1854. {
  1855. struct sky2_port *sky2 = netdev_priv(dev);
  1856. const struct sky2_hw *hw = sky2->hw;
  1857. u32 supported = sky2_supported_modes(hw);
  1858. if (ecmd->autoneg == AUTONEG_ENABLE) {
  1859. ecmd->advertising = supported;
  1860. sky2->duplex = -1;
  1861. sky2->speed = -1;
  1862. } else {
  1863. u32 setting;
  1864. switch (ecmd->speed) {
  1865. case SPEED_1000:
  1866. if (ecmd->duplex == DUPLEX_FULL)
  1867. setting = SUPPORTED_1000baseT_Full;
  1868. else if (ecmd->duplex == DUPLEX_HALF)
  1869. setting = SUPPORTED_1000baseT_Half;
  1870. else
  1871. return -EINVAL;
  1872. break;
  1873. case SPEED_100:
  1874. if (ecmd->duplex == DUPLEX_FULL)
  1875. setting = SUPPORTED_100baseT_Full;
  1876. else if (ecmd->duplex == DUPLEX_HALF)
  1877. setting = SUPPORTED_100baseT_Half;
  1878. else
  1879. return -EINVAL;
  1880. break;
  1881. case SPEED_10:
  1882. if (ecmd->duplex == DUPLEX_FULL)
  1883. setting = SUPPORTED_10baseT_Full;
  1884. else if (ecmd->duplex == DUPLEX_HALF)
  1885. setting = SUPPORTED_10baseT_Half;
  1886. else
  1887. return -EINVAL;
  1888. break;
  1889. default:
  1890. return -EINVAL;
  1891. }
  1892. if ((setting & supported) == 0)
  1893. return -EINVAL;
  1894. sky2->speed = ecmd->speed;
  1895. sky2->duplex = ecmd->duplex;
  1896. }
  1897. sky2->autoneg = ecmd->autoneg;
  1898. sky2->advertising = ecmd->advertising;
  1899. if (netif_running(dev))
  1900. sky2_phy_reinit(sky2);
  1901. return 0;
  1902. }
  1903. static void sky2_get_drvinfo(struct net_device *dev,
  1904. struct ethtool_drvinfo *info)
  1905. {
  1906. struct sky2_port *sky2 = netdev_priv(dev);
  1907. strcpy(info->driver, DRV_NAME);
  1908. strcpy(info->version, DRV_VERSION);
  1909. strcpy(info->fw_version, "N/A");
  1910. strcpy(info->bus_info, pci_name(sky2->hw->pdev));
  1911. }
  1912. static const struct sky2_stat {
  1913. char name[ETH_GSTRING_LEN];
  1914. u16 offset;
  1915. } sky2_stats[] = {
  1916. { "tx_bytes", GM_TXO_OK_HI },
  1917. { "rx_bytes", GM_RXO_OK_HI },
  1918. { "tx_broadcast", GM_TXF_BC_OK },
  1919. { "rx_broadcast", GM_RXF_BC_OK },
  1920. { "tx_multicast", GM_TXF_MC_OK },
  1921. { "rx_multicast", GM_RXF_MC_OK },
  1922. { "tx_unicast", GM_TXF_UC_OK },
  1923. { "rx_unicast", GM_RXF_UC_OK },
  1924. { "tx_mac_pause", GM_TXF_MPAUSE },
  1925. { "rx_mac_pause", GM_RXF_MPAUSE },
  1926. { "collisions", GM_TXF_SNG_COL },
  1927. { "late_collision",GM_TXF_LAT_COL },
  1928. { "aborted", GM_TXF_ABO_COL },
  1929. { "multi_collisions", GM_TXF_MUL_COL },
  1930. { "fifo_underrun", GM_TXE_FIFO_UR },
  1931. { "fifo_overflow", GM_RXE_FIFO_OV },
  1932. { "rx_toolong", GM_RXF_LNG_ERR },
  1933. { "rx_jabber", GM_RXF_JAB_PKT },
  1934. { "rx_runt", GM_RXE_FRAG },
  1935. { "rx_too_long", GM_RXF_LNG_ERR },
  1936. { "rx_fcs_error", GM_RXF_FCS_ERR },
  1937. };
  1938. static u32 sky2_get_rx_csum(struct net_device *dev)
  1939. {
  1940. struct sky2_port *sky2 = netdev_priv(dev);
  1941. return sky2->rx_csum;
  1942. }
  1943. static int sky2_set_rx_csum(struct net_device *dev, u32 data)
  1944. {
  1945. struct sky2_port *sky2 = netdev_priv(dev);
  1946. sky2->rx_csum = data;
  1947. sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
  1948. data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
  1949. return 0;
  1950. }
  1951. static u32 sky2_get_msglevel(struct net_device *netdev)
  1952. {
  1953. struct sky2_port *sky2 = netdev_priv(netdev);
  1954. return sky2->msg_enable;
  1955. }
  1956. static int sky2_nway_reset(struct net_device *dev)
  1957. {
  1958. struct sky2_port *sky2 = netdev_priv(dev);
  1959. if (sky2->autoneg != AUTONEG_ENABLE)
  1960. return -EINVAL;
  1961. sky2_phy_reinit(sky2);
  1962. return 0;
  1963. }
  1964. static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
  1965. {
  1966. struct sky2_hw *hw = sky2->hw;
  1967. unsigned port = sky2->port;
  1968. int i;
  1969. data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
  1970. | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
  1971. data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
  1972. | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
  1973. for (i = 2; i < count; i++)
  1974. data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
  1975. }
  1976. static void sky2_set_msglevel(struct net_device *netdev, u32 value)
  1977. {
  1978. struct sky2_port *sky2 = netdev_priv(netdev);
  1979. sky2->msg_enable = value;
  1980. }
  1981. static int sky2_get_stats_count(struct net_device *dev)
  1982. {
  1983. return ARRAY_SIZE(sky2_stats);
  1984. }
  1985. static void sky2_get_ethtool_stats(struct net_device *dev,
  1986. struct ethtool_stats *stats, u64 * data)
  1987. {
  1988. struct sky2_port *sky2 = netdev_priv(dev);
  1989. sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
  1990. }
  1991. static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
  1992. {
  1993. int i;
  1994. switch (stringset) {
  1995. case ETH_SS_STATS:
  1996. for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
  1997. memcpy(data + i * ETH_GSTRING_LEN,
  1998. sky2_stats[i].name, ETH_GSTRING_LEN);
  1999. break;
  2000. }
  2001. }
  2002. /* Use hardware MIB variables for critical path statistics and
  2003. * transmit feedback not reported at interrupt.
  2004. * Other errors are accounted for in interrupt handler.
  2005. */
  2006. static struct net_device_stats *sky2_get_stats(struct net_device *dev)
  2007. {
  2008. struct sky2_port *sky2 = netdev_priv(dev);
  2009. u64 data[13];
  2010. sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
  2011. sky2->net_stats.tx_bytes = data[0];
  2012. sky2->net_stats.rx_bytes = data[1];
  2013. sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
  2014. sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
  2015. sky2->net_stats.multicast = data[5] + data[7];
  2016. sky2->net_stats.collisions = data[10];
  2017. sky2->net_stats.tx_aborted_errors = data[12];
  2018. return &sky2->net_stats;
  2019. }
  2020. static int sky2_set_mac_address(struct net_device *dev, void *p)
  2021. {
  2022. struct sky2_port *sky2 = netdev_priv(dev);
  2023. struct sockaddr *addr = p;
  2024. if (!is_valid_ether_addr(addr->sa_data))
  2025. return -EADDRNOTAVAIL;
  2026. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  2027. memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
  2028. dev->dev_addr, ETH_ALEN);
  2029. memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
  2030. dev->dev_addr, ETH_ALEN);
  2031. if (netif_running(dev))
  2032. sky2_phy_reinit(sky2);
  2033. return 0;
  2034. }
  2035. static void sky2_set_multicast(struct net_device *dev)
  2036. {
  2037. struct sky2_port *sky2 = netdev_priv(dev);
  2038. struct sky2_hw *hw = sky2->hw;
  2039. unsigned port = sky2->port;
  2040. struct dev_mc_list *list = dev->mc_list;
  2041. u16 reg;
  2042. u8 filter[8];
  2043. memset(filter, 0, sizeof(filter));
  2044. reg = gma_read16(hw, port, GM_RX_CTRL);
  2045. reg |= GM_RXCR_UCF_ENA;
  2046. if (dev->flags & IFF_PROMISC) /* promiscuous */
  2047. reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
  2048. else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
  2049. memset(filter, 0xff, sizeof(filter));
  2050. else if (dev->mc_count == 0) /* no multicast */
  2051. reg &= ~GM_RXCR_MCF_ENA;
  2052. else {
  2053. int i;
  2054. reg |= GM_RXCR_MCF_ENA;
  2055. for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
  2056. u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
  2057. filter[bit / 8] |= 1 << (bit % 8);
  2058. }
  2059. }
  2060. gma_write16(hw, port, GM_MC_ADDR_H1,
  2061. (u16) filter[0] | ((u16) filter[1] << 8));
  2062. gma_write16(hw, port, GM_MC_ADDR_H2,
  2063. (u16) filter[2] | ((u16) filter[3] << 8));
  2064. gma_write16(hw, port, GM_MC_ADDR_H3,
  2065. (u16) filter[4] | ((u16) filter[5] << 8));
  2066. gma_write16(hw, port, GM_MC_ADDR_H4,
  2067. (u16) filter[6] | ((u16) filter[7] << 8));
  2068. gma_write16(hw, port, GM_RX_CTRL, reg);
  2069. }
  2070. /* Can have one global because blinking is controlled by
  2071. * ethtool and that is always under RTNL mutex
  2072. */
  2073. static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
  2074. {
  2075. u16 pg;
  2076. switch (hw->chip_id) {
  2077. case CHIP_ID_YUKON_XL:
  2078. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  2079. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  2080. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  2081. on ? (PHY_M_LEDC_LOS_CTRL(1) |
  2082. PHY_M_LEDC_INIT_CTRL(7) |
  2083. PHY_M_LEDC_STA1_CTRL(7) |
  2084. PHY_M_LEDC_STA0_CTRL(7))
  2085. : 0);
  2086. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  2087. break;
  2088. default:
  2089. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
  2090. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  2091. on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
  2092. PHY_M_LED_MO_10(MO_LED_ON) |
  2093. PHY_M_LED_MO_100(MO_LED_ON) |
  2094. PHY_M_LED_MO_1000(MO_LED_ON) |
  2095. PHY_M_LED_MO_RX(MO_LED_ON)
  2096. : PHY_M_LED_MO_DUP(MO_LED_OFF) |
  2097. PHY_M_LED_MO_10(MO_LED_OFF) |
  2098. PHY_M_LED_MO_100(MO_LED_OFF) |
  2099. PHY_M_LED_MO_1000(MO_LED_OFF) |
  2100. PHY_M_LED_MO_RX(MO_LED_OFF));
  2101. }
  2102. }
  2103. /* blink LED's for finding board */
  2104. static int sky2_phys_id(struct net_device *dev, u32 data)
  2105. {
  2106. struct sky2_port *sky2 = netdev_priv(dev);
  2107. struct sky2_hw *hw = sky2->hw;
  2108. unsigned port = sky2->port;
  2109. u16 ledctrl, ledover = 0;
  2110. long ms;
  2111. int interrupted;
  2112. int onoff = 1;
  2113. if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
  2114. ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
  2115. else
  2116. ms = data * 1000;
  2117. /* save initial values */
  2118. down(&sky2->phy_sema);
  2119. if (hw->chip_id == CHIP_ID_YUKON_XL) {
  2120. u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  2121. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  2122. ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  2123. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  2124. } else {
  2125. ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
  2126. ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
  2127. }
  2128. interrupted = 0;
  2129. while (!interrupted && ms > 0) {
  2130. sky2_led(hw, port, onoff);
  2131. onoff = !onoff;
  2132. up(&sky2->phy_sema);
  2133. interrupted = msleep_interruptible(250);
  2134. down(&sky2->phy_sema);
  2135. ms -= 250;
  2136. }
  2137. /* resume regularly scheduled programming */
  2138. if (hw->chip_id == CHIP_ID_YUKON_XL) {
  2139. u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  2140. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  2141. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
  2142. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  2143. } else {
  2144. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
  2145. gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
  2146. }
  2147. up(&sky2->phy_sema);
  2148. return 0;
  2149. }
  2150. static void sky2_get_pauseparam(struct net_device *dev,
  2151. struct ethtool_pauseparam *ecmd)
  2152. {
  2153. struct sky2_port *sky2 = netdev_priv(dev);
  2154. ecmd->tx_pause = sky2->tx_pause;
  2155. ecmd->rx_pause = sky2->rx_pause;
  2156. ecmd->autoneg = sky2->autoneg;
  2157. }
  2158. static int sky2_set_pauseparam(struct net_device *dev,
  2159. struct ethtool_pauseparam *ecmd)
  2160. {
  2161. struct sky2_port *sky2 = netdev_priv(dev);
  2162. int err = 0;
  2163. sky2->autoneg = ecmd->autoneg;
  2164. sky2->tx_pause = ecmd->tx_pause != 0;
  2165. sky2->rx_pause = ecmd->rx_pause != 0;
  2166. sky2_phy_reinit(sky2);
  2167. return err;
  2168. }
  2169. #ifdef CONFIG_PM
  2170. static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2171. {
  2172. struct sky2_port *sky2 = netdev_priv(dev);
  2173. wol->supported = WAKE_MAGIC;
  2174. wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
  2175. }
  2176. static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2177. {
  2178. struct sky2_port *sky2 = netdev_priv(dev);
  2179. struct sky2_hw *hw = sky2->hw;
  2180. if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
  2181. return -EOPNOTSUPP;
  2182. sky2->wol = wol->wolopts == WAKE_MAGIC;
  2183. if (sky2->wol) {
  2184. memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
  2185. sky2_write16(hw, WOL_CTRL_STAT,
  2186. WOL_CTL_ENA_PME_ON_MAGIC_PKT |
  2187. WOL_CTL_ENA_MAGIC_PKT_UNIT);
  2188. } else
  2189. sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
  2190. return 0;
  2191. }
  2192. #endif
  2193. static int sky2_get_coalesce(struct net_device *dev,
  2194. struct ethtool_coalesce *ecmd)
  2195. {
  2196. struct sky2_port *sky2 = netdev_priv(dev);
  2197. struct sky2_hw *hw = sky2->hw;
  2198. if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
  2199. ecmd->tx_coalesce_usecs = 0;
  2200. else {
  2201. u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
  2202. ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
  2203. }
  2204. ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
  2205. if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
  2206. ecmd->rx_coalesce_usecs = 0;
  2207. else {
  2208. u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
  2209. ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
  2210. }
  2211. ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
  2212. if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
  2213. ecmd->rx_coalesce_usecs_irq = 0;
  2214. else {
  2215. u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
  2216. ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
  2217. }
  2218. ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
  2219. return 0;
  2220. }
  2221. /* Note: this affect both ports */
  2222. static int sky2_set_coalesce(struct net_device *dev,
  2223. struct ethtool_coalesce *ecmd)
  2224. {
  2225. struct sky2_port *sky2 = netdev_priv(dev);
  2226. struct sky2_hw *hw = sky2->hw;
  2227. const u32 tmin = sky2_clk2us(hw, 1);
  2228. const u32 tmax = 5000;
  2229. if (ecmd->tx_coalesce_usecs != 0 &&
  2230. (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
  2231. return -EINVAL;
  2232. if (ecmd->rx_coalesce_usecs != 0 &&
  2233. (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
  2234. return -EINVAL;
  2235. if (ecmd->rx_coalesce_usecs_irq != 0 &&
  2236. (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
  2237. return -EINVAL;
  2238. if (ecmd->tx_max_coalesced_frames > 0xffff)
  2239. return -EINVAL;
  2240. if (ecmd->rx_max_coalesced_frames > 0xff)
  2241. return -EINVAL;
  2242. if (ecmd->rx_max_coalesced_frames_irq > 0xff)
  2243. return -EINVAL;
  2244. if (ecmd->tx_coalesce_usecs == 0)
  2245. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
  2246. else {
  2247. sky2_write32(hw, STAT_TX_TIMER_INI,
  2248. sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
  2249. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
  2250. }
  2251. sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
  2252. if (ecmd->rx_coalesce_usecs == 0)
  2253. sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
  2254. else {
  2255. sky2_write32(hw, STAT_LEV_TIMER_INI,
  2256. sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
  2257. sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
  2258. }
  2259. sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
  2260. if (ecmd->rx_coalesce_usecs_irq == 0)
  2261. sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
  2262. else {
  2263. sky2_write32(hw, STAT_TX_TIMER_INI,
  2264. sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
  2265. sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
  2266. }
  2267. sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
  2268. return 0;
  2269. }
  2270. static void sky2_get_ringparam(struct net_device *dev,
  2271. struct ethtool_ringparam *ering)
  2272. {
  2273. struct sky2_port *sky2 = netdev_priv(dev);
  2274. ering->rx_max_pending = RX_MAX_PENDING;
  2275. ering->rx_mini_max_pending = 0;
  2276. ering->rx_jumbo_max_pending = 0;
  2277. ering->tx_max_pending = TX_RING_SIZE - 1;
  2278. ering->rx_pending = sky2->rx_pending;
  2279. ering->rx_mini_pending = 0;
  2280. ering->rx_jumbo_pending = 0;
  2281. ering->tx_pending = sky2->tx_pending;
  2282. }
  2283. static int sky2_set_ringparam(struct net_device *dev,
  2284. struct ethtool_ringparam *ering)
  2285. {
  2286. struct sky2_port *sky2 = netdev_priv(dev);
  2287. int err = 0;
  2288. if (ering->rx_pending > RX_MAX_PENDING ||
  2289. ering->rx_pending < 8 ||
  2290. ering->tx_pending < MAX_SKB_TX_LE ||
  2291. ering->tx_pending > TX_RING_SIZE - 1)
  2292. return -EINVAL;
  2293. if (netif_running(dev))
  2294. sky2_down(dev);
  2295. sky2->rx_pending = ering->rx_pending;
  2296. sky2->tx_pending = ering->tx_pending;
  2297. if (netif_running(dev)) {
  2298. err = sky2_up(dev);
  2299. if (err)
  2300. dev_close(dev);
  2301. else
  2302. sky2_set_multicast(dev);
  2303. }
  2304. return err;
  2305. }
  2306. static int sky2_get_regs_len(struct net_device *dev)
  2307. {
  2308. return 0x4000;
  2309. }
  2310. /*
  2311. * Returns copy of control register region
  2312. * Note: access to the RAM address register set will cause timeouts.
  2313. */
  2314. static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  2315. void *p)
  2316. {
  2317. const struct sky2_port *sky2 = netdev_priv(dev);
  2318. const void __iomem *io = sky2->hw->regs;
  2319. BUG_ON(regs->len < B3_RI_WTO_R1);
  2320. regs->version = 1;
  2321. memset(p, 0, regs->len);
  2322. memcpy_fromio(p, io, B3_RAM_ADDR);
  2323. memcpy_fromio(p + B3_RI_WTO_R1,
  2324. io + B3_RI_WTO_R1,
  2325. regs->len - B3_RI_WTO_R1);
  2326. }
  2327. static struct ethtool_ops sky2_ethtool_ops = {
  2328. .get_settings = sky2_get_settings,
  2329. .set_settings = sky2_set_settings,
  2330. .get_drvinfo = sky2_get_drvinfo,
  2331. .get_msglevel = sky2_get_msglevel,
  2332. .set_msglevel = sky2_set_msglevel,
  2333. .nway_reset = sky2_nway_reset,
  2334. .get_regs_len = sky2_get_regs_len,
  2335. .get_regs = sky2_get_regs,
  2336. .get_link = ethtool_op_get_link,
  2337. .get_sg = ethtool_op_get_sg,
  2338. .set_sg = ethtool_op_set_sg,
  2339. .get_tx_csum = ethtool_op_get_tx_csum,
  2340. .set_tx_csum = ethtool_op_set_tx_csum,
  2341. .get_tso = ethtool_op_get_tso,
  2342. .set_tso = ethtool_op_set_tso,
  2343. .get_rx_csum = sky2_get_rx_csum,
  2344. .set_rx_csum = sky2_set_rx_csum,
  2345. .get_strings = sky2_get_strings,
  2346. .get_coalesce = sky2_get_coalesce,
  2347. .set_coalesce = sky2_set_coalesce,
  2348. .get_ringparam = sky2_get_ringparam,
  2349. .set_ringparam = sky2_set_ringparam,
  2350. .get_pauseparam = sky2_get_pauseparam,
  2351. .set_pauseparam = sky2_set_pauseparam,
  2352. #ifdef CONFIG_PM
  2353. .get_wol = sky2_get_wol,
  2354. .set_wol = sky2_set_wol,
  2355. #endif
  2356. .phys_id = sky2_phys_id,
  2357. .get_stats_count = sky2_get_stats_count,
  2358. .get_ethtool_stats = sky2_get_ethtool_stats,
  2359. .get_perm_addr = ethtool_op_get_perm_addr,
  2360. };
  2361. /* Initialize network device */
  2362. static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
  2363. unsigned port, int highmem)
  2364. {
  2365. struct sky2_port *sky2;
  2366. struct net_device *dev = alloc_etherdev(sizeof(*sky2));
  2367. if (!dev) {
  2368. printk(KERN_ERR "sky2 etherdev alloc failed");
  2369. return NULL;
  2370. }
  2371. SET_MODULE_OWNER(dev);
  2372. SET_NETDEV_DEV(dev, &hw->pdev->dev);
  2373. dev->irq = hw->pdev->irq;
  2374. dev->open = sky2_up;
  2375. dev->stop = sky2_down;
  2376. dev->do_ioctl = sky2_ioctl;
  2377. dev->hard_start_xmit = sky2_xmit_frame;
  2378. dev->get_stats = sky2_get_stats;
  2379. dev->set_multicast_list = sky2_set_multicast;
  2380. dev->set_mac_address = sky2_set_mac_address;
  2381. dev->change_mtu = sky2_change_mtu;
  2382. SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
  2383. dev->tx_timeout = sky2_tx_timeout;
  2384. dev->watchdog_timeo = TX_WATCHDOG;
  2385. if (port == 0)
  2386. dev->poll = sky2_poll;
  2387. dev->weight = NAPI_WEIGHT;
  2388. #ifdef CONFIG_NET_POLL_CONTROLLER
  2389. dev->poll_controller = sky2_netpoll;
  2390. #endif
  2391. sky2 = netdev_priv(dev);
  2392. sky2->netdev = dev;
  2393. sky2->hw = hw;
  2394. sky2->msg_enable = netif_msg_init(debug, default_msg);
  2395. spin_lock_init(&sky2->tx_lock);
  2396. /* Auto speed and flow control */
  2397. sky2->autoneg = AUTONEG_ENABLE;
  2398. sky2->tx_pause = 1;
  2399. sky2->rx_pause = 1;
  2400. sky2->duplex = -1;
  2401. sky2->speed = -1;
  2402. sky2->advertising = sky2_supported_modes(hw);
  2403. /* Receive checksum disabled for Yukon XL
  2404. * because of observed problems with incorrect
  2405. * values when multiple packets are received in one interrupt
  2406. */
  2407. sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
  2408. INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
  2409. init_MUTEX(&sky2->phy_sema);
  2410. sky2->tx_pending = TX_DEF_PENDING;
  2411. sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
  2412. sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
  2413. hw->dev[port] = dev;
  2414. sky2->port = port;
  2415. dev->features |= NETIF_F_LLTX;
  2416. if (hw->chip_id != CHIP_ID_YUKON_EC_U)
  2417. dev->features |= NETIF_F_TSO;
  2418. if (highmem)
  2419. dev->features |= NETIF_F_HIGHDMA;
  2420. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
  2421. #ifdef SKY2_VLAN_TAG_USED
  2422. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  2423. dev->vlan_rx_register = sky2_vlan_rx_register;
  2424. dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
  2425. #endif
  2426. /* read the mac address */
  2427. memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
  2428. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  2429. /* device is off until link detection */
  2430. netif_carrier_off(dev);
  2431. netif_stop_queue(dev);
  2432. return dev;
  2433. }
  2434. static inline void sky2_show_addr(struct net_device *dev)
  2435. {
  2436. const struct sky2_port *sky2 = netdev_priv(dev);
  2437. if (netif_msg_probe(sky2))
  2438. printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
  2439. dev->name,
  2440. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  2441. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  2442. }
  2443. static int __devinit sky2_probe(struct pci_dev *pdev,
  2444. const struct pci_device_id *ent)
  2445. {
  2446. struct net_device *dev, *dev1 = NULL;
  2447. struct sky2_hw *hw;
  2448. int err, pm_cap, using_dac = 0;
  2449. err = pci_enable_device(pdev);
  2450. if (err) {
  2451. printk(KERN_ERR PFX "%s cannot enable PCI device\n",
  2452. pci_name(pdev));
  2453. goto err_out;
  2454. }
  2455. err = pci_request_regions(pdev, DRV_NAME);
  2456. if (err) {
  2457. printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
  2458. pci_name(pdev));
  2459. goto err_out;
  2460. }
  2461. pci_set_master(pdev);
  2462. /* Find power-management capability. */
  2463. pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  2464. if (pm_cap == 0) {
  2465. printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
  2466. "aborting.\n");
  2467. err = -EIO;
  2468. goto err_out_free_regions;
  2469. }
  2470. if (sizeof(dma_addr_t) > sizeof(u32)) {
  2471. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  2472. if (!err)
  2473. using_dac = 1;
  2474. }
  2475. if (!using_dac) {
  2476. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  2477. if (err) {
  2478. printk(KERN_ERR PFX "%s no usable DMA configuration\n",
  2479. pci_name(pdev));
  2480. goto err_out_free_regions;
  2481. }
  2482. }
  2483. #ifdef __BIG_ENDIAN
  2484. /* byte swap descriptors in hardware */
  2485. {
  2486. u32 reg;
  2487. pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
  2488. reg |= PCI_REV_DESC;
  2489. pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
  2490. }
  2491. #endif
  2492. err = -ENOMEM;
  2493. hw = kmalloc(sizeof(*hw), GFP_KERNEL);
  2494. if (!hw) {
  2495. printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
  2496. pci_name(pdev));
  2497. goto err_out_free_regions;
  2498. }
  2499. memset(hw, 0, sizeof(*hw));
  2500. hw->pdev = pdev;
  2501. hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
  2502. if (!hw->regs) {
  2503. printk(KERN_ERR PFX "%s: cannot map device registers\n",
  2504. pci_name(pdev));
  2505. goto err_out_free_hw;
  2506. }
  2507. hw->pm_cap = pm_cap;
  2508. err = sky2_reset(hw);
  2509. if (err)
  2510. goto err_out_iounmap;
  2511. printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
  2512. DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
  2513. yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
  2514. hw->chip_id, hw->chip_rev);
  2515. dev = sky2_init_netdev(hw, 0, using_dac);
  2516. if (!dev)
  2517. goto err_out_free_pci;
  2518. err = register_netdev(dev);
  2519. if (err) {
  2520. printk(KERN_ERR PFX "%s: cannot register net device\n",
  2521. pci_name(pdev));
  2522. goto err_out_free_netdev;
  2523. }
  2524. sky2_show_addr(dev);
  2525. if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
  2526. if (register_netdev(dev1) == 0)
  2527. sky2_show_addr(dev1);
  2528. else {
  2529. /* Failure to register second port need not be fatal */
  2530. printk(KERN_WARNING PFX
  2531. "register of second port failed\n");
  2532. hw->dev[1] = NULL;
  2533. free_netdev(dev1);
  2534. }
  2535. }
  2536. err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
  2537. if (err) {
  2538. printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
  2539. pci_name(pdev), pdev->irq);
  2540. goto err_out_unregister;
  2541. }
  2542. hw->intr_mask = Y2_IS_BASE;
  2543. sky2_write32(hw, B0_IMSK, hw->intr_mask);
  2544. pci_set_drvdata(pdev, hw);
  2545. return 0;
  2546. err_out_unregister:
  2547. if (dev1) {
  2548. unregister_netdev(dev1);
  2549. free_netdev(dev1);
  2550. }
  2551. unregister_netdev(dev);
  2552. err_out_free_netdev:
  2553. free_netdev(dev);
  2554. err_out_free_pci:
  2555. sky2_write8(hw, B0_CTST, CS_RST_SET);
  2556. pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
  2557. err_out_iounmap:
  2558. iounmap(hw->regs);
  2559. err_out_free_hw:
  2560. kfree(hw);
  2561. err_out_free_regions:
  2562. pci_release_regions(pdev);
  2563. pci_disable_device(pdev);
  2564. err_out:
  2565. return err;
  2566. }
  2567. static void __devexit sky2_remove(struct pci_dev *pdev)
  2568. {
  2569. struct sky2_hw *hw = pci_get_drvdata(pdev);
  2570. struct net_device *dev0, *dev1;
  2571. if (!hw)
  2572. return;
  2573. dev0 = hw->dev[0];
  2574. dev1 = hw->dev[1];
  2575. if (dev1)
  2576. unregister_netdev(dev1);
  2577. unregister_netdev(dev0);
  2578. sky2_write32(hw, B0_IMSK, 0);
  2579. sky2_set_power_state(hw, PCI_D3hot);
  2580. sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
  2581. sky2_write8(hw, B0_CTST, CS_RST_SET);
  2582. sky2_read8(hw, B0_CTST);
  2583. free_irq(pdev->irq, hw);
  2584. pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
  2585. pci_release_regions(pdev);
  2586. pci_disable_device(pdev);
  2587. if (dev1)
  2588. free_netdev(dev1);
  2589. free_netdev(dev0);
  2590. iounmap(hw->regs);
  2591. kfree(hw);
  2592. pci_set_drvdata(pdev, NULL);
  2593. }
  2594. #ifdef CONFIG_PM
  2595. static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
  2596. {
  2597. struct sky2_hw *hw = pci_get_drvdata(pdev);
  2598. int i;
  2599. for (i = 0; i < 2; i++) {
  2600. struct net_device *dev = hw->dev[i];
  2601. if (dev) {
  2602. if (!netif_running(dev))
  2603. continue;
  2604. sky2_down(dev);
  2605. netif_device_detach(dev);
  2606. }
  2607. }
  2608. return sky2_set_power_state(hw, pci_choose_state(pdev, state));
  2609. }
  2610. static int sky2_resume(struct pci_dev *pdev)
  2611. {
  2612. struct sky2_hw *hw = pci_get_drvdata(pdev);
  2613. int i;
  2614. pci_restore_state(pdev);
  2615. pci_enable_wake(pdev, PCI_D0, 0);
  2616. sky2_set_power_state(hw, PCI_D0);
  2617. sky2_reset(hw);
  2618. for (i = 0; i < 2; i++) {
  2619. struct net_device *dev = hw->dev[i];
  2620. if (dev) {
  2621. if (netif_running(dev)) {
  2622. netif_device_attach(dev);
  2623. if (sky2_up(dev))
  2624. dev_close(dev);
  2625. }
  2626. }
  2627. }
  2628. return 0;
  2629. }
  2630. #endif
  2631. static struct pci_driver sky2_driver = {
  2632. .name = DRV_NAME,
  2633. .id_table = sky2_id_table,
  2634. .probe = sky2_probe,
  2635. .remove = __devexit_p(sky2_remove),
  2636. #ifdef CONFIG_PM
  2637. .suspend = sky2_suspend,
  2638. .resume = sky2_resume,
  2639. #endif
  2640. };
  2641. static int __init sky2_init_module(void)
  2642. {
  2643. return pci_register_driver(&sky2_driver);
  2644. }
  2645. static void __exit sky2_cleanup_module(void)
  2646. {
  2647. pci_unregister_driver(&sky2_driver);
  2648. }
  2649. module_init(sky2_init_module);
  2650. module_exit(sky2_cleanup_module);
  2651. MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
  2652. MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
  2653. MODULE_LICENSE("GPL");
  2654. MODULE_VERSION(DRV_VERSION);