phy-fsl-usb.c 27 KB

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  1. /*
  2. * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
  3. *
  4. * Author: Li Yang <LeoLi@freescale.com>
  5. * Jerry Huang <Chang-Ming.Huang@freescale.com>
  6. *
  7. * Initialization based on code from Shlomi Gridish.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful, but
  15. * WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17. * General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License along
  20. * with this program; if not, write to the Free Software Foundation, Inc.,
  21. * 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/module.h>
  24. #include <linux/kernel.h>
  25. #include <linux/delay.h>
  26. #include <linux/slab.h>
  27. #include <linux/proc_fs.h>
  28. #include <linux/errno.h>
  29. #include <linux/init.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/io.h>
  32. #include <linux/timer.h>
  33. #include <linux/usb.h>
  34. #include <linux/device.h>
  35. #include <linux/usb/ch9.h>
  36. #include <linux/usb/gadget.h>
  37. #include <linux/workqueue.h>
  38. #include <linux/time.h>
  39. #include <linux/fsl_devices.h>
  40. #include <linux/platform_device.h>
  41. #include <linux/uaccess.h>
  42. #include <asm/unaligned.h>
  43. #include "phy-fsl-usb.h"
  44. #define DRIVER_VERSION "Rev. 1.55"
  45. #define DRIVER_AUTHOR "Jerry Huang/Li Yang"
  46. #define DRIVER_DESC "Freescale USB OTG Transceiver Driver"
  47. #define DRIVER_INFO DRIVER_DESC " " DRIVER_VERSION
  48. static const char driver_name[] = "fsl-usb2-otg";
  49. const pm_message_t otg_suspend_state = {
  50. .event = 1,
  51. };
  52. #define HA_DATA_PULSE
  53. static struct usb_dr_mmap *usb_dr_regs;
  54. static struct fsl_otg *fsl_otg_dev;
  55. static int srp_wait_done;
  56. /* FSM timers */
  57. struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr,
  58. *b_ase0_brst_tmr, *b_se0_srp_tmr;
  59. /* Driver specific timers */
  60. struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr,
  61. *b_srp_wait_tmr, *a_wait_enum_tmr;
  62. static struct list_head active_timers;
  63. static struct fsl_otg_config fsl_otg_initdata = {
  64. .otg_port = 1,
  65. };
  66. #ifdef CONFIG_PPC32
  67. static u32 _fsl_readl_be(const unsigned __iomem *p)
  68. {
  69. return in_be32(p);
  70. }
  71. static u32 _fsl_readl_le(const unsigned __iomem *p)
  72. {
  73. return in_le32(p);
  74. }
  75. static void _fsl_writel_be(u32 v, unsigned __iomem *p)
  76. {
  77. out_be32(p, v);
  78. }
  79. static void _fsl_writel_le(u32 v, unsigned __iomem *p)
  80. {
  81. out_le32(p, v);
  82. }
  83. static u32 (*_fsl_readl)(const unsigned __iomem *p);
  84. static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
  85. #define fsl_readl(p) (*_fsl_readl)((p))
  86. #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
  87. #else
  88. #define fsl_readl(addr) readl(addr)
  89. #define fsl_writel(val, addr) writel(val, addr)
  90. #endif /* CONFIG_PPC32 */
  91. /* Routines to access transceiver ULPI registers */
  92. u8 view_ulpi(u8 addr)
  93. {
  94. u32 temp;
  95. temp = 0x40000000 | (addr << 16);
  96. fsl_writel(temp, &usb_dr_regs->ulpiview);
  97. udelay(1000);
  98. while (temp & 0x40)
  99. temp = fsl_readl(&usb_dr_regs->ulpiview);
  100. return (le32_to_cpu(temp) & 0x0000ff00) >> 8;
  101. }
  102. int write_ulpi(u8 addr, u8 data)
  103. {
  104. u32 temp;
  105. temp = 0x60000000 | (addr << 16) | data;
  106. fsl_writel(temp, &usb_dr_regs->ulpiview);
  107. return 0;
  108. }
  109. /* -------------------------------------------------------------*/
  110. /* Operations that will be called from OTG Finite State Machine */
  111. /* Charge vbus for vbus pulsing in SRP */
  112. void fsl_otg_chrg_vbus(int on)
  113. {
  114. u32 tmp;
  115. tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
  116. if (on)
  117. /* stop discharging, start charging */
  118. tmp = (tmp & ~OTGSC_CTRL_VBUS_DISCHARGE) |
  119. OTGSC_CTRL_VBUS_CHARGE;
  120. else
  121. /* stop charging */
  122. tmp &= ~OTGSC_CTRL_VBUS_CHARGE;
  123. fsl_writel(tmp, &usb_dr_regs->otgsc);
  124. }
  125. /* Discharge vbus through a resistor to ground */
  126. void fsl_otg_dischrg_vbus(int on)
  127. {
  128. u32 tmp;
  129. tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
  130. if (on)
  131. /* stop charging, start discharging */
  132. tmp = (tmp & ~OTGSC_CTRL_VBUS_CHARGE) |
  133. OTGSC_CTRL_VBUS_DISCHARGE;
  134. else
  135. /* stop discharging */
  136. tmp &= ~OTGSC_CTRL_VBUS_DISCHARGE;
  137. fsl_writel(tmp, &usb_dr_regs->otgsc);
  138. }
  139. /* A-device driver vbus, controlled through PP bit in PORTSC */
  140. void fsl_otg_drv_vbus(int on)
  141. {
  142. u32 tmp;
  143. if (on) {
  144. tmp = fsl_readl(&usb_dr_regs->portsc) & ~PORTSC_W1C_BITS;
  145. fsl_writel(tmp | PORTSC_PORT_POWER, &usb_dr_regs->portsc);
  146. } else {
  147. tmp = fsl_readl(&usb_dr_regs->portsc) &
  148. ~PORTSC_W1C_BITS & ~PORTSC_PORT_POWER;
  149. fsl_writel(tmp, &usb_dr_regs->portsc);
  150. }
  151. }
  152. /*
  153. * Pull-up D+, signalling connect by periperal. Also used in
  154. * data-line pulsing in SRP
  155. */
  156. void fsl_otg_loc_conn(int on)
  157. {
  158. u32 tmp;
  159. tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
  160. if (on)
  161. tmp |= OTGSC_CTRL_DATA_PULSING;
  162. else
  163. tmp &= ~OTGSC_CTRL_DATA_PULSING;
  164. fsl_writel(tmp, &usb_dr_regs->otgsc);
  165. }
  166. /*
  167. * Generate SOF by host. This is controlled through suspend/resume the
  168. * port. In host mode, controller will automatically send SOF.
  169. * Suspend will block the data on the port.
  170. */
  171. void fsl_otg_loc_sof(int on)
  172. {
  173. u32 tmp;
  174. tmp = fsl_readl(&fsl_otg_dev->dr_mem_map->portsc) & ~PORTSC_W1C_BITS;
  175. if (on)
  176. tmp |= PORTSC_PORT_FORCE_RESUME;
  177. else
  178. tmp |= PORTSC_PORT_SUSPEND;
  179. fsl_writel(tmp, &fsl_otg_dev->dr_mem_map->portsc);
  180. }
  181. /* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */
  182. void fsl_otg_start_pulse(void)
  183. {
  184. u32 tmp;
  185. srp_wait_done = 0;
  186. #ifdef HA_DATA_PULSE
  187. tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
  188. tmp |= OTGSC_HA_DATA_PULSE;
  189. fsl_writel(tmp, &usb_dr_regs->otgsc);
  190. #else
  191. fsl_otg_loc_conn(1);
  192. #endif
  193. fsl_otg_add_timer(b_data_pulse_tmr);
  194. }
  195. void b_data_pulse_end(unsigned long foo)
  196. {
  197. #ifdef HA_DATA_PULSE
  198. #else
  199. fsl_otg_loc_conn(0);
  200. #endif
  201. /* Do VBUS pulse after data pulse */
  202. fsl_otg_pulse_vbus();
  203. }
  204. void fsl_otg_pulse_vbus(void)
  205. {
  206. srp_wait_done = 0;
  207. fsl_otg_chrg_vbus(1);
  208. /* start the timer to end vbus charge */
  209. fsl_otg_add_timer(b_vbus_pulse_tmr);
  210. }
  211. void b_vbus_pulse_end(unsigned long foo)
  212. {
  213. fsl_otg_chrg_vbus(0);
  214. /*
  215. * As USB3300 using the same a_sess_vld and b_sess_vld voltage
  216. * we need to discharge the bus for a while to distinguish
  217. * residual voltage of vbus pulsing and A device pull up
  218. */
  219. fsl_otg_dischrg_vbus(1);
  220. fsl_otg_add_timer(b_srp_wait_tmr);
  221. }
  222. void b_srp_end(unsigned long foo)
  223. {
  224. fsl_otg_dischrg_vbus(0);
  225. srp_wait_done = 1;
  226. if ((fsl_otg_dev->phy.state == OTG_STATE_B_SRP_INIT) &&
  227. fsl_otg_dev->fsm.b_sess_vld)
  228. fsl_otg_dev->fsm.b_srp_done = 1;
  229. }
  230. /*
  231. * Workaround for a_host suspending too fast. When a_bus_req=0,
  232. * a_host will start by SRP. It needs to set b_hnp_enable before
  233. * actually suspending to start HNP
  234. */
  235. void a_wait_enum(unsigned long foo)
  236. {
  237. VDBG("a_wait_enum timeout\n");
  238. if (!fsl_otg_dev->phy.otg->host->b_hnp_enable)
  239. fsl_otg_add_timer(a_wait_enum_tmr);
  240. else
  241. otg_statemachine(&fsl_otg_dev->fsm);
  242. }
  243. /* The timeout callback function to set time out bit */
  244. void set_tmout(unsigned long indicator)
  245. {
  246. *(int *)indicator = 1;
  247. }
  248. /* Initialize timers */
  249. int fsl_otg_init_timers(struct otg_fsm *fsm)
  250. {
  251. /* FSM used timers */
  252. a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE,
  253. (unsigned long)&fsm->a_wait_vrise_tmout);
  254. if (!a_wait_vrise_tmr)
  255. return -ENOMEM;
  256. a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON,
  257. (unsigned long)&fsm->a_wait_bcon_tmout);
  258. if (!a_wait_bcon_tmr)
  259. return -ENOMEM;
  260. a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS,
  261. (unsigned long)&fsm->a_aidl_bdis_tmout);
  262. if (!a_aidl_bdis_tmr)
  263. return -ENOMEM;
  264. b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST,
  265. (unsigned long)&fsm->b_ase0_brst_tmout);
  266. if (!b_ase0_brst_tmr)
  267. return -ENOMEM;
  268. b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP,
  269. (unsigned long)&fsm->b_se0_srp);
  270. if (!b_se0_srp_tmr)
  271. return -ENOMEM;
  272. b_srp_fail_tmr = otg_timer_initializer(&set_tmout, TB_SRP_FAIL,
  273. (unsigned long)&fsm->b_srp_done);
  274. if (!b_srp_fail_tmr)
  275. return -ENOMEM;
  276. a_wait_enum_tmr = otg_timer_initializer(&a_wait_enum, 10,
  277. (unsigned long)&fsm);
  278. if (!a_wait_enum_tmr)
  279. return -ENOMEM;
  280. /* device driver used timers */
  281. b_srp_wait_tmr = otg_timer_initializer(&b_srp_end, TB_SRP_WAIT, 0);
  282. if (!b_srp_wait_tmr)
  283. return -ENOMEM;
  284. b_data_pulse_tmr = otg_timer_initializer(&b_data_pulse_end,
  285. TB_DATA_PLS, 0);
  286. if (!b_data_pulse_tmr)
  287. return -ENOMEM;
  288. b_vbus_pulse_tmr = otg_timer_initializer(&b_vbus_pulse_end,
  289. TB_VBUS_PLS, 0);
  290. if (!b_vbus_pulse_tmr)
  291. return -ENOMEM;
  292. return 0;
  293. }
  294. /* Uninitialize timers */
  295. void fsl_otg_uninit_timers(void)
  296. {
  297. /* FSM used timers */
  298. kfree(a_wait_vrise_tmr);
  299. kfree(a_wait_bcon_tmr);
  300. kfree(a_aidl_bdis_tmr);
  301. kfree(b_ase0_brst_tmr);
  302. kfree(b_se0_srp_tmr);
  303. kfree(b_srp_fail_tmr);
  304. kfree(a_wait_enum_tmr);
  305. /* device driver used timers */
  306. kfree(b_srp_wait_tmr);
  307. kfree(b_data_pulse_tmr);
  308. kfree(b_vbus_pulse_tmr);
  309. }
  310. /* Add timer to timer list */
  311. void fsl_otg_add_timer(void *gtimer)
  312. {
  313. struct fsl_otg_timer *timer = gtimer;
  314. struct fsl_otg_timer *tmp_timer;
  315. /*
  316. * Check if the timer is already in the active list,
  317. * if so update timer count
  318. */
  319. list_for_each_entry(tmp_timer, &active_timers, list)
  320. if (tmp_timer == timer) {
  321. timer->count = timer->expires;
  322. return;
  323. }
  324. timer->count = timer->expires;
  325. list_add_tail(&timer->list, &active_timers);
  326. }
  327. /* Remove timer from the timer list; clear timeout status */
  328. void fsl_otg_del_timer(void *gtimer)
  329. {
  330. struct fsl_otg_timer *timer = gtimer;
  331. struct fsl_otg_timer *tmp_timer, *del_tmp;
  332. list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list)
  333. if (tmp_timer == timer)
  334. list_del(&timer->list);
  335. }
  336. /*
  337. * Reduce timer count by 1, and find timeout conditions.
  338. * Called by fsl_otg 1ms timer interrupt
  339. */
  340. int fsl_otg_tick_timer(void)
  341. {
  342. struct fsl_otg_timer *tmp_timer, *del_tmp;
  343. int expired = 0;
  344. list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) {
  345. tmp_timer->count--;
  346. /* check if timer expires */
  347. if (!tmp_timer->count) {
  348. list_del(&tmp_timer->list);
  349. tmp_timer->function(tmp_timer->data);
  350. expired = 1;
  351. }
  352. }
  353. return expired;
  354. }
  355. /* Reset controller, not reset the bus */
  356. void otg_reset_controller(void)
  357. {
  358. u32 command;
  359. command = fsl_readl(&usb_dr_regs->usbcmd);
  360. command |= (1 << 1);
  361. fsl_writel(command, &usb_dr_regs->usbcmd);
  362. while (fsl_readl(&usb_dr_regs->usbcmd) & (1 << 1))
  363. ;
  364. }
  365. /* Call suspend/resume routines in host driver */
  366. int fsl_otg_start_host(struct otg_fsm *fsm, int on)
  367. {
  368. struct usb_otg *otg = fsm->otg;
  369. struct device *dev;
  370. struct fsl_otg *otg_dev = container_of(otg->phy, struct fsl_otg, phy);
  371. u32 retval = 0;
  372. if (!otg->host)
  373. return -ENODEV;
  374. dev = otg->host->controller;
  375. /*
  376. * Update a_vbus_vld state as a_vbus_vld int is disabled
  377. * in device mode
  378. */
  379. fsm->a_vbus_vld =
  380. !!(fsl_readl(&usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID);
  381. if (on) {
  382. /* start fsl usb host controller */
  383. if (otg_dev->host_working)
  384. goto end;
  385. else {
  386. otg_reset_controller();
  387. VDBG("host on......\n");
  388. if (dev->driver->pm && dev->driver->pm->resume) {
  389. retval = dev->driver->pm->resume(dev);
  390. if (fsm->id) {
  391. /* default-b */
  392. fsl_otg_drv_vbus(1);
  393. /*
  394. * Workaround: b_host can't driver
  395. * vbus, but PP in PORTSC needs to
  396. * be 1 for host to work.
  397. * So we set drv_vbus bit in
  398. * transceiver to 0 thru ULPI.
  399. */
  400. write_ulpi(0x0c, 0x20);
  401. }
  402. }
  403. otg_dev->host_working = 1;
  404. }
  405. } else {
  406. /* stop fsl usb host controller */
  407. if (!otg_dev->host_working)
  408. goto end;
  409. else {
  410. VDBG("host off......\n");
  411. if (dev && dev->driver) {
  412. if (dev->driver->pm && dev->driver->pm->suspend)
  413. retval = dev->driver->pm->suspend(dev);
  414. if (fsm->id)
  415. /* default-b */
  416. fsl_otg_drv_vbus(0);
  417. }
  418. otg_dev->host_working = 0;
  419. }
  420. }
  421. end:
  422. return retval;
  423. }
  424. /*
  425. * Call suspend and resume function in udc driver
  426. * to stop and start udc driver.
  427. */
  428. int fsl_otg_start_gadget(struct otg_fsm *fsm, int on)
  429. {
  430. struct usb_otg *otg = fsm->otg;
  431. struct device *dev;
  432. if (!otg->gadget || !otg->gadget->dev.parent)
  433. return -ENODEV;
  434. VDBG("gadget %s\n", on ? "on" : "off");
  435. dev = otg->gadget->dev.parent;
  436. if (on) {
  437. if (dev->driver->resume)
  438. dev->driver->resume(dev);
  439. } else {
  440. if (dev->driver->suspend)
  441. dev->driver->suspend(dev, otg_suspend_state);
  442. }
  443. return 0;
  444. }
  445. /*
  446. * Called by initialization code of host driver. Register host controller
  447. * to the OTG. Suspend host for OTG role detection.
  448. */
  449. static int fsl_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
  450. {
  451. struct fsl_otg *otg_dev;
  452. if (!otg)
  453. return -ENODEV;
  454. otg_dev = container_of(otg->phy, struct fsl_otg, phy);
  455. if (otg_dev != fsl_otg_dev)
  456. return -ENODEV;
  457. otg->host = host;
  458. otg_dev->fsm.a_bus_drop = 0;
  459. otg_dev->fsm.a_bus_req = 1;
  460. if (host) {
  461. VDBG("host off......\n");
  462. otg->host->otg_port = fsl_otg_initdata.otg_port;
  463. otg->host->is_b_host = otg_dev->fsm.id;
  464. /*
  465. * must leave time for khubd to finish its thing
  466. * before yanking the host driver out from under it,
  467. * so suspend the host after a short delay.
  468. */
  469. otg_dev->host_working = 1;
  470. schedule_delayed_work(&otg_dev->otg_event, 100);
  471. return 0;
  472. } else {
  473. /* host driver going away */
  474. if (!(fsl_readl(&otg_dev->dr_mem_map->otgsc) &
  475. OTGSC_STS_USB_ID)) {
  476. /* Mini-A cable connected */
  477. struct otg_fsm *fsm = &otg_dev->fsm;
  478. otg->phy->state = OTG_STATE_UNDEFINED;
  479. fsm->protocol = PROTO_UNDEF;
  480. }
  481. }
  482. otg_dev->host_working = 0;
  483. otg_statemachine(&otg_dev->fsm);
  484. return 0;
  485. }
  486. /* Called by initialization code of udc. Register udc to OTG. */
  487. static int fsl_otg_set_peripheral(struct usb_otg *otg,
  488. struct usb_gadget *gadget)
  489. {
  490. struct fsl_otg *otg_dev;
  491. if (!otg)
  492. return -ENODEV;
  493. otg_dev = container_of(otg->phy, struct fsl_otg, phy);
  494. VDBG("otg_dev 0x%x\n", (int)otg_dev);
  495. VDBG("fsl_otg_dev 0x%x\n", (int)fsl_otg_dev);
  496. if (otg_dev != fsl_otg_dev)
  497. return -ENODEV;
  498. if (!gadget) {
  499. if (!otg->default_a)
  500. otg->gadget->ops->vbus_draw(otg->gadget, 0);
  501. usb_gadget_vbus_disconnect(otg->gadget);
  502. otg->gadget = 0;
  503. otg_dev->fsm.b_bus_req = 0;
  504. otg_statemachine(&otg_dev->fsm);
  505. return 0;
  506. }
  507. otg->gadget = gadget;
  508. otg->gadget->is_a_peripheral = !otg_dev->fsm.id;
  509. otg_dev->fsm.b_bus_req = 1;
  510. /* start the gadget right away if the ID pin says Mini-B */
  511. pr_debug("ID pin=%d\n", otg_dev->fsm.id);
  512. if (otg_dev->fsm.id == 1) {
  513. fsl_otg_start_host(&otg_dev->fsm, 0);
  514. otg_drv_vbus(&otg_dev->fsm, 0);
  515. fsl_otg_start_gadget(&otg_dev->fsm, 1);
  516. }
  517. return 0;
  518. }
  519. /* Set OTG port power, only for B-device */
  520. static int fsl_otg_set_power(struct usb_phy *phy, unsigned mA)
  521. {
  522. if (!fsl_otg_dev)
  523. return -ENODEV;
  524. if (phy->state == OTG_STATE_B_PERIPHERAL)
  525. pr_info("FSL OTG: Draw %d mA\n", mA);
  526. return 0;
  527. }
  528. /*
  529. * Delayed pin detect interrupt processing.
  530. *
  531. * When the Mini-A cable is disconnected from the board,
  532. * the pin-detect interrupt happens before the disconnect
  533. * interrupts for the connected device(s). In order to
  534. * process the disconnect interrupt(s) prior to switching
  535. * roles, the pin-detect interrupts are delayed, and handled
  536. * by this routine.
  537. */
  538. static void fsl_otg_event(struct work_struct *work)
  539. {
  540. struct fsl_otg *og = container_of(work, struct fsl_otg, otg_event.work);
  541. struct otg_fsm *fsm = &og->fsm;
  542. if (fsm->id) { /* switch to gadget */
  543. fsl_otg_start_host(fsm, 0);
  544. otg_drv_vbus(fsm, 0);
  545. fsl_otg_start_gadget(fsm, 1);
  546. }
  547. }
  548. /* B-device start SRP */
  549. static int fsl_otg_start_srp(struct usb_otg *otg)
  550. {
  551. struct fsl_otg *otg_dev;
  552. if (!otg || otg->phy->state != OTG_STATE_B_IDLE)
  553. return -ENODEV;
  554. otg_dev = container_of(otg->phy, struct fsl_otg, phy);
  555. if (otg_dev != fsl_otg_dev)
  556. return -ENODEV;
  557. otg_dev->fsm.b_bus_req = 1;
  558. otg_statemachine(&otg_dev->fsm);
  559. return 0;
  560. }
  561. /* A_host suspend will call this function to start hnp */
  562. static int fsl_otg_start_hnp(struct usb_otg *otg)
  563. {
  564. struct fsl_otg *otg_dev;
  565. if (!otg)
  566. return -ENODEV;
  567. otg_dev = container_of(otg->phy, struct fsl_otg, phy);
  568. if (otg_dev != fsl_otg_dev)
  569. return -ENODEV;
  570. pr_debug("start_hnp...\n");
  571. /* clear a_bus_req to enter a_suspend state */
  572. otg_dev->fsm.a_bus_req = 0;
  573. otg_statemachine(&otg_dev->fsm);
  574. return 0;
  575. }
  576. /*
  577. * Interrupt handler. OTG/host/peripheral share the same int line.
  578. * OTG driver clears OTGSC interrupts and leaves USB interrupts
  579. * intact. It needs to have knowledge of some USB interrupts
  580. * such as port change.
  581. */
  582. irqreturn_t fsl_otg_isr(int irq, void *dev_id)
  583. {
  584. struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
  585. struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg;
  586. u32 otg_int_src, otg_sc;
  587. otg_sc = fsl_readl(&usb_dr_regs->otgsc);
  588. otg_int_src = otg_sc & OTGSC_INTSTS_MASK & (otg_sc >> 8);
  589. /* Only clear otg interrupts */
  590. fsl_writel(otg_sc, &usb_dr_regs->otgsc);
  591. /*FIXME: ID change not generate when init to 0 */
  592. fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
  593. otg->default_a = (fsm->id == 0);
  594. /* process OTG interrupts */
  595. if (otg_int_src) {
  596. if (otg_int_src & OTGSC_INTSTS_USB_ID) {
  597. fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
  598. otg->default_a = (fsm->id == 0);
  599. /* clear conn information */
  600. if (fsm->id)
  601. fsm->b_conn = 0;
  602. else
  603. fsm->a_conn = 0;
  604. if (otg->host)
  605. otg->host->is_b_host = fsm->id;
  606. if (otg->gadget)
  607. otg->gadget->is_a_peripheral = !fsm->id;
  608. VDBG("ID int (ID is %d)\n", fsm->id);
  609. if (fsm->id) { /* switch to gadget */
  610. schedule_delayed_work(
  611. &((struct fsl_otg *)dev_id)->otg_event,
  612. 100);
  613. } else { /* switch to host */
  614. cancel_delayed_work(&
  615. ((struct fsl_otg *)dev_id)->
  616. otg_event);
  617. fsl_otg_start_gadget(fsm, 0);
  618. otg_drv_vbus(fsm, 1);
  619. fsl_otg_start_host(fsm, 1);
  620. }
  621. return IRQ_HANDLED;
  622. }
  623. }
  624. return IRQ_NONE;
  625. }
  626. static struct otg_fsm_ops fsl_otg_ops = {
  627. .chrg_vbus = fsl_otg_chrg_vbus,
  628. .drv_vbus = fsl_otg_drv_vbus,
  629. .loc_conn = fsl_otg_loc_conn,
  630. .loc_sof = fsl_otg_loc_sof,
  631. .start_pulse = fsl_otg_start_pulse,
  632. .add_timer = fsl_otg_add_timer,
  633. .del_timer = fsl_otg_del_timer,
  634. .start_host = fsl_otg_start_host,
  635. .start_gadget = fsl_otg_start_gadget,
  636. };
  637. /* Initialize the global variable fsl_otg_dev and request IRQ for OTG */
  638. static int fsl_otg_conf(struct platform_device *pdev)
  639. {
  640. struct fsl_otg *fsl_otg_tc;
  641. int status;
  642. if (fsl_otg_dev)
  643. return 0;
  644. /* allocate space to fsl otg device */
  645. fsl_otg_tc = kzalloc(sizeof(struct fsl_otg), GFP_KERNEL);
  646. if (!fsl_otg_tc)
  647. return -ENOMEM;
  648. fsl_otg_tc->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
  649. if (!fsl_otg_tc->phy.otg) {
  650. kfree(fsl_otg_tc);
  651. return -ENOMEM;
  652. }
  653. INIT_DELAYED_WORK(&fsl_otg_tc->otg_event, fsl_otg_event);
  654. INIT_LIST_HEAD(&active_timers);
  655. status = fsl_otg_init_timers(&fsl_otg_tc->fsm);
  656. if (status) {
  657. pr_info("Couldn't init OTG timers\n");
  658. goto err;
  659. }
  660. spin_lock_init(&fsl_otg_tc->fsm.lock);
  661. /* Set OTG state machine operations */
  662. fsl_otg_tc->fsm.ops = &fsl_otg_ops;
  663. /* initialize the otg structure */
  664. fsl_otg_tc->phy.label = DRIVER_DESC;
  665. fsl_otg_tc->phy.dev = &pdev->dev;
  666. fsl_otg_tc->phy.set_power = fsl_otg_set_power;
  667. fsl_otg_tc->phy.otg->phy = &fsl_otg_tc->phy;
  668. fsl_otg_tc->phy.otg->set_host = fsl_otg_set_host;
  669. fsl_otg_tc->phy.otg->set_peripheral = fsl_otg_set_peripheral;
  670. fsl_otg_tc->phy.otg->start_hnp = fsl_otg_start_hnp;
  671. fsl_otg_tc->phy.otg->start_srp = fsl_otg_start_srp;
  672. fsl_otg_dev = fsl_otg_tc;
  673. /* Store the otg transceiver */
  674. status = usb_add_phy(&fsl_otg_tc->phy, USB_PHY_TYPE_USB2);
  675. if (status) {
  676. pr_warn(FSL_OTG_NAME ": unable to register OTG transceiver.\n");
  677. goto err;
  678. }
  679. return 0;
  680. err:
  681. fsl_otg_uninit_timers();
  682. kfree(fsl_otg_tc->phy.otg);
  683. kfree(fsl_otg_tc);
  684. return status;
  685. }
  686. /* OTG Initialization */
  687. int usb_otg_start(struct platform_device *pdev)
  688. {
  689. struct fsl_otg *p_otg;
  690. struct usb_phy *otg_trans = usb_get_phy(USB_PHY_TYPE_USB2);
  691. struct otg_fsm *fsm;
  692. int status;
  693. struct resource *res;
  694. u32 temp;
  695. struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
  696. p_otg = container_of(otg_trans, struct fsl_otg, phy);
  697. fsm = &p_otg->fsm;
  698. /* Initialize the state machine structure with default values */
  699. SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED);
  700. fsm->otg = p_otg->phy.otg;
  701. /* We don't require predefined MEM/IRQ resource index */
  702. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  703. if (!res)
  704. return -ENXIO;
  705. /* We don't request_mem_region here to enable resource sharing
  706. * with host/device */
  707. usb_dr_regs = ioremap(res->start, sizeof(struct usb_dr_mmap));
  708. p_otg->dr_mem_map = (struct usb_dr_mmap *)usb_dr_regs;
  709. pdata->regs = (void *)usb_dr_regs;
  710. if (pdata->init && pdata->init(pdev) != 0)
  711. return -EINVAL;
  712. if (pdata->big_endian_mmio) {
  713. _fsl_readl = _fsl_readl_be;
  714. _fsl_writel = _fsl_writel_be;
  715. } else {
  716. _fsl_readl = _fsl_readl_le;
  717. _fsl_writel = _fsl_writel_le;
  718. }
  719. /* request irq */
  720. p_otg->irq = platform_get_irq(pdev, 0);
  721. status = request_irq(p_otg->irq, fsl_otg_isr,
  722. IRQF_SHARED, driver_name, p_otg);
  723. if (status) {
  724. dev_dbg(p_otg->phy.dev, "can't get IRQ %d, error %d\n",
  725. p_otg->irq, status);
  726. iounmap(p_otg->dr_mem_map);
  727. kfree(p_otg->phy.otg);
  728. kfree(p_otg);
  729. return status;
  730. }
  731. /* stop the controller */
  732. temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
  733. temp &= ~USB_CMD_RUN_STOP;
  734. fsl_writel(temp, &p_otg->dr_mem_map->usbcmd);
  735. /* reset the controller */
  736. temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
  737. temp |= USB_CMD_CTRL_RESET;
  738. fsl_writel(temp, &p_otg->dr_mem_map->usbcmd);
  739. /* wait reset completed */
  740. while (fsl_readl(&p_otg->dr_mem_map->usbcmd) & USB_CMD_CTRL_RESET)
  741. ;
  742. /* configure the VBUSHS as IDLE(both host and device) */
  743. temp = USB_MODE_STREAM_DISABLE | (pdata->es ? USB_MODE_ES : 0);
  744. fsl_writel(temp, &p_otg->dr_mem_map->usbmode);
  745. /* configure PHY interface */
  746. temp = fsl_readl(&p_otg->dr_mem_map->portsc);
  747. temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
  748. switch (pdata->phy_mode) {
  749. case FSL_USB2_PHY_ULPI:
  750. temp |= PORTSC_PTS_ULPI;
  751. break;
  752. case FSL_USB2_PHY_UTMI_WIDE:
  753. temp |= PORTSC_PTW_16BIT;
  754. /* fall through */
  755. case FSL_USB2_PHY_UTMI:
  756. temp |= PORTSC_PTS_UTMI;
  757. /* fall through */
  758. default:
  759. break;
  760. }
  761. fsl_writel(temp, &p_otg->dr_mem_map->portsc);
  762. if (pdata->have_sysif_regs) {
  763. /* configure control enable IO output, big endian register */
  764. temp = __raw_readl(&p_otg->dr_mem_map->control);
  765. temp |= USB_CTRL_IOENB;
  766. __raw_writel(temp, &p_otg->dr_mem_map->control);
  767. }
  768. /* disable all interrupt and clear all OTGSC status */
  769. temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
  770. temp &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK;
  771. temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE;
  772. fsl_writel(temp, &p_otg->dr_mem_map->otgsc);
  773. /*
  774. * The identification (id) input is FALSE when a Mini-A plug is inserted
  775. * in the devices Mini-AB receptacle. Otherwise, this input is TRUE.
  776. * Also: record initial state of ID pin
  777. */
  778. if (fsl_readl(&p_otg->dr_mem_map->otgsc) & OTGSC_STS_USB_ID) {
  779. p_otg->phy.state = OTG_STATE_UNDEFINED;
  780. p_otg->fsm.id = 1;
  781. } else {
  782. p_otg->phy.state = OTG_STATE_A_IDLE;
  783. p_otg->fsm.id = 0;
  784. }
  785. pr_debug("initial ID pin=%d\n", p_otg->fsm.id);
  786. /* enable OTG ID pin interrupt */
  787. temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
  788. temp |= OTGSC_INTR_USB_ID_EN;
  789. temp &= ~(OTGSC_CTRL_VBUS_DISCHARGE | OTGSC_INTR_1MS_TIMER_EN);
  790. fsl_writel(temp, &p_otg->dr_mem_map->otgsc);
  791. return 0;
  792. }
  793. /*
  794. * state file in sysfs
  795. */
  796. static int show_fsl_usb2_otg_state(struct device *dev,
  797. struct device_attribute *attr, char *buf)
  798. {
  799. struct otg_fsm *fsm = &fsl_otg_dev->fsm;
  800. char *next = buf;
  801. unsigned size = PAGE_SIZE;
  802. unsigned long flags;
  803. int t;
  804. spin_lock_irqsave(&fsm->lock, flags);
  805. /* basic driver infomation */
  806. t = scnprintf(next, size,
  807. DRIVER_DESC "\n" "fsl_usb2_otg version: %s\n\n",
  808. DRIVER_VERSION);
  809. size -= t;
  810. next += t;
  811. /* Registers */
  812. t = scnprintf(next, size,
  813. "OTGSC: 0x%08x\n"
  814. "PORTSC: 0x%08x\n"
  815. "USBMODE: 0x%08x\n"
  816. "USBCMD: 0x%08x\n"
  817. "USBSTS: 0x%08x\n"
  818. "USBINTR: 0x%08x\n",
  819. fsl_readl(&usb_dr_regs->otgsc),
  820. fsl_readl(&usb_dr_regs->portsc),
  821. fsl_readl(&usb_dr_regs->usbmode),
  822. fsl_readl(&usb_dr_regs->usbcmd),
  823. fsl_readl(&usb_dr_regs->usbsts),
  824. fsl_readl(&usb_dr_regs->usbintr));
  825. size -= t;
  826. next += t;
  827. /* State */
  828. t = scnprintf(next, size,
  829. "OTG state: %s\n\n",
  830. usb_otg_state_string(fsl_otg_dev->phy.state));
  831. size -= t;
  832. next += t;
  833. /* State Machine Variables */
  834. t = scnprintf(next, size,
  835. "a_bus_req: %d\n"
  836. "b_bus_req: %d\n"
  837. "a_bus_resume: %d\n"
  838. "a_bus_suspend: %d\n"
  839. "a_conn: %d\n"
  840. "a_sess_vld: %d\n"
  841. "a_srp_det: %d\n"
  842. "a_vbus_vld: %d\n"
  843. "b_bus_resume: %d\n"
  844. "b_bus_suspend: %d\n"
  845. "b_conn: %d\n"
  846. "b_se0_srp: %d\n"
  847. "b_sess_end: %d\n"
  848. "b_sess_vld: %d\n"
  849. "id: %d\n",
  850. fsm->a_bus_req,
  851. fsm->b_bus_req,
  852. fsm->a_bus_resume,
  853. fsm->a_bus_suspend,
  854. fsm->a_conn,
  855. fsm->a_sess_vld,
  856. fsm->a_srp_det,
  857. fsm->a_vbus_vld,
  858. fsm->b_bus_resume,
  859. fsm->b_bus_suspend,
  860. fsm->b_conn,
  861. fsm->b_se0_srp,
  862. fsm->b_sess_end,
  863. fsm->b_sess_vld,
  864. fsm->id);
  865. size -= t;
  866. next += t;
  867. spin_unlock_irqrestore(&fsm->lock, flags);
  868. return PAGE_SIZE - size;
  869. }
  870. static DEVICE_ATTR(fsl_usb2_otg_state, S_IRUGO, show_fsl_usb2_otg_state, NULL);
  871. /* Char driver interface to control some OTG input */
  872. /*
  873. * Handle some ioctl command, such as get otg
  874. * status and set host suspend
  875. */
  876. static long fsl_otg_ioctl(struct file *file, unsigned int cmd,
  877. unsigned long arg)
  878. {
  879. u32 retval = 0;
  880. switch (cmd) {
  881. case GET_OTG_STATUS:
  882. retval = fsl_otg_dev->host_working;
  883. break;
  884. case SET_A_SUSPEND_REQ:
  885. fsl_otg_dev->fsm.a_suspend_req = arg;
  886. break;
  887. case SET_A_BUS_DROP:
  888. fsl_otg_dev->fsm.a_bus_drop = arg;
  889. break;
  890. case SET_A_BUS_REQ:
  891. fsl_otg_dev->fsm.a_bus_req = arg;
  892. break;
  893. case SET_B_BUS_REQ:
  894. fsl_otg_dev->fsm.b_bus_req = arg;
  895. break;
  896. default:
  897. break;
  898. }
  899. otg_statemachine(&fsl_otg_dev->fsm);
  900. return retval;
  901. }
  902. static int fsl_otg_open(struct inode *inode, struct file *file)
  903. {
  904. return 0;
  905. }
  906. static int fsl_otg_release(struct inode *inode, struct file *file)
  907. {
  908. return 0;
  909. }
  910. static const struct file_operations otg_fops = {
  911. .owner = THIS_MODULE,
  912. .llseek = NULL,
  913. .read = NULL,
  914. .write = NULL,
  915. .unlocked_ioctl = fsl_otg_ioctl,
  916. .open = fsl_otg_open,
  917. .release = fsl_otg_release,
  918. };
  919. static int fsl_otg_probe(struct platform_device *pdev)
  920. {
  921. int ret;
  922. if (!pdev->dev.platform_data)
  923. return -ENODEV;
  924. /* configure the OTG */
  925. ret = fsl_otg_conf(pdev);
  926. if (ret) {
  927. dev_err(&pdev->dev, "Couldn't configure OTG module\n");
  928. return ret;
  929. }
  930. /* start OTG */
  931. ret = usb_otg_start(pdev);
  932. if (ret) {
  933. dev_err(&pdev->dev, "Can't init FSL OTG device\n");
  934. return ret;
  935. }
  936. ret = register_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME, &otg_fops);
  937. if (ret) {
  938. dev_err(&pdev->dev, "unable to register FSL OTG device\n");
  939. return ret;
  940. }
  941. ret = device_create_file(&pdev->dev, &dev_attr_fsl_usb2_otg_state);
  942. if (ret)
  943. dev_warn(&pdev->dev, "Can't register sysfs attribute\n");
  944. return ret;
  945. }
  946. static int fsl_otg_remove(struct platform_device *pdev)
  947. {
  948. struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
  949. usb_remove_phy(&fsl_otg_dev->phy);
  950. free_irq(fsl_otg_dev->irq, fsl_otg_dev);
  951. iounmap((void *)usb_dr_regs);
  952. fsl_otg_uninit_timers();
  953. kfree(fsl_otg_dev->phy.otg);
  954. kfree(fsl_otg_dev);
  955. device_remove_file(&pdev->dev, &dev_attr_fsl_usb2_otg_state);
  956. unregister_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME);
  957. if (pdata->exit)
  958. pdata->exit(pdev);
  959. return 0;
  960. }
  961. struct platform_driver fsl_otg_driver = {
  962. .probe = fsl_otg_probe,
  963. .remove = fsl_otg_remove,
  964. .driver = {
  965. .name = driver_name,
  966. .owner = THIS_MODULE,
  967. },
  968. };
  969. module_platform_driver(fsl_otg_driver);
  970. MODULE_DESCRIPTION(DRIVER_INFO);
  971. MODULE_AUTHOR(DRIVER_AUTHOR);
  972. MODULE_LICENSE("GPL");