xhci.c 148 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/pci.h>
  23. #include <linux/irq.h>
  24. #include <linux/log2.h>
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/slab.h>
  28. #include <linux/dmi.h>
  29. #include "xhci.h"
  30. #define DRIVER_AUTHOR "Sarah Sharp"
  31. #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
  32. /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
  33. static int link_quirk;
  34. module_param(link_quirk, int, S_IRUGO | S_IWUSR);
  35. MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
  36. /* TODO: copied from ehci-hcd.c - can this be refactored? */
  37. /*
  38. * xhci_handshake - spin reading hc until handshake completes or fails
  39. * @ptr: address of hc register to be read
  40. * @mask: bits to look at in result of read
  41. * @done: value of those bits when handshake succeeds
  42. * @usec: timeout in microseconds
  43. *
  44. * Returns negative errno, or zero on success
  45. *
  46. * Success happens when the "mask" bits have the specified value (hardware
  47. * handshake done). There are two failure modes: "usec" have passed (major
  48. * hardware flakeout), or the register reads as all-ones (hardware removed).
  49. */
  50. int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
  51. u32 mask, u32 done, int usec)
  52. {
  53. u32 result;
  54. do {
  55. result = xhci_readl(xhci, ptr);
  56. if (result == ~(u32)0) /* card removed */
  57. return -ENODEV;
  58. result &= mask;
  59. if (result == done)
  60. return 0;
  61. udelay(1);
  62. usec--;
  63. } while (usec > 0);
  64. return -ETIMEDOUT;
  65. }
  66. /*
  67. * Disable interrupts and begin the xHCI halting process.
  68. */
  69. void xhci_quiesce(struct xhci_hcd *xhci)
  70. {
  71. u32 halted;
  72. u32 cmd;
  73. u32 mask;
  74. mask = ~(XHCI_IRQS);
  75. halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
  76. if (!halted)
  77. mask &= ~CMD_RUN;
  78. cmd = xhci_readl(xhci, &xhci->op_regs->command);
  79. cmd &= mask;
  80. xhci_writel(xhci, cmd, &xhci->op_regs->command);
  81. }
  82. /*
  83. * Force HC into halt state.
  84. *
  85. * Disable any IRQs and clear the run/stop bit.
  86. * HC will complete any current and actively pipelined transactions, and
  87. * should halt within 16 ms of the run/stop bit being cleared.
  88. * Read HC Halted bit in the status register to see when the HC is finished.
  89. */
  90. int xhci_halt(struct xhci_hcd *xhci)
  91. {
  92. int ret;
  93. xhci_dbg(xhci, "// Halt the HC\n");
  94. xhci_quiesce(xhci);
  95. ret = xhci_handshake(xhci, &xhci->op_regs->status,
  96. STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
  97. if (!ret) {
  98. xhci->xhc_state |= XHCI_STATE_HALTED;
  99. xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
  100. } else
  101. xhci_warn(xhci, "Host not halted after %u microseconds.\n",
  102. XHCI_MAX_HALT_USEC);
  103. return ret;
  104. }
  105. /*
  106. * Set the run bit and wait for the host to be running.
  107. */
  108. static int xhci_start(struct xhci_hcd *xhci)
  109. {
  110. u32 temp;
  111. int ret;
  112. temp = xhci_readl(xhci, &xhci->op_regs->command);
  113. temp |= (CMD_RUN);
  114. xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
  115. temp);
  116. xhci_writel(xhci, temp, &xhci->op_regs->command);
  117. /*
  118. * Wait for the HCHalted Status bit to be 0 to indicate the host is
  119. * running.
  120. */
  121. ret = xhci_handshake(xhci, &xhci->op_regs->status,
  122. STS_HALT, 0, XHCI_MAX_HALT_USEC);
  123. if (ret == -ETIMEDOUT)
  124. xhci_err(xhci, "Host took too long to start, "
  125. "waited %u microseconds.\n",
  126. XHCI_MAX_HALT_USEC);
  127. if (!ret)
  128. xhci->xhc_state &= ~XHCI_STATE_HALTED;
  129. return ret;
  130. }
  131. /*
  132. * Reset a halted HC.
  133. *
  134. * This resets pipelines, timers, counters, state machines, etc.
  135. * Transactions will be terminated immediately, and operational registers
  136. * will be set to their defaults.
  137. */
  138. int xhci_reset(struct xhci_hcd *xhci)
  139. {
  140. u32 command;
  141. u32 state;
  142. int ret, i;
  143. state = xhci_readl(xhci, &xhci->op_regs->status);
  144. if ((state & STS_HALT) == 0) {
  145. xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
  146. return 0;
  147. }
  148. xhci_dbg(xhci, "// Reset the HC\n");
  149. command = xhci_readl(xhci, &xhci->op_regs->command);
  150. command |= CMD_RESET;
  151. xhci_writel(xhci, command, &xhci->op_regs->command);
  152. ret = xhci_handshake(xhci, &xhci->op_regs->command,
  153. CMD_RESET, 0, 10 * 1000 * 1000);
  154. if (ret)
  155. return ret;
  156. xhci_dbg(xhci, "Wait for controller to be ready for doorbell rings\n");
  157. /*
  158. * xHCI cannot write to any doorbells or operational registers other
  159. * than status until the "Controller Not Ready" flag is cleared.
  160. */
  161. ret = xhci_handshake(xhci, &xhci->op_regs->status,
  162. STS_CNR, 0, 10 * 1000 * 1000);
  163. for (i = 0; i < 2; ++i) {
  164. xhci->bus_state[i].port_c_suspend = 0;
  165. xhci->bus_state[i].suspended_ports = 0;
  166. xhci->bus_state[i].resuming_ports = 0;
  167. }
  168. return ret;
  169. }
  170. #ifdef CONFIG_PCI
  171. static int xhci_free_msi(struct xhci_hcd *xhci)
  172. {
  173. int i;
  174. if (!xhci->msix_entries)
  175. return -EINVAL;
  176. for (i = 0; i < xhci->msix_count; i++)
  177. if (xhci->msix_entries[i].vector)
  178. free_irq(xhci->msix_entries[i].vector,
  179. xhci_to_hcd(xhci));
  180. return 0;
  181. }
  182. /*
  183. * Set up MSI
  184. */
  185. static int xhci_setup_msi(struct xhci_hcd *xhci)
  186. {
  187. int ret;
  188. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  189. ret = pci_enable_msi(pdev);
  190. if (ret) {
  191. xhci_dbg(xhci, "failed to allocate MSI entry\n");
  192. return ret;
  193. }
  194. ret = request_irq(pdev->irq, xhci_msi_irq,
  195. 0, "xhci_hcd", xhci_to_hcd(xhci));
  196. if (ret) {
  197. xhci_dbg(xhci, "disable MSI interrupt\n");
  198. pci_disable_msi(pdev);
  199. }
  200. return ret;
  201. }
  202. /*
  203. * Free IRQs
  204. * free all IRQs request
  205. */
  206. static void xhci_free_irq(struct xhci_hcd *xhci)
  207. {
  208. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  209. int ret;
  210. /* return if using legacy interrupt */
  211. if (xhci_to_hcd(xhci)->irq > 0)
  212. return;
  213. ret = xhci_free_msi(xhci);
  214. if (!ret)
  215. return;
  216. if (pdev->irq > 0)
  217. free_irq(pdev->irq, xhci_to_hcd(xhci));
  218. return;
  219. }
  220. /*
  221. * Set up MSI-X
  222. */
  223. static int xhci_setup_msix(struct xhci_hcd *xhci)
  224. {
  225. int i, ret = 0;
  226. struct usb_hcd *hcd = xhci_to_hcd(xhci);
  227. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  228. /*
  229. * calculate number of msi-x vectors supported.
  230. * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
  231. * with max number of interrupters based on the xhci HCSPARAMS1.
  232. * - num_online_cpus: maximum msi-x vectors per CPUs core.
  233. * Add additional 1 vector to ensure always available interrupt.
  234. */
  235. xhci->msix_count = min(num_online_cpus() + 1,
  236. HCS_MAX_INTRS(xhci->hcs_params1));
  237. xhci->msix_entries =
  238. kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
  239. GFP_KERNEL);
  240. if (!xhci->msix_entries) {
  241. xhci_err(xhci, "Failed to allocate MSI-X entries\n");
  242. return -ENOMEM;
  243. }
  244. for (i = 0; i < xhci->msix_count; i++) {
  245. xhci->msix_entries[i].entry = i;
  246. xhci->msix_entries[i].vector = 0;
  247. }
  248. ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
  249. if (ret) {
  250. xhci_dbg(xhci, "Failed to enable MSI-X\n");
  251. goto free_entries;
  252. }
  253. for (i = 0; i < xhci->msix_count; i++) {
  254. ret = request_irq(xhci->msix_entries[i].vector,
  255. xhci_msi_irq,
  256. 0, "xhci_hcd", xhci_to_hcd(xhci));
  257. if (ret)
  258. goto disable_msix;
  259. }
  260. hcd->msix_enabled = 1;
  261. return ret;
  262. disable_msix:
  263. xhci_dbg(xhci, "disable MSI-X interrupt\n");
  264. xhci_free_irq(xhci);
  265. pci_disable_msix(pdev);
  266. free_entries:
  267. kfree(xhci->msix_entries);
  268. xhci->msix_entries = NULL;
  269. return ret;
  270. }
  271. /* Free any IRQs and disable MSI-X */
  272. static void xhci_cleanup_msix(struct xhci_hcd *xhci)
  273. {
  274. struct usb_hcd *hcd = xhci_to_hcd(xhci);
  275. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  276. xhci_free_irq(xhci);
  277. if (xhci->msix_entries) {
  278. pci_disable_msix(pdev);
  279. kfree(xhci->msix_entries);
  280. xhci->msix_entries = NULL;
  281. } else {
  282. pci_disable_msi(pdev);
  283. }
  284. hcd->msix_enabled = 0;
  285. return;
  286. }
  287. static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
  288. {
  289. int i;
  290. if (xhci->msix_entries) {
  291. for (i = 0; i < xhci->msix_count; i++)
  292. synchronize_irq(xhci->msix_entries[i].vector);
  293. }
  294. }
  295. static int xhci_try_enable_msi(struct usb_hcd *hcd)
  296. {
  297. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  298. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  299. int ret;
  300. /*
  301. * Some Fresco Logic host controllers advertise MSI, but fail to
  302. * generate interrupts. Don't even try to enable MSI.
  303. */
  304. if (xhci->quirks & XHCI_BROKEN_MSI)
  305. goto legacy_irq;
  306. /* unregister the legacy interrupt */
  307. if (hcd->irq)
  308. free_irq(hcd->irq, hcd);
  309. hcd->irq = 0;
  310. ret = xhci_setup_msix(xhci);
  311. if (ret)
  312. /* fall back to msi*/
  313. ret = xhci_setup_msi(xhci);
  314. if (!ret)
  315. /* hcd->irq is 0, we have MSI */
  316. return 0;
  317. if (!pdev->irq) {
  318. xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
  319. return -EINVAL;
  320. }
  321. legacy_irq:
  322. /* fall back to legacy interrupt*/
  323. ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
  324. hcd->irq_descr, hcd);
  325. if (ret) {
  326. xhci_err(xhci, "request interrupt %d failed\n",
  327. pdev->irq);
  328. return ret;
  329. }
  330. hcd->irq = pdev->irq;
  331. return 0;
  332. }
  333. #else
  334. static int xhci_try_enable_msi(struct usb_hcd *hcd)
  335. {
  336. return 0;
  337. }
  338. static void xhci_cleanup_msix(struct xhci_hcd *xhci)
  339. {
  340. }
  341. static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
  342. {
  343. }
  344. #endif
  345. static void compliance_mode_recovery(unsigned long arg)
  346. {
  347. struct xhci_hcd *xhci;
  348. struct usb_hcd *hcd;
  349. u32 temp;
  350. int i;
  351. xhci = (struct xhci_hcd *)arg;
  352. for (i = 0; i < xhci->num_usb3_ports; i++) {
  353. temp = xhci_readl(xhci, xhci->usb3_ports[i]);
  354. if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
  355. /*
  356. * Compliance Mode Detected. Letting USB Core
  357. * handle the Warm Reset
  358. */
  359. xhci_dbg(xhci, "Compliance mode detected->port %d\n",
  360. i + 1);
  361. xhci_dbg(xhci, "Attempting compliance mode recovery\n");
  362. hcd = xhci->shared_hcd;
  363. if (hcd->state == HC_STATE_SUSPENDED)
  364. usb_hcd_resume_root_hub(hcd);
  365. usb_hcd_poll_rh_status(hcd);
  366. }
  367. }
  368. if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
  369. mod_timer(&xhci->comp_mode_recovery_timer,
  370. jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
  371. }
  372. /*
  373. * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
  374. * that causes ports behind that hardware to enter compliance mode sometimes.
  375. * The quirk creates a timer that polls every 2 seconds the link state of
  376. * each host controller's port and recovers it by issuing a Warm reset
  377. * if Compliance mode is detected, otherwise the port will become "dead" (no
  378. * device connections or disconnections will be detected anymore). Becasue no
  379. * status event is generated when entering compliance mode (per xhci spec),
  380. * this quirk is needed on systems that have the failing hardware installed.
  381. */
  382. static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
  383. {
  384. xhci->port_status_u0 = 0;
  385. init_timer(&xhci->comp_mode_recovery_timer);
  386. xhci->comp_mode_recovery_timer.data = (unsigned long) xhci;
  387. xhci->comp_mode_recovery_timer.function = compliance_mode_recovery;
  388. xhci->comp_mode_recovery_timer.expires = jiffies +
  389. msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
  390. set_timer_slack(&xhci->comp_mode_recovery_timer,
  391. msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
  392. add_timer(&xhci->comp_mode_recovery_timer);
  393. xhci_dbg(xhci, "Compliance mode recovery timer initialized\n");
  394. }
  395. /*
  396. * This function identifies the systems that have installed the SN65LVPE502CP
  397. * USB3.0 re-driver and that need the Compliance Mode Quirk.
  398. * Systems:
  399. * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
  400. */
  401. bool xhci_compliance_mode_recovery_timer_quirk_check(void)
  402. {
  403. const char *dmi_product_name, *dmi_sys_vendor;
  404. dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
  405. dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
  406. if (!dmi_product_name || !dmi_sys_vendor)
  407. return false;
  408. if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
  409. return false;
  410. if (strstr(dmi_product_name, "Z420") ||
  411. strstr(dmi_product_name, "Z620") ||
  412. strstr(dmi_product_name, "Z820") ||
  413. strstr(dmi_product_name, "Z1 Workstation"))
  414. return true;
  415. return false;
  416. }
  417. static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
  418. {
  419. return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
  420. }
  421. /*
  422. * Initialize memory for HCD and xHC (one-time init).
  423. *
  424. * Program the PAGESIZE register, initialize the device context array, create
  425. * device contexts (?), set up a command ring segment (or two?), create event
  426. * ring (one for now).
  427. */
  428. int xhci_init(struct usb_hcd *hcd)
  429. {
  430. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  431. int retval = 0;
  432. xhci_dbg(xhci, "xhci_init\n");
  433. spin_lock_init(&xhci->lock);
  434. if (xhci->hci_version == 0x95 && link_quirk) {
  435. xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
  436. xhci->quirks |= XHCI_LINK_TRB_QUIRK;
  437. } else {
  438. xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
  439. }
  440. retval = xhci_mem_init(xhci, GFP_KERNEL);
  441. xhci_dbg(xhci, "Finished xhci_init\n");
  442. /* Initializing Compliance Mode Recovery Data If Needed */
  443. if (xhci_compliance_mode_recovery_timer_quirk_check()) {
  444. xhci->quirks |= XHCI_COMP_MODE_QUIRK;
  445. compliance_mode_recovery_timer_init(xhci);
  446. }
  447. return retval;
  448. }
  449. /*-------------------------------------------------------------------------*/
  450. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  451. static void xhci_event_ring_work(unsigned long arg)
  452. {
  453. unsigned long flags;
  454. int temp;
  455. u64 temp_64;
  456. struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
  457. int i, j;
  458. xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
  459. spin_lock_irqsave(&xhci->lock, flags);
  460. temp = xhci_readl(xhci, &xhci->op_regs->status);
  461. xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
  462. if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
  463. (xhci->xhc_state & XHCI_STATE_HALTED)) {
  464. xhci_dbg(xhci, "HW died, polling stopped.\n");
  465. spin_unlock_irqrestore(&xhci->lock, flags);
  466. return;
  467. }
  468. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  469. xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
  470. xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
  471. xhci->error_bitmask = 0;
  472. xhci_dbg(xhci, "Event ring:\n");
  473. xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
  474. xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
  475. temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  476. temp_64 &= ~ERST_PTR_MASK;
  477. xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
  478. xhci_dbg(xhci, "Command ring:\n");
  479. xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
  480. xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
  481. xhci_dbg_cmd_ptrs(xhci);
  482. for (i = 0; i < MAX_HC_SLOTS; ++i) {
  483. if (!xhci->devs[i])
  484. continue;
  485. for (j = 0; j < 31; ++j) {
  486. xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]);
  487. }
  488. }
  489. spin_unlock_irqrestore(&xhci->lock, flags);
  490. if (!xhci->zombie)
  491. mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
  492. else
  493. xhci_dbg(xhci, "Quit polling the event ring.\n");
  494. }
  495. #endif
  496. static int xhci_run_finished(struct xhci_hcd *xhci)
  497. {
  498. if (xhci_start(xhci)) {
  499. xhci_halt(xhci);
  500. return -ENODEV;
  501. }
  502. xhci->shared_hcd->state = HC_STATE_RUNNING;
  503. xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
  504. if (xhci->quirks & XHCI_NEC_HOST)
  505. xhci_ring_cmd_db(xhci);
  506. xhci_dbg(xhci, "Finished xhci_run for USB3 roothub\n");
  507. return 0;
  508. }
  509. /*
  510. * Start the HC after it was halted.
  511. *
  512. * This function is called by the USB core when the HC driver is added.
  513. * Its opposite is xhci_stop().
  514. *
  515. * xhci_init() must be called once before this function can be called.
  516. * Reset the HC, enable device slot contexts, program DCBAAP, and
  517. * set command ring pointer and event ring pointer.
  518. *
  519. * Setup MSI-X vectors and enable interrupts.
  520. */
  521. int xhci_run(struct usb_hcd *hcd)
  522. {
  523. u32 temp;
  524. u64 temp_64;
  525. int ret;
  526. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  527. /* Start the xHCI host controller running only after the USB 2.0 roothub
  528. * is setup.
  529. */
  530. hcd->uses_new_polling = 1;
  531. if (!usb_hcd_is_primary_hcd(hcd))
  532. return xhci_run_finished(xhci);
  533. xhci_dbg(xhci, "xhci_run\n");
  534. ret = xhci_try_enable_msi(hcd);
  535. if (ret)
  536. return ret;
  537. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  538. init_timer(&xhci->event_ring_timer);
  539. xhci->event_ring_timer.data = (unsigned long) xhci;
  540. xhci->event_ring_timer.function = xhci_event_ring_work;
  541. /* Poll the event ring */
  542. xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
  543. xhci->zombie = 0;
  544. xhci_dbg(xhci, "Setting event ring polling timer\n");
  545. add_timer(&xhci->event_ring_timer);
  546. #endif
  547. xhci_dbg(xhci, "Command ring memory map follows:\n");
  548. xhci_debug_ring(xhci, xhci->cmd_ring);
  549. xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
  550. xhci_dbg_cmd_ptrs(xhci);
  551. xhci_dbg(xhci, "ERST memory map follows:\n");
  552. xhci_dbg_erst(xhci, &xhci->erst);
  553. xhci_dbg(xhci, "Event ring:\n");
  554. xhci_debug_ring(xhci, xhci->event_ring);
  555. xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
  556. temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  557. temp_64 &= ~ERST_PTR_MASK;
  558. xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
  559. xhci_dbg(xhci, "// Set the interrupt modulation register\n");
  560. temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
  561. temp &= ~ER_IRQ_INTERVAL_MASK;
  562. temp |= (u32) 160;
  563. xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
  564. /* Set the HCD state before we enable the irqs */
  565. temp = xhci_readl(xhci, &xhci->op_regs->command);
  566. temp |= (CMD_EIE);
  567. xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
  568. temp);
  569. xhci_writel(xhci, temp, &xhci->op_regs->command);
  570. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  571. xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
  572. xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
  573. xhci_writel(xhci, ER_IRQ_ENABLE(temp),
  574. &xhci->ir_set->irq_pending);
  575. xhci_print_ir_set(xhci, 0);
  576. if (xhci->quirks & XHCI_NEC_HOST)
  577. xhci_queue_vendor_command(xhci, 0, 0, 0,
  578. TRB_TYPE(TRB_NEC_GET_FW));
  579. xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
  580. return 0;
  581. }
  582. static void xhci_only_stop_hcd(struct usb_hcd *hcd)
  583. {
  584. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  585. spin_lock_irq(&xhci->lock);
  586. xhci_halt(xhci);
  587. /* The shared_hcd is going to be deallocated shortly (the USB core only
  588. * calls this function when allocation fails in usb_add_hcd(), or
  589. * usb_remove_hcd() is called). So we need to unset xHCI's pointer.
  590. */
  591. xhci->shared_hcd = NULL;
  592. spin_unlock_irq(&xhci->lock);
  593. }
  594. /*
  595. * Stop xHCI driver.
  596. *
  597. * This function is called by the USB core when the HC driver is removed.
  598. * Its opposite is xhci_run().
  599. *
  600. * Disable device contexts, disable IRQs, and quiesce the HC.
  601. * Reset the HC, finish any completed transactions, and cleanup memory.
  602. */
  603. void xhci_stop(struct usb_hcd *hcd)
  604. {
  605. u32 temp;
  606. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  607. if (!usb_hcd_is_primary_hcd(hcd)) {
  608. xhci_only_stop_hcd(xhci->shared_hcd);
  609. return;
  610. }
  611. spin_lock_irq(&xhci->lock);
  612. /* Make sure the xHC is halted for a USB3 roothub
  613. * (xhci_stop() could be called as part of failed init).
  614. */
  615. xhci_halt(xhci);
  616. xhci_reset(xhci);
  617. spin_unlock_irq(&xhci->lock);
  618. xhci_cleanup_msix(xhci);
  619. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  620. /* Tell the event ring poll function not to reschedule */
  621. xhci->zombie = 1;
  622. del_timer_sync(&xhci->event_ring_timer);
  623. #endif
  624. /* Deleting Compliance Mode Recovery Timer */
  625. if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
  626. (!(xhci_all_ports_seen_u0(xhci)))) {
  627. del_timer_sync(&xhci->comp_mode_recovery_timer);
  628. xhci_dbg(xhci, "%s: compliance mode recovery timer deleted\n",
  629. __func__);
  630. }
  631. if (xhci->quirks & XHCI_AMD_PLL_FIX)
  632. usb_amd_dev_put();
  633. xhci_dbg(xhci, "// Disabling event ring interrupts\n");
  634. temp = xhci_readl(xhci, &xhci->op_regs->status);
  635. xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
  636. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  637. xhci_writel(xhci, ER_IRQ_DISABLE(temp),
  638. &xhci->ir_set->irq_pending);
  639. xhci_print_ir_set(xhci, 0);
  640. xhci_dbg(xhci, "cleaning up memory\n");
  641. xhci_mem_cleanup(xhci);
  642. xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
  643. xhci_readl(xhci, &xhci->op_regs->status));
  644. }
  645. /*
  646. * Shutdown HC (not bus-specific)
  647. *
  648. * This is called when the machine is rebooting or halting. We assume that the
  649. * machine will be powered off, and the HC's internal state will be reset.
  650. * Don't bother to free memory.
  651. *
  652. * This will only ever be called with the main usb_hcd (the USB3 roothub).
  653. */
  654. void xhci_shutdown(struct usb_hcd *hcd)
  655. {
  656. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  657. if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
  658. usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
  659. spin_lock_irq(&xhci->lock);
  660. xhci_halt(xhci);
  661. spin_unlock_irq(&xhci->lock);
  662. xhci_cleanup_msix(xhci);
  663. xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
  664. xhci_readl(xhci, &xhci->op_regs->status));
  665. }
  666. #ifdef CONFIG_PM
  667. static void xhci_save_registers(struct xhci_hcd *xhci)
  668. {
  669. xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command);
  670. xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification);
  671. xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
  672. xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg);
  673. xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size);
  674. xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
  675. xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  676. xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  677. xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control);
  678. }
  679. static void xhci_restore_registers(struct xhci_hcd *xhci)
  680. {
  681. xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
  682. xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
  683. xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
  684. xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
  685. xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
  686. xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
  687. xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
  688. xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
  689. xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
  690. }
  691. static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
  692. {
  693. u64 val_64;
  694. /* step 2: initialize command ring buffer */
  695. val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
  696. val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
  697. (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
  698. xhci->cmd_ring->dequeue) &
  699. (u64) ~CMD_RING_RSVD_BITS) |
  700. xhci->cmd_ring->cycle_state;
  701. xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
  702. (long unsigned long) val_64);
  703. xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
  704. }
  705. /*
  706. * The whole command ring must be cleared to zero when we suspend the host.
  707. *
  708. * The host doesn't save the command ring pointer in the suspend well, so we
  709. * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
  710. * aligned, because of the reserved bits in the command ring dequeue pointer
  711. * register. Therefore, we can't just set the dequeue pointer back in the
  712. * middle of the ring (TRBs are 16-byte aligned).
  713. */
  714. static void xhci_clear_command_ring(struct xhci_hcd *xhci)
  715. {
  716. struct xhci_ring *ring;
  717. struct xhci_segment *seg;
  718. ring = xhci->cmd_ring;
  719. seg = ring->deq_seg;
  720. do {
  721. memset(seg->trbs, 0,
  722. sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
  723. seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
  724. cpu_to_le32(~TRB_CYCLE);
  725. seg = seg->next;
  726. } while (seg != ring->deq_seg);
  727. /* Reset the software enqueue and dequeue pointers */
  728. ring->deq_seg = ring->first_seg;
  729. ring->dequeue = ring->first_seg->trbs;
  730. ring->enq_seg = ring->deq_seg;
  731. ring->enqueue = ring->dequeue;
  732. ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
  733. /*
  734. * Ring is now zeroed, so the HW should look for change of ownership
  735. * when the cycle bit is set to 1.
  736. */
  737. ring->cycle_state = 1;
  738. /*
  739. * Reset the hardware dequeue pointer.
  740. * Yes, this will need to be re-written after resume, but we're paranoid
  741. * and want to make sure the hardware doesn't access bogus memory
  742. * because, say, the BIOS or an SMI started the host without changing
  743. * the command ring pointers.
  744. */
  745. xhci_set_cmd_ring_deq(xhci);
  746. }
  747. /*
  748. * Stop HC (not bus-specific)
  749. *
  750. * This is called when the machine transition into S3/S4 mode.
  751. *
  752. */
  753. int xhci_suspend(struct xhci_hcd *xhci)
  754. {
  755. int rc = 0;
  756. struct usb_hcd *hcd = xhci_to_hcd(xhci);
  757. u32 command;
  758. if (hcd->state != HC_STATE_SUSPENDED ||
  759. xhci->shared_hcd->state != HC_STATE_SUSPENDED)
  760. return -EINVAL;
  761. /* Don't poll the roothubs on bus suspend. */
  762. xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
  763. clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
  764. del_timer_sync(&hcd->rh_timer);
  765. spin_lock_irq(&xhci->lock);
  766. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  767. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
  768. /* step 1: stop endpoint */
  769. /* skipped assuming that port suspend has done */
  770. /* step 2: clear Run/Stop bit */
  771. command = xhci_readl(xhci, &xhci->op_regs->command);
  772. command &= ~CMD_RUN;
  773. xhci_writel(xhci, command, &xhci->op_regs->command);
  774. if (xhci_handshake(xhci, &xhci->op_regs->status,
  775. STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC)) {
  776. xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
  777. spin_unlock_irq(&xhci->lock);
  778. return -ETIMEDOUT;
  779. }
  780. xhci_clear_command_ring(xhci);
  781. /* step 3: save registers */
  782. xhci_save_registers(xhci);
  783. /* step 4: set CSS flag */
  784. command = xhci_readl(xhci, &xhci->op_regs->command);
  785. command |= CMD_CSS;
  786. xhci_writel(xhci, command, &xhci->op_regs->command);
  787. if (xhci_handshake(xhci, &xhci->op_regs->status,
  788. STS_SAVE, 0, 10 * 1000)) {
  789. xhci_warn(xhci, "WARN: xHC save state timeout\n");
  790. spin_unlock_irq(&xhci->lock);
  791. return -ETIMEDOUT;
  792. }
  793. spin_unlock_irq(&xhci->lock);
  794. /*
  795. * Deleting Compliance Mode Recovery Timer because the xHCI Host
  796. * is about to be suspended.
  797. */
  798. if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
  799. (!(xhci_all_ports_seen_u0(xhci)))) {
  800. del_timer_sync(&xhci->comp_mode_recovery_timer);
  801. xhci_dbg(xhci, "%s: compliance mode recovery timer deleted\n",
  802. __func__);
  803. }
  804. /* step 5: remove core well power */
  805. /* synchronize irq when using MSI-X */
  806. xhci_msix_sync_irqs(xhci);
  807. return rc;
  808. }
  809. /*
  810. * start xHC (not bus-specific)
  811. *
  812. * This is called when the machine transition from S3/S4 mode.
  813. *
  814. */
  815. int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
  816. {
  817. u32 command, temp = 0;
  818. struct usb_hcd *hcd = xhci_to_hcd(xhci);
  819. struct usb_hcd *secondary_hcd;
  820. int retval = 0;
  821. bool comp_timer_running = false;
  822. /* Wait a bit if either of the roothubs need to settle from the
  823. * transition into bus suspend.
  824. */
  825. if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
  826. time_before(jiffies,
  827. xhci->bus_state[1].next_statechange))
  828. msleep(100);
  829. set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  830. set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
  831. spin_lock_irq(&xhci->lock);
  832. if (xhci->quirks & XHCI_RESET_ON_RESUME)
  833. hibernated = true;
  834. if (!hibernated) {
  835. /* step 1: restore register */
  836. xhci_restore_registers(xhci);
  837. /* step 2: initialize command ring buffer */
  838. xhci_set_cmd_ring_deq(xhci);
  839. /* step 3: restore state and start state*/
  840. /* step 3: set CRS flag */
  841. command = xhci_readl(xhci, &xhci->op_regs->command);
  842. command |= CMD_CRS;
  843. xhci_writel(xhci, command, &xhci->op_regs->command);
  844. if (xhci_handshake(xhci, &xhci->op_regs->status,
  845. STS_RESTORE, 0, 10 * 1000)) {
  846. xhci_warn(xhci, "WARN: xHC restore state timeout\n");
  847. spin_unlock_irq(&xhci->lock);
  848. return -ETIMEDOUT;
  849. }
  850. temp = xhci_readl(xhci, &xhci->op_regs->status);
  851. }
  852. /* If restore operation fails, re-initialize the HC during resume */
  853. if ((temp & STS_SRE) || hibernated) {
  854. if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
  855. !(xhci_all_ports_seen_u0(xhci))) {
  856. del_timer_sync(&xhci->comp_mode_recovery_timer);
  857. xhci_dbg(xhci, "Compliance Mode Recovery Timer deleted!\n");
  858. }
  859. /* Let the USB core know _both_ roothubs lost power. */
  860. usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
  861. usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
  862. xhci_dbg(xhci, "Stop HCD\n");
  863. xhci_halt(xhci);
  864. xhci_reset(xhci);
  865. spin_unlock_irq(&xhci->lock);
  866. xhci_cleanup_msix(xhci);
  867. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  868. /* Tell the event ring poll function not to reschedule */
  869. xhci->zombie = 1;
  870. del_timer_sync(&xhci->event_ring_timer);
  871. #endif
  872. xhci_dbg(xhci, "// Disabling event ring interrupts\n");
  873. temp = xhci_readl(xhci, &xhci->op_regs->status);
  874. xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
  875. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  876. xhci_writel(xhci, ER_IRQ_DISABLE(temp),
  877. &xhci->ir_set->irq_pending);
  878. xhci_print_ir_set(xhci, 0);
  879. xhci_dbg(xhci, "cleaning up memory\n");
  880. xhci_mem_cleanup(xhci);
  881. xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
  882. xhci_readl(xhci, &xhci->op_regs->status));
  883. /* USB core calls the PCI reinit and start functions twice:
  884. * first with the primary HCD, and then with the secondary HCD.
  885. * If we don't do the same, the host will never be started.
  886. */
  887. if (!usb_hcd_is_primary_hcd(hcd))
  888. secondary_hcd = hcd;
  889. else
  890. secondary_hcd = xhci->shared_hcd;
  891. xhci_dbg(xhci, "Initialize the xhci_hcd\n");
  892. retval = xhci_init(hcd->primary_hcd);
  893. if (retval)
  894. return retval;
  895. comp_timer_running = true;
  896. xhci_dbg(xhci, "Start the primary HCD\n");
  897. retval = xhci_run(hcd->primary_hcd);
  898. if (!retval) {
  899. xhci_dbg(xhci, "Start the secondary HCD\n");
  900. retval = xhci_run(secondary_hcd);
  901. }
  902. hcd->state = HC_STATE_SUSPENDED;
  903. xhci->shared_hcd->state = HC_STATE_SUSPENDED;
  904. goto done;
  905. }
  906. /* step 4: set Run/Stop bit */
  907. command = xhci_readl(xhci, &xhci->op_regs->command);
  908. command |= CMD_RUN;
  909. xhci_writel(xhci, command, &xhci->op_regs->command);
  910. xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT,
  911. 0, 250 * 1000);
  912. /* step 5: walk topology and initialize portsc,
  913. * portpmsc and portli
  914. */
  915. /* this is done in bus_resume */
  916. /* step 6: restart each of the previously
  917. * Running endpoints by ringing their doorbells
  918. */
  919. spin_unlock_irq(&xhci->lock);
  920. done:
  921. if (retval == 0) {
  922. usb_hcd_resume_root_hub(hcd);
  923. usb_hcd_resume_root_hub(xhci->shared_hcd);
  924. }
  925. /*
  926. * If system is subject to the Quirk, Compliance Mode Timer needs to
  927. * be re-initialized Always after a system resume. Ports are subject
  928. * to suffer the Compliance Mode issue again. It doesn't matter if
  929. * ports have entered previously to U0 before system's suspension.
  930. */
  931. if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
  932. compliance_mode_recovery_timer_init(xhci);
  933. /* Re-enable port polling. */
  934. xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
  935. set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
  936. usb_hcd_poll_rh_status(hcd);
  937. return retval;
  938. }
  939. #endif /* CONFIG_PM */
  940. /*-------------------------------------------------------------------------*/
  941. /**
  942. * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
  943. * HCDs. Find the index for an endpoint given its descriptor. Use the return
  944. * value to right shift 1 for the bitmask.
  945. *
  946. * Index = (epnum * 2) + direction - 1,
  947. * where direction = 0 for OUT, 1 for IN.
  948. * For control endpoints, the IN index is used (OUT index is unused), so
  949. * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
  950. */
  951. unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
  952. {
  953. unsigned int index;
  954. if (usb_endpoint_xfer_control(desc))
  955. index = (unsigned int) (usb_endpoint_num(desc)*2);
  956. else
  957. index = (unsigned int) (usb_endpoint_num(desc)*2) +
  958. (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
  959. return index;
  960. }
  961. /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
  962. * address from the XHCI endpoint index.
  963. */
  964. unsigned int xhci_get_endpoint_address(unsigned int ep_index)
  965. {
  966. unsigned int number = DIV_ROUND_UP(ep_index, 2);
  967. unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
  968. return direction | number;
  969. }
  970. /* Find the flag for this endpoint (for use in the control context). Use the
  971. * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
  972. * bit 1, etc.
  973. */
  974. unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
  975. {
  976. return 1 << (xhci_get_endpoint_index(desc) + 1);
  977. }
  978. /* Find the flag for this endpoint (for use in the control context). Use the
  979. * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
  980. * bit 1, etc.
  981. */
  982. unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
  983. {
  984. return 1 << (ep_index + 1);
  985. }
  986. /* Compute the last valid endpoint context index. Basically, this is the
  987. * endpoint index plus one. For slot contexts with more than valid endpoint,
  988. * we find the most significant bit set in the added contexts flags.
  989. * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
  990. * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
  991. */
  992. unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
  993. {
  994. return fls(added_ctxs) - 1;
  995. }
  996. /* Returns 1 if the arguments are OK;
  997. * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
  998. */
  999. static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
  1000. struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
  1001. const char *func) {
  1002. struct xhci_hcd *xhci;
  1003. struct xhci_virt_device *virt_dev;
  1004. if (!hcd || (check_ep && !ep) || !udev) {
  1005. printk(KERN_DEBUG "xHCI %s called with invalid args\n",
  1006. func);
  1007. return -EINVAL;
  1008. }
  1009. if (!udev->parent) {
  1010. printk(KERN_DEBUG "xHCI %s called for root hub\n",
  1011. func);
  1012. return 0;
  1013. }
  1014. xhci = hcd_to_xhci(hcd);
  1015. if (xhci->xhc_state & XHCI_STATE_HALTED)
  1016. return -ENODEV;
  1017. if (check_virt_dev) {
  1018. if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
  1019. printk(KERN_DEBUG "xHCI %s called with unaddressed "
  1020. "device\n", func);
  1021. return -EINVAL;
  1022. }
  1023. virt_dev = xhci->devs[udev->slot_id];
  1024. if (virt_dev->udev != udev) {
  1025. printk(KERN_DEBUG "xHCI %s called with udev and "
  1026. "virt_dev does not match\n", func);
  1027. return -EINVAL;
  1028. }
  1029. }
  1030. return 1;
  1031. }
  1032. static int xhci_configure_endpoint(struct xhci_hcd *xhci,
  1033. struct usb_device *udev, struct xhci_command *command,
  1034. bool ctx_change, bool must_succeed);
  1035. /*
  1036. * Full speed devices may have a max packet size greater than 8 bytes, but the
  1037. * USB core doesn't know that until it reads the first 8 bytes of the
  1038. * descriptor. If the usb_device's max packet size changes after that point,
  1039. * we need to issue an evaluate context command and wait on it.
  1040. */
  1041. static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
  1042. unsigned int ep_index, struct urb *urb)
  1043. {
  1044. struct xhci_container_ctx *in_ctx;
  1045. struct xhci_container_ctx *out_ctx;
  1046. struct xhci_input_control_ctx *ctrl_ctx;
  1047. struct xhci_ep_ctx *ep_ctx;
  1048. int max_packet_size;
  1049. int hw_max_packet_size;
  1050. int ret = 0;
  1051. out_ctx = xhci->devs[slot_id]->out_ctx;
  1052. ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  1053. hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
  1054. max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
  1055. if (hw_max_packet_size != max_packet_size) {
  1056. xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
  1057. xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
  1058. max_packet_size);
  1059. xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
  1060. hw_max_packet_size);
  1061. xhci_dbg(xhci, "Issuing evaluate context command.\n");
  1062. /* Set up the input context flags for the command */
  1063. /* FIXME: This won't work if a non-default control endpoint
  1064. * changes max packet sizes.
  1065. */
  1066. in_ctx = xhci->devs[slot_id]->in_ctx;
  1067. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  1068. if (!ctrl_ctx) {
  1069. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  1070. __func__);
  1071. return -ENOMEM;
  1072. }
  1073. /* Set up the modified control endpoint 0 */
  1074. xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
  1075. xhci->devs[slot_id]->out_ctx, ep_index);
  1076. ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
  1077. ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
  1078. ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
  1079. ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
  1080. ctrl_ctx->drop_flags = 0;
  1081. xhci_dbg(xhci, "Slot %d input context\n", slot_id);
  1082. xhci_dbg_ctx(xhci, in_ctx, ep_index);
  1083. xhci_dbg(xhci, "Slot %d output context\n", slot_id);
  1084. xhci_dbg_ctx(xhci, out_ctx, ep_index);
  1085. ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
  1086. true, false);
  1087. /* Clean up the input context for later use by bandwidth
  1088. * functions.
  1089. */
  1090. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
  1091. }
  1092. return ret;
  1093. }
  1094. /*
  1095. * non-error returns are a promise to giveback() the urb later
  1096. * we drop ownership so next owner (or urb unlink) can get it
  1097. */
  1098. int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
  1099. {
  1100. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1101. struct xhci_td *buffer;
  1102. unsigned long flags;
  1103. int ret = 0;
  1104. unsigned int slot_id, ep_index;
  1105. struct urb_priv *urb_priv;
  1106. int size, i;
  1107. if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
  1108. true, true, __func__) <= 0)
  1109. return -EINVAL;
  1110. slot_id = urb->dev->slot_id;
  1111. ep_index = xhci_get_endpoint_index(&urb->ep->desc);
  1112. if (!HCD_HW_ACCESSIBLE(hcd)) {
  1113. if (!in_interrupt())
  1114. xhci_dbg(xhci, "urb submitted during PCI suspend\n");
  1115. ret = -ESHUTDOWN;
  1116. goto exit;
  1117. }
  1118. if (usb_endpoint_xfer_isoc(&urb->ep->desc))
  1119. size = urb->number_of_packets;
  1120. else
  1121. size = 1;
  1122. urb_priv = kzalloc(sizeof(struct urb_priv) +
  1123. size * sizeof(struct xhci_td *), mem_flags);
  1124. if (!urb_priv)
  1125. return -ENOMEM;
  1126. buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
  1127. if (!buffer) {
  1128. kfree(urb_priv);
  1129. return -ENOMEM;
  1130. }
  1131. for (i = 0; i < size; i++) {
  1132. urb_priv->td[i] = buffer;
  1133. buffer++;
  1134. }
  1135. urb_priv->length = size;
  1136. urb_priv->td_cnt = 0;
  1137. urb->hcpriv = urb_priv;
  1138. if (usb_endpoint_xfer_control(&urb->ep->desc)) {
  1139. /* Check to see if the max packet size for the default control
  1140. * endpoint changed during FS device enumeration
  1141. */
  1142. if (urb->dev->speed == USB_SPEED_FULL) {
  1143. ret = xhci_check_maxpacket(xhci, slot_id,
  1144. ep_index, urb);
  1145. if (ret < 0) {
  1146. xhci_urb_free_priv(xhci, urb_priv);
  1147. urb->hcpriv = NULL;
  1148. return ret;
  1149. }
  1150. }
  1151. /* We have a spinlock and interrupts disabled, so we must pass
  1152. * atomic context to this function, which may allocate memory.
  1153. */
  1154. spin_lock_irqsave(&xhci->lock, flags);
  1155. if (xhci->xhc_state & XHCI_STATE_DYING)
  1156. goto dying;
  1157. ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
  1158. slot_id, ep_index);
  1159. if (ret)
  1160. goto free_priv;
  1161. spin_unlock_irqrestore(&xhci->lock, flags);
  1162. } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
  1163. spin_lock_irqsave(&xhci->lock, flags);
  1164. if (xhci->xhc_state & XHCI_STATE_DYING)
  1165. goto dying;
  1166. if (xhci->devs[slot_id]->eps[ep_index].ep_state &
  1167. EP_GETTING_STREAMS) {
  1168. xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
  1169. "is transitioning to using streams.\n");
  1170. ret = -EINVAL;
  1171. } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
  1172. EP_GETTING_NO_STREAMS) {
  1173. xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
  1174. "is transitioning to "
  1175. "not having streams.\n");
  1176. ret = -EINVAL;
  1177. } else {
  1178. ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
  1179. slot_id, ep_index);
  1180. }
  1181. if (ret)
  1182. goto free_priv;
  1183. spin_unlock_irqrestore(&xhci->lock, flags);
  1184. } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
  1185. spin_lock_irqsave(&xhci->lock, flags);
  1186. if (xhci->xhc_state & XHCI_STATE_DYING)
  1187. goto dying;
  1188. ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
  1189. slot_id, ep_index);
  1190. if (ret)
  1191. goto free_priv;
  1192. spin_unlock_irqrestore(&xhci->lock, flags);
  1193. } else {
  1194. spin_lock_irqsave(&xhci->lock, flags);
  1195. if (xhci->xhc_state & XHCI_STATE_DYING)
  1196. goto dying;
  1197. ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
  1198. slot_id, ep_index);
  1199. if (ret)
  1200. goto free_priv;
  1201. spin_unlock_irqrestore(&xhci->lock, flags);
  1202. }
  1203. exit:
  1204. return ret;
  1205. dying:
  1206. xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
  1207. "non-responsive xHCI host.\n",
  1208. urb->ep->desc.bEndpointAddress, urb);
  1209. ret = -ESHUTDOWN;
  1210. free_priv:
  1211. xhci_urb_free_priv(xhci, urb_priv);
  1212. urb->hcpriv = NULL;
  1213. spin_unlock_irqrestore(&xhci->lock, flags);
  1214. return ret;
  1215. }
  1216. /* Get the right ring for the given URB.
  1217. * If the endpoint supports streams, boundary check the URB's stream ID.
  1218. * If the endpoint doesn't support streams, return the singular endpoint ring.
  1219. */
  1220. static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
  1221. struct urb *urb)
  1222. {
  1223. unsigned int slot_id;
  1224. unsigned int ep_index;
  1225. unsigned int stream_id;
  1226. struct xhci_virt_ep *ep;
  1227. slot_id = urb->dev->slot_id;
  1228. ep_index = xhci_get_endpoint_index(&urb->ep->desc);
  1229. stream_id = urb->stream_id;
  1230. ep = &xhci->devs[slot_id]->eps[ep_index];
  1231. /* Common case: no streams */
  1232. if (!(ep->ep_state & EP_HAS_STREAMS))
  1233. return ep->ring;
  1234. if (stream_id == 0) {
  1235. xhci_warn(xhci,
  1236. "WARN: Slot ID %u, ep index %u has streams, "
  1237. "but URB has no stream ID.\n",
  1238. slot_id, ep_index);
  1239. return NULL;
  1240. }
  1241. if (stream_id < ep->stream_info->num_streams)
  1242. return ep->stream_info->stream_rings[stream_id];
  1243. xhci_warn(xhci,
  1244. "WARN: Slot ID %u, ep index %u has "
  1245. "stream IDs 1 to %u allocated, "
  1246. "but stream ID %u is requested.\n",
  1247. slot_id, ep_index,
  1248. ep->stream_info->num_streams - 1,
  1249. stream_id);
  1250. return NULL;
  1251. }
  1252. /*
  1253. * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
  1254. * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
  1255. * should pick up where it left off in the TD, unless a Set Transfer Ring
  1256. * Dequeue Pointer is issued.
  1257. *
  1258. * The TRBs that make up the buffers for the canceled URB will be "removed" from
  1259. * the ring. Since the ring is a contiguous structure, they can't be physically
  1260. * removed. Instead, there are two options:
  1261. *
  1262. * 1) If the HC is in the middle of processing the URB to be canceled, we
  1263. * simply move the ring's dequeue pointer past those TRBs using the Set
  1264. * Transfer Ring Dequeue Pointer command. This will be the common case,
  1265. * when drivers timeout on the last submitted URB and attempt to cancel.
  1266. *
  1267. * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
  1268. * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
  1269. * HC will need to invalidate the any TRBs it has cached after the stop
  1270. * endpoint command, as noted in the xHCI 0.95 errata.
  1271. *
  1272. * 3) The TD may have completed by the time the Stop Endpoint Command
  1273. * completes, so software needs to handle that case too.
  1274. *
  1275. * This function should protect against the TD enqueueing code ringing the
  1276. * doorbell while this code is waiting for a Stop Endpoint command to complete.
  1277. * It also needs to account for multiple cancellations on happening at the same
  1278. * time for the same endpoint.
  1279. *
  1280. * Note that this function can be called in any context, or so says
  1281. * usb_hcd_unlink_urb()
  1282. */
  1283. int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  1284. {
  1285. unsigned long flags;
  1286. int ret, i;
  1287. u32 temp;
  1288. struct xhci_hcd *xhci;
  1289. struct urb_priv *urb_priv;
  1290. struct xhci_td *td;
  1291. unsigned int ep_index;
  1292. struct xhci_ring *ep_ring;
  1293. struct xhci_virt_ep *ep;
  1294. xhci = hcd_to_xhci(hcd);
  1295. spin_lock_irqsave(&xhci->lock, flags);
  1296. /* Make sure the URB hasn't completed or been unlinked already */
  1297. ret = usb_hcd_check_unlink_urb(hcd, urb, status);
  1298. if (ret || !urb->hcpriv)
  1299. goto done;
  1300. temp = xhci_readl(xhci, &xhci->op_regs->status);
  1301. if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
  1302. xhci_dbg(xhci, "HW died, freeing TD.\n");
  1303. urb_priv = urb->hcpriv;
  1304. for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
  1305. td = urb_priv->td[i];
  1306. if (!list_empty(&td->td_list))
  1307. list_del_init(&td->td_list);
  1308. if (!list_empty(&td->cancelled_td_list))
  1309. list_del_init(&td->cancelled_td_list);
  1310. }
  1311. usb_hcd_unlink_urb_from_ep(hcd, urb);
  1312. spin_unlock_irqrestore(&xhci->lock, flags);
  1313. usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
  1314. xhci_urb_free_priv(xhci, urb_priv);
  1315. return ret;
  1316. }
  1317. if ((xhci->xhc_state & XHCI_STATE_DYING) ||
  1318. (xhci->xhc_state & XHCI_STATE_HALTED)) {
  1319. xhci_dbg(xhci, "Ep 0x%x: URB %p to be canceled on "
  1320. "non-responsive xHCI host.\n",
  1321. urb->ep->desc.bEndpointAddress, urb);
  1322. /* Let the stop endpoint command watchdog timer (which set this
  1323. * state) finish cleaning up the endpoint TD lists. We must
  1324. * have caught it in the middle of dropping a lock and giving
  1325. * back an URB.
  1326. */
  1327. goto done;
  1328. }
  1329. ep_index = xhci_get_endpoint_index(&urb->ep->desc);
  1330. ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
  1331. ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
  1332. if (!ep_ring) {
  1333. ret = -EINVAL;
  1334. goto done;
  1335. }
  1336. urb_priv = urb->hcpriv;
  1337. i = urb_priv->td_cnt;
  1338. if (i < urb_priv->length)
  1339. xhci_dbg(xhci, "Cancel URB %p, dev %s, ep 0x%x, "
  1340. "starting at offset 0x%llx\n",
  1341. urb, urb->dev->devpath,
  1342. urb->ep->desc.bEndpointAddress,
  1343. (unsigned long long) xhci_trb_virt_to_dma(
  1344. urb_priv->td[i]->start_seg,
  1345. urb_priv->td[i]->first_trb));
  1346. for (; i < urb_priv->length; i++) {
  1347. td = urb_priv->td[i];
  1348. list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
  1349. }
  1350. /* Queue a stop endpoint command, but only if this is
  1351. * the first cancellation to be handled.
  1352. */
  1353. if (!(ep->ep_state & EP_HALT_PENDING)) {
  1354. ep->ep_state |= EP_HALT_PENDING;
  1355. ep->stop_cmds_pending++;
  1356. ep->stop_cmd_timer.expires = jiffies +
  1357. XHCI_STOP_EP_CMD_TIMEOUT * HZ;
  1358. add_timer(&ep->stop_cmd_timer);
  1359. xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0);
  1360. xhci_ring_cmd_db(xhci);
  1361. }
  1362. done:
  1363. spin_unlock_irqrestore(&xhci->lock, flags);
  1364. return ret;
  1365. }
  1366. /* Drop an endpoint from a new bandwidth configuration for this device.
  1367. * Only one call to this function is allowed per endpoint before
  1368. * check_bandwidth() or reset_bandwidth() must be called.
  1369. * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
  1370. * add the endpoint to the schedule with possibly new parameters denoted by a
  1371. * different endpoint descriptor in usb_host_endpoint.
  1372. * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
  1373. * not allowed.
  1374. *
  1375. * The USB core will not allow URBs to be queued to an endpoint that is being
  1376. * disabled, so there's no need for mutual exclusion to protect
  1377. * the xhci->devs[slot_id] structure.
  1378. */
  1379. int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  1380. struct usb_host_endpoint *ep)
  1381. {
  1382. struct xhci_hcd *xhci;
  1383. struct xhci_container_ctx *in_ctx, *out_ctx;
  1384. struct xhci_input_control_ctx *ctrl_ctx;
  1385. struct xhci_slot_ctx *slot_ctx;
  1386. unsigned int last_ctx;
  1387. unsigned int ep_index;
  1388. struct xhci_ep_ctx *ep_ctx;
  1389. u32 drop_flag;
  1390. u32 new_add_flags, new_drop_flags, new_slot_info;
  1391. int ret;
  1392. ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
  1393. if (ret <= 0)
  1394. return ret;
  1395. xhci = hcd_to_xhci(hcd);
  1396. if (xhci->xhc_state & XHCI_STATE_DYING)
  1397. return -ENODEV;
  1398. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  1399. drop_flag = xhci_get_endpoint_flag(&ep->desc);
  1400. if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
  1401. xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
  1402. __func__, drop_flag);
  1403. return 0;
  1404. }
  1405. in_ctx = xhci->devs[udev->slot_id]->in_ctx;
  1406. out_ctx = xhci->devs[udev->slot_id]->out_ctx;
  1407. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  1408. if (!ctrl_ctx) {
  1409. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  1410. __func__);
  1411. return 0;
  1412. }
  1413. ep_index = xhci_get_endpoint_index(&ep->desc);
  1414. ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  1415. /* If the HC already knows the endpoint is disabled,
  1416. * or the HCD has noted it is disabled, ignore this request
  1417. */
  1418. if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
  1419. cpu_to_le32(EP_STATE_DISABLED)) ||
  1420. le32_to_cpu(ctrl_ctx->drop_flags) &
  1421. xhci_get_endpoint_flag(&ep->desc)) {
  1422. xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
  1423. __func__, ep);
  1424. return 0;
  1425. }
  1426. ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
  1427. new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
  1428. ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
  1429. new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
  1430. last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags));
  1431. slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
  1432. /* Update the last valid endpoint context, if we deleted the last one */
  1433. if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) >
  1434. LAST_CTX(last_ctx)) {
  1435. slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
  1436. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
  1437. }
  1438. new_slot_info = le32_to_cpu(slot_ctx->dev_info);
  1439. xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
  1440. xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
  1441. (unsigned int) ep->desc.bEndpointAddress,
  1442. udev->slot_id,
  1443. (unsigned int) new_drop_flags,
  1444. (unsigned int) new_add_flags,
  1445. (unsigned int) new_slot_info);
  1446. return 0;
  1447. }
  1448. /* Add an endpoint to a new possible bandwidth configuration for this device.
  1449. * Only one call to this function is allowed per endpoint before
  1450. * check_bandwidth() or reset_bandwidth() must be called.
  1451. * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
  1452. * add the endpoint to the schedule with possibly new parameters denoted by a
  1453. * different endpoint descriptor in usb_host_endpoint.
  1454. * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
  1455. * not allowed.
  1456. *
  1457. * The USB core will not allow URBs to be queued to an endpoint until the
  1458. * configuration or alt setting is installed in the device, so there's no need
  1459. * for mutual exclusion to protect the xhci->devs[slot_id] structure.
  1460. */
  1461. int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  1462. struct usb_host_endpoint *ep)
  1463. {
  1464. struct xhci_hcd *xhci;
  1465. struct xhci_container_ctx *in_ctx, *out_ctx;
  1466. unsigned int ep_index;
  1467. struct xhci_slot_ctx *slot_ctx;
  1468. struct xhci_input_control_ctx *ctrl_ctx;
  1469. u32 added_ctxs;
  1470. unsigned int last_ctx;
  1471. u32 new_add_flags, new_drop_flags, new_slot_info;
  1472. struct xhci_virt_device *virt_dev;
  1473. int ret = 0;
  1474. ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
  1475. if (ret <= 0) {
  1476. /* So we won't queue a reset ep command for a root hub */
  1477. ep->hcpriv = NULL;
  1478. return ret;
  1479. }
  1480. xhci = hcd_to_xhci(hcd);
  1481. if (xhci->xhc_state & XHCI_STATE_DYING)
  1482. return -ENODEV;
  1483. added_ctxs = xhci_get_endpoint_flag(&ep->desc);
  1484. last_ctx = xhci_last_valid_endpoint(added_ctxs);
  1485. if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
  1486. /* FIXME when we have to issue an evaluate endpoint command to
  1487. * deal with ep0 max packet size changing once we get the
  1488. * descriptors
  1489. */
  1490. xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
  1491. __func__, added_ctxs);
  1492. return 0;
  1493. }
  1494. virt_dev = xhci->devs[udev->slot_id];
  1495. in_ctx = virt_dev->in_ctx;
  1496. out_ctx = virt_dev->out_ctx;
  1497. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  1498. if (!ctrl_ctx) {
  1499. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  1500. __func__);
  1501. return 0;
  1502. }
  1503. ep_index = xhci_get_endpoint_index(&ep->desc);
  1504. /* If this endpoint is already in use, and the upper layers are trying
  1505. * to add it again without dropping it, reject the addition.
  1506. */
  1507. if (virt_dev->eps[ep_index].ring &&
  1508. !(le32_to_cpu(ctrl_ctx->drop_flags) &
  1509. xhci_get_endpoint_flag(&ep->desc))) {
  1510. xhci_warn(xhci, "Trying to add endpoint 0x%x "
  1511. "without dropping it.\n",
  1512. (unsigned int) ep->desc.bEndpointAddress);
  1513. return -EINVAL;
  1514. }
  1515. /* If the HCD has already noted the endpoint is enabled,
  1516. * ignore this request.
  1517. */
  1518. if (le32_to_cpu(ctrl_ctx->add_flags) &
  1519. xhci_get_endpoint_flag(&ep->desc)) {
  1520. xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
  1521. __func__, ep);
  1522. return 0;
  1523. }
  1524. /*
  1525. * Configuration and alternate setting changes must be done in
  1526. * process context, not interrupt context (or so documenation
  1527. * for usb_set_interface() and usb_set_configuration() claim).
  1528. */
  1529. if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
  1530. dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
  1531. __func__, ep->desc.bEndpointAddress);
  1532. return -ENOMEM;
  1533. }
  1534. ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
  1535. new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
  1536. /* If xhci_endpoint_disable() was called for this endpoint, but the
  1537. * xHC hasn't been notified yet through the check_bandwidth() call,
  1538. * this re-adds a new state for the endpoint from the new endpoint
  1539. * descriptors. We must drop and re-add this endpoint, so we leave the
  1540. * drop flags alone.
  1541. */
  1542. new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
  1543. slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
  1544. /* Update the last valid endpoint context, if we just added one past */
  1545. if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) <
  1546. LAST_CTX(last_ctx)) {
  1547. slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
  1548. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
  1549. }
  1550. new_slot_info = le32_to_cpu(slot_ctx->dev_info);
  1551. /* Store the usb_device pointer for later use */
  1552. ep->hcpriv = udev;
  1553. xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
  1554. (unsigned int) ep->desc.bEndpointAddress,
  1555. udev->slot_id,
  1556. (unsigned int) new_drop_flags,
  1557. (unsigned int) new_add_flags,
  1558. (unsigned int) new_slot_info);
  1559. return 0;
  1560. }
  1561. static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
  1562. {
  1563. struct xhci_input_control_ctx *ctrl_ctx;
  1564. struct xhci_ep_ctx *ep_ctx;
  1565. struct xhci_slot_ctx *slot_ctx;
  1566. int i;
  1567. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  1568. if (!ctrl_ctx) {
  1569. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  1570. __func__);
  1571. return;
  1572. }
  1573. /* When a device's add flag and drop flag are zero, any subsequent
  1574. * configure endpoint command will leave that endpoint's state
  1575. * untouched. Make sure we don't leave any old state in the input
  1576. * endpoint contexts.
  1577. */
  1578. ctrl_ctx->drop_flags = 0;
  1579. ctrl_ctx->add_flags = 0;
  1580. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
  1581. slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
  1582. /* Endpoint 0 is always valid */
  1583. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
  1584. for (i = 1; i < 31; ++i) {
  1585. ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
  1586. ep_ctx->ep_info = 0;
  1587. ep_ctx->ep_info2 = 0;
  1588. ep_ctx->deq = 0;
  1589. ep_ctx->tx_info = 0;
  1590. }
  1591. }
  1592. static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
  1593. struct usb_device *udev, u32 *cmd_status)
  1594. {
  1595. int ret;
  1596. switch (*cmd_status) {
  1597. case COMP_ENOMEM:
  1598. dev_warn(&udev->dev, "Not enough host controller resources "
  1599. "for new device state.\n");
  1600. ret = -ENOMEM;
  1601. /* FIXME: can we allocate more resources for the HC? */
  1602. break;
  1603. case COMP_BW_ERR:
  1604. case COMP_2ND_BW_ERR:
  1605. dev_warn(&udev->dev, "Not enough bandwidth "
  1606. "for new device state.\n");
  1607. ret = -ENOSPC;
  1608. /* FIXME: can we go back to the old state? */
  1609. break;
  1610. case COMP_TRB_ERR:
  1611. /* the HCD set up something wrong */
  1612. dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
  1613. "add flag = 1, "
  1614. "and endpoint is not disabled.\n");
  1615. ret = -EINVAL;
  1616. break;
  1617. case COMP_DEV_ERR:
  1618. dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint "
  1619. "configure command.\n");
  1620. ret = -ENODEV;
  1621. break;
  1622. case COMP_SUCCESS:
  1623. dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
  1624. ret = 0;
  1625. break;
  1626. default:
  1627. xhci_err(xhci, "ERROR: unexpected command completion "
  1628. "code 0x%x.\n", *cmd_status);
  1629. ret = -EINVAL;
  1630. break;
  1631. }
  1632. return ret;
  1633. }
  1634. static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
  1635. struct usb_device *udev, u32 *cmd_status)
  1636. {
  1637. int ret;
  1638. struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
  1639. switch (*cmd_status) {
  1640. case COMP_EINVAL:
  1641. dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
  1642. "context command.\n");
  1643. ret = -EINVAL;
  1644. break;
  1645. case COMP_EBADSLT:
  1646. dev_warn(&udev->dev, "WARN: slot not enabled for"
  1647. "evaluate context command.\n");
  1648. ret = -EINVAL;
  1649. break;
  1650. case COMP_CTX_STATE:
  1651. dev_warn(&udev->dev, "WARN: invalid context state for "
  1652. "evaluate context command.\n");
  1653. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
  1654. ret = -EINVAL;
  1655. break;
  1656. case COMP_DEV_ERR:
  1657. dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate "
  1658. "context command.\n");
  1659. ret = -ENODEV;
  1660. break;
  1661. case COMP_MEL_ERR:
  1662. /* Max Exit Latency too large error */
  1663. dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
  1664. ret = -EINVAL;
  1665. break;
  1666. case COMP_SUCCESS:
  1667. dev_dbg(&udev->dev, "Successful evaluate context command\n");
  1668. ret = 0;
  1669. break;
  1670. default:
  1671. xhci_err(xhci, "ERROR: unexpected command completion "
  1672. "code 0x%x.\n", *cmd_status);
  1673. ret = -EINVAL;
  1674. break;
  1675. }
  1676. return ret;
  1677. }
  1678. static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
  1679. struct xhci_input_control_ctx *ctrl_ctx)
  1680. {
  1681. u32 valid_add_flags;
  1682. u32 valid_drop_flags;
  1683. /* Ignore the slot flag (bit 0), and the default control endpoint flag
  1684. * (bit 1). The default control endpoint is added during the Address
  1685. * Device command and is never removed until the slot is disabled.
  1686. */
  1687. valid_add_flags = ctrl_ctx->add_flags >> 2;
  1688. valid_drop_flags = ctrl_ctx->drop_flags >> 2;
  1689. /* Use hweight32 to count the number of ones in the add flags, or
  1690. * number of endpoints added. Don't count endpoints that are changed
  1691. * (both added and dropped).
  1692. */
  1693. return hweight32(valid_add_flags) -
  1694. hweight32(valid_add_flags & valid_drop_flags);
  1695. }
  1696. static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
  1697. struct xhci_input_control_ctx *ctrl_ctx)
  1698. {
  1699. u32 valid_add_flags;
  1700. u32 valid_drop_flags;
  1701. valid_add_flags = ctrl_ctx->add_flags >> 2;
  1702. valid_drop_flags = ctrl_ctx->drop_flags >> 2;
  1703. return hweight32(valid_drop_flags) -
  1704. hweight32(valid_add_flags & valid_drop_flags);
  1705. }
  1706. /*
  1707. * We need to reserve the new number of endpoints before the configure endpoint
  1708. * command completes. We can't subtract the dropped endpoints from the number
  1709. * of active endpoints until the command completes because we can oversubscribe
  1710. * the host in this case:
  1711. *
  1712. * - the first configure endpoint command drops more endpoints than it adds
  1713. * - a second configure endpoint command that adds more endpoints is queued
  1714. * - the first configure endpoint command fails, so the config is unchanged
  1715. * - the second command may succeed, even though there isn't enough resources
  1716. *
  1717. * Must be called with xhci->lock held.
  1718. */
  1719. static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
  1720. struct xhci_input_control_ctx *ctrl_ctx)
  1721. {
  1722. u32 added_eps;
  1723. added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
  1724. if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
  1725. xhci_dbg(xhci, "Not enough ep ctxs: "
  1726. "%u active, need to add %u, limit is %u.\n",
  1727. xhci->num_active_eps, added_eps,
  1728. xhci->limit_active_eps);
  1729. return -ENOMEM;
  1730. }
  1731. xhci->num_active_eps += added_eps;
  1732. xhci_dbg(xhci, "Adding %u ep ctxs, %u now active.\n", added_eps,
  1733. xhci->num_active_eps);
  1734. return 0;
  1735. }
  1736. /*
  1737. * The configure endpoint was failed by the xHC for some other reason, so we
  1738. * need to revert the resources that failed configuration would have used.
  1739. *
  1740. * Must be called with xhci->lock held.
  1741. */
  1742. static void xhci_free_host_resources(struct xhci_hcd *xhci,
  1743. struct xhci_input_control_ctx *ctrl_ctx)
  1744. {
  1745. u32 num_failed_eps;
  1746. num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
  1747. xhci->num_active_eps -= num_failed_eps;
  1748. xhci_dbg(xhci, "Removing %u failed ep ctxs, %u now active.\n",
  1749. num_failed_eps,
  1750. xhci->num_active_eps);
  1751. }
  1752. /*
  1753. * Now that the command has completed, clean up the active endpoint count by
  1754. * subtracting out the endpoints that were dropped (but not changed).
  1755. *
  1756. * Must be called with xhci->lock held.
  1757. */
  1758. static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
  1759. struct xhci_input_control_ctx *ctrl_ctx)
  1760. {
  1761. u32 num_dropped_eps;
  1762. num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
  1763. xhci->num_active_eps -= num_dropped_eps;
  1764. if (num_dropped_eps)
  1765. xhci_dbg(xhci, "Removing %u dropped ep ctxs, %u now active.\n",
  1766. num_dropped_eps,
  1767. xhci->num_active_eps);
  1768. }
  1769. static unsigned int xhci_get_block_size(struct usb_device *udev)
  1770. {
  1771. switch (udev->speed) {
  1772. case USB_SPEED_LOW:
  1773. case USB_SPEED_FULL:
  1774. return FS_BLOCK;
  1775. case USB_SPEED_HIGH:
  1776. return HS_BLOCK;
  1777. case USB_SPEED_SUPER:
  1778. return SS_BLOCK;
  1779. case USB_SPEED_UNKNOWN:
  1780. case USB_SPEED_WIRELESS:
  1781. default:
  1782. /* Should never happen */
  1783. return 1;
  1784. }
  1785. }
  1786. static unsigned int
  1787. xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
  1788. {
  1789. if (interval_bw->overhead[LS_OVERHEAD_TYPE])
  1790. return LS_OVERHEAD;
  1791. if (interval_bw->overhead[FS_OVERHEAD_TYPE])
  1792. return FS_OVERHEAD;
  1793. return HS_OVERHEAD;
  1794. }
  1795. /* If we are changing a LS/FS device under a HS hub,
  1796. * make sure (if we are activating a new TT) that the HS bus has enough
  1797. * bandwidth for this new TT.
  1798. */
  1799. static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
  1800. struct xhci_virt_device *virt_dev,
  1801. int old_active_eps)
  1802. {
  1803. struct xhci_interval_bw_table *bw_table;
  1804. struct xhci_tt_bw_info *tt_info;
  1805. /* Find the bandwidth table for the root port this TT is attached to. */
  1806. bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
  1807. tt_info = virt_dev->tt_info;
  1808. /* If this TT already had active endpoints, the bandwidth for this TT
  1809. * has already been added. Removing all periodic endpoints (and thus
  1810. * making the TT enactive) will only decrease the bandwidth used.
  1811. */
  1812. if (old_active_eps)
  1813. return 0;
  1814. if (old_active_eps == 0 && tt_info->active_eps != 0) {
  1815. if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
  1816. return -ENOMEM;
  1817. return 0;
  1818. }
  1819. /* Not sure why we would have no new active endpoints...
  1820. *
  1821. * Maybe because of an Evaluate Context change for a hub update or a
  1822. * control endpoint 0 max packet size change?
  1823. * FIXME: skip the bandwidth calculation in that case.
  1824. */
  1825. return 0;
  1826. }
  1827. static int xhci_check_ss_bw(struct xhci_hcd *xhci,
  1828. struct xhci_virt_device *virt_dev)
  1829. {
  1830. unsigned int bw_reserved;
  1831. bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
  1832. if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
  1833. return -ENOMEM;
  1834. bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
  1835. if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
  1836. return -ENOMEM;
  1837. return 0;
  1838. }
  1839. /*
  1840. * This algorithm is a very conservative estimate of the worst-case scheduling
  1841. * scenario for any one interval. The hardware dynamically schedules the
  1842. * packets, so we can't tell which microframe could be the limiting factor in
  1843. * the bandwidth scheduling. This only takes into account periodic endpoints.
  1844. *
  1845. * Obviously, we can't solve an NP complete problem to find the minimum worst
  1846. * case scenario. Instead, we come up with an estimate that is no less than
  1847. * the worst case bandwidth used for any one microframe, but may be an
  1848. * over-estimate.
  1849. *
  1850. * We walk the requirements for each endpoint by interval, starting with the
  1851. * smallest interval, and place packets in the schedule where there is only one
  1852. * possible way to schedule packets for that interval. In order to simplify
  1853. * this algorithm, we record the largest max packet size for each interval, and
  1854. * assume all packets will be that size.
  1855. *
  1856. * For interval 0, we obviously must schedule all packets for each interval.
  1857. * The bandwidth for interval 0 is just the amount of data to be transmitted
  1858. * (the sum of all max ESIT payload sizes, plus any overhead per packet times
  1859. * the number of packets).
  1860. *
  1861. * For interval 1, we have two possible microframes to schedule those packets
  1862. * in. For this algorithm, if we can schedule the same number of packets for
  1863. * each possible scheduling opportunity (each microframe), we will do so. The
  1864. * remaining number of packets will be saved to be transmitted in the gaps in
  1865. * the next interval's scheduling sequence.
  1866. *
  1867. * As we move those remaining packets to be scheduled with interval 2 packets,
  1868. * we have to double the number of remaining packets to transmit. This is
  1869. * because the intervals are actually powers of 2, and we would be transmitting
  1870. * the previous interval's packets twice in this interval. We also have to be
  1871. * sure that when we look at the largest max packet size for this interval, we
  1872. * also look at the largest max packet size for the remaining packets and take
  1873. * the greater of the two.
  1874. *
  1875. * The algorithm continues to evenly distribute packets in each scheduling
  1876. * opportunity, and push the remaining packets out, until we get to the last
  1877. * interval. Then those packets and their associated overhead are just added
  1878. * to the bandwidth used.
  1879. */
  1880. static int xhci_check_bw_table(struct xhci_hcd *xhci,
  1881. struct xhci_virt_device *virt_dev,
  1882. int old_active_eps)
  1883. {
  1884. unsigned int bw_reserved;
  1885. unsigned int max_bandwidth;
  1886. unsigned int bw_used;
  1887. unsigned int block_size;
  1888. struct xhci_interval_bw_table *bw_table;
  1889. unsigned int packet_size = 0;
  1890. unsigned int overhead = 0;
  1891. unsigned int packets_transmitted = 0;
  1892. unsigned int packets_remaining = 0;
  1893. unsigned int i;
  1894. if (virt_dev->udev->speed == USB_SPEED_SUPER)
  1895. return xhci_check_ss_bw(xhci, virt_dev);
  1896. if (virt_dev->udev->speed == USB_SPEED_HIGH) {
  1897. max_bandwidth = HS_BW_LIMIT;
  1898. /* Convert percent of bus BW reserved to blocks reserved */
  1899. bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
  1900. } else {
  1901. max_bandwidth = FS_BW_LIMIT;
  1902. bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
  1903. }
  1904. bw_table = virt_dev->bw_table;
  1905. /* We need to translate the max packet size and max ESIT payloads into
  1906. * the units the hardware uses.
  1907. */
  1908. block_size = xhci_get_block_size(virt_dev->udev);
  1909. /* If we are manipulating a LS/FS device under a HS hub, double check
  1910. * that the HS bus has enough bandwidth if we are activing a new TT.
  1911. */
  1912. if (virt_dev->tt_info) {
  1913. xhci_dbg(xhci, "Recalculating BW for rootport %u\n",
  1914. virt_dev->real_port);
  1915. if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
  1916. xhci_warn(xhci, "Not enough bandwidth on HS bus for "
  1917. "newly activated TT.\n");
  1918. return -ENOMEM;
  1919. }
  1920. xhci_dbg(xhci, "Recalculating BW for TT slot %u port %u\n",
  1921. virt_dev->tt_info->slot_id,
  1922. virt_dev->tt_info->ttport);
  1923. } else {
  1924. xhci_dbg(xhci, "Recalculating BW for rootport %u\n",
  1925. virt_dev->real_port);
  1926. }
  1927. /* Add in how much bandwidth will be used for interval zero, or the
  1928. * rounded max ESIT payload + number of packets * largest overhead.
  1929. */
  1930. bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
  1931. bw_table->interval_bw[0].num_packets *
  1932. xhci_get_largest_overhead(&bw_table->interval_bw[0]);
  1933. for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
  1934. unsigned int bw_added;
  1935. unsigned int largest_mps;
  1936. unsigned int interval_overhead;
  1937. /*
  1938. * How many packets could we transmit in this interval?
  1939. * If packets didn't fit in the previous interval, we will need
  1940. * to transmit that many packets twice within this interval.
  1941. */
  1942. packets_remaining = 2 * packets_remaining +
  1943. bw_table->interval_bw[i].num_packets;
  1944. /* Find the largest max packet size of this or the previous
  1945. * interval.
  1946. */
  1947. if (list_empty(&bw_table->interval_bw[i].endpoints))
  1948. largest_mps = 0;
  1949. else {
  1950. struct xhci_virt_ep *virt_ep;
  1951. struct list_head *ep_entry;
  1952. ep_entry = bw_table->interval_bw[i].endpoints.next;
  1953. virt_ep = list_entry(ep_entry,
  1954. struct xhci_virt_ep, bw_endpoint_list);
  1955. /* Convert to blocks, rounding up */
  1956. largest_mps = DIV_ROUND_UP(
  1957. virt_ep->bw_info.max_packet_size,
  1958. block_size);
  1959. }
  1960. if (largest_mps > packet_size)
  1961. packet_size = largest_mps;
  1962. /* Use the larger overhead of this or the previous interval. */
  1963. interval_overhead = xhci_get_largest_overhead(
  1964. &bw_table->interval_bw[i]);
  1965. if (interval_overhead > overhead)
  1966. overhead = interval_overhead;
  1967. /* How many packets can we evenly distribute across
  1968. * (1 << (i + 1)) possible scheduling opportunities?
  1969. */
  1970. packets_transmitted = packets_remaining >> (i + 1);
  1971. /* Add in the bandwidth used for those scheduled packets */
  1972. bw_added = packets_transmitted * (overhead + packet_size);
  1973. /* How many packets do we have remaining to transmit? */
  1974. packets_remaining = packets_remaining % (1 << (i + 1));
  1975. /* What largest max packet size should those packets have? */
  1976. /* If we've transmitted all packets, don't carry over the
  1977. * largest packet size.
  1978. */
  1979. if (packets_remaining == 0) {
  1980. packet_size = 0;
  1981. overhead = 0;
  1982. } else if (packets_transmitted > 0) {
  1983. /* Otherwise if we do have remaining packets, and we've
  1984. * scheduled some packets in this interval, take the
  1985. * largest max packet size from endpoints with this
  1986. * interval.
  1987. */
  1988. packet_size = largest_mps;
  1989. overhead = interval_overhead;
  1990. }
  1991. /* Otherwise carry over packet_size and overhead from the last
  1992. * time we had a remainder.
  1993. */
  1994. bw_used += bw_added;
  1995. if (bw_used > max_bandwidth) {
  1996. xhci_warn(xhci, "Not enough bandwidth. "
  1997. "Proposed: %u, Max: %u\n",
  1998. bw_used, max_bandwidth);
  1999. return -ENOMEM;
  2000. }
  2001. }
  2002. /*
  2003. * Ok, we know we have some packets left over after even-handedly
  2004. * scheduling interval 15. We don't know which microframes they will
  2005. * fit into, so we over-schedule and say they will be scheduled every
  2006. * microframe.
  2007. */
  2008. if (packets_remaining > 0)
  2009. bw_used += overhead + packet_size;
  2010. if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
  2011. unsigned int port_index = virt_dev->real_port - 1;
  2012. /* OK, we're manipulating a HS device attached to a
  2013. * root port bandwidth domain. Include the number of active TTs
  2014. * in the bandwidth used.
  2015. */
  2016. bw_used += TT_HS_OVERHEAD *
  2017. xhci->rh_bw[port_index].num_active_tts;
  2018. }
  2019. xhci_dbg(xhci, "Final bandwidth: %u, Limit: %u, Reserved: %u, "
  2020. "Available: %u " "percent\n",
  2021. bw_used, max_bandwidth, bw_reserved,
  2022. (max_bandwidth - bw_used - bw_reserved) * 100 /
  2023. max_bandwidth);
  2024. bw_used += bw_reserved;
  2025. if (bw_used > max_bandwidth) {
  2026. xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
  2027. bw_used, max_bandwidth);
  2028. return -ENOMEM;
  2029. }
  2030. bw_table->bw_used = bw_used;
  2031. return 0;
  2032. }
  2033. static bool xhci_is_async_ep(unsigned int ep_type)
  2034. {
  2035. return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
  2036. ep_type != ISOC_IN_EP &&
  2037. ep_type != INT_IN_EP);
  2038. }
  2039. static bool xhci_is_sync_in_ep(unsigned int ep_type)
  2040. {
  2041. return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
  2042. }
  2043. static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
  2044. {
  2045. unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
  2046. if (ep_bw->ep_interval == 0)
  2047. return SS_OVERHEAD_BURST +
  2048. (ep_bw->mult * ep_bw->num_packets *
  2049. (SS_OVERHEAD + mps));
  2050. return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
  2051. (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
  2052. 1 << ep_bw->ep_interval);
  2053. }
  2054. void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
  2055. struct xhci_bw_info *ep_bw,
  2056. struct xhci_interval_bw_table *bw_table,
  2057. struct usb_device *udev,
  2058. struct xhci_virt_ep *virt_ep,
  2059. struct xhci_tt_bw_info *tt_info)
  2060. {
  2061. struct xhci_interval_bw *interval_bw;
  2062. int normalized_interval;
  2063. if (xhci_is_async_ep(ep_bw->type))
  2064. return;
  2065. if (udev->speed == USB_SPEED_SUPER) {
  2066. if (xhci_is_sync_in_ep(ep_bw->type))
  2067. xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
  2068. xhci_get_ss_bw_consumed(ep_bw);
  2069. else
  2070. xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
  2071. xhci_get_ss_bw_consumed(ep_bw);
  2072. return;
  2073. }
  2074. /* SuperSpeed endpoints never get added to intervals in the table, so
  2075. * this check is only valid for HS/FS/LS devices.
  2076. */
  2077. if (list_empty(&virt_ep->bw_endpoint_list))
  2078. return;
  2079. /* For LS/FS devices, we need to translate the interval expressed in
  2080. * microframes to frames.
  2081. */
  2082. if (udev->speed == USB_SPEED_HIGH)
  2083. normalized_interval = ep_bw->ep_interval;
  2084. else
  2085. normalized_interval = ep_bw->ep_interval - 3;
  2086. if (normalized_interval == 0)
  2087. bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
  2088. interval_bw = &bw_table->interval_bw[normalized_interval];
  2089. interval_bw->num_packets -= ep_bw->num_packets;
  2090. switch (udev->speed) {
  2091. case USB_SPEED_LOW:
  2092. interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
  2093. break;
  2094. case USB_SPEED_FULL:
  2095. interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
  2096. break;
  2097. case USB_SPEED_HIGH:
  2098. interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
  2099. break;
  2100. case USB_SPEED_SUPER:
  2101. case USB_SPEED_UNKNOWN:
  2102. case USB_SPEED_WIRELESS:
  2103. /* Should never happen because only LS/FS/HS endpoints will get
  2104. * added to the endpoint list.
  2105. */
  2106. return;
  2107. }
  2108. if (tt_info)
  2109. tt_info->active_eps -= 1;
  2110. list_del_init(&virt_ep->bw_endpoint_list);
  2111. }
  2112. static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
  2113. struct xhci_bw_info *ep_bw,
  2114. struct xhci_interval_bw_table *bw_table,
  2115. struct usb_device *udev,
  2116. struct xhci_virt_ep *virt_ep,
  2117. struct xhci_tt_bw_info *tt_info)
  2118. {
  2119. struct xhci_interval_bw *interval_bw;
  2120. struct xhci_virt_ep *smaller_ep;
  2121. int normalized_interval;
  2122. if (xhci_is_async_ep(ep_bw->type))
  2123. return;
  2124. if (udev->speed == USB_SPEED_SUPER) {
  2125. if (xhci_is_sync_in_ep(ep_bw->type))
  2126. xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
  2127. xhci_get_ss_bw_consumed(ep_bw);
  2128. else
  2129. xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
  2130. xhci_get_ss_bw_consumed(ep_bw);
  2131. return;
  2132. }
  2133. /* For LS/FS devices, we need to translate the interval expressed in
  2134. * microframes to frames.
  2135. */
  2136. if (udev->speed == USB_SPEED_HIGH)
  2137. normalized_interval = ep_bw->ep_interval;
  2138. else
  2139. normalized_interval = ep_bw->ep_interval - 3;
  2140. if (normalized_interval == 0)
  2141. bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
  2142. interval_bw = &bw_table->interval_bw[normalized_interval];
  2143. interval_bw->num_packets += ep_bw->num_packets;
  2144. switch (udev->speed) {
  2145. case USB_SPEED_LOW:
  2146. interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
  2147. break;
  2148. case USB_SPEED_FULL:
  2149. interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
  2150. break;
  2151. case USB_SPEED_HIGH:
  2152. interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
  2153. break;
  2154. case USB_SPEED_SUPER:
  2155. case USB_SPEED_UNKNOWN:
  2156. case USB_SPEED_WIRELESS:
  2157. /* Should never happen because only LS/FS/HS endpoints will get
  2158. * added to the endpoint list.
  2159. */
  2160. return;
  2161. }
  2162. if (tt_info)
  2163. tt_info->active_eps += 1;
  2164. /* Insert the endpoint into the list, largest max packet size first. */
  2165. list_for_each_entry(smaller_ep, &interval_bw->endpoints,
  2166. bw_endpoint_list) {
  2167. if (ep_bw->max_packet_size >=
  2168. smaller_ep->bw_info.max_packet_size) {
  2169. /* Add the new ep before the smaller endpoint */
  2170. list_add_tail(&virt_ep->bw_endpoint_list,
  2171. &smaller_ep->bw_endpoint_list);
  2172. return;
  2173. }
  2174. }
  2175. /* Add the new endpoint at the end of the list. */
  2176. list_add_tail(&virt_ep->bw_endpoint_list,
  2177. &interval_bw->endpoints);
  2178. }
  2179. void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
  2180. struct xhci_virt_device *virt_dev,
  2181. int old_active_eps)
  2182. {
  2183. struct xhci_root_port_bw_info *rh_bw_info;
  2184. if (!virt_dev->tt_info)
  2185. return;
  2186. rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
  2187. if (old_active_eps == 0 &&
  2188. virt_dev->tt_info->active_eps != 0) {
  2189. rh_bw_info->num_active_tts += 1;
  2190. rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
  2191. } else if (old_active_eps != 0 &&
  2192. virt_dev->tt_info->active_eps == 0) {
  2193. rh_bw_info->num_active_tts -= 1;
  2194. rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
  2195. }
  2196. }
  2197. static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
  2198. struct xhci_virt_device *virt_dev,
  2199. struct xhci_container_ctx *in_ctx)
  2200. {
  2201. struct xhci_bw_info ep_bw_info[31];
  2202. int i;
  2203. struct xhci_input_control_ctx *ctrl_ctx;
  2204. int old_active_eps = 0;
  2205. if (virt_dev->tt_info)
  2206. old_active_eps = virt_dev->tt_info->active_eps;
  2207. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  2208. if (!ctrl_ctx) {
  2209. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  2210. __func__);
  2211. return -ENOMEM;
  2212. }
  2213. for (i = 0; i < 31; i++) {
  2214. if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
  2215. continue;
  2216. /* Make a copy of the BW info in case we need to revert this */
  2217. memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
  2218. sizeof(ep_bw_info[i]));
  2219. /* Drop the endpoint from the interval table if the endpoint is
  2220. * being dropped or changed.
  2221. */
  2222. if (EP_IS_DROPPED(ctrl_ctx, i))
  2223. xhci_drop_ep_from_interval_table(xhci,
  2224. &virt_dev->eps[i].bw_info,
  2225. virt_dev->bw_table,
  2226. virt_dev->udev,
  2227. &virt_dev->eps[i],
  2228. virt_dev->tt_info);
  2229. }
  2230. /* Overwrite the information stored in the endpoints' bw_info */
  2231. xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
  2232. for (i = 0; i < 31; i++) {
  2233. /* Add any changed or added endpoints to the interval table */
  2234. if (EP_IS_ADDED(ctrl_ctx, i))
  2235. xhci_add_ep_to_interval_table(xhci,
  2236. &virt_dev->eps[i].bw_info,
  2237. virt_dev->bw_table,
  2238. virt_dev->udev,
  2239. &virt_dev->eps[i],
  2240. virt_dev->tt_info);
  2241. }
  2242. if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
  2243. /* Ok, this fits in the bandwidth we have.
  2244. * Update the number of active TTs.
  2245. */
  2246. xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
  2247. return 0;
  2248. }
  2249. /* We don't have enough bandwidth for this, revert the stored info. */
  2250. for (i = 0; i < 31; i++) {
  2251. if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
  2252. continue;
  2253. /* Drop the new copies of any added or changed endpoints from
  2254. * the interval table.
  2255. */
  2256. if (EP_IS_ADDED(ctrl_ctx, i)) {
  2257. xhci_drop_ep_from_interval_table(xhci,
  2258. &virt_dev->eps[i].bw_info,
  2259. virt_dev->bw_table,
  2260. virt_dev->udev,
  2261. &virt_dev->eps[i],
  2262. virt_dev->tt_info);
  2263. }
  2264. /* Revert the endpoint back to its old information */
  2265. memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
  2266. sizeof(ep_bw_info[i]));
  2267. /* Add any changed or dropped endpoints back into the table */
  2268. if (EP_IS_DROPPED(ctrl_ctx, i))
  2269. xhci_add_ep_to_interval_table(xhci,
  2270. &virt_dev->eps[i].bw_info,
  2271. virt_dev->bw_table,
  2272. virt_dev->udev,
  2273. &virt_dev->eps[i],
  2274. virt_dev->tt_info);
  2275. }
  2276. return -ENOMEM;
  2277. }
  2278. /* Issue a configure endpoint command or evaluate context command
  2279. * and wait for it to finish.
  2280. */
  2281. static int xhci_configure_endpoint(struct xhci_hcd *xhci,
  2282. struct usb_device *udev,
  2283. struct xhci_command *command,
  2284. bool ctx_change, bool must_succeed)
  2285. {
  2286. int ret;
  2287. int timeleft;
  2288. unsigned long flags;
  2289. struct xhci_container_ctx *in_ctx;
  2290. struct xhci_input_control_ctx *ctrl_ctx;
  2291. struct completion *cmd_completion;
  2292. u32 *cmd_status;
  2293. struct xhci_virt_device *virt_dev;
  2294. union xhci_trb *cmd_trb;
  2295. spin_lock_irqsave(&xhci->lock, flags);
  2296. virt_dev = xhci->devs[udev->slot_id];
  2297. if (command)
  2298. in_ctx = command->in_ctx;
  2299. else
  2300. in_ctx = virt_dev->in_ctx;
  2301. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  2302. if (!ctrl_ctx) {
  2303. spin_unlock_irqrestore(&xhci->lock, flags);
  2304. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  2305. __func__);
  2306. return -ENOMEM;
  2307. }
  2308. if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
  2309. xhci_reserve_host_resources(xhci, ctrl_ctx)) {
  2310. spin_unlock_irqrestore(&xhci->lock, flags);
  2311. xhci_warn(xhci, "Not enough host resources, "
  2312. "active endpoint contexts = %u\n",
  2313. xhci->num_active_eps);
  2314. return -ENOMEM;
  2315. }
  2316. if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
  2317. xhci_reserve_bandwidth(xhci, virt_dev, in_ctx)) {
  2318. if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
  2319. xhci_free_host_resources(xhci, ctrl_ctx);
  2320. spin_unlock_irqrestore(&xhci->lock, flags);
  2321. xhci_warn(xhci, "Not enough bandwidth\n");
  2322. return -ENOMEM;
  2323. }
  2324. if (command) {
  2325. cmd_completion = command->completion;
  2326. cmd_status = &command->status;
  2327. command->command_trb = xhci->cmd_ring->enqueue;
  2328. /* Enqueue pointer can be left pointing to the link TRB,
  2329. * we must handle that
  2330. */
  2331. if (TRB_TYPE_LINK_LE32(command->command_trb->link.control))
  2332. command->command_trb =
  2333. xhci->cmd_ring->enq_seg->next->trbs;
  2334. list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
  2335. } else {
  2336. cmd_completion = &virt_dev->cmd_completion;
  2337. cmd_status = &virt_dev->cmd_status;
  2338. }
  2339. init_completion(cmd_completion);
  2340. cmd_trb = xhci->cmd_ring->dequeue;
  2341. if (!ctx_change)
  2342. ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
  2343. udev->slot_id, must_succeed);
  2344. else
  2345. ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
  2346. udev->slot_id, must_succeed);
  2347. if (ret < 0) {
  2348. if (command)
  2349. list_del(&command->cmd_list);
  2350. if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
  2351. xhci_free_host_resources(xhci, ctrl_ctx);
  2352. spin_unlock_irqrestore(&xhci->lock, flags);
  2353. xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
  2354. return -ENOMEM;
  2355. }
  2356. xhci_ring_cmd_db(xhci);
  2357. spin_unlock_irqrestore(&xhci->lock, flags);
  2358. /* Wait for the configure endpoint command to complete */
  2359. timeleft = wait_for_completion_interruptible_timeout(
  2360. cmd_completion,
  2361. XHCI_CMD_DEFAULT_TIMEOUT);
  2362. if (timeleft <= 0) {
  2363. xhci_warn(xhci, "%s while waiting for %s command\n",
  2364. timeleft == 0 ? "Timeout" : "Signal",
  2365. ctx_change == 0 ?
  2366. "configure endpoint" :
  2367. "evaluate context");
  2368. /* cancel the configure endpoint command */
  2369. ret = xhci_cancel_cmd(xhci, command, cmd_trb);
  2370. if (ret < 0)
  2371. return ret;
  2372. return -ETIME;
  2373. }
  2374. if (!ctx_change)
  2375. ret = xhci_configure_endpoint_result(xhci, udev, cmd_status);
  2376. else
  2377. ret = xhci_evaluate_context_result(xhci, udev, cmd_status);
  2378. if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
  2379. spin_lock_irqsave(&xhci->lock, flags);
  2380. /* If the command failed, remove the reserved resources.
  2381. * Otherwise, clean up the estimate to include dropped eps.
  2382. */
  2383. if (ret)
  2384. xhci_free_host_resources(xhci, ctrl_ctx);
  2385. else
  2386. xhci_finish_resource_reservation(xhci, ctrl_ctx);
  2387. spin_unlock_irqrestore(&xhci->lock, flags);
  2388. }
  2389. return ret;
  2390. }
  2391. /* Called after one or more calls to xhci_add_endpoint() or
  2392. * xhci_drop_endpoint(). If this call fails, the USB core is expected
  2393. * to call xhci_reset_bandwidth().
  2394. *
  2395. * Since we are in the middle of changing either configuration or
  2396. * installing a new alt setting, the USB core won't allow URBs to be
  2397. * enqueued for any endpoint on the old config or interface. Nothing
  2398. * else should be touching the xhci->devs[slot_id] structure, so we
  2399. * don't need to take the xhci->lock for manipulating that.
  2400. */
  2401. int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
  2402. {
  2403. int i;
  2404. int ret = 0;
  2405. struct xhci_hcd *xhci;
  2406. struct xhci_virt_device *virt_dev;
  2407. struct xhci_input_control_ctx *ctrl_ctx;
  2408. struct xhci_slot_ctx *slot_ctx;
  2409. ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
  2410. if (ret <= 0)
  2411. return ret;
  2412. xhci = hcd_to_xhci(hcd);
  2413. if (xhci->xhc_state & XHCI_STATE_DYING)
  2414. return -ENODEV;
  2415. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  2416. virt_dev = xhci->devs[udev->slot_id];
  2417. /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
  2418. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  2419. if (!ctrl_ctx) {
  2420. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  2421. __func__);
  2422. return -ENOMEM;
  2423. }
  2424. ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
  2425. ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
  2426. ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
  2427. /* Don't issue the command if there's no endpoints to update. */
  2428. if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
  2429. ctrl_ctx->drop_flags == 0)
  2430. return 0;
  2431. xhci_dbg(xhci, "New Input Control Context:\n");
  2432. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
  2433. xhci_dbg_ctx(xhci, virt_dev->in_ctx,
  2434. LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
  2435. ret = xhci_configure_endpoint(xhci, udev, NULL,
  2436. false, false);
  2437. if (ret) {
  2438. /* Callee should call reset_bandwidth() */
  2439. return ret;
  2440. }
  2441. xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
  2442. xhci_dbg_ctx(xhci, virt_dev->out_ctx,
  2443. LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
  2444. /* Free any rings that were dropped, but not changed. */
  2445. for (i = 1; i < 31; ++i) {
  2446. if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
  2447. !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))))
  2448. xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
  2449. }
  2450. xhci_zero_in_ctx(xhci, virt_dev);
  2451. /*
  2452. * Install any rings for completely new endpoints or changed endpoints,
  2453. * and free or cache any old rings from changed endpoints.
  2454. */
  2455. for (i = 1; i < 31; ++i) {
  2456. if (!virt_dev->eps[i].new_ring)
  2457. continue;
  2458. /* Only cache or free the old ring if it exists.
  2459. * It may not if this is the first add of an endpoint.
  2460. */
  2461. if (virt_dev->eps[i].ring) {
  2462. xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
  2463. }
  2464. virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
  2465. virt_dev->eps[i].new_ring = NULL;
  2466. }
  2467. return ret;
  2468. }
  2469. void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
  2470. {
  2471. struct xhci_hcd *xhci;
  2472. struct xhci_virt_device *virt_dev;
  2473. int i, ret;
  2474. ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
  2475. if (ret <= 0)
  2476. return;
  2477. xhci = hcd_to_xhci(hcd);
  2478. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  2479. virt_dev = xhci->devs[udev->slot_id];
  2480. /* Free any rings allocated for added endpoints */
  2481. for (i = 0; i < 31; ++i) {
  2482. if (virt_dev->eps[i].new_ring) {
  2483. xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
  2484. virt_dev->eps[i].new_ring = NULL;
  2485. }
  2486. }
  2487. xhci_zero_in_ctx(xhci, virt_dev);
  2488. }
  2489. static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
  2490. struct xhci_container_ctx *in_ctx,
  2491. struct xhci_container_ctx *out_ctx,
  2492. struct xhci_input_control_ctx *ctrl_ctx,
  2493. u32 add_flags, u32 drop_flags)
  2494. {
  2495. ctrl_ctx->add_flags = cpu_to_le32(add_flags);
  2496. ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
  2497. xhci_slot_copy(xhci, in_ctx, out_ctx);
  2498. ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
  2499. xhci_dbg(xhci, "Input Context:\n");
  2500. xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
  2501. }
  2502. static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
  2503. unsigned int slot_id, unsigned int ep_index,
  2504. struct xhci_dequeue_state *deq_state)
  2505. {
  2506. struct xhci_input_control_ctx *ctrl_ctx;
  2507. struct xhci_container_ctx *in_ctx;
  2508. struct xhci_ep_ctx *ep_ctx;
  2509. u32 added_ctxs;
  2510. dma_addr_t addr;
  2511. in_ctx = xhci->devs[slot_id]->in_ctx;
  2512. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  2513. if (!ctrl_ctx) {
  2514. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  2515. __func__);
  2516. return;
  2517. }
  2518. xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
  2519. xhci->devs[slot_id]->out_ctx, ep_index);
  2520. ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
  2521. addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
  2522. deq_state->new_deq_ptr);
  2523. if (addr == 0) {
  2524. xhci_warn(xhci, "WARN Cannot submit config ep after "
  2525. "reset ep command\n");
  2526. xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
  2527. deq_state->new_deq_seg,
  2528. deq_state->new_deq_ptr);
  2529. return;
  2530. }
  2531. ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
  2532. added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
  2533. xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
  2534. xhci->devs[slot_id]->out_ctx, ctrl_ctx,
  2535. added_ctxs, added_ctxs);
  2536. }
  2537. void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
  2538. struct usb_device *udev, unsigned int ep_index)
  2539. {
  2540. struct xhci_dequeue_state deq_state;
  2541. struct xhci_virt_ep *ep;
  2542. xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
  2543. ep = &xhci->devs[udev->slot_id]->eps[ep_index];
  2544. /* We need to move the HW's dequeue pointer past this TD,
  2545. * or it will attempt to resend it on the next doorbell ring.
  2546. */
  2547. xhci_find_new_dequeue_state(xhci, udev->slot_id,
  2548. ep_index, ep->stopped_stream, ep->stopped_td,
  2549. &deq_state);
  2550. /* HW with the reset endpoint quirk will use the saved dequeue state to
  2551. * issue a configure endpoint command later.
  2552. */
  2553. if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
  2554. xhci_dbg(xhci, "Queueing new dequeue state\n");
  2555. xhci_queue_new_dequeue_state(xhci, udev->slot_id,
  2556. ep_index, ep->stopped_stream, &deq_state);
  2557. } else {
  2558. /* Better hope no one uses the input context between now and the
  2559. * reset endpoint completion!
  2560. * XXX: No idea how this hardware will react when stream rings
  2561. * are enabled.
  2562. */
  2563. xhci_dbg(xhci, "Setting up input context for "
  2564. "configure endpoint command\n");
  2565. xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
  2566. ep_index, &deq_state);
  2567. }
  2568. }
  2569. /* Deal with stalled endpoints. The core should have sent the control message
  2570. * to clear the halt condition. However, we need to make the xHCI hardware
  2571. * reset its sequence number, since a device will expect a sequence number of
  2572. * zero after the halt condition is cleared.
  2573. * Context: in_interrupt
  2574. */
  2575. void xhci_endpoint_reset(struct usb_hcd *hcd,
  2576. struct usb_host_endpoint *ep)
  2577. {
  2578. struct xhci_hcd *xhci;
  2579. struct usb_device *udev;
  2580. unsigned int ep_index;
  2581. unsigned long flags;
  2582. int ret;
  2583. struct xhci_virt_ep *virt_ep;
  2584. xhci = hcd_to_xhci(hcd);
  2585. udev = (struct usb_device *) ep->hcpriv;
  2586. /* Called with a root hub endpoint (or an endpoint that wasn't added
  2587. * with xhci_add_endpoint()
  2588. */
  2589. if (!ep->hcpriv)
  2590. return;
  2591. ep_index = xhci_get_endpoint_index(&ep->desc);
  2592. virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
  2593. if (!virt_ep->stopped_td) {
  2594. xhci_dbg(xhci, "Endpoint 0x%x not halted, refusing to reset.\n",
  2595. ep->desc.bEndpointAddress);
  2596. return;
  2597. }
  2598. if (usb_endpoint_xfer_control(&ep->desc)) {
  2599. xhci_dbg(xhci, "Control endpoint stall already handled.\n");
  2600. return;
  2601. }
  2602. xhci_dbg(xhci, "Queueing reset endpoint command\n");
  2603. spin_lock_irqsave(&xhci->lock, flags);
  2604. ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
  2605. /*
  2606. * Can't change the ring dequeue pointer until it's transitioned to the
  2607. * stopped state, which is only upon a successful reset endpoint
  2608. * command. Better hope that last command worked!
  2609. */
  2610. if (!ret) {
  2611. xhci_cleanup_stalled_ring(xhci, udev, ep_index);
  2612. kfree(virt_ep->stopped_td);
  2613. xhci_ring_cmd_db(xhci);
  2614. }
  2615. virt_ep->stopped_td = NULL;
  2616. virt_ep->stopped_trb = NULL;
  2617. virt_ep->stopped_stream = 0;
  2618. spin_unlock_irqrestore(&xhci->lock, flags);
  2619. if (ret)
  2620. xhci_warn(xhci, "FIXME allocate a new ring segment\n");
  2621. }
  2622. static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
  2623. struct usb_device *udev, struct usb_host_endpoint *ep,
  2624. unsigned int slot_id)
  2625. {
  2626. int ret;
  2627. unsigned int ep_index;
  2628. unsigned int ep_state;
  2629. if (!ep)
  2630. return -EINVAL;
  2631. ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
  2632. if (ret <= 0)
  2633. return -EINVAL;
  2634. if (ep->ss_ep_comp.bmAttributes == 0) {
  2635. xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
  2636. " descriptor for ep 0x%x does not support streams\n",
  2637. ep->desc.bEndpointAddress);
  2638. return -EINVAL;
  2639. }
  2640. ep_index = xhci_get_endpoint_index(&ep->desc);
  2641. ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
  2642. if (ep_state & EP_HAS_STREAMS ||
  2643. ep_state & EP_GETTING_STREAMS) {
  2644. xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
  2645. "already has streams set up.\n",
  2646. ep->desc.bEndpointAddress);
  2647. xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
  2648. "dynamic stream context array reallocation.\n");
  2649. return -EINVAL;
  2650. }
  2651. if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
  2652. xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
  2653. "endpoint 0x%x; URBs are pending.\n",
  2654. ep->desc.bEndpointAddress);
  2655. return -EINVAL;
  2656. }
  2657. return 0;
  2658. }
  2659. static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
  2660. unsigned int *num_streams, unsigned int *num_stream_ctxs)
  2661. {
  2662. unsigned int max_streams;
  2663. /* The stream context array size must be a power of two */
  2664. *num_stream_ctxs = roundup_pow_of_two(*num_streams);
  2665. /*
  2666. * Find out how many primary stream array entries the host controller
  2667. * supports. Later we may use secondary stream arrays (similar to 2nd
  2668. * level page entries), but that's an optional feature for xHCI host
  2669. * controllers. xHCs must support at least 4 stream IDs.
  2670. */
  2671. max_streams = HCC_MAX_PSA(xhci->hcc_params);
  2672. if (*num_stream_ctxs > max_streams) {
  2673. xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
  2674. max_streams);
  2675. *num_stream_ctxs = max_streams;
  2676. *num_streams = max_streams;
  2677. }
  2678. }
  2679. /* Returns an error code if one of the endpoint already has streams.
  2680. * This does not change any data structures, it only checks and gathers
  2681. * information.
  2682. */
  2683. static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
  2684. struct usb_device *udev,
  2685. struct usb_host_endpoint **eps, unsigned int num_eps,
  2686. unsigned int *num_streams, u32 *changed_ep_bitmask)
  2687. {
  2688. unsigned int max_streams;
  2689. unsigned int endpoint_flag;
  2690. int i;
  2691. int ret;
  2692. for (i = 0; i < num_eps; i++) {
  2693. ret = xhci_check_streams_endpoint(xhci, udev,
  2694. eps[i], udev->slot_id);
  2695. if (ret < 0)
  2696. return ret;
  2697. max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
  2698. if (max_streams < (*num_streams - 1)) {
  2699. xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
  2700. eps[i]->desc.bEndpointAddress,
  2701. max_streams);
  2702. *num_streams = max_streams+1;
  2703. }
  2704. endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
  2705. if (*changed_ep_bitmask & endpoint_flag)
  2706. return -EINVAL;
  2707. *changed_ep_bitmask |= endpoint_flag;
  2708. }
  2709. return 0;
  2710. }
  2711. static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
  2712. struct usb_device *udev,
  2713. struct usb_host_endpoint **eps, unsigned int num_eps)
  2714. {
  2715. u32 changed_ep_bitmask = 0;
  2716. unsigned int slot_id;
  2717. unsigned int ep_index;
  2718. unsigned int ep_state;
  2719. int i;
  2720. slot_id = udev->slot_id;
  2721. if (!xhci->devs[slot_id])
  2722. return 0;
  2723. for (i = 0; i < num_eps; i++) {
  2724. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2725. ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
  2726. /* Are streams already being freed for the endpoint? */
  2727. if (ep_state & EP_GETTING_NO_STREAMS) {
  2728. xhci_warn(xhci, "WARN Can't disable streams for "
  2729. "endpoint 0x%x, "
  2730. "streams are being disabled already\n",
  2731. eps[i]->desc.bEndpointAddress);
  2732. return 0;
  2733. }
  2734. /* Are there actually any streams to free? */
  2735. if (!(ep_state & EP_HAS_STREAMS) &&
  2736. !(ep_state & EP_GETTING_STREAMS)) {
  2737. xhci_warn(xhci, "WARN Can't disable streams for "
  2738. "endpoint 0x%x, "
  2739. "streams are already disabled!\n",
  2740. eps[i]->desc.bEndpointAddress);
  2741. xhci_warn(xhci, "WARN xhci_free_streams() called "
  2742. "with non-streams endpoint\n");
  2743. return 0;
  2744. }
  2745. changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
  2746. }
  2747. return changed_ep_bitmask;
  2748. }
  2749. /*
  2750. * The USB device drivers use this function (though the HCD interface in USB
  2751. * core) to prepare a set of bulk endpoints to use streams. Streams are used to
  2752. * coordinate mass storage command queueing across multiple endpoints (basically
  2753. * a stream ID == a task ID).
  2754. *
  2755. * Setting up streams involves allocating the same size stream context array
  2756. * for each endpoint and issuing a configure endpoint command for all endpoints.
  2757. *
  2758. * Don't allow the call to succeed if one endpoint only supports one stream
  2759. * (which means it doesn't support streams at all).
  2760. *
  2761. * Drivers may get less stream IDs than they asked for, if the host controller
  2762. * hardware or endpoints claim they can't support the number of requested
  2763. * stream IDs.
  2764. */
  2765. int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
  2766. struct usb_host_endpoint **eps, unsigned int num_eps,
  2767. unsigned int num_streams, gfp_t mem_flags)
  2768. {
  2769. int i, ret;
  2770. struct xhci_hcd *xhci;
  2771. struct xhci_virt_device *vdev;
  2772. struct xhci_command *config_cmd;
  2773. struct xhci_input_control_ctx *ctrl_ctx;
  2774. unsigned int ep_index;
  2775. unsigned int num_stream_ctxs;
  2776. unsigned long flags;
  2777. u32 changed_ep_bitmask = 0;
  2778. if (!eps)
  2779. return -EINVAL;
  2780. /* Add one to the number of streams requested to account for
  2781. * stream 0 that is reserved for xHCI usage.
  2782. */
  2783. num_streams += 1;
  2784. xhci = hcd_to_xhci(hcd);
  2785. xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
  2786. num_streams);
  2787. config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
  2788. if (!config_cmd) {
  2789. xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
  2790. return -ENOMEM;
  2791. }
  2792. ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
  2793. if (!ctrl_ctx) {
  2794. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  2795. __func__);
  2796. xhci_free_command(xhci, config_cmd);
  2797. return -ENOMEM;
  2798. }
  2799. /* Check to make sure all endpoints are not already configured for
  2800. * streams. While we're at it, find the maximum number of streams that
  2801. * all the endpoints will support and check for duplicate endpoints.
  2802. */
  2803. spin_lock_irqsave(&xhci->lock, flags);
  2804. ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
  2805. num_eps, &num_streams, &changed_ep_bitmask);
  2806. if (ret < 0) {
  2807. xhci_free_command(xhci, config_cmd);
  2808. spin_unlock_irqrestore(&xhci->lock, flags);
  2809. return ret;
  2810. }
  2811. if (num_streams <= 1) {
  2812. xhci_warn(xhci, "WARN: endpoints can't handle "
  2813. "more than one stream.\n");
  2814. xhci_free_command(xhci, config_cmd);
  2815. spin_unlock_irqrestore(&xhci->lock, flags);
  2816. return -EINVAL;
  2817. }
  2818. vdev = xhci->devs[udev->slot_id];
  2819. /* Mark each endpoint as being in transition, so
  2820. * xhci_urb_enqueue() will reject all URBs.
  2821. */
  2822. for (i = 0; i < num_eps; i++) {
  2823. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2824. vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
  2825. }
  2826. spin_unlock_irqrestore(&xhci->lock, flags);
  2827. /* Setup internal data structures and allocate HW data structures for
  2828. * streams (but don't install the HW structures in the input context
  2829. * until we're sure all memory allocation succeeded).
  2830. */
  2831. xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
  2832. xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
  2833. num_stream_ctxs, num_streams);
  2834. for (i = 0; i < num_eps; i++) {
  2835. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2836. vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
  2837. num_stream_ctxs,
  2838. num_streams, mem_flags);
  2839. if (!vdev->eps[ep_index].stream_info)
  2840. goto cleanup;
  2841. /* Set maxPstreams in endpoint context and update deq ptr to
  2842. * point to stream context array. FIXME
  2843. */
  2844. }
  2845. /* Set up the input context for a configure endpoint command. */
  2846. for (i = 0; i < num_eps; i++) {
  2847. struct xhci_ep_ctx *ep_ctx;
  2848. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2849. ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
  2850. xhci_endpoint_copy(xhci, config_cmd->in_ctx,
  2851. vdev->out_ctx, ep_index);
  2852. xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
  2853. vdev->eps[ep_index].stream_info);
  2854. }
  2855. /* Tell the HW to drop its old copy of the endpoint context info
  2856. * and add the updated copy from the input context.
  2857. */
  2858. xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
  2859. vdev->out_ctx, ctrl_ctx,
  2860. changed_ep_bitmask, changed_ep_bitmask);
  2861. /* Issue and wait for the configure endpoint command */
  2862. ret = xhci_configure_endpoint(xhci, udev, config_cmd,
  2863. false, false);
  2864. /* xHC rejected the configure endpoint command for some reason, so we
  2865. * leave the old ring intact and free our internal streams data
  2866. * structure.
  2867. */
  2868. if (ret < 0)
  2869. goto cleanup;
  2870. spin_lock_irqsave(&xhci->lock, flags);
  2871. for (i = 0; i < num_eps; i++) {
  2872. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2873. vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
  2874. xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
  2875. udev->slot_id, ep_index);
  2876. vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
  2877. }
  2878. xhci_free_command(xhci, config_cmd);
  2879. spin_unlock_irqrestore(&xhci->lock, flags);
  2880. /* Subtract 1 for stream 0, which drivers can't use */
  2881. return num_streams - 1;
  2882. cleanup:
  2883. /* If it didn't work, free the streams! */
  2884. for (i = 0; i < num_eps; i++) {
  2885. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2886. xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
  2887. vdev->eps[ep_index].stream_info = NULL;
  2888. /* FIXME Unset maxPstreams in endpoint context and
  2889. * update deq ptr to point to normal string ring.
  2890. */
  2891. vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
  2892. vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
  2893. xhci_endpoint_zero(xhci, vdev, eps[i]);
  2894. }
  2895. xhci_free_command(xhci, config_cmd);
  2896. return -ENOMEM;
  2897. }
  2898. /* Transition the endpoint from using streams to being a "normal" endpoint
  2899. * without streams.
  2900. *
  2901. * Modify the endpoint context state, submit a configure endpoint command,
  2902. * and free all endpoint rings for streams if that completes successfully.
  2903. */
  2904. int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
  2905. struct usb_host_endpoint **eps, unsigned int num_eps,
  2906. gfp_t mem_flags)
  2907. {
  2908. int i, ret;
  2909. struct xhci_hcd *xhci;
  2910. struct xhci_virt_device *vdev;
  2911. struct xhci_command *command;
  2912. struct xhci_input_control_ctx *ctrl_ctx;
  2913. unsigned int ep_index;
  2914. unsigned long flags;
  2915. u32 changed_ep_bitmask;
  2916. xhci = hcd_to_xhci(hcd);
  2917. vdev = xhci->devs[udev->slot_id];
  2918. /* Set up a configure endpoint command to remove the streams rings */
  2919. spin_lock_irqsave(&xhci->lock, flags);
  2920. changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
  2921. udev, eps, num_eps);
  2922. if (changed_ep_bitmask == 0) {
  2923. spin_unlock_irqrestore(&xhci->lock, flags);
  2924. return -EINVAL;
  2925. }
  2926. /* Use the xhci_command structure from the first endpoint. We may have
  2927. * allocated too many, but the driver may call xhci_free_streams() for
  2928. * each endpoint it grouped into one call to xhci_alloc_streams().
  2929. */
  2930. ep_index = xhci_get_endpoint_index(&eps[0]->desc);
  2931. command = vdev->eps[ep_index].stream_info->free_streams_command;
  2932. ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx);
  2933. if (!ctrl_ctx) {
  2934. spin_unlock_irqrestore(&xhci->lock, flags);
  2935. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  2936. __func__);
  2937. return -EINVAL;
  2938. }
  2939. for (i = 0; i < num_eps; i++) {
  2940. struct xhci_ep_ctx *ep_ctx;
  2941. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2942. ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
  2943. xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
  2944. EP_GETTING_NO_STREAMS;
  2945. xhci_endpoint_copy(xhci, command->in_ctx,
  2946. vdev->out_ctx, ep_index);
  2947. xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx,
  2948. &vdev->eps[ep_index]);
  2949. }
  2950. xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
  2951. vdev->out_ctx, ctrl_ctx,
  2952. changed_ep_bitmask, changed_ep_bitmask);
  2953. spin_unlock_irqrestore(&xhci->lock, flags);
  2954. /* Issue and wait for the configure endpoint command,
  2955. * which must succeed.
  2956. */
  2957. ret = xhci_configure_endpoint(xhci, udev, command,
  2958. false, true);
  2959. /* xHC rejected the configure endpoint command for some reason, so we
  2960. * leave the streams rings intact.
  2961. */
  2962. if (ret < 0)
  2963. return ret;
  2964. spin_lock_irqsave(&xhci->lock, flags);
  2965. for (i = 0; i < num_eps; i++) {
  2966. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2967. xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
  2968. vdev->eps[ep_index].stream_info = NULL;
  2969. /* FIXME Unset maxPstreams in endpoint context and
  2970. * update deq ptr to point to normal string ring.
  2971. */
  2972. vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
  2973. vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
  2974. }
  2975. spin_unlock_irqrestore(&xhci->lock, flags);
  2976. return 0;
  2977. }
  2978. /*
  2979. * Deletes endpoint resources for endpoints that were active before a Reset
  2980. * Device command, or a Disable Slot command. The Reset Device command leaves
  2981. * the control endpoint intact, whereas the Disable Slot command deletes it.
  2982. *
  2983. * Must be called with xhci->lock held.
  2984. */
  2985. void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
  2986. struct xhci_virt_device *virt_dev, bool drop_control_ep)
  2987. {
  2988. int i;
  2989. unsigned int num_dropped_eps = 0;
  2990. unsigned int drop_flags = 0;
  2991. for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
  2992. if (virt_dev->eps[i].ring) {
  2993. drop_flags |= 1 << i;
  2994. num_dropped_eps++;
  2995. }
  2996. }
  2997. xhci->num_active_eps -= num_dropped_eps;
  2998. if (num_dropped_eps)
  2999. xhci_dbg(xhci, "Dropped %u ep ctxs, flags = 0x%x, "
  3000. "%u now active.\n",
  3001. num_dropped_eps, drop_flags,
  3002. xhci->num_active_eps);
  3003. }
  3004. /*
  3005. * This submits a Reset Device Command, which will set the device state to 0,
  3006. * set the device address to 0, and disable all the endpoints except the default
  3007. * control endpoint. The USB core should come back and call
  3008. * xhci_address_device(), and then re-set up the configuration. If this is
  3009. * called because of a usb_reset_and_verify_device(), then the old alternate
  3010. * settings will be re-installed through the normal bandwidth allocation
  3011. * functions.
  3012. *
  3013. * Wait for the Reset Device command to finish. Remove all structures
  3014. * associated with the endpoints that were disabled. Clear the input device
  3015. * structure? Cache the rings? Reset the control endpoint 0 max packet size?
  3016. *
  3017. * If the virt_dev to be reset does not exist or does not match the udev,
  3018. * it means the device is lost, possibly due to the xHC restore error and
  3019. * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
  3020. * re-allocate the device.
  3021. */
  3022. int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
  3023. {
  3024. int ret, i;
  3025. unsigned long flags;
  3026. struct xhci_hcd *xhci;
  3027. unsigned int slot_id;
  3028. struct xhci_virt_device *virt_dev;
  3029. struct xhci_command *reset_device_cmd;
  3030. int timeleft;
  3031. int last_freed_endpoint;
  3032. struct xhci_slot_ctx *slot_ctx;
  3033. int old_active_eps = 0;
  3034. ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
  3035. if (ret <= 0)
  3036. return ret;
  3037. xhci = hcd_to_xhci(hcd);
  3038. slot_id = udev->slot_id;
  3039. virt_dev = xhci->devs[slot_id];
  3040. if (!virt_dev) {
  3041. xhci_dbg(xhci, "The device to be reset with slot ID %u does "
  3042. "not exist. Re-allocate the device\n", slot_id);
  3043. ret = xhci_alloc_dev(hcd, udev);
  3044. if (ret == 1)
  3045. return 0;
  3046. else
  3047. return -EINVAL;
  3048. }
  3049. if (virt_dev->udev != udev) {
  3050. /* If the virt_dev and the udev does not match, this virt_dev
  3051. * may belong to another udev.
  3052. * Re-allocate the device.
  3053. */
  3054. xhci_dbg(xhci, "The device to be reset with slot ID %u does "
  3055. "not match the udev. Re-allocate the device\n",
  3056. slot_id);
  3057. ret = xhci_alloc_dev(hcd, udev);
  3058. if (ret == 1)
  3059. return 0;
  3060. else
  3061. return -EINVAL;
  3062. }
  3063. /* If device is not setup, there is no point in resetting it */
  3064. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
  3065. if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
  3066. SLOT_STATE_DISABLED)
  3067. return 0;
  3068. xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
  3069. /* Allocate the command structure that holds the struct completion.
  3070. * Assume we're in process context, since the normal device reset
  3071. * process has to wait for the device anyway. Storage devices are
  3072. * reset as part of error handling, so use GFP_NOIO instead of
  3073. * GFP_KERNEL.
  3074. */
  3075. reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
  3076. if (!reset_device_cmd) {
  3077. xhci_dbg(xhci, "Couldn't allocate command structure.\n");
  3078. return -ENOMEM;
  3079. }
  3080. /* Attempt to submit the Reset Device command to the command ring */
  3081. spin_lock_irqsave(&xhci->lock, flags);
  3082. reset_device_cmd->command_trb = xhci->cmd_ring->enqueue;
  3083. /* Enqueue pointer can be left pointing to the link TRB,
  3084. * we must handle that
  3085. */
  3086. if (TRB_TYPE_LINK_LE32(reset_device_cmd->command_trb->link.control))
  3087. reset_device_cmd->command_trb =
  3088. xhci->cmd_ring->enq_seg->next->trbs;
  3089. list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
  3090. ret = xhci_queue_reset_device(xhci, slot_id);
  3091. if (ret) {
  3092. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  3093. list_del(&reset_device_cmd->cmd_list);
  3094. spin_unlock_irqrestore(&xhci->lock, flags);
  3095. goto command_cleanup;
  3096. }
  3097. xhci_ring_cmd_db(xhci);
  3098. spin_unlock_irqrestore(&xhci->lock, flags);
  3099. /* Wait for the Reset Device command to finish */
  3100. timeleft = wait_for_completion_interruptible_timeout(
  3101. reset_device_cmd->completion,
  3102. USB_CTRL_SET_TIMEOUT);
  3103. if (timeleft <= 0) {
  3104. xhci_warn(xhci, "%s while waiting for reset device command\n",
  3105. timeleft == 0 ? "Timeout" : "Signal");
  3106. spin_lock_irqsave(&xhci->lock, flags);
  3107. /* The timeout might have raced with the event ring handler, so
  3108. * only delete from the list if the item isn't poisoned.
  3109. */
  3110. if (reset_device_cmd->cmd_list.next != LIST_POISON1)
  3111. list_del(&reset_device_cmd->cmd_list);
  3112. spin_unlock_irqrestore(&xhci->lock, flags);
  3113. ret = -ETIME;
  3114. goto command_cleanup;
  3115. }
  3116. /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
  3117. * unless we tried to reset a slot ID that wasn't enabled,
  3118. * or the device wasn't in the addressed or configured state.
  3119. */
  3120. ret = reset_device_cmd->status;
  3121. switch (ret) {
  3122. case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
  3123. case COMP_CTX_STATE: /* 0.96 completion code for same thing */
  3124. xhci_info(xhci, "Can't reset device (slot ID %u) in %s state\n",
  3125. slot_id,
  3126. xhci_get_slot_state(xhci, virt_dev->out_ctx));
  3127. xhci_info(xhci, "Not freeing device rings.\n");
  3128. /* Don't treat this as an error. May change my mind later. */
  3129. ret = 0;
  3130. goto command_cleanup;
  3131. case COMP_SUCCESS:
  3132. xhci_dbg(xhci, "Successful reset device command.\n");
  3133. break;
  3134. default:
  3135. if (xhci_is_vendor_info_code(xhci, ret))
  3136. break;
  3137. xhci_warn(xhci, "Unknown completion code %u for "
  3138. "reset device command.\n", ret);
  3139. ret = -EINVAL;
  3140. goto command_cleanup;
  3141. }
  3142. /* Free up host controller endpoint resources */
  3143. if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
  3144. spin_lock_irqsave(&xhci->lock, flags);
  3145. /* Don't delete the default control endpoint resources */
  3146. xhci_free_device_endpoint_resources(xhci, virt_dev, false);
  3147. spin_unlock_irqrestore(&xhci->lock, flags);
  3148. }
  3149. /* Everything but endpoint 0 is disabled, so free or cache the rings. */
  3150. last_freed_endpoint = 1;
  3151. for (i = 1; i < 31; ++i) {
  3152. struct xhci_virt_ep *ep = &virt_dev->eps[i];
  3153. if (ep->ep_state & EP_HAS_STREAMS) {
  3154. xhci_free_stream_info(xhci, ep->stream_info);
  3155. ep->stream_info = NULL;
  3156. ep->ep_state &= ~EP_HAS_STREAMS;
  3157. }
  3158. if (ep->ring) {
  3159. xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
  3160. last_freed_endpoint = i;
  3161. }
  3162. if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
  3163. xhci_drop_ep_from_interval_table(xhci,
  3164. &virt_dev->eps[i].bw_info,
  3165. virt_dev->bw_table,
  3166. udev,
  3167. &virt_dev->eps[i],
  3168. virt_dev->tt_info);
  3169. xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
  3170. }
  3171. /* If necessary, update the number of active TTs on this root port */
  3172. xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
  3173. xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
  3174. xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
  3175. ret = 0;
  3176. command_cleanup:
  3177. xhci_free_command(xhci, reset_device_cmd);
  3178. return ret;
  3179. }
  3180. /*
  3181. * At this point, the struct usb_device is about to go away, the device has
  3182. * disconnected, and all traffic has been stopped and the endpoints have been
  3183. * disabled. Free any HC data structures associated with that device.
  3184. */
  3185. void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
  3186. {
  3187. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  3188. struct xhci_virt_device *virt_dev;
  3189. unsigned long flags;
  3190. u32 state;
  3191. int i, ret;
  3192. ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
  3193. /* If the host is halted due to driver unload, we still need to free the
  3194. * device.
  3195. */
  3196. if (ret <= 0 && ret != -ENODEV)
  3197. return;
  3198. virt_dev = xhci->devs[udev->slot_id];
  3199. /* Stop any wayward timer functions (which may grab the lock) */
  3200. for (i = 0; i < 31; ++i) {
  3201. virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
  3202. del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
  3203. }
  3204. if (udev->usb2_hw_lpm_enabled) {
  3205. xhci_set_usb2_hardware_lpm(hcd, udev, 0);
  3206. udev->usb2_hw_lpm_enabled = 0;
  3207. }
  3208. spin_lock_irqsave(&xhci->lock, flags);
  3209. /* Don't disable the slot if the host controller is dead. */
  3210. state = xhci_readl(xhci, &xhci->op_regs->status);
  3211. if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
  3212. (xhci->xhc_state & XHCI_STATE_HALTED)) {
  3213. xhci_free_virt_device(xhci, udev->slot_id);
  3214. spin_unlock_irqrestore(&xhci->lock, flags);
  3215. return;
  3216. }
  3217. if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
  3218. spin_unlock_irqrestore(&xhci->lock, flags);
  3219. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  3220. return;
  3221. }
  3222. xhci_ring_cmd_db(xhci);
  3223. spin_unlock_irqrestore(&xhci->lock, flags);
  3224. /*
  3225. * Event command completion handler will free any data structures
  3226. * associated with the slot. XXX Can free sleep?
  3227. */
  3228. }
  3229. /*
  3230. * Checks if we have enough host controller resources for the default control
  3231. * endpoint.
  3232. *
  3233. * Must be called with xhci->lock held.
  3234. */
  3235. static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
  3236. {
  3237. if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
  3238. xhci_dbg(xhci, "Not enough ep ctxs: "
  3239. "%u active, need to add 1, limit is %u.\n",
  3240. xhci->num_active_eps, xhci->limit_active_eps);
  3241. return -ENOMEM;
  3242. }
  3243. xhci->num_active_eps += 1;
  3244. xhci_dbg(xhci, "Adding 1 ep ctx, %u now active.\n",
  3245. xhci->num_active_eps);
  3246. return 0;
  3247. }
  3248. /*
  3249. * Returns 0 if the xHC ran out of device slots, the Enable Slot command
  3250. * timed out, or allocating memory failed. Returns 1 on success.
  3251. */
  3252. int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
  3253. {
  3254. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  3255. unsigned long flags;
  3256. int timeleft;
  3257. int ret;
  3258. union xhci_trb *cmd_trb;
  3259. spin_lock_irqsave(&xhci->lock, flags);
  3260. cmd_trb = xhci->cmd_ring->dequeue;
  3261. ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
  3262. if (ret) {
  3263. spin_unlock_irqrestore(&xhci->lock, flags);
  3264. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  3265. return 0;
  3266. }
  3267. xhci_ring_cmd_db(xhci);
  3268. spin_unlock_irqrestore(&xhci->lock, flags);
  3269. /* XXX: how much time for xHC slot assignment? */
  3270. timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
  3271. XHCI_CMD_DEFAULT_TIMEOUT);
  3272. if (timeleft <= 0) {
  3273. xhci_warn(xhci, "%s while waiting for a slot\n",
  3274. timeleft == 0 ? "Timeout" : "Signal");
  3275. /* cancel the enable slot request */
  3276. return xhci_cancel_cmd(xhci, NULL, cmd_trb);
  3277. }
  3278. if (!xhci->slot_id) {
  3279. xhci_err(xhci, "Error while assigning device slot ID\n");
  3280. return 0;
  3281. }
  3282. if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
  3283. spin_lock_irqsave(&xhci->lock, flags);
  3284. ret = xhci_reserve_host_control_ep_resources(xhci);
  3285. if (ret) {
  3286. spin_unlock_irqrestore(&xhci->lock, flags);
  3287. xhci_warn(xhci, "Not enough host resources, "
  3288. "active endpoint contexts = %u\n",
  3289. xhci->num_active_eps);
  3290. goto disable_slot;
  3291. }
  3292. spin_unlock_irqrestore(&xhci->lock, flags);
  3293. }
  3294. /* Use GFP_NOIO, since this function can be called from
  3295. * xhci_discover_or_reset_device(), which may be called as part of
  3296. * mass storage driver error handling.
  3297. */
  3298. if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) {
  3299. xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
  3300. goto disable_slot;
  3301. }
  3302. udev->slot_id = xhci->slot_id;
  3303. /* Is this a LS or FS device under a HS hub? */
  3304. /* Hub or peripherial? */
  3305. return 1;
  3306. disable_slot:
  3307. /* Disable slot, if we can do it without mem alloc */
  3308. spin_lock_irqsave(&xhci->lock, flags);
  3309. if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
  3310. xhci_ring_cmd_db(xhci);
  3311. spin_unlock_irqrestore(&xhci->lock, flags);
  3312. return 0;
  3313. }
  3314. /*
  3315. * Issue an Address Device command (which will issue a SetAddress request to
  3316. * the device).
  3317. * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
  3318. * we should only issue and wait on one address command at the same time.
  3319. *
  3320. * We add one to the device address issued by the hardware because the USB core
  3321. * uses address 1 for the root hubs (even though they're not really devices).
  3322. */
  3323. int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
  3324. {
  3325. unsigned long flags;
  3326. int timeleft;
  3327. struct xhci_virt_device *virt_dev;
  3328. int ret = 0;
  3329. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  3330. struct xhci_slot_ctx *slot_ctx;
  3331. struct xhci_input_control_ctx *ctrl_ctx;
  3332. u64 temp_64;
  3333. union xhci_trb *cmd_trb;
  3334. if (!udev->slot_id) {
  3335. xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
  3336. return -EINVAL;
  3337. }
  3338. virt_dev = xhci->devs[udev->slot_id];
  3339. if (WARN_ON(!virt_dev)) {
  3340. /*
  3341. * In plug/unplug torture test with an NEC controller,
  3342. * a zero-dereference was observed once due to virt_dev = 0.
  3343. * Print useful debug rather than crash if it is observed again!
  3344. */
  3345. xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
  3346. udev->slot_id);
  3347. return -EINVAL;
  3348. }
  3349. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
  3350. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  3351. if (!ctrl_ctx) {
  3352. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  3353. __func__);
  3354. return -EINVAL;
  3355. }
  3356. /*
  3357. * If this is the first Set Address since device plug-in or
  3358. * virt_device realloaction after a resume with an xHCI power loss,
  3359. * then set up the slot context.
  3360. */
  3361. if (!slot_ctx->dev_info)
  3362. xhci_setup_addressable_virt_dev(xhci, udev);
  3363. /* Otherwise, update the control endpoint ring enqueue pointer. */
  3364. else
  3365. xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
  3366. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
  3367. ctrl_ctx->drop_flags = 0;
  3368. xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
  3369. xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
  3370. spin_lock_irqsave(&xhci->lock, flags);
  3371. cmd_trb = xhci->cmd_ring->dequeue;
  3372. ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
  3373. udev->slot_id);
  3374. if (ret) {
  3375. spin_unlock_irqrestore(&xhci->lock, flags);
  3376. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  3377. return ret;
  3378. }
  3379. xhci_ring_cmd_db(xhci);
  3380. spin_unlock_irqrestore(&xhci->lock, flags);
  3381. /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
  3382. timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
  3383. XHCI_CMD_DEFAULT_TIMEOUT);
  3384. /* FIXME: From section 4.3.4: "Software shall be responsible for timing
  3385. * the SetAddress() "recovery interval" required by USB and aborting the
  3386. * command on a timeout.
  3387. */
  3388. if (timeleft <= 0) {
  3389. xhci_warn(xhci, "%s while waiting for address device command\n",
  3390. timeleft == 0 ? "Timeout" : "Signal");
  3391. /* cancel the address device command */
  3392. ret = xhci_cancel_cmd(xhci, NULL, cmd_trb);
  3393. if (ret < 0)
  3394. return ret;
  3395. return -ETIME;
  3396. }
  3397. switch (virt_dev->cmd_status) {
  3398. case COMP_CTX_STATE:
  3399. case COMP_EBADSLT:
  3400. xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
  3401. udev->slot_id);
  3402. ret = -EINVAL;
  3403. break;
  3404. case COMP_TX_ERR:
  3405. dev_warn(&udev->dev, "Device not responding to set address.\n");
  3406. ret = -EPROTO;
  3407. break;
  3408. case COMP_DEV_ERR:
  3409. dev_warn(&udev->dev, "ERROR: Incompatible device for address "
  3410. "device command.\n");
  3411. ret = -ENODEV;
  3412. break;
  3413. case COMP_SUCCESS:
  3414. xhci_dbg(xhci, "Successful Address Device command\n");
  3415. break;
  3416. default:
  3417. xhci_err(xhci, "ERROR: unexpected command completion "
  3418. "code 0x%x.\n", virt_dev->cmd_status);
  3419. xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
  3420. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
  3421. ret = -EINVAL;
  3422. break;
  3423. }
  3424. if (ret) {
  3425. return ret;
  3426. }
  3427. temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
  3428. xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64);
  3429. xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n",
  3430. udev->slot_id,
  3431. &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
  3432. (unsigned long long)
  3433. le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
  3434. xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
  3435. (unsigned long long)virt_dev->out_ctx->dma);
  3436. xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
  3437. xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
  3438. xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
  3439. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
  3440. /*
  3441. * USB core uses address 1 for the roothubs, so we add one to the
  3442. * address given back to us by the HC.
  3443. */
  3444. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
  3445. /* Use kernel assigned address for devices; store xHC assigned
  3446. * address locally. */
  3447. virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK)
  3448. + 1;
  3449. /* Zero the input context control for later use */
  3450. ctrl_ctx->add_flags = 0;
  3451. ctrl_ctx->drop_flags = 0;
  3452. xhci_dbg(xhci, "Internal device address = %d\n", virt_dev->address);
  3453. return 0;
  3454. }
  3455. /*
  3456. * Transfer the port index into real index in the HW port status
  3457. * registers. Caculate offset between the port's PORTSC register
  3458. * and port status base. Divide the number of per port register
  3459. * to get the real index. The raw port number bases 1.
  3460. */
  3461. int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
  3462. {
  3463. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  3464. __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
  3465. __le32 __iomem *addr;
  3466. int raw_port;
  3467. if (hcd->speed != HCD_USB3)
  3468. addr = xhci->usb2_ports[port1 - 1];
  3469. else
  3470. addr = xhci->usb3_ports[port1 - 1];
  3471. raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
  3472. return raw_port;
  3473. }
  3474. /*
  3475. * Issue an Evaluate Context command to change the Maximum Exit Latency in the
  3476. * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
  3477. */
  3478. static int xhci_change_max_exit_latency(struct xhci_hcd *xhci,
  3479. struct usb_device *udev, u16 max_exit_latency)
  3480. {
  3481. struct xhci_virt_device *virt_dev;
  3482. struct xhci_command *command;
  3483. struct xhci_input_control_ctx *ctrl_ctx;
  3484. struct xhci_slot_ctx *slot_ctx;
  3485. unsigned long flags;
  3486. int ret;
  3487. spin_lock_irqsave(&xhci->lock, flags);
  3488. if (max_exit_latency == xhci->devs[udev->slot_id]->current_mel) {
  3489. spin_unlock_irqrestore(&xhci->lock, flags);
  3490. return 0;
  3491. }
  3492. /* Attempt to issue an Evaluate Context command to change the MEL. */
  3493. virt_dev = xhci->devs[udev->slot_id];
  3494. command = xhci->lpm_command;
  3495. ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx);
  3496. if (!ctrl_ctx) {
  3497. spin_unlock_irqrestore(&xhci->lock, flags);
  3498. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  3499. __func__);
  3500. return -ENOMEM;
  3501. }
  3502. xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
  3503. spin_unlock_irqrestore(&xhci->lock, flags);
  3504. ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
  3505. slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
  3506. slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
  3507. slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
  3508. xhci_dbg(xhci, "Set up evaluate context for LPM MEL change.\n");
  3509. xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
  3510. xhci_dbg_ctx(xhci, command->in_ctx, 0);
  3511. /* Issue and wait for the evaluate context command. */
  3512. ret = xhci_configure_endpoint(xhci, udev, command,
  3513. true, true);
  3514. xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
  3515. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
  3516. if (!ret) {
  3517. spin_lock_irqsave(&xhci->lock, flags);
  3518. virt_dev->current_mel = max_exit_latency;
  3519. spin_unlock_irqrestore(&xhci->lock, flags);
  3520. }
  3521. return ret;
  3522. }
  3523. #ifdef CONFIG_PM_RUNTIME
  3524. /* BESL to HIRD Encoding array for USB2 LPM */
  3525. static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
  3526. 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
  3527. /* Calculate HIRD/BESL for USB2 PORTPMSC*/
  3528. static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
  3529. struct usb_device *udev)
  3530. {
  3531. int u2del, besl, besl_host;
  3532. int besl_device = 0;
  3533. u32 field;
  3534. u2del = HCS_U2_LATENCY(xhci->hcs_params3);
  3535. field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
  3536. if (field & USB_BESL_SUPPORT) {
  3537. for (besl_host = 0; besl_host < 16; besl_host++) {
  3538. if (xhci_besl_encoding[besl_host] >= u2del)
  3539. break;
  3540. }
  3541. /* Use baseline BESL value as default */
  3542. if (field & USB_BESL_BASELINE_VALID)
  3543. besl_device = USB_GET_BESL_BASELINE(field);
  3544. else if (field & USB_BESL_DEEP_VALID)
  3545. besl_device = USB_GET_BESL_DEEP(field);
  3546. } else {
  3547. if (u2del <= 50)
  3548. besl_host = 0;
  3549. else
  3550. besl_host = (u2del - 51) / 75 + 1;
  3551. }
  3552. besl = besl_host + besl_device;
  3553. if (besl > 15)
  3554. besl = 15;
  3555. return besl;
  3556. }
  3557. /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
  3558. static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
  3559. {
  3560. u32 field;
  3561. int l1;
  3562. int besld = 0;
  3563. int hirdm = 0;
  3564. field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
  3565. /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
  3566. l1 = udev->l1_params.timeout / 256;
  3567. /* device has preferred BESLD */
  3568. if (field & USB_BESL_DEEP_VALID) {
  3569. besld = USB_GET_BESL_DEEP(field);
  3570. hirdm = 1;
  3571. }
  3572. return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
  3573. }
  3574. static int xhci_usb2_software_lpm_test(struct usb_hcd *hcd,
  3575. struct usb_device *udev)
  3576. {
  3577. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  3578. struct dev_info *dev_info;
  3579. __le32 __iomem **port_array;
  3580. __le32 __iomem *addr, *pm_addr;
  3581. u32 temp, dev_id;
  3582. unsigned int port_num;
  3583. unsigned long flags;
  3584. int hird;
  3585. int ret;
  3586. if (hcd->speed == HCD_USB3 || !xhci->sw_lpm_support ||
  3587. !udev->lpm_capable)
  3588. return -EINVAL;
  3589. /* we only support lpm for non-hub device connected to root hub yet */
  3590. if (!udev->parent || udev->parent->parent ||
  3591. udev->descriptor.bDeviceClass == USB_CLASS_HUB)
  3592. return -EINVAL;
  3593. spin_lock_irqsave(&xhci->lock, flags);
  3594. /* Look for devices in lpm_failed_devs list */
  3595. dev_id = le16_to_cpu(udev->descriptor.idVendor) << 16 |
  3596. le16_to_cpu(udev->descriptor.idProduct);
  3597. list_for_each_entry(dev_info, &xhci->lpm_failed_devs, list) {
  3598. if (dev_info->dev_id == dev_id) {
  3599. ret = -EINVAL;
  3600. goto finish;
  3601. }
  3602. }
  3603. port_array = xhci->usb2_ports;
  3604. port_num = udev->portnum - 1;
  3605. if (port_num > HCS_MAX_PORTS(xhci->hcs_params1)) {
  3606. xhci_dbg(xhci, "invalid port number %d\n", udev->portnum);
  3607. ret = -EINVAL;
  3608. goto finish;
  3609. }
  3610. /*
  3611. * Test USB 2.0 software LPM.
  3612. * FIXME: some xHCI 1.0 hosts may implement a new register to set up
  3613. * hardware-controlled USB 2.0 LPM. See section 5.4.11 and 4.23.5.1.1.1
  3614. * in the June 2011 errata release.
  3615. */
  3616. xhci_dbg(xhci, "test port %d software LPM\n", port_num);
  3617. /*
  3618. * Set L1 Device Slot and HIRD/BESL.
  3619. * Check device's USB 2.0 extension descriptor to determine whether
  3620. * HIRD or BESL shoule be used. See USB2.0 LPM errata.
  3621. */
  3622. pm_addr = port_array[port_num] + PORTPMSC;
  3623. hird = xhci_calculate_hird_besl(xhci, udev);
  3624. temp = PORT_L1DS(udev->slot_id) | PORT_HIRD(hird);
  3625. xhci_writel(xhci, temp, pm_addr);
  3626. /* Set port link state to U2(L1) */
  3627. addr = port_array[port_num];
  3628. xhci_set_link_state(xhci, port_array, port_num, XDEV_U2);
  3629. /* wait for ACK */
  3630. spin_unlock_irqrestore(&xhci->lock, flags);
  3631. msleep(10);
  3632. spin_lock_irqsave(&xhci->lock, flags);
  3633. /* Check L1 Status */
  3634. ret = xhci_handshake(xhci, pm_addr,
  3635. PORT_L1S_MASK, PORT_L1S_SUCCESS, 125);
  3636. if (ret != -ETIMEDOUT) {
  3637. /* enter L1 successfully */
  3638. temp = xhci_readl(xhci, addr);
  3639. xhci_dbg(xhci, "port %d entered L1 state, port status 0x%x\n",
  3640. port_num, temp);
  3641. ret = 0;
  3642. } else {
  3643. temp = xhci_readl(xhci, pm_addr);
  3644. xhci_dbg(xhci, "port %d software lpm failed, L1 status %d\n",
  3645. port_num, temp & PORT_L1S_MASK);
  3646. ret = -EINVAL;
  3647. }
  3648. /* Resume the port */
  3649. xhci_set_link_state(xhci, port_array, port_num, XDEV_U0);
  3650. spin_unlock_irqrestore(&xhci->lock, flags);
  3651. msleep(10);
  3652. spin_lock_irqsave(&xhci->lock, flags);
  3653. /* Clear PLC */
  3654. xhci_test_and_clear_bit(xhci, port_array, port_num, PORT_PLC);
  3655. /* Check PORTSC to make sure the device is in the right state */
  3656. if (!ret) {
  3657. temp = xhci_readl(xhci, addr);
  3658. xhci_dbg(xhci, "resumed port %d status 0x%x\n", port_num, temp);
  3659. if (!(temp & PORT_CONNECT) || !(temp & PORT_PE) ||
  3660. (temp & PORT_PLS_MASK) != XDEV_U0) {
  3661. xhci_dbg(xhci, "port L1 resume fail\n");
  3662. ret = -EINVAL;
  3663. }
  3664. }
  3665. if (ret) {
  3666. /* Insert dev to lpm_failed_devs list */
  3667. xhci_warn(xhci, "device LPM test failed, may disconnect and "
  3668. "re-enumerate\n");
  3669. dev_info = kzalloc(sizeof(struct dev_info), GFP_ATOMIC);
  3670. if (!dev_info) {
  3671. ret = -ENOMEM;
  3672. goto finish;
  3673. }
  3674. dev_info->dev_id = dev_id;
  3675. INIT_LIST_HEAD(&dev_info->list);
  3676. list_add(&dev_info->list, &xhci->lpm_failed_devs);
  3677. } else {
  3678. xhci_ring_device(xhci, udev->slot_id);
  3679. }
  3680. finish:
  3681. spin_unlock_irqrestore(&xhci->lock, flags);
  3682. return ret;
  3683. }
  3684. int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
  3685. struct usb_device *udev, int enable)
  3686. {
  3687. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  3688. __le32 __iomem **port_array;
  3689. __le32 __iomem *pm_addr, *hlpm_addr;
  3690. u32 pm_val, hlpm_val, field;
  3691. unsigned int port_num;
  3692. unsigned long flags;
  3693. int hird, exit_latency;
  3694. int ret;
  3695. if (hcd->speed == HCD_USB3 || !xhci->hw_lpm_support ||
  3696. !udev->lpm_capable)
  3697. return -EPERM;
  3698. if (!udev->parent || udev->parent->parent ||
  3699. udev->descriptor.bDeviceClass == USB_CLASS_HUB)
  3700. return -EPERM;
  3701. if (udev->usb2_hw_lpm_capable != 1)
  3702. return -EPERM;
  3703. spin_lock_irqsave(&xhci->lock, flags);
  3704. port_array = xhci->usb2_ports;
  3705. port_num = udev->portnum - 1;
  3706. pm_addr = port_array[port_num] + PORTPMSC;
  3707. pm_val = xhci_readl(xhci, pm_addr);
  3708. hlpm_addr = port_array[port_num] + PORTHLPMC;
  3709. field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
  3710. xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
  3711. enable ? "enable" : "disable", port_num);
  3712. if (enable) {
  3713. /* Host supports BESL timeout instead of HIRD */
  3714. if (udev->usb2_hw_lpm_besl_capable) {
  3715. /* if device doesn't have a preferred BESL value use a
  3716. * default one which works with mixed HIRD and BESL
  3717. * systems. See XHCI_DEFAULT_BESL definition in xhci.h
  3718. */
  3719. if ((field & USB_BESL_SUPPORT) &&
  3720. (field & USB_BESL_BASELINE_VALID))
  3721. hird = USB_GET_BESL_BASELINE(field);
  3722. else
  3723. hird = udev->l1_params.besl;
  3724. exit_latency = xhci_besl_encoding[hird];
  3725. spin_unlock_irqrestore(&xhci->lock, flags);
  3726. /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
  3727. * input context for link powermanagement evaluate
  3728. * context commands. It is protected by hcd->bandwidth
  3729. * mutex and is shared by all devices. We need to set
  3730. * the max ext latency in USB 2 BESL LPM as well, so
  3731. * use the same mutex and xhci_change_max_exit_latency()
  3732. */
  3733. mutex_lock(hcd->bandwidth_mutex);
  3734. ret = xhci_change_max_exit_latency(xhci, udev,
  3735. exit_latency);
  3736. mutex_unlock(hcd->bandwidth_mutex);
  3737. if (ret < 0)
  3738. return ret;
  3739. spin_lock_irqsave(&xhci->lock, flags);
  3740. hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
  3741. xhci_writel(xhci, hlpm_val, hlpm_addr);
  3742. /* flush write */
  3743. xhci_readl(xhci, hlpm_addr);
  3744. } else {
  3745. hird = xhci_calculate_hird_besl(xhci, udev);
  3746. }
  3747. pm_val &= ~PORT_HIRD_MASK;
  3748. pm_val |= PORT_HIRD(hird) | PORT_RWE;
  3749. xhci_writel(xhci, pm_val, pm_addr);
  3750. pm_val = xhci_readl(xhci, pm_addr);
  3751. pm_val |= PORT_HLE;
  3752. xhci_writel(xhci, pm_val, pm_addr);
  3753. /* flush write */
  3754. xhci_readl(xhci, pm_addr);
  3755. } else {
  3756. pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK);
  3757. xhci_writel(xhci, pm_val, pm_addr);
  3758. /* flush write */
  3759. xhci_readl(xhci, pm_addr);
  3760. if (udev->usb2_hw_lpm_besl_capable) {
  3761. spin_unlock_irqrestore(&xhci->lock, flags);
  3762. mutex_lock(hcd->bandwidth_mutex);
  3763. xhci_change_max_exit_latency(xhci, udev, 0);
  3764. mutex_unlock(hcd->bandwidth_mutex);
  3765. return 0;
  3766. }
  3767. }
  3768. spin_unlock_irqrestore(&xhci->lock, flags);
  3769. return 0;
  3770. }
  3771. /* check if a usb2 port supports a given extened capability protocol
  3772. * only USB2 ports extended protocol capability values are cached.
  3773. * Return 1 if capability is supported
  3774. */
  3775. static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
  3776. unsigned capability)
  3777. {
  3778. u32 port_offset, port_count;
  3779. int i;
  3780. for (i = 0; i < xhci->num_ext_caps; i++) {
  3781. if (xhci->ext_caps[i] & capability) {
  3782. /* port offsets starts at 1 */
  3783. port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
  3784. port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
  3785. if (port >= port_offset &&
  3786. port < port_offset + port_count)
  3787. return 1;
  3788. }
  3789. }
  3790. return 0;
  3791. }
  3792. int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
  3793. {
  3794. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  3795. int ret;
  3796. int portnum = udev->portnum - 1;
  3797. ret = xhci_usb2_software_lpm_test(hcd, udev);
  3798. if (!ret) {
  3799. xhci_dbg(xhci, "software LPM test succeed\n");
  3800. if (xhci->hw_lpm_support == 1 &&
  3801. xhci_check_usb2_port_capability(xhci, portnum, XHCI_HLC)) {
  3802. udev->usb2_hw_lpm_capable = 1;
  3803. udev->l1_params.timeout = XHCI_L1_TIMEOUT;
  3804. udev->l1_params.besl = XHCI_DEFAULT_BESL;
  3805. if (xhci_check_usb2_port_capability(xhci, portnum,
  3806. XHCI_BLC))
  3807. udev->usb2_hw_lpm_besl_capable = 1;
  3808. ret = xhci_set_usb2_hardware_lpm(hcd, udev, 1);
  3809. if (!ret)
  3810. udev->usb2_hw_lpm_enabled = 1;
  3811. }
  3812. }
  3813. return 0;
  3814. }
  3815. #else
  3816. int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
  3817. struct usb_device *udev, int enable)
  3818. {
  3819. return 0;
  3820. }
  3821. int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
  3822. {
  3823. return 0;
  3824. }
  3825. #endif /* CONFIG_PM_RUNTIME */
  3826. /*---------------------- USB 3.0 Link PM functions ------------------------*/
  3827. #ifdef CONFIG_PM
  3828. /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
  3829. static unsigned long long xhci_service_interval_to_ns(
  3830. struct usb_endpoint_descriptor *desc)
  3831. {
  3832. return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
  3833. }
  3834. static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
  3835. enum usb3_link_state state)
  3836. {
  3837. unsigned long long sel;
  3838. unsigned long long pel;
  3839. unsigned int max_sel_pel;
  3840. char *state_name;
  3841. switch (state) {
  3842. case USB3_LPM_U1:
  3843. /* Convert SEL and PEL stored in nanoseconds to microseconds */
  3844. sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
  3845. pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
  3846. max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
  3847. state_name = "U1";
  3848. break;
  3849. case USB3_LPM_U2:
  3850. sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
  3851. pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
  3852. max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
  3853. state_name = "U2";
  3854. break;
  3855. default:
  3856. dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
  3857. __func__);
  3858. return USB3_LPM_DISABLED;
  3859. }
  3860. if (sel <= max_sel_pel && pel <= max_sel_pel)
  3861. return USB3_LPM_DEVICE_INITIATED;
  3862. if (sel > max_sel_pel)
  3863. dev_dbg(&udev->dev, "Device-initiated %s disabled "
  3864. "due to long SEL %llu ms\n",
  3865. state_name, sel);
  3866. else
  3867. dev_dbg(&udev->dev, "Device-initiated %s disabled "
  3868. "due to long PEL %llu ms\n",
  3869. state_name, pel);
  3870. return USB3_LPM_DISABLED;
  3871. }
  3872. /* Returns the hub-encoded U1 timeout value.
  3873. * The U1 timeout should be the maximum of the following values:
  3874. * - For control endpoints, U1 system exit latency (SEL) * 3
  3875. * - For bulk endpoints, U1 SEL * 5
  3876. * - For interrupt endpoints:
  3877. * - Notification EPs, U1 SEL * 3
  3878. * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
  3879. * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
  3880. */
  3881. static u16 xhci_calculate_intel_u1_timeout(struct usb_device *udev,
  3882. struct usb_endpoint_descriptor *desc)
  3883. {
  3884. unsigned long long timeout_ns;
  3885. int ep_type;
  3886. int intr_type;
  3887. ep_type = usb_endpoint_type(desc);
  3888. switch (ep_type) {
  3889. case USB_ENDPOINT_XFER_CONTROL:
  3890. timeout_ns = udev->u1_params.sel * 3;
  3891. break;
  3892. case USB_ENDPOINT_XFER_BULK:
  3893. timeout_ns = udev->u1_params.sel * 5;
  3894. break;
  3895. case USB_ENDPOINT_XFER_INT:
  3896. intr_type = usb_endpoint_interrupt_type(desc);
  3897. if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
  3898. timeout_ns = udev->u1_params.sel * 3;
  3899. break;
  3900. }
  3901. /* Otherwise the calculation is the same as isoc eps */
  3902. case USB_ENDPOINT_XFER_ISOC:
  3903. timeout_ns = xhci_service_interval_to_ns(desc);
  3904. timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
  3905. if (timeout_ns < udev->u1_params.sel * 2)
  3906. timeout_ns = udev->u1_params.sel * 2;
  3907. break;
  3908. default:
  3909. return 0;
  3910. }
  3911. /* The U1 timeout is encoded in 1us intervals. */
  3912. timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
  3913. /* Don't return a timeout of zero, because that's USB3_LPM_DISABLED. */
  3914. if (timeout_ns == USB3_LPM_DISABLED)
  3915. timeout_ns++;
  3916. /* If the necessary timeout value is bigger than what we can set in the
  3917. * USB 3.0 hub, we have to disable hub-initiated U1.
  3918. */
  3919. if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
  3920. return timeout_ns;
  3921. dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
  3922. "due to long timeout %llu ms\n", timeout_ns);
  3923. return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
  3924. }
  3925. /* Returns the hub-encoded U2 timeout value.
  3926. * The U2 timeout should be the maximum of:
  3927. * - 10 ms (to avoid the bandwidth impact on the scheduler)
  3928. * - largest bInterval of any active periodic endpoint (to avoid going
  3929. * into lower power link states between intervals).
  3930. * - the U2 Exit Latency of the device
  3931. */
  3932. static u16 xhci_calculate_intel_u2_timeout(struct usb_device *udev,
  3933. struct usb_endpoint_descriptor *desc)
  3934. {
  3935. unsigned long long timeout_ns;
  3936. unsigned long long u2_del_ns;
  3937. timeout_ns = 10 * 1000 * 1000;
  3938. if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
  3939. (xhci_service_interval_to_ns(desc) > timeout_ns))
  3940. timeout_ns = xhci_service_interval_to_ns(desc);
  3941. u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
  3942. if (u2_del_ns > timeout_ns)
  3943. timeout_ns = u2_del_ns;
  3944. /* The U2 timeout is encoded in 256us intervals */
  3945. timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
  3946. /* If the necessary timeout value is bigger than what we can set in the
  3947. * USB 3.0 hub, we have to disable hub-initiated U2.
  3948. */
  3949. if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
  3950. return timeout_ns;
  3951. dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
  3952. "due to long timeout %llu ms\n", timeout_ns);
  3953. return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
  3954. }
  3955. static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
  3956. struct usb_device *udev,
  3957. struct usb_endpoint_descriptor *desc,
  3958. enum usb3_link_state state,
  3959. u16 *timeout)
  3960. {
  3961. if (state == USB3_LPM_U1) {
  3962. if (xhci->quirks & XHCI_INTEL_HOST)
  3963. return xhci_calculate_intel_u1_timeout(udev, desc);
  3964. } else {
  3965. if (xhci->quirks & XHCI_INTEL_HOST)
  3966. return xhci_calculate_intel_u2_timeout(udev, desc);
  3967. }
  3968. return USB3_LPM_DISABLED;
  3969. }
  3970. static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
  3971. struct usb_device *udev,
  3972. struct usb_endpoint_descriptor *desc,
  3973. enum usb3_link_state state,
  3974. u16 *timeout)
  3975. {
  3976. u16 alt_timeout;
  3977. alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
  3978. desc, state, timeout);
  3979. /* If we found we can't enable hub-initiated LPM, or
  3980. * the U1 or U2 exit latency was too high to allow
  3981. * device-initiated LPM as well, just stop searching.
  3982. */
  3983. if (alt_timeout == USB3_LPM_DISABLED ||
  3984. alt_timeout == USB3_LPM_DEVICE_INITIATED) {
  3985. *timeout = alt_timeout;
  3986. return -E2BIG;
  3987. }
  3988. if (alt_timeout > *timeout)
  3989. *timeout = alt_timeout;
  3990. return 0;
  3991. }
  3992. static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
  3993. struct usb_device *udev,
  3994. struct usb_host_interface *alt,
  3995. enum usb3_link_state state,
  3996. u16 *timeout)
  3997. {
  3998. int j;
  3999. for (j = 0; j < alt->desc.bNumEndpoints; j++) {
  4000. if (xhci_update_timeout_for_endpoint(xhci, udev,
  4001. &alt->endpoint[j].desc, state, timeout))
  4002. return -E2BIG;
  4003. continue;
  4004. }
  4005. return 0;
  4006. }
  4007. static int xhci_check_intel_tier_policy(struct usb_device *udev,
  4008. enum usb3_link_state state)
  4009. {
  4010. struct usb_device *parent;
  4011. unsigned int num_hubs;
  4012. if (state == USB3_LPM_U2)
  4013. return 0;
  4014. /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
  4015. for (parent = udev->parent, num_hubs = 0; parent->parent;
  4016. parent = parent->parent)
  4017. num_hubs++;
  4018. if (num_hubs < 2)
  4019. return 0;
  4020. dev_dbg(&udev->dev, "Disabling U1 link state for device"
  4021. " below second-tier hub.\n");
  4022. dev_dbg(&udev->dev, "Plug device into first-tier hub "
  4023. "to decrease power consumption.\n");
  4024. return -E2BIG;
  4025. }
  4026. static int xhci_check_tier_policy(struct xhci_hcd *xhci,
  4027. struct usb_device *udev,
  4028. enum usb3_link_state state)
  4029. {
  4030. if (xhci->quirks & XHCI_INTEL_HOST)
  4031. return xhci_check_intel_tier_policy(udev, state);
  4032. return -EINVAL;
  4033. }
  4034. /* Returns the U1 or U2 timeout that should be enabled.
  4035. * If the tier check or timeout setting functions return with a non-zero exit
  4036. * code, that means the timeout value has been finalized and we shouldn't look
  4037. * at any more endpoints.
  4038. */
  4039. static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
  4040. struct usb_device *udev, enum usb3_link_state state)
  4041. {
  4042. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  4043. struct usb_host_config *config;
  4044. char *state_name;
  4045. int i;
  4046. u16 timeout = USB3_LPM_DISABLED;
  4047. if (state == USB3_LPM_U1)
  4048. state_name = "U1";
  4049. else if (state == USB3_LPM_U2)
  4050. state_name = "U2";
  4051. else {
  4052. dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
  4053. state);
  4054. return timeout;
  4055. }
  4056. if (xhci_check_tier_policy(xhci, udev, state) < 0)
  4057. return timeout;
  4058. /* Gather some information about the currently installed configuration
  4059. * and alternate interface settings.
  4060. */
  4061. if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
  4062. state, &timeout))
  4063. return timeout;
  4064. config = udev->actconfig;
  4065. if (!config)
  4066. return timeout;
  4067. for (i = 0; i < USB_MAXINTERFACES; i++) {
  4068. struct usb_driver *driver;
  4069. struct usb_interface *intf = config->interface[i];
  4070. if (!intf)
  4071. continue;
  4072. /* Check if any currently bound drivers want hub-initiated LPM
  4073. * disabled.
  4074. */
  4075. if (intf->dev.driver) {
  4076. driver = to_usb_driver(intf->dev.driver);
  4077. if (driver && driver->disable_hub_initiated_lpm) {
  4078. dev_dbg(&udev->dev, "Hub-initiated %s disabled "
  4079. "at request of driver %s\n",
  4080. state_name, driver->name);
  4081. return xhci_get_timeout_no_hub_lpm(udev, state);
  4082. }
  4083. }
  4084. /* Not sure how this could happen... */
  4085. if (!intf->cur_altsetting)
  4086. continue;
  4087. if (xhci_update_timeout_for_interface(xhci, udev,
  4088. intf->cur_altsetting,
  4089. state, &timeout))
  4090. return timeout;
  4091. }
  4092. return timeout;
  4093. }
  4094. static int calculate_max_exit_latency(struct usb_device *udev,
  4095. enum usb3_link_state state_changed,
  4096. u16 hub_encoded_timeout)
  4097. {
  4098. unsigned long long u1_mel_us = 0;
  4099. unsigned long long u2_mel_us = 0;
  4100. unsigned long long mel_us = 0;
  4101. bool disabling_u1;
  4102. bool disabling_u2;
  4103. bool enabling_u1;
  4104. bool enabling_u2;
  4105. disabling_u1 = (state_changed == USB3_LPM_U1 &&
  4106. hub_encoded_timeout == USB3_LPM_DISABLED);
  4107. disabling_u2 = (state_changed == USB3_LPM_U2 &&
  4108. hub_encoded_timeout == USB3_LPM_DISABLED);
  4109. enabling_u1 = (state_changed == USB3_LPM_U1 &&
  4110. hub_encoded_timeout != USB3_LPM_DISABLED);
  4111. enabling_u2 = (state_changed == USB3_LPM_U2 &&
  4112. hub_encoded_timeout != USB3_LPM_DISABLED);
  4113. /* If U1 was already enabled and we're not disabling it,
  4114. * or we're going to enable U1, account for the U1 max exit latency.
  4115. */
  4116. if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
  4117. enabling_u1)
  4118. u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
  4119. if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
  4120. enabling_u2)
  4121. u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
  4122. if (u1_mel_us > u2_mel_us)
  4123. mel_us = u1_mel_us;
  4124. else
  4125. mel_us = u2_mel_us;
  4126. /* xHCI host controller max exit latency field is only 16 bits wide. */
  4127. if (mel_us > MAX_EXIT) {
  4128. dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
  4129. "is too big.\n", mel_us);
  4130. return -E2BIG;
  4131. }
  4132. return mel_us;
  4133. }
  4134. /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
  4135. int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
  4136. struct usb_device *udev, enum usb3_link_state state)
  4137. {
  4138. struct xhci_hcd *xhci;
  4139. u16 hub_encoded_timeout;
  4140. int mel;
  4141. int ret;
  4142. xhci = hcd_to_xhci(hcd);
  4143. /* The LPM timeout values are pretty host-controller specific, so don't
  4144. * enable hub-initiated timeouts unless the vendor has provided
  4145. * information about their timeout algorithm.
  4146. */
  4147. if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
  4148. !xhci->devs[udev->slot_id])
  4149. return USB3_LPM_DISABLED;
  4150. hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
  4151. mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
  4152. if (mel < 0) {
  4153. /* Max Exit Latency is too big, disable LPM. */
  4154. hub_encoded_timeout = USB3_LPM_DISABLED;
  4155. mel = 0;
  4156. }
  4157. ret = xhci_change_max_exit_latency(xhci, udev, mel);
  4158. if (ret)
  4159. return ret;
  4160. return hub_encoded_timeout;
  4161. }
  4162. int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
  4163. struct usb_device *udev, enum usb3_link_state state)
  4164. {
  4165. struct xhci_hcd *xhci;
  4166. u16 mel;
  4167. int ret;
  4168. xhci = hcd_to_xhci(hcd);
  4169. if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
  4170. !xhci->devs[udev->slot_id])
  4171. return 0;
  4172. mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
  4173. ret = xhci_change_max_exit_latency(xhci, udev, mel);
  4174. if (ret)
  4175. return ret;
  4176. return 0;
  4177. }
  4178. #else /* CONFIG_PM */
  4179. int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
  4180. struct usb_device *udev, enum usb3_link_state state)
  4181. {
  4182. return USB3_LPM_DISABLED;
  4183. }
  4184. int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
  4185. struct usb_device *udev, enum usb3_link_state state)
  4186. {
  4187. return 0;
  4188. }
  4189. #endif /* CONFIG_PM */
  4190. /*-------------------------------------------------------------------------*/
  4191. /* Once a hub descriptor is fetched for a device, we need to update the xHC's
  4192. * internal data structures for the device.
  4193. */
  4194. int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
  4195. struct usb_tt *tt, gfp_t mem_flags)
  4196. {
  4197. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  4198. struct xhci_virt_device *vdev;
  4199. struct xhci_command *config_cmd;
  4200. struct xhci_input_control_ctx *ctrl_ctx;
  4201. struct xhci_slot_ctx *slot_ctx;
  4202. unsigned long flags;
  4203. unsigned think_time;
  4204. int ret;
  4205. /* Ignore root hubs */
  4206. if (!hdev->parent)
  4207. return 0;
  4208. vdev = xhci->devs[hdev->slot_id];
  4209. if (!vdev) {
  4210. xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
  4211. return -EINVAL;
  4212. }
  4213. config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
  4214. if (!config_cmd) {
  4215. xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
  4216. return -ENOMEM;
  4217. }
  4218. ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
  4219. if (!ctrl_ctx) {
  4220. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  4221. __func__);
  4222. xhci_free_command(xhci, config_cmd);
  4223. return -ENOMEM;
  4224. }
  4225. spin_lock_irqsave(&xhci->lock, flags);
  4226. if (hdev->speed == USB_SPEED_HIGH &&
  4227. xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
  4228. xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
  4229. xhci_free_command(xhci, config_cmd);
  4230. spin_unlock_irqrestore(&xhci->lock, flags);
  4231. return -ENOMEM;
  4232. }
  4233. xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
  4234. ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
  4235. slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
  4236. slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
  4237. if (tt->multi)
  4238. slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
  4239. if (xhci->hci_version > 0x95) {
  4240. xhci_dbg(xhci, "xHCI version %x needs hub "
  4241. "TT think time and number of ports\n",
  4242. (unsigned int) xhci->hci_version);
  4243. slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
  4244. /* Set TT think time - convert from ns to FS bit times.
  4245. * 0 = 8 FS bit times, 1 = 16 FS bit times,
  4246. * 2 = 24 FS bit times, 3 = 32 FS bit times.
  4247. *
  4248. * xHCI 1.0: this field shall be 0 if the device is not a
  4249. * High-spped hub.
  4250. */
  4251. think_time = tt->think_time;
  4252. if (think_time != 0)
  4253. think_time = (think_time / 666) - 1;
  4254. if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
  4255. slot_ctx->tt_info |=
  4256. cpu_to_le32(TT_THINK_TIME(think_time));
  4257. } else {
  4258. xhci_dbg(xhci, "xHCI version %x doesn't need hub "
  4259. "TT think time or number of ports\n",
  4260. (unsigned int) xhci->hci_version);
  4261. }
  4262. slot_ctx->dev_state = 0;
  4263. spin_unlock_irqrestore(&xhci->lock, flags);
  4264. xhci_dbg(xhci, "Set up %s for hub device.\n",
  4265. (xhci->hci_version > 0x95) ?
  4266. "configure endpoint" : "evaluate context");
  4267. xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
  4268. xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
  4269. /* Issue and wait for the configure endpoint or
  4270. * evaluate context command.
  4271. */
  4272. if (xhci->hci_version > 0x95)
  4273. ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
  4274. false, false);
  4275. else
  4276. ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
  4277. true, false);
  4278. xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
  4279. xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
  4280. xhci_free_command(xhci, config_cmd);
  4281. return ret;
  4282. }
  4283. int xhci_get_frame(struct usb_hcd *hcd)
  4284. {
  4285. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  4286. /* EHCI mods by the periodic size. Why? */
  4287. return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
  4288. }
  4289. int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
  4290. {
  4291. struct xhci_hcd *xhci;
  4292. struct device *dev = hcd->self.controller;
  4293. int retval;
  4294. u32 temp;
  4295. /* Accept arbitrarily long scatter-gather lists */
  4296. hcd->self.sg_tablesize = ~0;
  4297. /* XHCI controllers don't stop the ep queue on short packets :| */
  4298. hcd->self.no_stop_on_short = 1;
  4299. if (usb_hcd_is_primary_hcd(hcd)) {
  4300. xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
  4301. if (!xhci)
  4302. return -ENOMEM;
  4303. *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
  4304. xhci->main_hcd = hcd;
  4305. /* Mark the first roothub as being USB 2.0.
  4306. * The xHCI driver will register the USB 3.0 roothub.
  4307. */
  4308. hcd->speed = HCD_USB2;
  4309. hcd->self.root_hub->speed = USB_SPEED_HIGH;
  4310. /*
  4311. * USB 2.0 roothub under xHCI has an integrated TT,
  4312. * (rate matching hub) as opposed to having an OHCI/UHCI
  4313. * companion controller.
  4314. */
  4315. hcd->has_tt = 1;
  4316. } else {
  4317. /* xHCI private pointer was set in xhci_pci_probe for the second
  4318. * registered roothub.
  4319. */
  4320. xhci = hcd_to_xhci(hcd);
  4321. temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
  4322. if (HCC_64BIT_ADDR(temp)) {
  4323. xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
  4324. dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
  4325. } else {
  4326. dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
  4327. }
  4328. return 0;
  4329. }
  4330. xhci->cap_regs = hcd->regs;
  4331. xhci->op_regs = hcd->regs +
  4332. HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
  4333. xhci->run_regs = hcd->regs +
  4334. (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
  4335. /* Cache read-only capability registers */
  4336. xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
  4337. xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
  4338. xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
  4339. xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
  4340. xhci->hci_version = HC_VERSION(xhci->hcc_params);
  4341. xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
  4342. xhci_print_registers(xhci);
  4343. get_quirks(dev, xhci);
  4344. /* Make sure the HC is halted. */
  4345. retval = xhci_halt(xhci);
  4346. if (retval)
  4347. goto error;
  4348. xhci_dbg(xhci, "Resetting HCD\n");
  4349. /* Reset the internal HC memory state and registers. */
  4350. retval = xhci_reset(xhci);
  4351. if (retval)
  4352. goto error;
  4353. xhci_dbg(xhci, "Reset complete\n");
  4354. temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
  4355. if (HCC_64BIT_ADDR(temp)) {
  4356. xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
  4357. dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
  4358. } else {
  4359. dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
  4360. }
  4361. xhci_dbg(xhci, "Calling HCD init\n");
  4362. /* Initialize HCD and host controller data structures. */
  4363. retval = xhci_init(hcd);
  4364. if (retval)
  4365. goto error;
  4366. xhci_dbg(xhci, "Called HCD init\n");
  4367. return 0;
  4368. error:
  4369. kfree(xhci);
  4370. return retval;
  4371. }
  4372. MODULE_DESCRIPTION(DRIVER_DESC);
  4373. MODULE_AUTHOR(DRIVER_AUTHOR);
  4374. MODULE_LICENSE("GPL");
  4375. static int __init xhci_hcd_init(void)
  4376. {
  4377. int retval;
  4378. retval = xhci_register_pci();
  4379. if (retval < 0) {
  4380. printk(KERN_DEBUG "Problem registering PCI driver.");
  4381. return retval;
  4382. }
  4383. retval = xhci_register_plat();
  4384. if (retval < 0) {
  4385. printk(KERN_DEBUG "Problem registering platform driver.");
  4386. goto unreg_pci;
  4387. }
  4388. /*
  4389. * Check the compiler generated sizes of structures that must be laid
  4390. * out in specific ways for hardware access.
  4391. */
  4392. BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
  4393. BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
  4394. BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
  4395. /* xhci_device_control has eight fields, and also
  4396. * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
  4397. */
  4398. BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
  4399. BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
  4400. BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
  4401. BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
  4402. BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
  4403. /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
  4404. BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
  4405. return 0;
  4406. unreg_pci:
  4407. xhci_unregister_pci();
  4408. return retval;
  4409. }
  4410. module_init(xhci_hcd_init);
  4411. static void __exit xhci_hcd_cleanup(void)
  4412. {
  4413. xhci_unregister_pci();
  4414. xhci_unregister_plat();
  4415. }
  4416. module_exit(xhci_hcd_cleanup);