xhci-hub.c 36 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/gfp.h>
  23. #include <asm/unaligned.h>
  24. #include "xhci.h"
  25. #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  26. #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  27. PORT_RC | PORT_PLC | PORT_PE)
  28. /* USB 3.0 BOS descriptor and a capability descriptor, combined */
  29. static u8 usb_bos_descriptor [] = {
  30. USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
  31. USB_DT_BOS, /* __u8 bDescriptorType */
  32. 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
  33. 0x1, /* __u8 bNumDeviceCaps */
  34. /* First device capability */
  35. USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
  36. USB_DT_DEVICE_CAPABILITY, /* Device Capability */
  37. USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
  38. 0x00, /* bmAttributes, LTM off by default */
  39. USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
  40. 0x03, /* bFunctionalitySupport,
  41. USB 3.0 speed only */
  42. 0x00, /* bU1DevExitLat, set later. */
  43. 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
  44. };
  45. static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
  46. struct usb_hub_descriptor *desc, int ports)
  47. {
  48. u16 temp;
  49. desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
  50. desc->bHubContrCurrent = 0;
  51. desc->bNbrPorts = ports;
  52. temp = 0;
  53. /* Bits 1:0 - support per-port power switching, or power always on */
  54. if (HCC_PPC(xhci->hcc_params))
  55. temp |= HUB_CHAR_INDV_PORT_LPSM;
  56. else
  57. temp |= HUB_CHAR_NO_LPSM;
  58. /* Bit 2 - root hubs are not part of a compound device */
  59. /* Bits 4:3 - individual port over current protection */
  60. temp |= HUB_CHAR_INDV_PORT_OCPM;
  61. /* Bits 6:5 - no TTs in root ports */
  62. /* Bit 7 - no port indicators */
  63. desc->wHubCharacteristics = cpu_to_le16(temp);
  64. }
  65. /* Fill in the USB 2.0 roothub descriptor */
  66. static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  67. struct usb_hub_descriptor *desc)
  68. {
  69. int ports;
  70. u16 temp;
  71. __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
  72. u32 portsc;
  73. unsigned int i;
  74. ports = xhci->num_usb2_ports;
  75. xhci_common_hub_descriptor(xhci, desc, ports);
  76. desc->bDescriptorType = USB_DT_HUB;
  77. temp = 1 + (ports / 8);
  78. desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
  79. /* The Device Removable bits are reported on a byte granularity.
  80. * If the port doesn't exist within that byte, the bit is set to 0.
  81. */
  82. memset(port_removable, 0, sizeof(port_removable));
  83. for (i = 0; i < ports; i++) {
  84. portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
  85. /* If a device is removable, PORTSC reports a 0, same as in the
  86. * hub descriptor DeviceRemovable bits.
  87. */
  88. if (portsc & PORT_DEV_REMOVE)
  89. /* This math is hairy because bit 0 of DeviceRemovable
  90. * is reserved, and bit 1 is for port 1, etc.
  91. */
  92. port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
  93. }
  94. /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
  95. * ports on it. The USB 2.0 specification says that there are two
  96. * variable length fields at the end of the hub descriptor:
  97. * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
  98. * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
  99. * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
  100. * 0xFF, so we initialize the both arrays (DeviceRemovable and
  101. * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
  102. * set of ports that actually exist.
  103. */
  104. memset(desc->u.hs.DeviceRemovable, 0xff,
  105. sizeof(desc->u.hs.DeviceRemovable));
  106. memset(desc->u.hs.PortPwrCtrlMask, 0xff,
  107. sizeof(desc->u.hs.PortPwrCtrlMask));
  108. for (i = 0; i < (ports + 1 + 7) / 8; i++)
  109. memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
  110. sizeof(__u8));
  111. }
  112. /* Fill in the USB 3.0 roothub descriptor */
  113. static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  114. struct usb_hub_descriptor *desc)
  115. {
  116. int ports;
  117. u16 port_removable;
  118. u32 portsc;
  119. unsigned int i;
  120. ports = xhci->num_usb3_ports;
  121. xhci_common_hub_descriptor(xhci, desc, ports);
  122. desc->bDescriptorType = USB_DT_SS_HUB;
  123. desc->bDescLength = USB_DT_SS_HUB_SIZE;
  124. /* header decode latency should be zero for roothubs,
  125. * see section 4.23.5.2.
  126. */
  127. desc->u.ss.bHubHdrDecLat = 0;
  128. desc->u.ss.wHubDelay = 0;
  129. port_removable = 0;
  130. /* bit 0 is reserved, bit 1 is for port 1, etc. */
  131. for (i = 0; i < ports; i++) {
  132. portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
  133. if (portsc & PORT_DEV_REMOVE)
  134. port_removable |= 1 << (i + 1);
  135. }
  136. desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
  137. }
  138. static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  139. struct usb_hub_descriptor *desc)
  140. {
  141. if (hcd->speed == HCD_USB3)
  142. xhci_usb3_hub_descriptor(hcd, xhci, desc);
  143. else
  144. xhci_usb2_hub_descriptor(hcd, xhci, desc);
  145. }
  146. static unsigned int xhci_port_speed(unsigned int port_status)
  147. {
  148. if (DEV_LOWSPEED(port_status))
  149. return USB_PORT_STAT_LOW_SPEED;
  150. if (DEV_HIGHSPEED(port_status))
  151. return USB_PORT_STAT_HIGH_SPEED;
  152. /*
  153. * FIXME: Yes, we should check for full speed, but the core uses that as
  154. * a default in portspeed() in usb/core/hub.c (which is the only place
  155. * USB_PORT_STAT_*_SPEED is used).
  156. */
  157. return 0;
  158. }
  159. /*
  160. * These bits are Read Only (RO) and should be saved and written to the
  161. * registers: 0, 3, 10:13, 30
  162. * connect status, over-current status, port speed, and device removable.
  163. * connect status and port speed are also sticky - meaning they're in
  164. * the AUX well and they aren't changed by a hot, warm, or cold reset.
  165. */
  166. #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
  167. /*
  168. * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
  169. * bits 5:8, 9, 14:15, 25:27
  170. * link state, port power, port indicator state, "wake on" enable state
  171. */
  172. #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
  173. /*
  174. * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
  175. * bit 4 (port reset)
  176. */
  177. #define XHCI_PORT_RW1S ((1<<4))
  178. /*
  179. * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
  180. * bits 1, 17, 18, 19, 20, 21, 22, 23
  181. * port enable/disable, and
  182. * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
  183. * over-current, reset, link state, and L1 change
  184. */
  185. #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
  186. /*
  187. * Bit 16 is RW, and writing a '1' to it causes the link state control to be
  188. * latched in
  189. */
  190. #define XHCI_PORT_RW ((1<<16))
  191. /*
  192. * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
  193. * bits 2, 24, 28:31
  194. */
  195. #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
  196. /*
  197. * Given a port state, this function returns a value that would result in the
  198. * port being in the same state, if the value was written to the port status
  199. * control register.
  200. * Save Read Only (RO) bits and save read/write bits where
  201. * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
  202. * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
  203. */
  204. u32 xhci_port_state_to_neutral(u32 state)
  205. {
  206. /* Save read-only status and port state */
  207. return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
  208. }
  209. /*
  210. * find slot id based on port number.
  211. * @port: The one-based port number from one of the two split roothubs.
  212. */
  213. int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  214. u16 port)
  215. {
  216. int slot_id;
  217. int i;
  218. enum usb_device_speed speed;
  219. slot_id = 0;
  220. for (i = 0; i < MAX_HC_SLOTS; i++) {
  221. if (!xhci->devs[i])
  222. continue;
  223. speed = xhci->devs[i]->udev->speed;
  224. if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
  225. && xhci->devs[i]->fake_port == port) {
  226. slot_id = i;
  227. break;
  228. }
  229. }
  230. return slot_id;
  231. }
  232. /*
  233. * Stop device
  234. * It issues stop endpoint command for EP 0 to 30. And wait the last command
  235. * to complete.
  236. * suspend will set to 1, if suspend bit need to set in command.
  237. */
  238. static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
  239. {
  240. struct xhci_virt_device *virt_dev;
  241. struct xhci_command *cmd;
  242. unsigned long flags;
  243. int timeleft;
  244. int ret;
  245. int i;
  246. ret = 0;
  247. virt_dev = xhci->devs[slot_id];
  248. cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
  249. if (!cmd) {
  250. xhci_dbg(xhci, "Couldn't allocate command structure.\n");
  251. return -ENOMEM;
  252. }
  253. spin_lock_irqsave(&xhci->lock, flags);
  254. for (i = LAST_EP_INDEX; i > 0; i--) {
  255. if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
  256. xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
  257. }
  258. cmd->command_trb = xhci->cmd_ring->enqueue;
  259. list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
  260. xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
  261. xhci_ring_cmd_db(xhci);
  262. spin_unlock_irqrestore(&xhci->lock, flags);
  263. /* Wait for last stop endpoint command to finish */
  264. timeleft = wait_for_completion_interruptible_timeout(
  265. cmd->completion,
  266. USB_CTRL_SET_TIMEOUT);
  267. if (timeleft <= 0) {
  268. xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
  269. timeleft == 0 ? "Timeout" : "Signal");
  270. spin_lock_irqsave(&xhci->lock, flags);
  271. /* The timeout might have raced with the event ring handler, so
  272. * only delete from the list if the item isn't poisoned.
  273. */
  274. if (cmd->cmd_list.next != LIST_POISON1)
  275. list_del(&cmd->cmd_list);
  276. spin_unlock_irqrestore(&xhci->lock, flags);
  277. ret = -ETIME;
  278. goto command_cleanup;
  279. }
  280. command_cleanup:
  281. xhci_free_command(xhci, cmd);
  282. return ret;
  283. }
  284. /*
  285. * Ring device, it rings the all doorbells unconditionally.
  286. */
  287. void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
  288. {
  289. int i;
  290. for (i = 0; i < LAST_EP_INDEX + 1; i++)
  291. if (xhci->devs[slot_id]->eps[i].ring &&
  292. xhci->devs[slot_id]->eps[i].ring->dequeue)
  293. xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
  294. return;
  295. }
  296. static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  297. u16 wIndex, __le32 __iomem *addr, u32 port_status)
  298. {
  299. /* Don't allow the USB core to disable SuperSpeed ports. */
  300. if (hcd->speed == HCD_USB3) {
  301. xhci_dbg(xhci, "Ignoring request to disable "
  302. "SuperSpeed port.\n");
  303. return;
  304. }
  305. /* Write 1 to disable the port */
  306. xhci_writel(xhci, port_status | PORT_PE, addr);
  307. port_status = xhci_readl(xhci, addr);
  308. xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
  309. wIndex, port_status);
  310. }
  311. static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
  312. u16 wIndex, __le32 __iomem *addr, u32 port_status)
  313. {
  314. char *port_change_bit;
  315. u32 status;
  316. switch (wValue) {
  317. case USB_PORT_FEAT_C_RESET:
  318. status = PORT_RC;
  319. port_change_bit = "reset";
  320. break;
  321. case USB_PORT_FEAT_C_BH_PORT_RESET:
  322. status = PORT_WRC;
  323. port_change_bit = "warm(BH) reset";
  324. break;
  325. case USB_PORT_FEAT_C_CONNECTION:
  326. status = PORT_CSC;
  327. port_change_bit = "connect";
  328. break;
  329. case USB_PORT_FEAT_C_OVER_CURRENT:
  330. status = PORT_OCC;
  331. port_change_bit = "over-current";
  332. break;
  333. case USB_PORT_FEAT_C_ENABLE:
  334. status = PORT_PEC;
  335. port_change_bit = "enable/disable";
  336. break;
  337. case USB_PORT_FEAT_C_SUSPEND:
  338. status = PORT_PLC;
  339. port_change_bit = "suspend/resume";
  340. break;
  341. case USB_PORT_FEAT_C_PORT_LINK_STATE:
  342. status = PORT_PLC;
  343. port_change_bit = "link state";
  344. break;
  345. default:
  346. /* Should never happen */
  347. return;
  348. }
  349. /* Change bits are all write 1 to clear */
  350. xhci_writel(xhci, port_status | status, addr);
  351. port_status = xhci_readl(xhci, addr);
  352. xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
  353. port_change_bit, wIndex, port_status);
  354. }
  355. static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
  356. {
  357. int max_ports;
  358. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  359. if (hcd->speed == HCD_USB3) {
  360. max_ports = xhci->num_usb3_ports;
  361. *port_array = xhci->usb3_ports;
  362. } else {
  363. max_ports = xhci->num_usb2_ports;
  364. *port_array = xhci->usb2_ports;
  365. }
  366. return max_ports;
  367. }
  368. void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
  369. int port_id, u32 link_state)
  370. {
  371. u32 temp;
  372. temp = xhci_readl(xhci, port_array[port_id]);
  373. temp = xhci_port_state_to_neutral(temp);
  374. temp &= ~PORT_PLS_MASK;
  375. temp |= PORT_LINK_STROBE | link_state;
  376. xhci_writel(xhci, temp, port_array[port_id]);
  377. }
  378. static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
  379. __le32 __iomem **port_array, int port_id, u16 wake_mask)
  380. {
  381. u32 temp;
  382. temp = xhci_readl(xhci, port_array[port_id]);
  383. temp = xhci_port_state_to_neutral(temp);
  384. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
  385. temp |= PORT_WKCONN_E;
  386. else
  387. temp &= ~PORT_WKCONN_E;
  388. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
  389. temp |= PORT_WKDISC_E;
  390. else
  391. temp &= ~PORT_WKDISC_E;
  392. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
  393. temp |= PORT_WKOC_E;
  394. else
  395. temp &= ~PORT_WKOC_E;
  396. xhci_writel(xhci, temp, port_array[port_id]);
  397. }
  398. /* Test and clear port RWC bit */
  399. void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
  400. int port_id, u32 port_bit)
  401. {
  402. u32 temp;
  403. temp = xhci_readl(xhci, port_array[port_id]);
  404. if (temp & port_bit) {
  405. temp = xhci_port_state_to_neutral(temp);
  406. temp |= port_bit;
  407. xhci_writel(xhci, temp, port_array[port_id]);
  408. }
  409. }
  410. /* Updates Link Status for USB 2.1 port */
  411. static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
  412. {
  413. if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
  414. *status |= USB_PORT_STAT_L1;
  415. }
  416. /* Updates Link Status for super Speed port */
  417. static void xhci_hub_report_usb3_link_state(u32 *status, u32 status_reg)
  418. {
  419. u32 pls = status_reg & PORT_PLS_MASK;
  420. /* resume state is a xHCI internal state.
  421. * Do not report it to usb core.
  422. */
  423. if (pls == XDEV_RESUME)
  424. return;
  425. /* When the CAS bit is set then warm reset
  426. * should be performed on port
  427. */
  428. if (status_reg & PORT_CAS) {
  429. /* The CAS bit can be set while the port is
  430. * in any link state.
  431. * Only roothubs have CAS bit, so we
  432. * pretend to be in compliance mode
  433. * unless we're already in compliance
  434. * or the inactive state.
  435. */
  436. if (pls != USB_SS_PORT_LS_COMP_MOD &&
  437. pls != USB_SS_PORT_LS_SS_INACTIVE) {
  438. pls = USB_SS_PORT_LS_COMP_MOD;
  439. }
  440. /* Return also connection bit -
  441. * hub state machine resets port
  442. * when this bit is set.
  443. */
  444. pls |= USB_PORT_STAT_CONNECTION;
  445. } else {
  446. /*
  447. * If CAS bit isn't set but the Port is already at
  448. * Compliance Mode, fake a connection so the USB core
  449. * notices the Compliance state and resets the port.
  450. * This resolves an issue generated by the SN65LVPE502CP
  451. * in which sometimes the port enters compliance mode
  452. * caused by a delay on the host-device negotiation.
  453. */
  454. if (pls == USB_SS_PORT_LS_COMP_MOD)
  455. pls |= USB_PORT_STAT_CONNECTION;
  456. }
  457. /* update status field */
  458. *status |= pls;
  459. }
  460. /*
  461. * Function for Compliance Mode Quirk.
  462. *
  463. * This Function verifies if all xhc USB3 ports have entered U0, if so,
  464. * the compliance mode timer is deleted. A port won't enter
  465. * compliance mode if it has previously entered U0.
  466. */
  467. void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, u16 wIndex)
  468. {
  469. u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
  470. bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
  471. if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
  472. return;
  473. if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
  474. xhci->port_status_u0 |= 1 << wIndex;
  475. if (xhci->port_status_u0 == all_ports_seen_u0) {
  476. del_timer_sync(&xhci->comp_mode_recovery_timer);
  477. xhci_dbg(xhci, "All USB3 ports have entered U0 already!\n");
  478. xhci_dbg(xhci, "Compliance Mode Recovery Timer Deleted.\n");
  479. }
  480. }
  481. }
  482. /*
  483. * Converts a raw xHCI port status into the format that external USB 2.0 or USB
  484. * 3.0 hubs use.
  485. *
  486. * Possible side effects:
  487. * - Mark a port as being done with device resume,
  488. * and ring the endpoint doorbells.
  489. * - Stop the Synopsys redriver Compliance Mode polling.
  490. */
  491. static u32 xhci_get_port_status(struct usb_hcd *hcd,
  492. struct xhci_bus_state *bus_state,
  493. __le32 __iomem **port_array,
  494. u16 wIndex, u32 raw_port_status)
  495. {
  496. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  497. u32 status = 0;
  498. int slot_id;
  499. /* wPortChange bits */
  500. if (raw_port_status & PORT_CSC)
  501. status |= USB_PORT_STAT_C_CONNECTION << 16;
  502. if (raw_port_status & PORT_PEC)
  503. status |= USB_PORT_STAT_C_ENABLE << 16;
  504. if ((raw_port_status & PORT_OCC))
  505. status |= USB_PORT_STAT_C_OVERCURRENT << 16;
  506. if ((raw_port_status & PORT_RC))
  507. status |= USB_PORT_STAT_C_RESET << 16;
  508. /* USB3.0 only */
  509. if (hcd->speed == HCD_USB3) {
  510. if ((raw_port_status & PORT_PLC))
  511. status |= USB_PORT_STAT_C_LINK_STATE << 16;
  512. if ((raw_port_status & PORT_WRC))
  513. status |= USB_PORT_STAT_C_BH_RESET << 16;
  514. }
  515. if (hcd->speed != HCD_USB3) {
  516. if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
  517. && (raw_port_status & PORT_POWER))
  518. status |= USB_PORT_STAT_SUSPEND;
  519. }
  520. if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
  521. !DEV_SUPERSPEED(raw_port_status)) {
  522. if ((raw_port_status & PORT_RESET) ||
  523. !(raw_port_status & PORT_PE))
  524. return 0xffffffff;
  525. if (time_after_eq(jiffies,
  526. bus_state->resume_done[wIndex])) {
  527. xhci_dbg(xhci, "Resume USB2 port %d\n",
  528. wIndex + 1);
  529. bus_state->resume_done[wIndex] = 0;
  530. clear_bit(wIndex, &bus_state->resuming_ports);
  531. xhci_set_link_state(xhci, port_array, wIndex,
  532. XDEV_U0);
  533. xhci_dbg(xhci, "set port %d resume\n",
  534. wIndex + 1);
  535. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  536. wIndex + 1);
  537. if (!slot_id) {
  538. xhci_dbg(xhci, "slot_id is zero\n");
  539. return 0xffffffff;
  540. }
  541. xhci_ring_device(xhci, slot_id);
  542. bus_state->port_c_suspend |= 1 << wIndex;
  543. bus_state->suspended_ports &= ~(1 << wIndex);
  544. } else {
  545. /*
  546. * The resume has been signaling for less than
  547. * 20ms. Report the port status as SUSPEND,
  548. * let the usbcore check port status again
  549. * and clear resume signaling later.
  550. */
  551. status |= USB_PORT_STAT_SUSPEND;
  552. }
  553. }
  554. if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0
  555. && (raw_port_status & PORT_POWER)
  556. && (bus_state->suspended_ports & (1 << wIndex))) {
  557. bus_state->suspended_ports &= ~(1 << wIndex);
  558. if (hcd->speed != HCD_USB3)
  559. bus_state->port_c_suspend |= 1 << wIndex;
  560. }
  561. if (raw_port_status & PORT_CONNECT) {
  562. status |= USB_PORT_STAT_CONNECTION;
  563. status |= xhci_port_speed(raw_port_status);
  564. }
  565. if (raw_port_status & PORT_PE)
  566. status |= USB_PORT_STAT_ENABLE;
  567. if (raw_port_status & PORT_OC)
  568. status |= USB_PORT_STAT_OVERCURRENT;
  569. if (raw_port_status & PORT_RESET)
  570. status |= USB_PORT_STAT_RESET;
  571. if (raw_port_status & PORT_POWER) {
  572. if (hcd->speed == HCD_USB3)
  573. status |= USB_SS_PORT_STAT_POWER;
  574. else
  575. status |= USB_PORT_STAT_POWER;
  576. }
  577. /* Update Port Link State */
  578. if (hcd->speed == HCD_USB3) {
  579. xhci_hub_report_usb3_link_state(&status, raw_port_status);
  580. /*
  581. * Verify if all USB3 Ports Have entered U0 already.
  582. * Delete Compliance Mode Timer if so.
  583. */
  584. xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
  585. } else {
  586. xhci_hub_report_usb2_link_state(&status, raw_port_status);
  587. }
  588. if (bus_state->port_c_suspend & (1 << wIndex))
  589. status |= 1 << USB_PORT_FEAT_C_SUSPEND;
  590. return status;
  591. }
  592. int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
  593. u16 wIndex, char *buf, u16 wLength)
  594. {
  595. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  596. int max_ports;
  597. unsigned long flags;
  598. u32 temp, status;
  599. int retval = 0;
  600. __le32 __iomem **port_array;
  601. int slot_id;
  602. struct xhci_bus_state *bus_state;
  603. u16 link_state = 0;
  604. u16 wake_mask = 0;
  605. u16 timeout = 0;
  606. max_ports = xhci_get_ports(hcd, &port_array);
  607. bus_state = &xhci->bus_state[hcd_index(hcd)];
  608. spin_lock_irqsave(&xhci->lock, flags);
  609. switch (typeReq) {
  610. case GetHubStatus:
  611. /* No power source, over-current reported per port */
  612. memset(buf, 0, 4);
  613. break;
  614. case GetHubDescriptor:
  615. /* Check to make sure userspace is asking for the USB 3.0 hub
  616. * descriptor for the USB 3.0 roothub. If not, we stall the
  617. * endpoint, like external hubs do.
  618. */
  619. if (hcd->speed == HCD_USB3 &&
  620. (wLength < USB_DT_SS_HUB_SIZE ||
  621. wValue != (USB_DT_SS_HUB << 8))) {
  622. xhci_dbg(xhci, "Wrong hub descriptor type for "
  623. "USB 3.0 roothub.\n");
  624. goto error;
  625. }
  626. xhci_hub_descriptor(hcd, xhci,
  627. (struct usb_hub_descriptor *) buf);
  628. break;
  629. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  630. if ((wValue & 0xff00) != (USB_DT_BOS << 8))
  631. goto error;
  632. if (hcd->speed != HCD_USB3)
  633. goto error;
  634. /* Set the U1 and U2 exit latencies. */
  635. memcpy(buf, &usb_bos_descriptor,
  636. USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
  637. temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
  638. buf[12] = HCS_U1_LATENCY(temp);
  639. put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
  640. /* Indicate whether the host has LTM support. */
  641. temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
  642. if (HCC_LTC(temp))
  643. buf[8] |= USB_LTM_SUPPORT;
  644. spin_unlock_irqrestore(&xhci->lock, flags);
  645. return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  646. case GetPortStatus:
  647. if (!wIndex || wIndex > max_ports)
  648. goto error;
  649. wIndex--;
  650. temp = xhci_readl(xhci, port_array[wIndex]);
  651. if (temp == 0xffffffff) {
  652. retval = -ENODEV;
  653. break;
  654. }
  655. status = xhci_get_port_status(hcd, bus_state, port_array,
  656. wIndex, temp);
  657. if (status == 0xffffffff)
  658. goto error;
  659. xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
  660. wIndex, temp);
  661. xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
  662. put_unaligned(cpu_to_le32(status), (__le32 *) buf);
  663. break;
  664. case SetPortFeature:
  665. if (wValue == USB_PORT_FEAT_LINK_STATE)
  666. link_state = (wIndex & 0xff00) >> 3;
  667. if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
  668. wake_mask = wIndex & 0xff00;
  669. /* The MSB of wIndex is the U1/U2 timeout */
  670. timeout = (wIndex & 0xff00) >> 8;
  671. wIndex &= 0xff;
  672. if (!wIndex || wIndex > max_ports)
  673. goto error;
  674. wIndex--;
  675. temp = xhci_readl(xhci, port_array[wIndex]);
  676. if (temp == 0xffffffff) {
  677. retval = -ENODEV;
  678. break;
  679. }
  680. temp = xhci_port_state_to_neutral(temp);
  681. /* FIXME: What new port features do we need to support? */
  682. switch (wValue) {
  683. case USB_PORT_FEAT_SUSPEND:
  684. temp = xhci_readl(xhci, port_array[wIndex]);
  685. if ((temp & PORT_PLS_MASK) != XDEV_U0) {
  686. /* Resume the port to U0 first */
  687. xhci_set_link_state(xhci, port_array, wIndex,
  688. XDEV_U0);
  689. spin_unlock_irqrestore(&xhci->lock, flags);
  690. msleep(10);
  691. spin_lock_irqsave(&xhci->lock, flags);
  692. }
  693. /* In spec software should not attempt to suspend
  694. * a port unless the port reports that it is in the
  695. * enabled (PED = ‘1’,PLS < ‘3’) state.
  696. */
  697. temp = xhci_readl(xhci, port_array[wIndex]);
  698. if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
  699. || (temp & PORT_PLS_MASK) >= XDEV_U3) {
  700. xhci_warn(xhci, "USB core suspending device "
  701. "not in U0/U1/U2.\n");
  702. goto error;
  703. }
  704. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  705. wIndex + 1);
  706. if (!slot_id) {
  707. xhci_warn(xhci, "slot_id is zero\n");
  708. goto error;
  709. }
  710. /* unlock to execute stop endpoint commands */
  711. spin_unlock_irqrestore(&xhci->lock, flags);
  712. xhci_stop_device(xhci, slot_id, 1);
  713. spin_lock_irqsave(&xhci->lock, flags);
  714. xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
  715. spin_unlock_irqrestore(&xhci->lock, flags);
  716. msleep(10); /* wait device to enter */
  717. spin_lock_irqsave(&xhci->lock, flags);
  718. temp = xhci_readl(xhci, port_array[wIndex]);
  719. bus_state->suspended_ports |= 1 << wIndex;
  720. break;
  721. case USB_PORT_FEAT_LINK_STATE:
  722. temp = xhci_readl(xhci, port_array[wIndex]);
  723. /* Disable port */
  724. if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
  725. xhci_dbg(xhci, "Disable port %d\n", wIndex);
  726. temp = xhci_port_state_to_neutral(temp);
  727. /*
  728. * Clear all change bits, so that we get a new
  729. * connection event.
  730. */
  731. temp |= PORT_CSC | PORT_PEC | PORT_WRC |
  732. PORT_OCC | PORT_RC | PORT_PLC |
  733. PORT_CEC;
  734. xhci_writel(xhci, temp | PORT_PE,
  735. port_array[wIndex]);
  736. temp = xhci_readl(xhci, port_array[wIndex]);
  737. break;
  738. }
  739. /* Put link in RxDetect (enable port) */
  740. if (link_state == USB_SS_PORT_LS_RX_DETECT) {
  741. xhci_dbg(xhci, "Enable port %d\n", wIndex);
  742. xhci_set_link_state(xhci, port_array, wIndex,
  743. link_state);
  744. temp = xhci_readl(xhci, port_array[wIndex]);
  745. break;
  746. }
  747. /* Software should not attempt to set
  748. * port link state above '3' (U3) and the port
  749. * must be enabled.
  750. */
  751. if ((temp & PORT_PE) == 0 ||
  752. (link_state > USB_SS_PORT_LS_U3)) {
  753. xhci_warn(xhci, "Cannot set link state.\n");
  754. goto error;
  755. }
  756. if (link_state == USB_SS_PORT_LS_U3) {
  757. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  758. wIndex + 1);
  759. if (slot_id) {
  760. /* unlock to execute stop endpoint
  761. * commands */
  762. spin_unlock_irqrestore(&xhci->lock,
  763. flags);
  764. xhci_stop_device(xhci, slot_id, 1);
  765. spin_lock_irqsave(&xhci->lock, flags);
  766. }
  767. }
  768. xhci_set_link_state(xhci, port_array, wIndex,
  769. link_state);
  770. spin_unlock_irqrestore(&xhci->lock, flags);
  771. msleep(20); /* wait device to enter */
  772. spin_lock_irqsave(&xhci->lock, flags);
  773. temp = xhci_readl(xhci, port_array[wIndex]);
  774. if (link_state == USB_SS_PORT_LS_U3)
  775. bus_state->suspended_ports |= 1 << wIndex;
  776. break;
  777. case USB_PORT_FEAT_POWER:
  778. /*
  779. * Turn on ports, even if there isn't per-port switching.
  780. * HC will report connect events even before this is set.
  781. * However, khubd will ignore the roothub events until
  782. * the roothub is registered.
  783. */
  784. xhci_writel(xhci, temp | PORT_POWER,
  785. port_array[wIndex]);
  786. temp = xhci_readl(xhci, port_array[wIndex]);
  787. xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
  788. spin_unlock_irqrestore(&xhci->lock, flags);
  789. temp = usb_acpi_power_manageable(hcd->self.root_hub,
  790. wIndex);
  791. if (temp)
  792. usb_acpi_set_power_state(hcd->self.root_hub,
  793. wIndex, true);
  794. spin_lock_irqsave(&xhci->lock, flags);
  795. break;
  796. case USB_PORT_FEAT_RESET:
  797. temp = (temp | PORT_RESET);
  798. xhci_writel(xhci, temp, port_array[wIndex]);
  799. temp = xhci_readl(xhci, port_array[wIndex]);
  800. xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
  801. break;
  802. case USB_PORT_FEAT_REMOTE_WAKE_MASK:
  803. xhci_set_remote_wake_mask(xhci, port_array,
  804. wIndex, wake_mask);
  805. temp = xhci_readl(xhci, port_array[wIndex]);
  806. xhci_dbg(xhci, "set port remote wake mask, "
  807. "actual port %d status = 0x%x\n",
  808. wIndex, temp);
  809. break;
  810. case USB_PORT_FEAT_BH_PORT_RESET:
  811. temp |= PORT_WR;
  812. xhci_writel(xhci, temp, port_array[wIndex]);
  813. temp = xhci_readl(xhci, port_array[wIndex]);
  814. break;
  815. case USB_PORT_FEAT_U1_TIMEOUT:
  816. if (hcd->speed != HCD_USB3)
  817. goto error;
  818. temp = xhci_readl(xhci, port_array[wIndex] + PORTPMSC);
  819. temp &= ~PORT_U1_TIMEOUT_MASK;
  820. temp |= PORT_U1_TIMEOUT(timeout);
  821. xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC);
  822. break;
  823. case USB_PORT_FEAT_U2_TIMEOUT:
  824. if (hcd->speed != HCD_USB3)
  825. goto error;
  826. temp = xhci_readl(xhci, port_array[wIndex] + PORTPMSC);
  827. temp &= ~PORT_U2_TIMEOUT_MASK;
  828. temp |= PORT_U2_TIMEOUT(timeout);
  829. xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC);
  830. break;
  831. default:
  832. goto error;
  833. }
  834. /* unblock any posted writes */
  835. temp = xhci_readl(xhci, port_array[wIndex]);
  836. break;
  837. case ClearPortFeature:
  838. if (!wIndex || wIndex > max_ports)
  839. goto error;
  840. wIndex--;
  841. temp = xhci_readl(xhci, port_array[wIndex]);
  842. if (temp == 0xffffffff) {
  843. retval = -ENODEV;
  844. break;
  845. }
  846. /* FIXME: What new port features do we need to support? */
  847. temp = xhci_port_state_to_neutral(temp);
  848. switch (wValue) {
  849. case USB_PORT_FEAT_SUSPEND:
  850. temp = xhci_readl(xhci, port_array[wIndex]);
  851. xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
  852. xhci_dbg(xhci, "PORTSC %04x\n", temp);
  853. if (temp & PORT_RESET)
  854. goto error;
  855. if ((temp & PORT_PLS_MASK) == XDEV_U3) {
  856. if ((temp & PORT_PE) == 0)
  857. goto error;
  858. xhci_set_link_state(xhci, port_array, wIndex,
  859. XDEV_RESUME);
  860. spin_unlock_irqrestore(&xhci->lock, flags);
  861. msleep(20);
  862. spin_lock_irqsave(&xhci->lock, flags);
  863. xhci_set_link_state(xhci, port_array, wIndex,
  864. XDEV_U0);
  865. }
  866. bus_state->port_c_suspend |= 1 << wIndex;
  867. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  868. wIndex + 1);
  869. if (!slot_id) {
  870. xhci_dbg(xhci, "slot_id is zero\n");
  871. goto error;
  872. }
  873. xhci_ring_device(xhci, slot_id);
  874. break;
  875. case USB_PORT_FEAT_C_SUSPEND:
  876. bus_state->port_c_suspend &= ~(1 << wIndex);
  877. case USB_PORT_FEAT_C_RESET:
  878. case USB_PORT_FEAT_C_BH_PORT_RESET:
  879. case USB_PORT_FEAT_C_CONNECTION:
  880. case USB_PORT_FEAT_C_OVER_CURRENT:
  881. case USB_PORT_FEAT_C_ENABLE:
  882. case USB_PORT_FEAT_C_PORT_LINK_STATE:
  883. xhci_clear_port_change_bit(xhci, wValue, wIndex,
  884. port_array[wIndex], temp);
  885. break;
  886. case USB_PORT_FEAT_ENABLE:
  887. xhci_disable_port(hcd, xhci, wIndex,
  888. port_array[wIndex], temp);
  889. break;
  890. case USB_PORT_FEAT_POWER:
  891. xhci_writel(xhci, temp & ~PORT_POWER,
  892. port_array[wIndex]);
  893. spin_unlock_irqrestore(&xhci->lock, flags);
  894. temp = usb_acpi_power_manageable(hcd->self.root_hub,
  895. wIndex);
  896. if (temp)
  897. usb_acpi_set_power_state(hcd->self.root_hub,
  898. wIndex, false);
  899. spin_lock_irqsave(&xhci->lock, flags);
  900. break;
  901. default:
  902. goto error;
  903. }
  904. break;
  905. default:
  906. error:
  907. /* "stall" on error */
  908. retval = -EPIPE;
  909. }
  910. spin_unlock_irqrestore(&xhci->lock, flags);
  911. return retval;
  912. }
  913. /*
  914. * Returns 0 if the status hasn't changed, or the number of bytes in buf.
  915. * Ports are 0-indexed from the HCD point of view,
  916. * and 1-indexed from the USB core pointer of view.
  917. *
  918. * Note that the status change bits will be cleared as soon as a port status
  919. * change event is generated, so we use the saved status from that event.
  920. */
  921. int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
  922. {
  923. unsigned long flags;
  924. u32 temp, status;
  925. u32 mask;
  926. int i, retval;
  927. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  928. int max_ports;
  929. __le32 __iomem **port_array;
  930. struct xhci_bus_state *bus_state;
  931. bool reset_change = false;
  932. max_ports = xhci_get_ports(hcd, &port_array);
  933. bus_state = &xhci->bus_state[hcd_index(hcd)];
  934. /* Initial status is no changes */
  935. retval = (max_ports + 8) / 8;
  936. memset(buf, 0, retval);
  937. /*
  938. * Inform the usbcore about resume-in-progress by returning
  939. * a non-zero value even if there are no status changes.
  940. */
  941. status = bus_state->resuming_ports;
  942. mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
  943. spin_lock_irqsave(&xhci->lock, flags);
  944. /* For each port, did anything change? If so, set that bit in buf. */
  945. for (i = 0; i < max_ports; i++) {
  946. temp = xhci_readl(xhci, port_array[i]);
  947. if (temp == 0xffffffff) {
  948. retval = -ENODEV;
  949. break;
  950. }
  951. if ((temp & mask) != 0 ||
  952. (bus_state->port_c_suspend & 1 << i) ||
  953. (bus_state->resume_done[i] && time_after_eq(
  954. jiffies, bus_state->resume_done[i]))) {
  955. buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
  956. status = 1;
  957. }
  958. if ((temp & PORT_RC))
  959. reset_change = true;
  960. }
  961. if (!status && !reset_change) {
  962. xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
  963. clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
  964. }
  965. spin_unlock_irqrestore(&xhci->lock, flags);
  966. return status ? retval : 0;
  967. }
  968. #ifdef CONFIG_PM
  969. int xhci_bus_suspend(struct usb_hcd *hcd)
  970. {
  971. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  972. int max_ports, port_index;
  973. __le32 __iomem **port_array;
  974. struct xhci_bus_state *bus_state;
  975. unsigned long flags;
  976. max_ports = xhci_get_ports(hcd, &port_array);
  977. bus_state = &xhci->bus_state[hcd_index(hcd)];
  978. spin_lock_irqsave(&xhci->lock, flags);
  979. if (hcd->self.root_hub->do_remote_wakeup) {
  980. if (bus_state->resuming_ports) {
  981. spin_unlock_irqrestore(&xhci->lock, flags);
  982. xhci_dbg(xhci, "suspend failed because "
  983. "a port is resuming\n");
  984. return -EBUSY;
  985. }
  986. }
  987. port_index = max_ports;
  988. bus_state->bus_suspended = 0;
  989. while (port_index--) {
  990. /* suspend the port if the port is not suspended */
  991. u32 t1, t2;
  992. int slot_id;
  993. t1 = xhci_readl(xhci, port_array[port_index]);
  994. t2 = xhci_port_state_to_neutral(t1);
  995. if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
  996. xhci_dbg(xhci, "port %d not suspended\n", port_index);
  997. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  998. port_index + 1);
  999. if (slot_id) {
  1000. spin_unlock_irqrestore(&xhci->lock, flags);
  1001. xhci_stop_device(xhci, slot_id, 1);
  1002. spin_lock_irqsave(&xhci->lock, flags);
  1003. }
  1004. t2 &= ~PORT_PLS_MASK;
  1005. t2 |= PORT_LINK_STROBE | XDEV_U3;
  1006. set_bit(port_index, &bus_state->bus_suspended);
  1007. }
  1008. /* USB core sets remote wake mask for USB 3.0 hubs,
  1009. * including the USB 3.0 roothub, but only if CONFIG_PM_RUNTIME
  1010. * is enabled, so also enable remote wake here.
  1011. */
  1012. if (hcd->self.root_hub->do_remote_wakeup) {
  1013. if (t1 & PORT_CONNECT) {
  1014. t2 |= PORT_WKOC_E | PORT_WKDISC_E;
  1015. t2 &= ~PORT_WKCONN_E;
  1016. } else {
  1017. t2 |= PORT_WKOC_E | PORT_WKCONN_E;
  1018. t2 &= ~PORT_WKDISC_E;
  1019. }
  1020. } else
  1021. t2 &= ~PORT_WAKE_BITS;
  1022. t1 = xhci_port_state_to_neutral(t1);
  1023. if (t1 != t2)
  1024. xhci_writel(xhci, t2, port_array[port_index]);
  1025. if (hcd->speed != HCD_USB3) {
  1026. /* enable remote wake up for USB 2.0 */
  1027. __le32 __iomem *addr;
  1028. u32 tmp;
  1029. /* Get the port power control register address. */
  1030. addr = port_array[port_index] + PORTPMSC;
  1031. tmp = xhci_readl(xhci, addr);
  1032. tmp |= PORT_RWE;
  1033. xhci_writel(xhci, tmp, addr);
  1034. }
  1035. }
  1036. hcd->state = HC_STATE_SUSPENDED;
  1037. bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
  1038. spin_unlock_irqrestore(&xhci->lock, flags);
  1039. return 0;
  1040. }
  1041. int xhci_bus_resume(struct usb_hcd *hcd)
  1042. {
  1043. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1044. int max_ports, port_index;
  1045. __le32 __iomem **port_array;
  1046. struct xhci_bus_state *bus_state;
  1047. u32 temp;
  1048. unsigned long flags;
  1049. max_ports = xhci_get_ports(hcd, &port_array);
  1050. bus_state = &xhci->bus_state[hcd_index(hcd)];
  1051. if (time_before(jiffies, bus_state->next_statechange))
  1052. msleep(5);
  1053. spin_lock_irqsave(&xhci->lock, flags);
  1054. if (!HCD_HW_ACCESSIBLE(hcd)) {
  1055. spin_unlock_irqrestore(&xhci->lock, flags);
  1056. return -ESHUTDOWN;
  1057. }
  1058. /* delay the irqs */
  1059. temp = xhci_readl(xhci, &xhci->op_regs->command);
  1060. temp &= ~CMD_EIE;
  1061. xhci_writel(xhci, temp, &xhci->op_regs->command);
  1062. port_index = max_ports;
  1063. while (port_index--) {
  1064. /* Check whether need resume ports. If needed
  1065. resume port and disable remote wakeup */
  1066. u32 temp;
  1067. int slot_id;
  1068. temp = xhci_readl(xhci, port_array[port_index]);
  1069. if (DEV_SUPERSPEED(temp))
  1070. temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
  1071. else
  1072. temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
  1073. if (test_bit(port_index, &bus_state->bus_suspended) &&
  1074. (temp & PORT_PLS_MASK)) {
  1075. if (DEV_SUPERSPEED(temp)) {
  1076. xhci_set_link_state(xhci, port_array,
  1077. port_index, XDEV_U0);
  1078. } else {
  1079. xhci_set_link_state(xhci, port_array,
  1080. port_index, XDEV_RESUME);
  1081. spin_unlock_irqrestore(&xhci->lock, flags);
  1082. msleep(20);
  1083. spin_lock_irqsave(&xhci->lock, flags);
  1084. xhci_set_link_state(xhci, port_array,
  1085. port_index, XDEV_U0);
  1086. }
  1087. /* wait for the port to enter U0 and report port link
  1088. * state change.
  1089. */
  1090. spin_unlock_irqrestore(&xhci->lock, flags);
  1091. msleep(20);
  1092. spin_lock_irqsave(&xhci->lock, flags);
  1093. /* Clear PLC */
  1094. xhci_test_and_clear_bit(xhci, port_array, port_index,
  1095. PORT_PLC);
  1096. slot_id = xhci_find_slot_id_by_port(hcd,
  1097. xhci, port_index + 1);
  1098. if (slot_id)
  1099. xhci_ring_device(xhci, slot_id);
  1100. } else
  1101. xhci_writel(xhci, temp, port_array[port_index]);
  1102. if (hcd->speed != HCD_USB3) {
  1103. /* disable remote wake up for USB 2.0 */
  1104. __le32 __iomem *addr;
  1105. u32 tmp;
  1106. /* Add one to the port status register address to get
  1107. * the port power control register address.
  1108. */
  1109. addr = port_array[port_index] + PORTPMSC;
  1110. tmp = xhci_readl(xhci, addr);
  1111. tmp &= ~PORT_RWE;
  1112. xhci_writel(xhci, tmp, addr);
  1113. }
  1114. }
  1115. (void) xhci_readl(xhci, &xhci->op_regs->command);
  1116. bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
  1117. /* re-enable irqs */
  1118. temp = xhci_readl(xhci, &xhci->op_regs->command);
  1119. temp |= CMD_EIE;
  1120. xhci_writel(xhci, temp, &xhci->op_regs->command);
  1121. temp = xhci_readl(xhci, &xhci->op_regs->command);
  1122. spin_unlock_irqrestore(&xhci->lock, flags);
  1123. return 0;
  1124. }
  1125. #endif /* CONFIG_PM */