fusbh200.h 24 KB

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  1. #ifndef __LINUX_FUSBH200_H
  2. #define __LINUX_FUSBH200_H
  3. /* definitions used for the EHCI driver */
  4. /*
  5. * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  6. * __leXX (normally) or __beXX (given FUSBH200_BIG_ENDIAN_DESC), depending on
  7. * the host controller implementation.
  8. *
  9. * To facilitate the strongest possible byte-order checking from "sparse"
  10. * and so on, we use __leXX unless that's not practical.
  11. */
  12. #define __hc32 __le32
  13. #define __hc16 __le16
  14. /* statistics can be kept for tuning/monitoring */
  15. struct fusbh200_stats {
  16. /* irq usage */
  17. unsigned long normal;
  18. unsigned long error;
  19. unsigned long iaa;
  20. unsigned long lost_iaa;
  21. /* termination of urbs from core */
  22. unsigned long complete;
  23. unsigned long unlink;
  24. };
  25. /* fusbh200_hcd->lock guards shared data against other CPUs:
  26. * fusbh200_hcd: async, unlink, periodic (and shadow), ...
  27. * usb_host_endpoint: hcpriv
  28. * fusbh200_qh: qh_next, qtd_list
  29. * fusbh200_qtd: qtd_list
  30. *
  31. * Also, hold this lock when talking to HC registers or
  32. * when updating hw_* fields in shared qh/qtd/... structures.
  33. */
  34. #define FUSBH200_MAX_ROOT_PORTS 1 /* see HCS_N_PORTS */
  35. /*
  36. * fusbh200_rh_state values of FUSBH200_RH_RUNNING or above mean that the
  37. * controller may be doing DMA. Lower values mean there's no DMA.
  38. */
  39. enum fusbh200_rh_state {
  40. FUSBH200_RH_HALTED,
  41. FUSBH200_RH_SUSPENDED,
  42. FUSBH200_RH_RUNNING,
  43. FUSBH200_RH_STOPPING
  44. };
  45. /*
  46. * Timer events, ordered by increasing delay length.
  47. * Always update event_delays_ns[] and event_handlers[] (defined in
  48. * ehci-timer.c) in parallel with this list.
  49. */
  50. enum fusbh200_hrtimer_event {
  51. FUSBH200_HRTIMER_POLL_ASS, /* Poll for async schedule off */
  52. FUSBH200_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
  53. FUSBH200_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
  54. FUSBH200_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
  55. FUSBH200_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
  56. FUSBH200_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
  57. FUSBH200_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
  58. FUSBH200_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
  59. FUSBH200_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
  60. FUSBH200_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
  61. FUSBH200_HRTIMER_NUM_EVENTS /* Must come last */
  62. };
  63. #define FUSBH200_HRTIMER_NO_EVENT 99
  64. struct fusbh200_hcd { /* one per controller */
  65. /* timing support */
  66. enum fusbh200_hrtimer_event next_hrtimer_event;
  67. unsigned enabled_hrtimer_events;
  68. ktime_t hr_timeouts[FUSBH200_HRTIMER_NUM_EVENTS];
  69. struct hrtimer hrtimer;
  70. int PSS_poll_count;
  71. int ASS_poll_count;
  72. int died_poll_count;
  73. /* glue to PCI and HCD framework */
  74. struct fusbh200_caps __iomem *caps;
  75. struct fusbh200_regs __iomem *regs;
  76. struct fusbh200_dbg_port __iomem *debug;
  77. __u32 hcs_params; /* cached register copy */
  78. spinlock_t lock;
  79. enum fusbh200_rh_state rh_state;
  80. /* general schedule support */
  81. bool scanning:1;
  82. bool need_rescan:1;
  83. bool intr_unlinking:1;
  84. bool async_unlinking:1;
  85. bool shutdown:1;
  86. struct fusbh200_qh *qh_scan_next;
  87. /* async schedule support */
  88. struct fusbh200_qh *async;
  89. struct fusbh200_qh *dummy; /* For AMD quirk use */
  90. struct fusbh200_qh *async_unlink;
  91. struct fusbh200_qh *async_unlink_last;
  92. struct fusbh200_qh *async_iaa;
  93. unsigned async_unlink_cycle;
  94. unsigned async_count; /* async activity count */
  95. /* periodic schedule support */
  96. #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
  97. unsigned periodic_size;
  98. __hc32 *periodic; /* hw periodic table */
  99. dma_addr_t periodic_dma;
  100. struct list_head intr_qh_list;
  101. unsigned i_thresh; /* uframes HC might cache */
  102. union fusbh200_shadow *pshadow; /* mirror hw periodic table */
  103. struct fusbh200_qh *intr_unlink;
  104. struct fusbh200_qh *intr_unlink_last;
  105. unsigned intr_unlink_cycle;
  106. unsigned now_frame; /* frame from HC hardware */
  107. unsigned next_frame; /* scan periodic, start here */
  108. unsigned intr_count; /* intr activity count */
  109. unsigned isoc_count; /* isoc activity count */
  110. unsigned periodic_count; /* periodic activity count */
  111. unsigned uframe_periodic_max; /* max periodic time per uframe */
  112. /* list of itds completed while now_frame was still active */
  113. struct list_head cached_itd_list;
  114. struct fusbh200_itd *last_itd_to_free;
  115. /* per root hub port */
  116. unsigned long reset_done [FUSBH200_MAX_ROOT_PORTS];
  117. /* bit vectors (one bit per port) */
  118. unsigned long bus_suspended; /* which ports were
  119. already suspended at the start of a bus suspend */
  120. unsigned long companion_ports; /* which ports are
  121. dedicated to the companion controller */
  122. unsigned long owned_ports; /* which ports are
  123. owned by the companion during a bus suspend */
  124. unsigned long port_c_suspend; /* which ports have
  125. the change-suspend feature turned on */
  126. unsigned long suspended_ports; /* which ports are
  127. suspended */
  128. unsigned long resuming_ports; /* which ports have
  129. started to resume */
  130. /* per-HC memory pools (could be per-bus, but ...) */
  131. struct dma_pool *qh_pool; /* qh per active urb */
  132. struct dma_pool *qtd_pool; /* one or more per qh */
  133. struct dma_pool *itd_pool; /* itd per iso urb */
  134. unsigned random_frame;
  135. unsigned long next_statechange;
  136. ktime_t last_periodic_enable;
  137. u32 command;
  138. /* SILICON QUIRKS */
  139. unsigned need_io_watchdog:1;
  140. unsigned fs_i_thresh:1; /* Intel iso scheduling */
  141. u8 sbrn; /* packed release number */
  142. /* irq statistics */
  143. #ifdef FUSBH200_STATS
  144. struct fusbh200_stats stats;
  145. # define COUNT(x) do { (x)++; } while (0)
  146. #else
  147. # define COUNT(x) do {} while (0)
  148. #endif
  149. /* debug files */
  150. #ifdef DEBUG
  151. struct dentry *debug_dir;
  152. #endif
  153. };
  154. /* convert between an HCD pointer and the corresponding FUSBH200_HCD */
  155. static inline struct fusbh200_hcd *hcd_to_fusbh200 (struct usb_hcd *hcd)
  156. {
  157. return (struct fusbh200_hcd *) (hcd->hcd_priv);
  158. }
  159. static inline struct usb_hcd *fusbh200_to_hcd (struct fusbh200_hcd *fusbh200)
  160. {
  161. return container_of ((void *) fusbh200, struct usb_hcd, hcd_priv);
  162. }
  163. /*-------------------------------------------------------------------------*/
  164. /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
  165. /* Section 2.2 Host Controller Capability Registers */
  166. struct fusbh200_caps {
  167. /* these fields are specified as 8 and 16 bit registers,
  168. * but some hosts can't perform 8 or 16 bit PCI accesses.
  169. * some hosts treat caplength and hciversion as parts of a 32-bit
  170. * register, others treat them as two separate registers, this
  171. * affects the memory map for big endian controllers.
  172. */
  173. u32 hc_capbase;
  174. #define HC_LENGTH(fusbh200, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
  175. (fusbh200_big_endian_capbase(fusbh200) ? 24 : 0)))
  176. #define HC_VERSION(fusbh200, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
  177. (fusbh200_big_endian_capbase(fusbh200) ? 0 : 16)))
  178. u32 hcs_params; /* HCSPARAMS - offset 0x4 */
  179. #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
  180. u32 hcc_params; /* HCCPARAMS - offset 0x8 */
  181. #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
  182. #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
  183. u8 portroute[8]; /* nibbles for routing - offset 0xC */
  184. };
  185. /* Section 2.3 Host Controller Operational Registers */
  186. struct fusbh200_regs {
  187. /* USBCMD: offset 0x00 */
  188. u32 command;
  189. /* EHCI 1.1 addendum */
  190. /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
  191. #define CMD_PARK (1<<11) /* enable "park" on async qh */
  192. #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
  193. #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
  194. #define CMD_ASE (1<<5) /* async schedule enable */
  195. #define CMD_PSE (1<<4) /* periodic schedule enable */
  196. /* 3:2 is periodic frame list size */
  197. #define CMD_RESET (1<<1) /* reset HC not bus */
  198. #define CMD_RUN (1<<0) /* start/stop HC */
  199. /* USBSTS: offset 0x04 */
  200. u32 status;
  201. #define STS_ASS (1<<15) /* Async Schedule Status */
  202. #define STS_PSS (1<<14) /* Periodic Schedule Status */
  203. #define STS_RECL (1<<13) /* Reclamation */
  204. #define STS_HALT (1<<12) /* Not running (any reason) */
  205. /* some bits reserved */
  206. /* these STS_* flags are also intr_enable bits (USBINTR) */
  207. #define STS_IAA (1<<5) /* Interrupted on async advance */
  208. #define STS_FATAL (1<<4) /* such as some PCI access errors */
  209. #define STS_FLR (1<<3) /* frame list rolled over */
  210. #define STS_PCD (1<<2) /* port change detect */
  211. #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
  212. #define STS_INT (1<<0) /* "normal" completion (short, ...) */
  213. /* USBINTR: offset 0x08 */
  214. u32 intr_enable;
  215. /* FRINDEX: offset 0x0C */
  216. u32 frame_index; /* current microframe number */
  217. /* CTRLDSSEGMENT: offset 0x10 */
  218. u32 segment; /* address bits 63:32 if needed */
  219. /* PERIODICLISTBASE: offset 0x14 */
  220. u32 frame_list; /* points to periodic list */
  221. /* ASYNCLISTADDR: offset 0x18 */
  222. u32 async_next; /* address of next async queue head */
  223. u32 reserved1;
  224. /* PORTSC: offset 0x20 */
  225. u32 port_status;
  226. /* 31:23 reserved */
  227. #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
  228. #define PORT_RESET (1<<8) /* reset port */
  229. #define PORT_SUSPEND (1<<7) /* suspend port */
  230. #define PORT_RESUME (1<<6) /* resume it */
  231. #define PORT_PEC (1<<3) /* port enable change */
  232. #define PORT_PE (1<<2) /* port enable */
  233. #define PORT_CSC (1<<1) /* connect status change */
  234. #define PORT_CONNECT (1<<0) /* device connected */
  235. #define PORT_RWC_BITS (PORT_CSC | PORT_PEC)
  236. u32 reserved2[3];
  237. /* BMCSR: offset 0x30 */
  238. u32 bmcsr; /* Bus Moniter Control/Status Register */
  239. #define BMCSR_HOST_SPD_TYP (3<<9)
  240. #define BMCSR_VBUS_OFF (1<<4)
  241. #define BMCSR_INT_POLARITY (1<<3)
  242. /* BMISR: offset 0x34 */
  243. u32 bmisr; /* Bus Moniter Interrupt Status Register*/
  244. #define BMISR_OVC (1<<1)
  245. /* BMIER: offset 0x38 */
  246. u32 bmier; /* Bus Moniter Interrupt Enable Register */
  247. #define BMIER_OVC_EN (1<<1)
  248. #define BMIER_VBUS_ERR_EN (1<<0)
  249. };
  250. /* Appendix C, Debug port ... intended for use with special "debug devices"
  251. * that can help if there's no serial console. (nonstandard enumeration.)
  252. */
  253. struct fusbh200_dbg_port {
  254. u32 control;
  255. #define DBGP_OWNER (1<<30)
  256. #define DBGP_ENABLED (1<<28)
  257. #define DBGP_DONE (1<<16)
  258. #define DBGP_INUSE (1<<10)
  259. #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
  260. # define DBGP_ERR_BAD 1
  261. # define DBGP_ERR_SIGNAL 2
  262. #define DBGP_ERROR (1<<6)
  263. #define DBGP_GO (1<<5)
  264. #define DBGP_OUT (1<<4)
  265. #define DBGP_LEN(x) (((x)>>0)&0x0f)
  266. u32 pids;
  267. #define DBGP_PID_GET(x) (((x)>>16)&0xff)
  268. #define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
  269. u32 data03;
  270. u32 data47;
  271. u32 address;
  272. #define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
  273. };
  274. #ifdef CONFIG_EARLY_PRINTK_DBGP
  275. #include <linux/init.h>
  276. extern int __init early_dbgp_init(char *s);
  277. extern struct console early_dbgp_console;
  278. #endif /* CONFIG_EARLY_PRINTK_DBGP */
  279. struct usb_hcd;
  280. static inline int xen_dbgp_reset_prep(struct usb_hcd *hcd)
  281. {
  282. return 1; /* Shouldn't this be 0? */
  283. }
  284. static inline int xen_dbgp_external_startup(struct usb_hcd *hcd)
  285. {
  286. return -1;
  287. }
  288. #ifdef CONFIG_EARLY_PRINTK_DBGP
  289. /* Call backs from fusbh200 host driver to fusbh200 debug driver */
  290. extern int dbgp_external_startup(struct usb_hcd *);
  291. extern int dbgp_reset_prep(struct usb_hcd *hcd);
  292. #else
  293. static inline int dbgp_reset_prep(struct usb_hcd *hcd)
  294. {
  295. return xen_dbgp_reset_prep(hcd);
  296. }
  297. static inline int dbgp_external_startup(struct usb_hcd *hcd)
  298. {
  299. return xen_dbgp_external_startup(hcd);
  300. }
  301. #endif
  302. /*-------------------------------------------------------------------------*/
  303. #define QTD_NEXT(fusbh200, dma) cpu_to_hc32(fusbh200, (u32)dma)
  304. /*
  305. * EHCI Specification 0.95 Section 3.5
  306. * QTD: describe data transfer components (buffer, direction, ...)
  307. * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
  308. *
  309. * These are associated only with "QH" (Queue Head) structures,
  310. * used with control, bulk, and interrupt transfers.
  311. */
  312. struct fusbh200_qtd {
  313. /* first part defined by EHCI spec */
  314. __hc32 hw_next; /* see EHCI 3.5.1 */
  315. __hc32 hw_alt_next; /* see EHCI 3.5.2 */
  316. __hc32 hw_token; /* see EHCI 3.5.3 */
  317. #define QTD_TOGGLE (1 << 31) /* data toggle */
  318. #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
  319. #define QTD_IOC (1 << 15) /* interrupt on complete */
  320. #define QTD_CERR(tok) (((tok)>>10) & 0x3)
  321. #define QTD_PID(tok) (((tok)>>8) & 0x3)
  322. #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
  323. #define QTD_STS_HALT (1 << 6) /* halted on error */
  324. #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
  325. #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
  326. #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
  327. #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
  328. #define QTD_STS_STS (1 << 1) /* split transaction state */
  329. #define QTD_STS_PING (1 << 0) /* issue PING? */
  330. #define ACTIVE_BIT(fusbh200) cpu_to_hc32(fusbh200, QTD_STS_ACTIVE)
  331. #define HALT_BIT(fusbh200) cpu_to_hc32(fusbh200, QTD_STS_HALT)
  332. #define STATUS_BIT(fusbh200) cpu_to_hc32(fusbh200, QTD_STS_STS)
  333. __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
  334. __hc32 hw_buf_hi [5]; /* Appendix B */
  335. /* the rest is HCD-private */
  336. dma_addr_t qtd_dma; /* qtd address */
  337. struct list_head qtd_list; /* sw qtd list */
  338. struct urb *urb; /* qtd's urb */
  339. size_t length; /* length of buffer */
  340. } __attribute__ ((aligned (32)));
  341. /* mask NakCnt+T in qh->hw_alt_next */
  342. #define QTD_MASK(fusbh200) cpu_to_hc32 (fusbh200, ~0x1f)
  343. #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
  344. /*-------------------------------------------------------------------------*/
  345. /* type tag from {qh,itd,fstn}->hw_next */
  346. #define Q_NEXT_TYPE(fusbh200,dma) ((dma) & cpu_to_hc32(fusbh200, 3 << 1))
  347. /*
  348. * Now the following defines are not converted using the
  349. * cpu_to_le32() macro anymore, since we have to support
  350. * "dynamic" switching between be and le support, so that the driver
  351. * can be used on one system with SoC EHCI controller using big-endian
  352. * descriptors as well as a normal little-endian PCI EHCI controller.
  353. */
  354. /* values for that type tag */
  355. #define Q_TYPE_ITD (0 << 1)
  356. #define Q_TYPE_QH (1 << 1)
  357. #define Q_TYPE_SITD (2 << 1)
  358. #define Q_TYPE_FSTN (3 << 1)
  359. /* next async queue entry, or pointer to interrupt/periodic QH */
  360. #define QH_NEXT(fusbh200,dma) (cpu_to_hc32(fusbh200, (((u32)dma)&~0x01f)|Q_TYPE_QH))
  361. /* for periodic/async schedules and qtd lists, mark end of list */
  362. #define FUSBH200_LIST_END(fusbh200) cpu_to_hc32(fusbh200, 1) /* "null pointer" to hw */
  363. /*
  364. * Entries in periodic shadow table are pointers to one of four kinds
  365. * of data structure. That's dictated by the hardware; a type tag is
  366. * encoded in the low bits of the hardware's periodic schedule. Use
  367. * Q_NEXT_TYPE to get the tag.
  368. *
  369. * For entries in the async schedule, the type tag always says "qh".
  370. */
  371. union fusbh200_shadow {
  372. struct fusbh200_qh *qh; /* Q_TYPE_QH */
  373. struct fusbh200_itd *itd; /* Q_TYPE_ITD */
  374. struct fusbh200_fstn *fstn; /* Q_TYPE_FSTN */
  375. __hc32 *hw_next; /* (all types) */
  376. void *ptr;
  377. };
  378. /*-------------------------------------------------------------------------*/
  379. /*
  380. * EHCI Specification 0.95 Section 3.6
  381. * QH: describes control/bulk/interrupt endpoints
  382. * See Fig 3-7 "Queue Head Structure Layout".
  383. *
  384. * These appear in both the async and (for interrupt) periodic schedules.
  385. */
  386. /* first part defined by EHCI spec */
  387. struct fusbh200_qh_hw {
  388. __hc32 hw_next; /* see EHCI 3.6.1 */
  389. __hc32 hw_info1; /* see EHCI 3.6.2 */
  390. #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
  391. #define QH_HEAD (1 << 15) /* Head of async reclamation list */
  392. #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
  393. #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
  394. #define QH_LOW_SPEED (1 << 12)
  395. #define QH_FULL_SPEED (0 << 12)
  396. #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
  397. __hc32 hw_info2; /* see EHCI 3.6.2 */
  398. #define QH_SMASK 0x000000ff
  399. #define QH_CMASK 0x0000ff00
  400. #define QH_HUBADDR 0x007f0000
  401. #define QH_HUBPORT 0x3f800000
  402. #define QH_MULT 0xc0000000
  403. __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
  404. /* qtd overlay (hardware parts of a struct fusbh200_qtd) */
  405. __hc32 hw_qtd_next;
  406. __hc32 hw_alt_next;
  407. __hc32 hw_token;
  408. __hc32 hw_buf [5];
  409. __hc32 hw_buf_hi [5];
  410. } __attribute__ ((aligned(32)));
  411. struct fusbh200_qh {
  412. struct fusbh200_qh_hw *hw; /* Must come first */
  413. /* the rest is HCD-private */
  414. dma_addr_t qh_dma; /* address of qh */
  415. union fusbh200_shadow qh_next; /* ptr to qh; or periodic */
  416. struct list_head qtd_list; /* sw qtd list */
  417. struct list_head intr_node; /* list of intr QHs */
  418. struct fusbh200_qtd *dummy;
  419. struct fusbh200_qh *unlink_next; /* next on unlink list */
  420. unsigned unlink_cycle;
  421. u8 needs_rescan; /* Dequeue during giveback */
  422. u8 qh_state;
  423. #define QH_STATE_LINKED 1 /* HC sees this */
  424. #define QH_STATE_UNLINK 2 /* HC may still see this */
  425. #define QH_STATE_IDLE 3 /* HC doesn't see this */
  426. #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
  427. #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
  428. u8 xacterrs; /* XactErr retry counter */
  429. #define QH_XACTERR_MAX 32 /* XactErr retry limit */
  430. /* periodic schedule info */
  431. u8 usecs; /* intr bandwidth */
  432. u8 gap_uf; /* uframes split/csplit gap */
  433. u8 c_usecs; /* ... split completion bw */
  434. u16 tt_usecs; /* tt downstream bandwidth */
  435. unsigned short period; /* polling interval */
  436. unsigned short start; /* where polling starts */
  437. #define NO_FRAME ((unsigned short)~0) /* pick new start */
  438. struct usb_device *dev; /* access to TT */
  439. unsigned is_out:1; /* bulk or intr OUT */
  440. unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
  441. };
  442. /*-------------------------------------------------------------------------*/
  443. /* description of one iso transaction (up to 3 KB data if highspeed) */
  444. struct fusbh200_iso_packet {
  445. /* These will be copied to iTD when scheduling */
  446. u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
  447. __hc32 transaction; /* itd->hw_transaction[i] |= */
  448. u8 cross; /* buf crosses pages */
  449. /* for full speed OUT splits */
  450. u32 buf1;
  451. };
  452. /* temporary schedule data for packets from iso urbs (both speeds)
  453. * each packet is one logical usb transaction to the device (not TT),
  454. * beginning at stream->next_uframe
  455. */
  456. struct fusbh200_iso_sched {
  457. struct list_head td_list;
  458. unsigned span;
  459. struct fusbh200_iso_packet packet [0];
  460. };
  461. /*
  462. * fusbh200_iso_stream - groups all (s)itds for this endpoint.
  463. * acts like a qh would, if EHCI had them for ISO.
  464. */
  465. struct fusbh200_iso_stream {
  466. /* first field matches fusbh200_hq, but is NULL */
  467. struct fusbh200_qh_hw *hw;
  468. u8 bEndpointAddress;
  469. u8 highspeed;
  470. struct list_head td_list; /* queued itds */
  471. struct list_head free_list; /* list of unused itds */
  472. struct usb_device *udev;
  473. struct usb_host_endpoint *ep;
  474. /* output of (re)scheduling */
  475. int next_uframe;
  476. __hc32 splits;
  477. /* the rest is derived from the endpoint descriptor,
  478. * trusting urb->interval == f(epdesc->bInterval) and
  479. * including the extra info for hw_bufp[0..2]
  480. */
  481. u8 usecs, c_usecs;
  482. u16 interval;
  483. u16 tt_usecs;
  484. u16 maxp;
  485. u16 raw_mask;
  486. unsigned bandwidth;
  487. /* This is used to initialize iTD's hw_bufp fields */
  488. __hc32 buf0;
  489. __hc32 buf1;
  490. __hc32 buf2;
  491. /* this is used to initialize sITD's tt info */
  492. __hc32 address;
  493. };
  494. /*-------------------------------------------------------------------------*/
  495. /*
  496. * EHCI Specification 0.95 Section 3.3
  497. * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
  498. *
  499. * Schedule records for high speed iso xfers
  500. */
  501. struct fusbh200_itd {
  502. /* first part defined by EHCI spec */
  503. __hc32 hw_next; /* see EHCI 3.3.1 */
  504. __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
  505. #define FUSBH200_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
  506. #define FUSBH200_ISOC_BUF_ERR (1<<30) /* Data buffer error */
  507. #define FUSBH200_ISOC_BABBLE (1<<29) /* babble detected */
  508. #define FUSBH200_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
  509. #define FUSBH200_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
  510. #define FUSBH200_ITD_IOC (1 << 15) /* interrupt on complete */
  511. #define ITD_ACTIVE(fusbh200) cpu_to_hc32(fusbh200, FUSBH200_ISOC_ACTIVE)
  512. __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
  513. __hc32 hw_bufp_hi [7]; /* Appendix B */
  514. /* the rest is HCD-private */
  515. dma_addr_t itd_dma; /* for this itd */
  516. union fusbh200_shadow itd_next; /* ptr to periodic q entry */
  517. struct urb *urb;
  518. struct fusbh200_iso_stream *stream; /* endpoint's queue */
  519. struct list_head itd_list; /* list of stream's itds */
  520. /* any/all hw_transactions here may be used by that urb */
  521. unsigned frame; /* where scheduled */
  522. unsigned pg;
  523. unsigned index[8]; /* in urb->iso_frame_desc */
  524. } __attribute__ ((aligned (32)));
  525. /*-------------------------------------------------------------------------*/
  526. /*
  527. * EHCI Specification 0.96 Section 3.7
  528. * Periodic Frame Span Traversal Node (FSTN)
  529. *
  530. * Manages split interrupt transactions (using TT) that span frame boundaries
  531. * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
  532. * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
  533. * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
  534. */
  535. struct fusbh200_fstn {
  536. __hc32 hw_next; /* any periodic q entry */
  537. __hc32 hw_prev; /* qh or FUSBH200_LIST_END */
  538. /* the rest is HCD-private */
  539. dma_addr_t fstn_dma;
  540. union fusbh200_shadow fstn_next; /* ptr to periodic q entry */
  541. } __attribute__ ((aligned (32)));
  542. /*-------------------------------------------------------------------------*/
  543. /* Prepare the PORTSC wakeup flags during controller suspend/resume */
  544. #define fusbh200_prepare_ports_for_controller_suspend(fusbh200, do_wakeup) \
  545. fusbh200_adjust_port_wakeup_flags(fusbh200, true, do_wakeup);
  546. #define fusbh200_prepare_ports_for_controller_resume(fusbh200) \
  547. fusbh200_adjust_port_wakeup_flags(fusbh200, false, false);
  548. /*-------------------------------------------------------------------------*/
  549. /*
  550. * Some EHCI controllers have a Transaction Translator built into the
  551. * root hub. This is a non-standard feature. Each controller will need
  552. * to add code to the following inline functions, and call them as
  553. * needed (mostly in root hub code).
  554. */
  555. static inline unsigned int
  556. fusbh200_get_speed(struct fusbh200_hcd *fusbh200, unsigned int portsc)
  557. {
  558. return (readl(&fusbh200->regs->bmcsr)
  559. & BMCSR_HOST_SPD_TYP) >> 9;
  560. }
  561. /* Returns the speed of a device attached to a port on the root hub. */
  562. static inline unsigned int
  563. fusbh200_port_speed(struct fusbh200_hcd *fusbh200, unsigned int portsc)
  564. {
  565. switch (fusbh200_get_speed(fusbh200, portsc)) {
  566. case 0:
  567. return 0;
  568. case 1:
  569. return USB_PORT_STAT_LOW_SPEED;
  570. case 2:
  571. default:
  572. return USB_PORT_STAT_HIGH_SPEED;
  573. }
  574. }
  575. /*-------------------------------------------------------------------------*/
  576. #define fusbh200_has_fsl_portno_bug(e) (0)
  577. /*
  578. * While most USB host controllers implement their registers in
  579. * little-endian format, a minority (celleb companion chip) implement
  580. * them in big endian format.
  581. *
  582. * This attempts to support either format at compile time without a
  583. * runtime penalty, or both formats with the additional overhead
  584. * of checking a flag bit.
  585. *
  586. */
  587. #define fusbh200_big_endian_mmio(e) 0
  588. #define fusbh200_big_endian_capbase(e) 0
  589. static inline unsigned int fusbh200_readl(const struct fusbh200_hcd *fusbh200,
  590. __u32 __iomem * regs)
  591. {
  592. return readl(regs);
  593. }
  594. static inline void fusbh200_writel(const struct fusbh200_hcd *fusbh200,
  595. const unsigned int val, __u32 __iomem *regs)
  596. {
  597. writel(val, regs);
  598. }
  599. /* cpu to fusbh200 */
  600. static inline __hc32 cpu_to_hc32 (const struct fusbh200_hcd *fusbh200, const u32 x)
  601. {
  602. return cpu_to_le32(x);
  603. }
  604. /* fusbh200 to cpu */
  605. static inline u32 hc32_to_cpu (const struct fusbh200_hcd *fusbh200, const __hc32 x)
  606. {
  607. return le32_to_cpu(x);
  608. }
  609. static inline u32 hc32_to_cpup (const struct fusbh200_hcd *fusbh200, const __hc32 *x)
  610. {
  611. return le32_to_cpup(x);
  612. }
  613. /*-------------------------------------------------------------------------*/
  614. static inline unsigned fusbh200_read_frame_index(struct fusbh200_hcd *fusbh200)
  615. {
  616. return fusbh200_readl(fusbh200, &fusbh200->regs->frame_index);
  617. }
  618. #define fusbh200_itdlen(urb, desc, t) ({ \
  619. usb_pipein((urb)->pipe) ? \
  620. (desc)->length - FUSBH200_ITD_LENGTH(t) : \
  621. FUSBH200_ITD_LENGTH(t); \
  622. })
  623. /*-------------------------------------------------------------------------*/
  624. #ifndef DEBUG
  625. #define STUB_DEBUG_FILES
  626. #endif /* DEBUG */
  627. /*-------------------------------------------------------------------------*/
  628. #endif /* __LINUX_FUSBH200_H */