ehci.h 26 KB

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  1. /*
  2. * Copyright (c) 2001-2002 by David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the
  6. * Free Software Foundation; either version 2 of the License, or (at your
  7. * option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software Foundation,
  16. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. #ifndef __LINUX_EHCI_HCD_H
  19. #define __LINUX_EHCI_HCD_H
  20. /* definitions used for the EHCI driver */
  21. /*
  22. * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  23. * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  24. * the host controller implementation.
  25. *
  26. * To facilitate the strongest possible byte-order checking from "sparse"
  27. * and so on, we use __leXX unless that's not practical.
  28. */
  29. #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  30. typedef __u32 __bitwise __hc32;
  31. typedef __u16 __bitwise __hc16;
  32. #else
  33. #define __hc32 __le32
  34. #define __hc16 __le16
  35. #endif
  36. /* statistics can be kept for tuning/monitoring */
  37. #ifdef DEBUG
  38. #define EHCI_STATS
  39. #endif
  40. struct ehci_stats {
  41. /* irq usage */
  42. unsigned long normal;
  43. unsigned long error;
  44. unsigned long iaa;
  45. unsigned long lost_iaa;
  46. /* termination of urbs from core */
  47. unsigned long complete;
  48. unsigned long unlink;
  49. };
  50. /* ehci_hcd->lock guards shared data against other CPUs:
  51. * ehci_hcd: async, unlink, periodic (and shadow), ...
  52. * usb_host_endpoint: hcpriv
  53. * ehci_qh: qh_next, qtd_list
  54. * ehci_qtd: qtd_list
  55. *
  56. * Also, hold this lock when talking to HC registers or
  57. * when updating hw_* fields in shared qh/qtd/... structures.
  58. */
  59. #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
  60. /*
  61. * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
  62. * controller may be doing DMA. Lower values mean there's no DMA.
  63. */
  64. enum ehci_rh_state {
  65. EHCI_RH_HALTED,
  66. EHCI_RH_SUSPENDED,
  67. EHCI_RH_RUNNING,
  68. EHCI_RH_STOPPING
  69. };
  70. /*
  71. * Timer events, ordered by increasing delay length.
  72. * Always update event_delays_ns[] and event_handlers[] (defined in
  73. * ehci-timer.c) in parallel with this list.
  74. */
  75. enum ehci_hrtimer_event {
  76. EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */
  77. EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
  78. EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
  79. EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
  80. EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
  81. EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
  82. EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
  83. EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
  84. EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
  85. EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
  86. EHCI_HRTIMER_NUM_EVENTS /* Must come last */
  87. };
  88. #define EHCI_HRTIMER_NO_EVENT 99
  89. struct ehci_hcd { /* one per controller */
  90. /* timing support */
  91. enum ehci_hrtimer_event next_hrtimer_event;
  92. unsigned enabled_hrtimer_events;
  93. ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
  94. struct hrtimer hrtimer;
  95. int PSS_poll_count;
  96. int ASS_poll_count;
  97. int died_poll_count;
  98. /* glue to PCI and HCD framework */
  99. struct ehci_caps __iomem *caps;
  100. struct ehci_regs __iomem *regs;
  101. struct ehci_dbg_port __iomem *debug;
  102. __u32 hcs_params; /* cached register copy */
  103. spinlock_t lock;
  104. enum ehci_rh_state rh_state;
  105. /* general schedule support */
  106. bool scanning:1;
  107. bool need_rescan:1;
  108. bool intr_unlinking:1;
  109. bool iaa_in_progress:1;
  110. bool async_unlinking:1;
  111. bool shutdown:1;
  112. struct ehci_qh *qh_scan_next;
  113. /* async schedule support */
  114. struct ehci_qh *async;
  115. struct ehci_qh *dummy; /* For AMD quirk use */
  116. struct list_head async_unlink;
  117. struct list_head async_idle;
  118. unsigned async_unlink_cycle;
  119. unsigned async_count; /* async activity count */
  120. /* periodic schedule support */
  121. #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
  122. unsigned periodic_size;
  123. __hc32 *periodic; /* hw periodic table */
  124. dma_addr_t periodic_dma;
  125. struct list_head intr_qh_list;
  126. unsigned i_thresh; /* uframes HC might cache */
  127. union ehci_shadow *pshadow; /* mirror hw periodic table */
  128. struct list_head intr_unlink;
  129. unsigned intr_unlink_cycle;
  130. unsigned now_frame; /* frame from HC hardware */
  131. unsigned last_iso_frame; /* last frame scanned for iso */
  132. unsigned intr_count; /* intr activity count */
  133. unsigned isoc_count; /* isoc activity count */
  134. unsigned periodic_count; /* periodic activity count */
  135. unsigned uframe_periodic_max; /* max periodic time per uframe */
  136. /* list of itds & sitds completed while now_frame was still active */
  137. struct list_head cached_itd_list;
  138. struct ehci_itd *last_itd_to_free;
  139. struct list_head cached_sitd_list;
  140. struct ehci_sitd *last_sitd_to_free;
  141. /* per root hub port */
  142. unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
  143. /* bit vectors (one bit per port) */
  144. unsigned long bus_suspended; /* which ports were
  145. already suspended at the start of a bus suspend */
  146. unsigned long companion_ports; /* which ports are
  147. dedicated to the companion controller */
  148. unsigned long owned_ports; /* which ports are
  149. owned by the companion during a bus suspend */
  150. unsigned long port_c_suspend; /* which ports have
  151. the change-suspend feature turned on */
  152. unsigned long suspended_ports; /* which ports are
  153. suspended */
  154. unsigned long resuming_ports; /* which ports have
  155. started to resume */
  156. /* per-HC memory pools (could be per-bus, but ...) */
  157. struct dma_pool *qh_pool; /* qh per active urb */
  158. struct dma_pool *qtd_pool; /* one or more per qh */
  159. struct dma_pool *itd_pool; /* itd per iso urb */
  160. struct dma_pool *sitd_pool; /* sitd per split iso urb */
  161. unsigned random_frame;
  162. unsigned long next_statechange;
  163. ktime_t last_periodic_enable;
  164. u32 command;
  165. /* SILICON QUIRKS */
  166. unsigned no_selective_suspend:1;
  167. unsigned has_fsl_port_bug:1; /* FreeScale */
  168. unsigned big_endian_mmio:1;
  169. unsigned big_endian_desc:1;
  170. unsigned big_endian_capbase:1;
  171. unsigned has_amcc_usb23:1;
  172. unsigned need_io_watchdog:1;
  173. unsigned amd_pll_fix:1;
  174. unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
  175. unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
  176. unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */
  177. unsigned need_oc_pp_cycle:1; /* MPC834X port power */
  178. /* required for usb32 quirk */
  179. #define OHCI_CTRL_HCFS (3 << 6)
  180. #define OHCI_USB_OPER (2 << 6)
  181. #define OHCI_USB_SUSPEND (3 << 6)
  182. #define OHCI_HCCTRL_OFFSET 0x4
  183. #define OHCI_HCCTRL_LEN 0x4
  184. __hc32 *ohci_hcctrl_reg;
  185. unsigned has_hostpc:1;
  186. unsigned has_ppcd:1; /* support per-port change bits */
  187. u8 sbrn; /* packed release number */
  188. /* irq statistics */
  189. #ifdef EHCI_STATS
  190. struct ehci_stats stats;
  191. # define COUNT(x) do { (x)++; } while (0)
  192. #else
  193. # define COUNT(x) do {} while (0)
  194. #endif
  195. /* debug files */
  196. #ifdef DEBUG
  197. struct dentry *debug_dir;
  198. #endif
  199. /* platform-specific data -- must come last */
  200. unsigned long priv[0] __aligned(sizeof(s64));
  201. };
  202. /* convert between an HCD pointer and the corresponding EHCI_HCD */
  203. static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
  204. {
  205. return (struct ehci_hcd *) (hcd->hcd_priv);
  206. }
  207. static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
  208. {
  209. return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
  210. }
  211. /*-------------------------------------------------------------------------*/
  212. #include <linux/usb/ehci_def.h>
  213. /*-------------------------------------------------------------------------*/
  214. #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
  215. /*
  216. * EHCI Specification 0.95 Section 3.5
  217. * QTD: describe data transfer components (buffer, direction, ...)
  218. * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
  219. *
  220. * These are associated only with "QH" (Queue Head) structures,
  221. * used with control, bulk, and interrupt transfers.
  222. */
  223. struct ehci_qtd {
  224. /* first part defined by EHCI spec */
  225. __hc32 hw_next; /* see EHCI 3.5.1 */
  226. __hc32 hw_alt_next; /* see EHCI 3.5.2 */
  227. __hc32 hw_token; /* see EHCI 3.5.3 */
  228. #define QTD_TOGGLE (1 << 31) /* data toggle */
  229. #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
  230. #define QTD_IOC (1 << 15) /* interrupt on complete */
  231. #define QTD_CERR(tok) (((tok)>>10) & 0x3)
  232. #define QTD_PID(tok) (((tok)>>8) & 0x3)
  233. #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
  234. #define QTD_STS_HALT (1 << 6) /* halted on error */
  235. #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
  236. #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
  237. #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
  238. #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
  239. #define QTD_STS_STS (1 << 1) /* split transaction state */
  240. #define QTD_STS_PING (1 << 0) /* issue PING? */
  241. #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
  242. #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
  243. #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
  244. __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
  245. __hc32 hw_buf_hi [5]; /* Appendix B */
  246. /* the rest is HCD-private */
  247. dma_addr_t qtd_dma; /* qtd address */
  248. struct list_head qtd_list; /* sw qtd list */
  249. struct urb *urb; /* qtd's urb */
  250. size_t length; /* length of buffer */
  251. } __attribute__ ((aligned (32)));
  252. /* mask NakCnt+T in qh->hw_alt_next */
  253. #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
  254. #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
  255. /*-------------------------------------------------------------------------*/
  256. /* type tag from {qh,itd,sitd,fstn}->hw_next */
  257. #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
  258. /*
  259. * Now the following defines are not converted using the
  260. * cpu_to_le32() macro anymore, since we have to support
  261. * "dynamic" switching between be and le support, so that the driver
  262. * can be used on one system with SoC EHCI controller using big-endian
  263. * descriptors as well as a normal little-endian PCI EHCI controller.
  264. */
  265. /* values for that type tag */
  266. #define Q_TYPE_ITD (0 << 1)
  267. #define Q_TYPE_QH (1 << 1)
  268. #define Q_TYPE_SITD (2 << 1)
  269. #define Q_TYPE_FSTN (3 << 1)
  270. /* next async queue entry, or pointer to interrupt/periodic QH */
  271. #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
  272. /* for periodic/async schedules and qtd lists, mark end of list */
  273. #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
  274. /*
  275. * Entries in periodic shadow table are pointers to one of four kinds
  276. * of data structure. That's dictated by the hardware; a type tag is
  277. * encoded in the low bits of the hardware's periodic schedule. Use
  278. * Q_NEXT_TYPE to get the tag.
  279. *
  280. * For entries in the async schedule, the type tag always says "qh".
  281. */
  282. union ehci_shadow {
  283. struct ehci_qh *qh; /* Q_TYPE_QH */
  284. struct ehci_itd *itd; /* Q_TYPE_ITD */
  285. struct ehci_sitd *sitd; /* Q_TYPE_SITD */
  286. struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
  287. __hc32 *hw_next; /* (all types) */
  288. void *ptr;
  289. };
  290. /*-------------------------------------------------------------------------*/
  291. /*
  292. * EHCI Specification 0.95 Section 3.6
  293. * QH: describes control/bulk/interrupt endpoints
  294. * See Fig 3-7 "Queue Head Structure Layout".
  295. *
  296. * These appear in both the async and (for interrupt) periodic schedules.
  297. */
  298. /* first part defined by EHCI spec */
  299. struct ehci_qh_hw {
  300. __hc32 hw_next; /* see EHCI 3.6.1 */
  301. __hc32 hw_info1; /* see EHCI 3.6.2 */
  302. #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
  303. #define QH_HEAD (1 << 15) /* Head of async reclamation list */
  304. #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
  305. #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
  306. #define QH_LOW_SPEED (1 << 12)
  307. #define QH_FULL_SPEED (0 << 12)
  308. #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
  309. __hc32 hw_info2; /* see EHCI 3.6.2 */
  310. #define QH_SMASK 0x000000ff
  311. #define QH_CMASK 0x0000ff00
  312. #define QH_HUBADDR 0x007f0000
  313. #define QH_HUBPORT 0x3f800000
  314. #define QH_MULT 0xc0000000
  315. __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
  316. /* qtd overlay (hardware parts of a struct ehci_qtd) */
  317. __hc32 hw_qtd_next;
  318. __hc32 hw_alt_next;
  319. __hc32 hw_token;
  320. __hc32 hw_buf [5];
  321. __hc32 hw_buf_hi [5];
  322. } __attribute__ ((aligned(32)));
  323. struct ehci_qh {
  324. struct ehci_qh_hw *hw; /* Must come first */
  325. /* the rest is HCD-private */
  326. dma_addr_t qh_dma; /* address of qh */
  327. union ehci_shadow qh_next; /* ptr to qh; or periodic */
  328. struct list_head qtd_list; /* sw qtd list */
  329. struct list_head intr_node; /* list of intr QHs */
  330. struct ehci_qtd *dummy;
  331. struct list_head unlink_node;
  332. unsigned unlink_cycle;
  333. u8 qh_state;
  334. #define QH_STATE_LINKED 1 /* HC sees this */
  335. #define QH_STATE_UNLINK 2 /* HC may still see this */
  336. #define QH_STATE_IDLE 3 /* HC doesn't see this */
  337. #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
  338. #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
  339. u8 xacterrs; /* XactErr retry counter */
  340. #define QH_XACTERR_MAX 32 /* XactErr retry limit */
  341. /* periodic schedule info */
  342. u8 usecs; /* intr bandwidth */
  343. u8 gap_uf; /* uframes split/csplit gap */
  344. u8 c_usecs; /* ... split completion bw */
  345. u16 tt_usecs; /* tt downstream bandwidth */
  346. unsigned short period; /* polling interval */
  347. unsigned short start; /* where polling starts */
  348. #define NO_FRAME ((unsigned short)~0) /* pick new start */
  349. struct usb_device *dev; /* access to TT */
  350. unsigned is_out:1; /* bulk or intr OUT */
  351. unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
  352. unsigned dequeue_during_giveback:1;
  353. unsigned exception:1; /* got a fault, or an unlink
  354. was requested */
  355. };
  356. /*-------------------------------------------------------------------------*/
  357. /* description of one iso transaction (up to 3 KB data if highspeed) */
  358. struct ehci_iso_packet {
  359. /* These will be copied to iTD when scheduling */
  360. u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
  361. __hc32 transaction; /* itd->hw_transaction[i] |= */
  362. u8 cross; /* buf crosses pages */
  363. /* for full speed OUT splits */
  364. u32 buf1;
  365. };
  366. /* temporary schedule data for packets from iso urbs (both speeds)
  367. * each packet is one logical usb transaction to the device (not TT),
  368. * beginning at stream->next_uframe
  369. */
  370. struct ehci_iso_sched {
  371. struct list_head td_list;
  372. unsigned span;
  373. struct ehci_iso_packet packet [0];
  374. };
  375. /*
  376. * ehci_iso_stream - groups all (s)itds for this endpoint.
  377. * acts like a qh would, if EHCI had them for ISO.
  378. */
  379. struct ehci_iso_stream {
  380. /* first field matches ehci_hq, but is NULL */
  381. struct ehci_qh_hw *hw;
  382. u8 bEndpointAddress;
  383. u8 highspeed;
  384. struct list_head td_list; /* queued itds/sitds */
  385. struct list_head free_list; /* list of unused itds/sitds */
  386. struct usb_device *udev;
  387. struct usb_host_endpoint *ep;
  388. /* output of (re)scheduling */
  389. int next_uframe;
  390. __hc32 splits;
  391. /* the rest is derived from the endpoint descriptor,
  392. * trusting urb->interval == f(epdesc->bInterval) and
  393. * including the extra info for hw_bufp[0..2]
  394. */
  395. u8 usecs, c_usecs;
  396. u16 interval;
  397. u16 tt_usecs;
  398. u16 maxp;
  399. u16 raw_mask;
  400. unsigned bandwidth;
  401. /* This is used to initialize iTD's hw_bufp fields */
  402. __hc32 buf0;
  403. __hc32 buf1;
  404. __hc32 buf2;
  405. /* this is used to initialize sITD's tt info */
  406. __hc32 address;
  407. };
  408. /*-------------------------------------------------------------------------*/
  409. /*
  410. * EHCI Specification 0.95 Section 3.3
  411. * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
  412. *
  413. * Schedule records for high speed iso xfers
  414. */
  415. struct ehci_itd {
  416. /* first part defined by EHCI spec */
  417. __hc32 hw_next; /* see EHCI 3.3.1 */
  418. __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
  419. #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
  420. #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
  421. #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
  422. #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
  423. #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
  424. #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
  425. #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
  426. __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
  427. __hc32 hw_bufp_hi [7]; /* Appendix B */
  428. /* the rest is HCD-private */
  429. dma_addr_t itd_dma; /* for this itd */
  430. union ehci_shadow itd_next; /* ptr to periodic q entry */
  431. struct urb *urb;
  432. struct ehci_iso_stream *stream; /* endpoint's queue */
  433. struct list_head itd_list; /* list of stream's itds */
  434. /* any/all hw_transactions here may be used by that urb */
  435. unsigned frame; /* where scheduled */
  436. unsigned pg;
  437. unsigned index[8]; /* in urb->iso_frame_desc */
  438. } __attribute__ ((aligned (32)));
  439. /*-------------------------------------------------------------------------*/
  440. /*
  441. * EHCI Specification 0.95 Section 3.4
  442. * siTD, aka split-transaction isochronous Transfer Descriptor
  443. * ... describe full speed iso xfers through TT in hubs
  444. * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
  445. */
  446. struct ehci_sitd {
  447. /* first part defined by EHCI spec */
  448. __hc32 hw_next;
  449. /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
  450. __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
  451. __hc32 hw_uframe; /* EHCI table 3-10 */
  452. __hc32 hw_results; /* EHCI table 3-11 */
  453. #define SITD_IOC (1 << 31) /* interrupt on completion */
  454. #define SITD_PAGE (1 << 30) /* buffer 0/1 */
  455. #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
  456. #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
  457. #define SITD_STS_ERR (1 << 6) /* error from TT */
  458. #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
  459. #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
  460. #define SITD_STS_XACT (1 << 3) /* illegal IN response */
  461. #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
  462. #define SITD_STS_STS (1 << 1) /* split transaction state */
  463. #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
  464. __hc32 hw_buf [2]; /* EHCI table 3-12 */
  465. __hc32 hw_backpointer; /* EHCI table 3-13 */
  466. __hc32 hw_buf_hi [2]; /* Appendix B */
  467. /* the rest is HCD-private */
  468. dma_addr_t sitd_dma;
  469. union ehci_shadow sitd_next; /* ptr to periodic q entry */
  470. struct urb *urb;
  471. struct ehci_iso_stream *stream; /* endpoint's queue */
  472. struct list_head sitd_list; /* list of stream's sitds */
  473. unsigned frame;
  474. unsigned index;
  475. } __attribute__ ((aligned (32)));
  476. /*-------------------------------------------------------------------------*/
  477. /*
  478. * EHCI Specification 0.96 Section 3.7
  479. * Periodic Frame Span Traversal Node (FSTN)
  480. *
  481. * Manages split interrupt transactions (using TT) that span frame boundaries
  482. * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
  483. * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
  484. * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
  485. */
  486. struct ehci_fstn {
  487. __hc32 hw_next; /* any periodic q entry */
  488. __hc32 hw_prev; /* qh or EHCI_LIST_END */
  489. /* the rest is HCD-private */
  490. dma_addr_t fstn_dma;
  491. union ehci_shadow fstn_next; /* ptr to periodic q entry */
  492. } __attribute__ ((aligned (32)));
  493. /*-------------------------------------------------------------------------*/
  494. /* Prepare the PORTSC wakeup flags during controller suspend/resume */
  495. #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
  496. ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
  497. #define ehci_prepare_ports_for_controller_resume(ehci) \
  498. ehci_adjust_port_wakeup_flags(ehci, false, false);
  499. /*-------------------------------------------------------------------------*/
  500. #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
  501. /*
  502. * Some EHCI controllers have a Transaction Translator built into the
  503. * root hub. This is a non-standard feature. Each controller will need
  504. * to add code to the following inline functions, and call them as
  505. * needed (mostly in root hub code).
  506. */
  507. #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
  508. /* Returns the speed of a device attached to a port on the root hub. */
  509. static inline unsigned int
  510. ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
  511. {
  512. if (ehci_is_TDI(ehci)) {
  513. switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
  514. case 0:
  515. return 0;
  516. case 1:
  517. return USB_PORT_STAT_LOW_SPEED;
  518. case 2:
  519. default:
  520. return USB_PORT_STAT_HIGH_SPEED;
  521. }
  522. }
  523. return USB_PORT_STAT_HIGH_SPEED;
  524. }
  525. #else
  526. #define ehci_is_TDI(e) (0)
  527. #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
  528. #endif
  529. /*-------------------------------------------------------------------------*/
  530. #ifdef CONFIG_PPC_83xx
  531. /* Some Freescale processors have an erratum in which the TT
  532. * port number in the queue head was 0..N-1 instead of 1..N.
  533. */
  534. #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
  535. #else
  536. #define ehci_has_fsl_portno_bug(e) (0)
  537. #endif
  538. /*
  539. * While most USB host controllers implement their registers in
  540. * little-endian format, a minority (celleb companion chip) implement
  541. * them in big endian format.
  542. *
  543. * This attempts to support either format at compile time without a
  544. * runtime penalty, or both formats with the additional overhead
  545. * of checking a flag bit.
  546. *
  547. * ehci_big_endian_capbase is a special quirk for controllers that
  548. * implement the HC capability registers as separate registers and not
  549. * as fields of a 32-bit register.
  550. */
  551. #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  552. #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
  553. #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
  554. #else
  555. #define ehci_big_endian_mmio(e) 0
  556. #define ehci_big_endian_capbase(e) 0
  557. #endif
  558. /*
  559. * Big-endian read/write functions are arch-specific.
  560. * Other arches can be added if/when they're needed.
  561. */
  562. #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
  563. #define readl_be(addr) __raw_readl((__force unsigned *)addr)
  564. #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
  565. #endif
  566. static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
  567. __u32 __iomem * regs)
  568. {
  569. #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  570. return ehci_big_endian_mmio(ehci) ?
  571. readl_be(regs) :
  572. readl(regs);
  573. #else
  574. return readl(regs);
  575. #endif
  576. }
  577. static inline void ehci_writel(const struct ehci_hcd *ehci,
  578. const unsigned int val, __u32 __iomem *regs)
  579. {
  580. #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  581. ehci_big_endian_mmio(ehci) ?
  582. writel_be(val, regs) :
  583. writel(val, regs);
  584. #else
  585. writel(val, regs);
  586. #endif
  587. }
  588. /*
  589. * On certain ppc-44x SoC there is a HW issue, that could only worked around with
  590. * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
  591. * Other common bits are dependent on has_amcc_usb23 quirk flag.
  592. */
  593. #ifdef CONFIG_44x
  594. static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
  595. {
  596. u32 hc_control;
  597. hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
  598. if (operational)
  599. hc_control |= OHCI_USB_OPER;
  600. else
  601. hc_control |= OHCI_USB_SUSPEND;
  602. writel_be(hc_control, ehci->ohci_hcctrl_reg);
  603. (void) readl_be(ehci->ohci_hcctrl_reg);
  604. }
  605. #else
  606. static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
  607. { }
  608. #endif
  609. /*-------------------------------------------------------------------------*/
  610. /*
  611. * The AMCC 440EPx not only implements its EHCI registers in big-endian
  612. * format, but also its DMA data structures (descriptors).
  613. *
  614. * EHCI controllers accessed through PCI work normally (little-endian
  615. * everywhere), so we won't bother supporting a BE-only mode for now.
  616. */
  617. #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  618. #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
  619. /* cpu to ehci */
  620. static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
  621. {
  622. return ehci_big_endian_desc(ehci)
  623. ? (__force __hc32)cpu_to_be32(x)
  624. : (__force __hc32)cpu_to_le32(x);
  625. }
  626. /* ehci to cpu */
  627. static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
  628. {
  629. return ehci_big_endian_desc(ehci)
  630. ? be32_to_cpu((__force __be32)x)
  631. : le32_to_cpu((__force __le32)x);
  632. }
  633. static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
  634. {
  635. return ehci_big_endian_desc(ehci)
  636. ? be32_to_cpup((__force __be32 *)x)
  637. : le32_to_cpup((__force __le32 *)x);
  638. }
  639. #else
  640. /* cpu to ehci */
  641. static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
  642. {
  643. return cpu_to_le32(x);
  644. }
  645. /* ehci to cpu */
  646. static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
  647. {
  648. return le32_to_cpu(x);
  649. }
  650. static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
  651. {
  652. return le32_to_cpup(x);
  653. }
  654. #endif
  655. /*-------------------------------------------------------------------------*/
  656. #define ehci_dbg(ehci, fmt, args...) \
  657. dev_dbg(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
  658. #define ehci_err(ehci, fmt, args...) \
  659. dev_err(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
  660. #define ehci_info(ehci, fmt, args...) \
  661. dev_info(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
  662. #define ehci_warn(ehci, fmt, args...) \
  663. dev_warn(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
  664. #ifdef VERBOSE_DEBUG
  665. # define ehci_vdbg ehci_dbg
  666. #else
  667. static inline void ehci_vdbg(struct ehci_hcd *ehci, ...) {}
  668. #endif
  669. #ifndef DEBUG
  670. #define STUB_DEBUG_FILES
  671. #endif /* DEBUG */
  672. /*-------------------------------------------------------------------------*/
  673. /* Declarations of things exported for use by ehci platform drivers */
  674. struct ehci_driver_overrides {
  675. size_t extra_priv_size;
  676. int (*reset)(struct usb_hcd *hcd);
  677. };
  678. extern void ehci_init_driver(struct hc_driver *drv,
  679. const struct ehci_driver_overrides *over);
  680. extern int ehci_setup(struct usb_hcd *hcd);
  681. extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
  682. u32 mask, u32 done, int usec);
  683. #ifdef CONFIG_PM
  684. extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
  685. extern int ehci_resume(struct usb_hcd *hcd, bool hibernated);
  686. #endif /* CONFIG_PM */
  687. #endif /* __LINUX_EHCI_HCD_H */