omap_udc.c 76 KB

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  1. /*
  2. * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
  3. *
  4. * Copyright (C) 2004 Texas Instruments, Inc.
  5. * Copyright (C) 2004-2005 David Brownell
  6. *
  7. * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #undef DEBUG
  15. #undef VERBOSE
  16. #include <linux/module.h>
  17. #include <linux/kernel.h>
  18. #include <linux/ioport.h>
  19. #include <linux/types.h>
  20. #include <linux/errno.h>
  21. #include <linux/delay.h>
  22. #include <linux/slab.h>
  23. #include <linux/init.h>
  24. #include <linux/timer.h>
  25. #include <linux/list.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/proc_fs.h>
  28. #include <linux/mm.h>
  29. #include <linux/moduleparam.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/usb/ch9.h>
  32. #include <linux/usb/gadget.h>
  33. #include <linux/usb/otg.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/clk.h>
  36. #include <linux/err.h>
  37. #include <linux/prefetch.h>
  38. #include <linux/io.h>
  39. #include <asm/byteorder.h>
  40. #include <asm/irq.h>
  41. #include <asm/unaligned.h>
  42. #include <asm/mach-types.h>
  43. #include <linux/omap-dma.h>
  44. #include <mach/usb.h>
  45. #include "omap_udc.h"
  46. #undef USB_TRACE
  47. /* bulk DMA seems to be behaving for both IN and OUT */
  48. #define USE_DMA
  49. /* ISO too */
  50. #define USE_ISO
  51. #define DRIVER_DESC "OMAP UDC driver"
  52. #define DRIVER_VERSION "4 October 2004"
  53. #define OMAP_DMA_USB_W2FC_TX0 29
  54. #define OMAP_DMA_USB_W2FC_RX0 26
  55. /*
  56. * The OMAP UDC needs _very_ early endpoint setup: before enabling the
  57. * D+ pullup to allow enumeration. That's too early for the gadget
  58. * framework to use from usb_endpoint_enable(), which happens after
  59. * enumeration as part of activating an interface. (But if we add an
  60. * optional new "UDC not yet running" state to the gadget driver model,
  61. * even just during driver binding, the endpoint autoconfig logic is the
  62. * natural spot to manufacture new endpoints.)
  63. *
  64. * So instead of using endpoint enable calls to control the hardware setup,
  65. * this driver defines a "fifo mode" parameter. It's used during driver
  66. * initialization to choose among a set of pre-defined endpoint configs.
  67. * See omap_udc_setup() for available modes, or to add others. That code
  68. * lives in an init section, so use this driver as a module if you need
  69. * to change the fifo mode after the kernel boots.
  70. *
  71. * Gadget drivers normally ignore endpoints they don't care about, and
  72. * won't include them in configuration descriptors. That means only
  73. * misbehaving hosts would even notice they exist.
  74. */
  75. #ifdef USE_ISO
  76. static unsigned fifo_mode = 3;
  77. #else
  78. static unsigned fifo_mode;
  79. #endif
  80. /* "modprobe omap_udc fifo_mode=42", or else as a kernel
  81. * boot parameter "omap_udc:fifo_mode=42"
  82. */
  83. module_param(fifo_mode, uint, 0);
  84. MODULE_PARM_DESC(fifo_mode, "endpoint configuration");
  85. #ifdef USE_DMA
  86. static bool use_dma = 1;
  87. /* "modprobe omap_udc use_dma=y", or else as a kernel
  88. * boot parameter "omap_udc:use_dma=y"
  89. */
  90. module_param(use_dma, bool, 0);
  91. MODULE_PARM_DESC(use_dma, "enable/disable DMA");
  92. #else /* !USE_DMA */
  93. /* save a bit of code */
  94. #define use_dma 0
  95. #endif /* !USE_DMA */
  96. static const char driver_name[] = "omap_udc";
  97. static const char driver_desc[] = DRIVER_DESC;
  98. /*-------------------------------------------------------------------------*/
  99. /* there's a notion of "current endpoint" for modifying endpoint
  100. * state, and PIO access to its FIFO.
  101. */
  102. static void use_ep(struct omap_ep *ep, u16 select)
  103. {
  104. u16 num = ep->bEndpointAddress & 0x0f;
  105. if (ep->bEndpointAddress & USB_DIR_IN)
  106. num |= UDC_EP_DIR;
  107. omap_writew(num | select, UDC_EP_NUM);
  108. /* when select, MUST deselect later !! */
  109. }
  110. static inline void deselect_ep(void)
  111. {
  112. u16 w;
  113. w = omap_readw(UDC_EP_NUM);
  114. w &= ~UDC_EP_SEL;
  115. omap_writew(w, UDC_EP_NUM);
  116. /* 6 wait states before TX will happen */
  117. }
  118. static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
  119. /*-------------------------------------------------------------------------*/
  120. static int omap_ep_enable(struct usb_ep *_ep,
  121. const struct usb_endpoint_descriptor *desc)
  122. {
  123. struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
  124. struct omap_udc *udc;
  125. unsigned long flags;
  126. u16 maxp;
  127. /* catch various bogus parameters */
  128. if (!_ep || !desc
  129. || desc->bDescriptorType != USB_DT_ENDPOINT
  130. || ep->bEndpointAddress != desc->bEndpointAddress
  131. || ep->maxpacket < usb_endpoint_maxp(desc)) {
  132. DBG("%s, bad ep or descriptor\n", __func__);
  133. return -EINVAL;
  134. }
  135. maxp = usb_endpoint_maxp(desc);
  136. if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
  137. && maxp != ep->maxpacket)
  138. || usb_endpoint_maxp(desc) > ep->maxpacket
  139. || !desc->wMaxPacketSize) {
  140. DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
  141. return -ERANGE;
  142. }
  143. #ifdef USE_ISO
  144. if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
  145. && desc->bInterval != 1)) {
  146. /* hardware wants period = 1; USB allows 2^(Interval-1) */
  147. DBG("%s, unsupported ISO period %dms\n", _ep->name,
  148. 1 << (desc->bInterval - 1));
  149. return -EDOM;
  150. }
  151. #else
  152. if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
  153. DBG("%s, ISO nyet\n", _ep->name);
  154. return -EDOM;
  155. }
  156. #endif
  157. /* xfer types must match, except that interrupt ~= bulk */
  158. if (ep->bmAttributes != desc->bmAttributes
  159. && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
  160. && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
  161. DBG("%s, %s type mismatch\n", __func__, _ep->name);
  162. return -EINVAL;
  163. }
  164. udc = ep->udc;
  165. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
  166. DBG("%s, bogus device state\n", __func__);
  167. return -ESHUTDOWN;
  168. }
  169. spin_lock_irqsave(&udc->lock, flags);
  170. ep->ep.desc = desc;
  171. ep->irqs = 0;
  172. ep->stopped = 0;
  173. ep->ep.maxpacket = maxp;
  174. /* set endpoint to initial state */
  175. ep->dma_channel = 0;
  176. ep->has_dma = 0;
  177. ep->lch = -1;
  178. use_ep(ep, UDC_EP_SEL);
  179. omap_writew(udc->clr_halt, UDC_CTRL);
  180. ep->ackwait = 0;
  181. deselect_ep();
  182. if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
  183. list_add(&ep->iso, &udc->iso);
  184. /* maybe assign a DMA channel to this endpoint */
  185. if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
  186. /* FIXME ISO can dma, but prefers first channel */
  187. dma_channel_claim(ep, 0);
  188. /* PIO OUT may RX packets */
  189. if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
  190. && !ep->has_dma
  191. && !(ep->bEndpointAddress & USB_DIR_IN)) {
  192. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  193. ep->ackwait = 1 + ep->double_buf;
  194. }
  195. spin_unlock_irqrestore(&udc->lock, flags);
  196. VDBG("%s enabled\n", _ep->name);
  197. return 0;
  198. }
  199. static void nuke(struct omap_ep *, int status);
  200. static int omap_ep_disable(struct usb_ep *_ep)
  201. {
  202. struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
  203. unsigned long flags;
  204. if (!_ep || !ep->ep.desc) {
  205. DBG("%s, %s not enabled\n", __func__,
  206. _ep ? ep->ep.name : NULL);
  207. return -EINVAL;
  208. }
  209. spin_lock_irqsave(&ep->udc->lock, flags);
  210. ep->ep.desc = NULL;
  211. nuke(ep, -ESHUTDOWN);
  212. ep->ep.maxpacket = ep->maxpacket;
  213. ep->has_dma = 0;
  214. omap_writew(UDC_SET_HALT, UDC_CTRL);
  215. list_del_init(&ep->iso);
  216. del_timer(&ep->timer);
  217. spin_unlock_irqrestore(&ep->udc->lock, flags);
  218. VDBG("%s disabled\n", _ep->name);
  219. return 0;
  220. }
  221. /*-------------------------------------------------------------------------*/
  222. static struct usb_request *
  223. omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  224. {
  225. struct omap_req *req;
  226. req = kzalloc(sizeof(*req), gfp_flags);
  227. if (!req)
  228. return NULL;
  229. INIT_LIST_HEAD(&req->queue);
  230. return &req->req;
  231. }
  232. static void
  233. omap_free_request(struct usb_ep *ep, struct usb_request *_req)
  234. {
  235. struct omap_req *req = container_of(_req, struct omap_req, req);
  236. kfree(req);
  237. }
  238. /*-------------------------------------------------------------------------*/
  239. static void
  240. done(struct omap_ep *ep, struct omap_req *req, int status)
  241. {
  242. struct omap_udc *udc = ep->udc;
  243. unsigned stopped = ep->stopped;
  244. list_del_init(&req->queue);
  245. if (req->req.status == -EINPROGRESS)
  246. req->req.status = status;
  247. else
  248. status = req->req.status;
  249. if (use_dma && ep->has_dma)
  250. usb_gadget_unmap_request(&udc->gadget, &req->req,
  251. (ep->bEndpointAddress & USB_DIR_IN));
  252. #ifndef USB_TRACE
  253. if (status && status != -ESHUTDOWN)
  254. #endif
  255. VDBG("complete %s req %p stat %d len %u/%u\n",
  256. ep->ep.name, &req->req, status,
  257. req->req.actual, req->req.length);
  258. /* don't modify queue heads during completion callback */
  259. ep->stopped = 1;
  260. spin_unlock(&ep->udc->lock);
  261. req->req.complete(&ep->ep, &req->req);
  262. spin_lock(&ep->udc->lock);
  263. ep->stopped = stopped;
  264. }
  265. /*-------------------------------------------------------------------------*/
  266. #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
  267. #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
  268. #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
  269. #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
  270. static inline int
  271. write_packet(u8 *buf, struct omap_req *req, unsigned max)
  272. {
  273. unsigned len;
  274. u16 *wp;
  275. len = min(req->req.length - req->req.actual, max);
  276. req->req.actual += len;
  277. max = len;
  278. if (likely((((int)buf) & 1) == 0)) {
  279. wp = (u16 *)buf;
  280. while (max >= 2) {
  281. omap_writew(*wp++, UDC_DATA);
  282. max -= 2;
  283. }
  284. buf = (u8 *)wp;
  285. }
  286. while (max--)
  287. omap_writeb(*buf++, UDC_DATA);
  288. return len;
  289. }
  290. /* FIXME change r/w fifo calling convention */
  291. /* return: 0 = still running, 1 = completed, negative = errno */
  292. static int write_fifo(struct omap_ep *ep, struct omap_req *req)
  293. {
  294. u8 *buf;
  295. unsigned count;
  296. int is_last;
  297. u16 ep_stat;
  298. buf = req->req.buf + req->req.actual;
  299. prefetch(buf);
  300. /* PIO-IN isn't double buffered except for iso */
  301. ep_stat = omap_readw(UDC_STAT_FLG);
  302. if (ep_stat & UDC_FIFO_UNWRITABLE)
  303. return 0;
  304. count = ep->ep.maxpacket;
  305. count = write_packet(buf, req, count);
  306. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  307. ep->ackwait = 1;
  308. /* last packet is often short (sometimes a zlp) */
  309. if (count != ep->ep.maxpacket)
  310. is_last = 1;
  311. else if (req->req.length == req->req.actual
  312. && !req->req.zero)
  313. is_last = 1;
  314. else
  315. is_last = 0;
  316. /* NOTE: requests complete when all IN data is in a
  317. * FIFO (or sometimes later, if a zlp was needed).
  318. * Use usb_ep_fifo_status() where needed.
  319. */
  320. if (is_last)
  321. done(ep, req, 0);
  322. return is_last;
  323. }
  324. static inline int
  325. read_packet(u8 *buf, struct omap_req *req, unsigned avail)
  326. {
  327. unsigned len;
  328. u16 *wp;
  329. len = min(req->req.length - req->req.actual, avail);
  330. req->req.actual += len;
  331. avail = len;
  332. if (likely((((int)buf) & 1) == 0)) {
  333. wp = (u16 *)buf;
  334. while (avail >= 2) {
  335. *wp++ = omap_readw(UDC_DATA);
  336. avail -= 2;
  337. }
  338. buf = (u8 *)wp;
  339. }
  340. while (avail--)
  341. *buf++ = omap_readb(UDC_DATA);
  342. return len;
  343. }
  344. /* return: 0 = still running, 1 = queue empty, negative = errno */
  345. static int read_fifo(struct omap_ep *ep, struct omap_req *req)
  346. {
  347. u8 *buf;
  348. unsigned count, avail;
  349. int is_last;
  350. buf = req->req.buf + req->req.actual;
  351. prefetchw(buf);
  352. for (;;) {
  353. u16 ep_stat = omap_readw(UDC_STAT_FLG);
  354. is_last = 0;
  355. if (ep_stat & FIFO_EMPTY) {
  356. if (!ep->double_buf)
  357. break;
  358. ep->fnf = 1;
  359. }
  360. if (ep_stat & UDC_EP_HALTED)
  361. break;
  362. if (ep_stat & UDC_FIFO_FULL)
  363. avail = ep->ep.maxpacket;
  364. else {
  365. avail = omap_readw(UDC_RXFSTAT);
  366. ep->fnf = ep->double_buf;
  367. }
  368. count = read_packet(buf, req, avail);
  369. /* partial packet reads may not be errors */
  370. if (count < ep->ep.maxpacket) {
  371. is_last = 1;
  372. /* overflowed this request? flush extra data */
  373. if (count != avail) {
  374. req->req.status = -EOVERFLOW;
  375. avail -= count;
  376. while (avail--)
  377. omap_readw(UDC_DATA);
  378. }
  379. } else if (req->req.length == req->req.actual)
  380. is_last = 1;
  381. else
  382. is_last = 0;
  383. if (!ep->bEndpointAddress)
  384. break;
  385. if (is_last)
  386. done(ep, req, 0);
  387. break;
  388. }
  389. return is_last;
  390. }
  391. /*-------------------------------------------------------------------------*/
  392. static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
  393. {
  394. dma_addr_t end;
  395. /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
  396. * the last transfer's bytecount by more than a FIFO's worth.
  397. */
  398. if (cpu_is_omap15xx())
  399. return 0;
  400. end = omap_get_dma_src_pos(ep->lch);
  401. if (end == ep->dma_counter)
  402. return 0;
  403. end |= start & (0xffff << 16);
  404. if (end < start)
  405. end += 0x10000;
  406. return end - start;
  407. }
  408. static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
  409. {
  410. dma_addr_t end;
  411. end = omap_get_dma_dst_pos(ep->lch);
  412. if (end == ep->dma_counter)
  413. return 0;
  414. end |= start & (0xffff << 16);
  415. if (cpu_is_omap15xx())
  416. end++;
  417. if (end < start)
  418. end += 0x10000;
  419. return end - start;
  420. }
  421. /* Each USB transfer request using DMA maps to one or more DMA transfers.
  422. * When DMA completion isn't request completion, the UDC continues with
  423. * the next DMA transfer for that USB transfer.
  424. */
  425. static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
  426. {
  427. u16 txdma_ctrl, w;
  428. unsigned length = req->req.length - req->req.actual;
  429. const int sync_mode = cpu_is_omap15xx()
  430. ? OMAP_DMA_SYNC_FRAME
  431. : OMAP_DMA_SYNC_ELEMENT;
  432. int dma_trigger = 0;
  433. /* measure length in either bytes or packets */
  434. if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
  435. || (cpu_is_omap15xx() && length < ep->maxpacket)) {
  436. txdma_ctrl = UDC_TXN_EOT | length;
  437. omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
  438. length, 1, sync_mode, dma_trigger, 0);
  439. } else {
  440. length = min(length / ep->maxpacket,
  441. (unsigned) UDC_TXN_TSC + 1);
  442. txdma_ctrl = length;
  443. omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
  444. ep->ep.maxpacket >> 1, length, sync_mode,
  445. dma_trigger, 0);
  446. length *= ep->maxpacket;
  447. }
  448. omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
  449. OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
  450. 0, 0);
  451. omap_start_dma(ep->lch);
  452. ep->dma_counter = omap_get_dma_src_pos(ep->lch);
  453. w = omap_readw(UDC_DMA_IRQ_EN);
  454. w |= UDC_TX_DONE_IE(ep->dma_channel);
  455. omap_writew(w, UDC_DMA_IRQ_EN);
  456. omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
  457. req->dma_bytes = length;
  458. }
  459. static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
  460. {
  461. u16 w;
  462. if (status == 0) {
  463. req->req.actual += req->dma_bytes;
  464. /* return if this request needs to send data or zlp */
  465. if (req->req.actual < req->req.length)
  466. return;
  467. if (req->req.zero
  468. && req->dma_bytes != 0
  469. && (req->req.actual % ep->maxpacket) == 0)
  470. return;
  471. } else
  472. req->req.actual += dma_src_len(ep, req->req.dma
  473. + req->req.actual);
  474. /* tx completion */
  475. omap_stop_dma(ep->lch);
  476. w = omap_readw(UDC_DMA_IRQ_EN);
  477. w &= ~UDC_TX_DONE_IE(ep->dma_channel);
  478. omap_writew(w, UDC_DMA_IRQ_EN);
  479. done(ep, req, status);
  480. }
  481. static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
  482. {
  483. unsigned packets = req->req.length - req->req.actual;
  484. int dma_trigger = 0;
  485. u16 w;
  486. /* set up this DMA transfer, enable the fifo, start */
  487. packets /= ep->ep.maxpacket;
  488. packets = min(packets, (unsigned)UDC_RXN_TC + 1);
  489. req->dma_bytes = packets * ep->ep.maxpacket;
  490. omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
  491. ep->ep.maxpacket >> 1, packets,
  492. OMAP_DMA_SYNC_ELEMENT,
  493. dma_trigger, 0);
  494. omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
  495. OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
  496. 0, 0);
  497. ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
  498. omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
  499. w = omap_readw(UDC_DMA_IRQ_EN);
  500. w |= UDC_RX_EOT_IE(ep->dma_channel);
  501. omap_writew(w, UDC_DMA_IRQ_EN);
  502. omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
  503. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  504. omap_start_dma(ep->lch);
  505. }
  506. static void
  507. finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
  508. {
  509. u16 count, w;
  510. if (status == 0)
  511. ep->dma_counter = (u16) (req->req.dma + req->req.actual);
  512. count = dma_dest_len(ep, req->req.dma + req->req.actual);
  513. count += req->req.actual;
  514. if (one)
  515. count--;
  516. if (count <= req->req.length)
  517. req->req.actual = count;
  518. if (count != req->dma_bytes || status)
  519. omap_stop_dma(ep->lch);
  520. /* if this wasn't short, request may need another transfer */
  521. else if (req->req.actual < req->req.length)
  522. return;
  523. /* rx completion */
  524. w = omap_readw(UDC_DMA_IRQ_EN);
  525. w &= ~UDC_RX_EOT_IE(ep->dma_channel);
  526. omap_writew(w, UDC_DMA_IRQ_EN);
  527. done(ep, req, status);
  528. }
  529. static void dma_irq(struct omap_udc *udc, u16 irq_src)
  530. {
  531. u16 dman_stat = omap_readw(UDC_DMAN_STAT);
  532. struct omap_ep *ep;
  533. struct omap_req *req;
  534. /* IN dma: tx to host */
  535. if (irq_src & UDC_TXN_DONE) {
  536. ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
  537. ep->irqs++;
  538. /* can see TXN_DONE after dma abort */
  539. if (!list_empty(&ep->queue)) {
  540. req = container_of(ep->queue.next,
  541. struct omap_req, queue);
  542. finish_in_dma(ep, req, 0);
  543. }
  544. omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
  545. if (!list_empty(&ep->queue)) {
  546. req = container_of(ep->queue.next,
  547. struct omap_req, queue);
  548. next_in_dma(ep, req);
  549. }
  550. }
  551. /* OUT dma: rx from host */
  552. if (irq_src & UDC_RXN_EOT) {
  553. ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
  554. ep->irqs++;
  555. /* can see RXN_EOT after dma abort */
  556. if (!list_empty(&ep->queue)) {
  557. req = container_of(ep->queue.next,
  558. struct omap_req, queue);
  559. finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
  560. }
  561. omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
  562. if (!list_empty(&ep->queue)) {
  563. req = container_of(ep->queue.next,
  564. struct omap_req, queue);
  565. next_out_dma(ep, req);
  566. }
  567. }
  568. if (irq_src & UDC_RXN_CNT) {
  569. ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
  570. ep->irqs++;
  571. /* omap15xx does this unasked... */
  572. VDBG("%s, RX_CNT irq?\n", ep->ep.name);
  573. omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
  574. }
  575. }
  576. static void dma_error(int lch, u16 ch_status, void *data)
  577. {
  578. struct omap_ep *ep = data;
  579. /* if ch_status & OMAP_DMA_DROP_IRQ ... */
  580. /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
  581. ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
  582. /* complete current transfer ... */
  583. }
  584. static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
  585. {
  586. u16 reg;
  587. int status, restart, is_in;
  588. int dma_channel;
  589. is_in = ep->bEndpointAddress & USB_DIR_IN;
  590. if (is_in)
  591. reg = omap_readw(UDC_TXDMA_CFG);
  592. else
  593. reg = omap_readw(UDC_RXDMA_CFG);
  594. reg |= UDC_DMA_REQ; /* "pulse" activated */
  595. ep->dma_channel = 0;
  596. ep->lch = -1;
  597. if (channel == 0 || channel > 3) {
  598. if ((reg & 0x0f00) == 0)
  599. channel = 3;
  600. else if ((reg & 0x00f0) == 0)
  601. channel = 2;
  602. else if ((reg & 0x000f) == 0) /* preferred for ISO */
  603. channel = 1;
  604. else {
  605. status = -EMLINK;
  606. goto just_restart;
  607. }
  608. }
  609. reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
  610. ep->dma_channel = channel;
  611. if (is_in) {
  612. dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
  613. status = omap_request_dma(dma_channel,
  614. ep->ep.name, dma_error, ep, &ep->lch);
  615. if (status == 0) {
  616. omap_writew(reg, UDC_TXDMA_CFG);
  617. /* EMIFF or SDRC */
  618. omap_set_dma_src_burst_mode(ep->lch,
  619. OMAP_DMA_DATA_BURST_4);
  620. omap_set_dma_src_data_pack(ep->lch, 1);
  621. /* TIPB */
  622. omap_set_dma_dest_params(ep->lch,
  623. OMAP_DMA_PORT_TIPB,
  624. OMAP_DMA_AMODE_CONSTANT,
  625. UDC_DATA_DMA,
  626. 0, 0);
  627. }
  628. } else {
  629. dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
  630. status = omap_request_dma(dma_channel,
  631. ep->ep.name, dma_error, ep, &ep->lch);
  632. if (status == 0) {
  633. omap_writew(reg, UDC_RXDMA_CFG);
  634. /* TIPB */
  635. omap_set_dma_src_params(ep->lch,
  636. OMAP_DMA_PORT_TIPB,
  637. OMAP_DMA_AMODE_CONSTANT,
  638. UDC_DATA_DMA,
  639. 0, 0);
  640. /* EMIFF or SDRC */
  641. omap_set_dma_dest_burst_mode(ep->lch,
  642. OMAP_DMA_DATA_BURST_4);
  643. omap_set_dma_dest_data_pack(ep->lch, 1);
  644. }
  645. }
  646. if (status)
  647. ep->dma_channel = 0;
  648. else {
  649. ep->has_dma = 1;
  650. omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
  651. /* channel type P: hw synch (fifo) */
  652. if (!cpu_is_omap15xx())
  653. omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
  654. }
  655. just_restart:
  656. /* restart any queue, even if the claim failed */
  657. restart = !ep->stopped && !list_empty(&ep->queue);
  658. if (status)
  659. DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
  660. restart ? " (restart)" : "");
  661. else
  662. DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
  663. is_in ? 't' : 'r',
  664. ep->dma_channel - 1, ep->lch,
  665. restart ? " (restart)" : "");
  666. if (restart) {
  667. struct omap_req *req;
  668. req = container_of(ep->queue.next, struct omap_req, queue);
  669. if (ep->has_dma)
  670. (is_in ? next_in_dma : next_out_dma)(ep, req);
  671. else {
  672. use_ep(ep, UDC_EP_SEL);
  673. (is_in ? write_fifo : read_fifo)(ep, req);
  674. deselect_ep();
  675. if (!is_in) {
  676. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  677. ep->ackwait = 1 + ep->double_buf;
  678. }
  679. /* IN: 6 wait states before it'll tx */
  680. }
  681. }
  682. }
  683. static void dma_channel_release(struct omap_ep *ep)
  684. {
  685. int shift = 4 * (ep->dma_channel - 1);
  686. u16 mask = 0x0f << shift;
  687. struct omap_req *req;
  688. int active;
  689. /* abort any active usb transfer request */
  690. if (!list_empty(&ep->queue))
  691. req = container_of(ep->queue.next, struct omap_req, queue);
  692. else
  693. req = NULL;
  694. active = omap_get_dma_active_status(ep->lch);
  695. DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
  696. active ? "active" : "idle",
  697. (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
  698. ep->dma_channel - 1, req);
  699. /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
  700. * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
  701. */
  702. /* wait till current packet DMA finishes, and fifo empties */
  703. if (ep->bEndpointAddress & USB_DIR_IN) {
  704. omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
  705. UDC_TXDMA_CFG);
  706. if (req) {
  707. finish_in_dma(ep, req, -ECONNRESET);
  708. /* clear FIFO; hosts probably won't empty it */
  709. use_ep(ep, UDC_EP_SEL);
  710. omap_writew(UDC_CLR_EP, UDC_CTRL);
  711. deselect_ep();
  712. }
  713. while (omap_readw(UDC_TXDMA_CFG) & mask)
  714. udelay(10);
  715. } else {
  716. omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
  717. UDC_RXDMA_CFG);
  718. /* dma empties the fifo */
  719. while (omap_readw(UDC_RXDMA_CFG) & mask)
  720. udelay(10);
  721. if (req)
  722. finish_out_dma(ep, req, -ECONNRESET, 0);
  723. }
  724. omap_free_dma(ep->lch);
  725. ep->dma_channel = 0;
  726. ep->lch = -1;
  727. /* has_dma still set, till endpoint is fully quiesced */
  728. }
  729. /*-------------------------------------------------------------------------*/
  730. static int
  731. omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  732. {
  733. struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
  734. struct omap_req *req = container_of(_req, struct omap_req, req);
  735. struct omap_udc *udc;
  736. unsigned long flags;
  737. int is_iso = 0;
  738. /* catch various bogus parameters */
  739. if (!_req || !req->req.complete || !req->req.buf
  740. || !list_empty(&req->queue)) {
  741. DBG("%s, bad params\n", __func__);
  742. return -EINVAL;
  743. }
  744. if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
  745. DBG("%s, bad ep\n", __func__);
  746. return -EINVAL;
  747. }
  748. if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
  749. if (req->req.length > ep->ep.maxpacket)
  750. return -EMSGSIZE;
  751. is_iso = 1;
  752. }
  753. /* this isn't bogus, but OMAP DMA isn't the only hardware to
  754. * have a hard time with partial packet reads... reject it.
  755. */
  756. if (use_dma
  757. && ep->has_dma
  758. && ep->bEndpointAddress != 0
  759. && (ep->bEndpointAddress & USB_DIR_IN) == 0
  760. && (req->req.length % ep->ep.maxpacket) != 0) {
  761. DBG("%s, no partial packet OUT reads\n", __func__);
  762. return -EMSGSIZE;
  763. }
  764. udc = ep->udc;
  765. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
  766. return -ESHUTDOWN;
  767. if (use_dma && ep->has_dma)
  768. usb_gadget_map_request(&udc->gadget, &req->req,
  769. (ep->bEndpointAddress & USB_DIR_IN));
  770. VDBG("%s queue req %p, len %d buf %p\n",
  771. ep->ep.name, _req, _req->length, _req->buf);
  772. spin_lock_irqsave(&udc->lock, flags);
  773. req->req.status = -EINPROGRESS;
  774. req->req.actual = 0;
  775. /* maybe kickstart non-iso i/o queues */
  776. if (is_iso) {
  777. u16 w;
  778. w = omap_readw(UDC_IRQ_EN);
  779. w |= UDC_SOF_IE;
  780. omap_writew(w, UDC_IRQ_EN);
  781. } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
  782. int is_in;
  783. if (ep->bEndpointAddress == 0) {
  784. if (!udc->ep0_pending || !list_empty(&ep->queue)) {
  785. spin_unlock_irqrestore(&udc->lock, flags);
  786. return -EL2HLT;
  787. }
  788. /* empty DATA stage? */
  789. is_in = udc->ep0_in;
  790. if (!req->req.length) {
  791. /* chip became CONFIGURED or ADDRESSED
  792. * earlier; drivers may already have queued
  793. * requests to non-control endpoints
  794. */
  795. if (udc->ep0_set_config) {
  796. u16 irq_en = omap_readw(UDC_IRQ_EN);
  797. irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
  798. if (!udc->ep0_reset_config)
  799. irq_en |= UDC_EPN_RX_IE
  800. | UDC_EPN_TX_IE;
  801. omap_writew(irq_en, UDC_IRQ_EN);
  802. }
  803. /* STATUS for zero length DATA stages is
  804. * always an IN ... even for IN transfers,
  805. * a weird case which seem to stall OMAP.
  806. */
  807. omap_writew(UDC_EP_SEL | UDC_EP_DIR,
  808. UDC_EP_NUM);
  809. omap_writew(UDC_CLR_EP, UDC_CTRL);
  810. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  811. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  812. /* cleanup */
  813. udc->ep0_pending = 0;
  814. done(ep, req, 0);
  815. req = NULL;
  816. /* non-empty DATA stage */
  817. } else if (is_in) {
  818. omap_writew(UDC_EP_SEL | UDC_EP_DIR,
  819. UDC_EP_NUM);
  820. } else {
  821. if (udc->ep0_setup)
  822. goto irq_wait;
  823. omap_writew(UDC_EP_SEL, UDC_EP_NUM);
  824. }
  825. } else {
  826. is_in = ep->bEndpointAddress & USB_DIR_IN;
  827. if (!ep->has_dma)
  828. use_ep(ep, UDC_EP_SEL);
  829. /* if ISO: SOF IRQs must be enabled/disabled! */
  830. }
  831. if (ep->has_dma)
  832. (is_in ? next_in_dma : next_out_dma)(ep, req);
  833. else if (req) {
  834. if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
  835. req = NULL;
  836. deselect_ep();
  837. if (!is_in) {
  838. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  839. ep->ackwait = 1 + ep->double_buf;
  840. }
  841. /* IN: 6 wait states before it'll tx */
  842. }
  843. }
  844. irq_wait:
  845. /* irq handler advances the queue */
  846. if (req != NULL)
  847. list_add_tail(&req->queue, &ep->queue);
  848. spin_unlock_irqrestore(&udc->lock, flags);
  849. return 0;
  850. }
  851. static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  852. {
  853. struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
  854. struct omap_req *req;
  855. unsigned long flags;
  856. if (!_ep || !_req)
  857. return -EINVAL;
  858. spin_lock_irqsave(&ep->udc->lock, flags);
  859. /* make sure it's actually queued on this endpoint */
  860. list_for_each_entry(req, &ep->queue, queue) {
  861. if (&req->req == _req)
  862. break;
  863. }
  864. if (&req->req != _req) {
  865. spin_unlock_irqrestore(&ep->udc->lock, flags);
  866. return -EINVAL;
  867. }
  868. if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
  869. int channel = ep->dma_channel;
  870. /* releasing the channel cancels the request,
  871. * reclaiming the channel restarts the queue
  872. */
  873. dma_channel_release(ep);
  874. dma_channel_claim(ep, channel);
  875. } else
  876. done(ep, req, -ECONNRESET);
  877. spin_unlock_irqrestore(&ep->udc->lock, flags);
  878. return 0;
  879. }
  880. /*-------------------------------------------------------------------------*/
  881. static int omap_ep_set_halt(struct usb_ep *_ep, int value)
  882. {
  883. struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
  884. unsigned long flags;
  885. int status = -EOPNOTSUPP;
  886. spin_lock_irqsave(&ep->udc->lock, flags);
  887. /* just use protocol stalls for ep0; real halts are annoying */
  888. if (ep->bEndpointAddress == 0) {
  889. if (!ep->udc->ep0_pending)
  890. status = -EINVAL;
  891. else if (value) {
  892. if (ep->udc->ep0_set_config) {
  893. WARNING("error changing config?\n");
  894. omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
  895. }
  896. omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
  897. ep->udc->ep0_pending = 0;
  898. status = 0;
  899. } else /* NOP */
  900. status = 0;
  901. /* otherwise, all active non-ISO endpoints can halt */
  902. } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
  903. /* IN endpoints must already be idle */
  904. if ((ep->bEndpointAddress & USB_DIR_IN)
  905. && !list_empty(&ep->queue)) {
  906. status = -EAGAIN;
  907. goto done;
  908. }
  909. if (value) {
  910. int channel;
  911. if (use_dma && ep->dma_channel
  912. && !list_empty(&ep->queue)) {
  913. channel = ep->dma_channel;
  914. dma_channel_release(ep);
  915. } else
  916. channel = 0;
  917. use_ep(ep, UDC_EP_SEL);
  918. if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
  919. omap_writew(UDC_SET_HALT, UDC_CTRL);
  920. status = 0;
  921. } else
  922. status = -EAGAIN;
  923. deselect_ep();
  924. if (channel)
  925. dma_channel_claim(ep, channel);
  926. } else {
  927. use_ep(ep, 0);
  928. omap_writew(ep->udc->clr_halt, UDC_CTRL);
  929. ep->ackwait = 0;
  930. if (!(ep->bEndpointAddress & USB_DIR_IN)) {
  931. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  932. ep->ackwait = 1 + ep->double_buf;
  933. }
  934. }
  935. }
  936. done:
  937. VDBG("%s %s halt stat %d\n", ep->ep.name,
  938. value ? "set" : "clear", status);
  939. spin_unlock_irqrestore(&ep->udc->lock, flags);
  940. return status;
  941. }
  942. static struct usb_ep_ops omap_ep_ops = {
  943. .enable = omap_ep_enable,
  944. .disable = omap_ep_disable,
  945. .alloc_request = omap_alloc_request,
  946. .free_request = omap_free_request,
  947. .queue = omap_ep_queue,
  948. .dequeue = omap_ep_dequeue,
  949. .set_halt = omap_ep_set_halt,
  950. /* fifo_status ... report bytes in fifo */
  951. /* fifo_flush ... flush fifo */
  952. };
  953. /*-------------------------------------------------------------------------*/
  954. static int omap_get_frame(struct usb_gadget *gadget)
  955. {
  956. u16 sof = omap_readw(UDC_SOF);
  957. return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
  958. }
  959. static int omap_wakeup(struct usb_gadget *gadget)
  960. {
  961. struct omap_udc *udc;
  962. unsigned long flags;
  963. int retval = -EHOSTUNREACH;
  964. udc = container_of(gadget, struct omap_udc, gadget);
  965. spin_lock_irqsave(&udc->lock, flags);
  966. if (udc->devstat & UDC_SUS) {
  967. /* NOTE: OTG spec erratum says that OTG devices may
  968. * issue wakeups without host enable.
  969. */
  970. if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
  971. DBG("remote wakeup...\n");
  972. omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
  973. retval = 0;
  974. }
  975. /* NOTE: non-OTG systems may use SRP TOO... */
  976. } else if (!(udc->devstat & UDC_ATT)) {
  977. if (!IS_ERR_OR_NULL(udc->transceiver))
  978. retval = otg_start_srp(udc->transceiver->otg);
  979. }
  980. spin_unlock_irqrestore(&udc->lock, flags);
  981. return retval;
  982. }
  983. static int
  984. omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
  985. {
  986. struct omap_udc *udc;
  987. unsigned long flags;
  988. u16 syscon1;
  989. udc = container_of(gadget, struct omap_udc, gadget);
  990. spin_lock_irqsave(&udc->lock, flags);
  991. syscon1 = omap_readw(UDC_SYSCON1);
  992. if (is_selfpowered)
  993. syscon1 |= UDC_SELF_PWR;
  994. else
  995. syscon1 &= ~UDC_SELF_PWR;
  996. omap_writew(syscon1, UDC_SYSCON1);
  997. spin_unlock_irqrestore(&udc->lock, flags);
  998. return 0;
  999. }
  1000. static int can_pullup(struct omap_udc *udc)
  1001. {
  1002. return udc->driver && udc->softconnect && udc->vbus_active;
  1003. }
  1004. static void pullup_enable(struct omap_udc *udc)
  1005. {
  1006. u16 w;
  1007. w = omap_readw(UDC_SYSCON1);
  1008. w |= UDC_PULLUP_EN;
  1009. omap_writew(w, UDC_SYSCON1);
  1010. if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
  1011. u32 l;
  1012. l = omap_readl(OTG_CTRL);
  1013. l |= OTG_BSESSVLD;
  1014. omap_writel(l, OTG_CTRL);
  1015. }
  1016. omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
  1017. }
  1018. static void pullup_disable(struct omap_udc *udc)
  1019. {
  1020. u16 w;
  1021. if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
  1022. u32 l;
  1023. l = omap_readl(OTG_CTRL);
  1024. l &= ~OTG_BSESSVLD;
  1025. omap_writel(l, OTG_CTRL);
  1026. }
  1027. omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
  1028. w = omap_readw(UDC_SYSCON1);
  1029. w &= ~UDC_PULLUP_EN;
  1030. omap_writew(w, UDC_SYSCON1);
  1031. }
  1032. static struct omap_udc *udc;
  1033. static void omap_udc_enable_clock(int enable)
  1034. {
  1035. if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
  1036. return;
  1037. if (enable) {
  1038. clk_enable(udc->dc_clk);
  1039. clk_enable(udc->hhc_clk);
  1040. udelay(100);
  1041. } else {
  1042. clk_disable(udc->hhc_clk);
  1043. clk_disable(udc->dc_clk);
  1044. }
  1045. }
  1046. /*
  1047. * Called by whatever detects VBUS sessions: external transceiver
  1048. * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
  1049. */
  1050. static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
  1051. {
  1052. struct omap_udc *udc;
  1053. unsigned long flags;
  1054. u32 l;
  1055. udc = container_of(gadget, struct omap_udc, gadget);
  1056. spin_lock_irqsave(&udc->lock, flags);
  1057. VDBG("VBUS %s\n", is_active ? "on" : "off");
  1058. udc->vbus_active = (is_active != 0);
  1059. if (cpu_is_omap15xx()) {
  1060. /* "software" detect, ignored if !VBUS_MODE_1510 */
  1061. l = omap_readl(FUNC_MUX_CTRL_0);
  1062. if (is_active)
  1063. l |= VBUS_CTRL_1510;
  1064. else
  1065. l &= ~VBUS_CTRL_1510;
  1066. omap_writel(l, FUNC_MUX_CTRL_0);
  1067. }
  1068. if (udc->dc_clk != NULL && is_active) {
  1069. if (!udc->clk_requested) {
  1070. omap_udc_enable_clock(1);
  1071. udc->clk_requested = 1;
  1072. }
  1073. }
  1074. if (can_pullup(udc))
  1075. pullup_enable(udc);
  1076. else
  1077. pullup_disable(udc);
  1078. if (udc->dc_clk != NULL && !is_active) {
  1079. if (udc->clk_requested) {
  1080. omap_udc_enable_clock(0);
  1081. udc->clk_requested = 0;
  1082. }
  1083. }
  1084. spin_unlock_irqrestore(&udc->lock, flags);
  1085. return 0;
  1086. }
  1087. static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
  1088. {
  1089. struct omap_udc *udc;
  1090. udc = container_of(gadget, struct omap_udc, gadget);
  1091. if (!IS_ERR_OR_NULL(udc->transceiver))
  1092. return usb_phy_set_power(udc->transceiver, mA);
  1093. return -EOPNOTSUPP;
  1094. }
  1095. static int omap_pullup(struct usb_gadget *gadget, int is_on)
  1096. {
  1097. struct omap_udc *udc;
  1098. unsigned long flags;
  1099. udc = container_of(gadget, struct omap_udc, gadget);
  1100. spin_lock_irqsave(&udc->lock, flags);
  1101. udc->softconnect = (is_on != 0);
  1102. if (can_pullup(udc))
  1103. pullup_enable(udc);
  1104. else
  1105. pullup_disable(udc);
  1106. spin_unlock_irqrestore(&udc->lock, flags);
  1107. return 0;
  1108. }
  1109. static int omap_udc_start(struct usb_gadget *g,
  1110. struct usb_gadget_driver *driver);
  1111. static int omap_udc_stop(struct usb_gadget *g,
  1112. struct usb_gadget_driver *driver);
  1113. static const struct usb_gadget_ops omap_gadget_ops = {
  1114. .get_frame = omap_get_frame,
  1115. .wakeup = omap_wakeup,
  1116. .set_selfpowered = omap_set_selfpowered,
  1117. .vbus_session = omap_vbus_session,
  1118. .vbus_draw = omap_vbus_draw,
  1119. .pullup = omap_pullup,
  1120. .udc_start = omap_udc_start,
  1121. .udc_stop = omap_udc_stop,
  1122. };
  1123. /*-------------------------------------------------------------------------*/
  1124. /* dequeue ALL requests; caller holds udc->lock */
  1125. static void nuke(struct omap_ep *ep, int status)
  1126. {
  1127. struct omap_req *req;
  1128. ep->stopped = 1;
  1129. if (use_dma && ep->dma_channel)
  1130. dma_channel_release(ep);
  1131. use_ep(ep, 0);
  1132. omap_writew(UDC_CLR_EP, UDC_CTRL);
  1133. if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
  1134. omap_writew(UDC_SET_HALT, UDC_CTRL);
  1135. while (!list_empty(&ep->queue)) {
  1136. req = list_entry(ep->queue.next, struct omap_req, queue);
  1137. done(ep, req, status);
  1138. }
  1139. }
  1140. /* caller holds udc->lock */
  1141. static void udc_quiesce(struct omap_udc *udc)
  1142. {
  1143. struct omap_ep *ep;
  1144. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1145. nuke(&udc->ep[0], -ESHUTDOWN);
  1146. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
  1147. nuke(ep, -ESHUTDOWN);
  1148. }
  1149. /*-------------------------------------------------------------------------*/
  1150. static void update_otg(struct omap_udc *udc)
  1151. {
  1152. u16 devstat;
  1153. if (!gadget_is_otg(&udc->gadget))
  1154. return;
  1155. if (omap_readl(OTG_CTRL) & OTG_ID)
  1156. devstat = omap_readw(UDC_DEVSTAT);
  1157. else
  1158. devstat = 0;
  1159. udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
  1160. udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
  1161. udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
  1162. /* Enable HNP early, avoiding races on suspend irq path.
  1163. * ASSUMES OTG state machine B_BUS_REQ input is true.
  1164. */
  1165. if (udc->gadget.b_hnp_enable) {
  1166. u32 l;
  1167. l = omap_readl(OTG_CTRL);
  1168. l |= OTG_B_HNPEN | OTG_B_BUSREQ;
  1169. l &= ~OTG_PULLUP;
  1170. omap_writel(l, OTG_CTRL);
  1171. }
  1172. }
  1173. static void ep0_irq(struct omap_udc *udc, u16 irq_src)
  1174. {
  1175. struct omap_ep *ep0 = &udc->ep[0];
  1176. struct omap_req *req = NULL;
  1177. ep0->irqs++;
  1178. /* Clear any pending requests and then scrub any rx/tx state
  1179. * before starting to handle the SETUP request.
  1180. */
  1181. if (irq_src & UDC_SETUP) {
  1182. u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
  1183. nuke(ep0, 0);
  1184. if (ack) {
  1185. omap_writew(ack, UDC_IRQ_SRC);
  1186. irq_src = UDC_SETUP;
  1187. }
  1188. }
  1189. /* IN/OUT packets mean we're in the DATA or STATUS stage.
  1190. * This driver uses only uses protocol stalls (ep0 never halts),
  1191. * and if we got this far the gadget driver already had a
  1192. * chance to stall. Tries to be forgiving of host oddities.
  1193. *
  1194. * NOTE: the last chance gadget drivers have to stall control
  1195. * requests is during their request completion callback.
  1196. */
  1197. if (!list_empty(&ep0->queue))
  1198. req = container_of(ep0->queue.next, struct omap_req, queue);
  1199. /* IN == TX to host */
  1200. if (irq_src & UDC_EP0_TX) {
  1201. int stat;
  1202. omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
  1203. omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
  1204. stat = omap_readw(UDC_STAT_FLG);
  1205. if (stat & UDC_ACK) {
  1206. if (udc->ep0_in) {
  1207. /* write next IN packet from response,
  1208. * or set up the status stage.
  1209. */
  1210. if (req)
  1211. stat = write_fifo(ep0, req);
  1212. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  1213. if (!req && udc->ep0_pending) {
  1214. omap_writew(UDC_EP_SEL, UDC_EP_NUM);
  1215. omap_writew(UDC_CLR_EP, UDC_CTRL);
  1216. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1217. omap_writew(0, UDC_EP_NUM);
  1218. udc->ep0_pending = 0;
  1219. } /* else: 6 wait states before it'll tx */
  1220. } else {
  1221. /* ack status stage of OUT transfer */
  1222. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  1223. if (req)
  1224. done(ep0, req, 0);
  1225. }
  1226. req = NULL;
  1227. } else if (stat & UDC_STALL) {
  1228. omap_writew(UDC_CLR_HALT, UDC_CTRL);
  1229. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  1230. } else {
  1231. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  1232. }
  1233. }
  1234. /* OUT == RX from host */
  1235. if (irq_src & UDC_EP0_RX) {
  1236. int stat;
  1237. omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
  1238. omap_writew(UDC_EP_SEL, UDC_EP_NUM);
  1239. stat = omap_readw(UDC_STAT_FLG);
  1240. if (stat & UDC_ACK) {
  1241. if (!udc->ep0_in) {
  1242. stat = 0;
  1243. /* read next OUT packet of request, maybe
  1244. * reactiviting the fifo; stall on errors.
  1245. */
  1246. stat = read_fifo(ep0, req);
  1247. if (!req || stat < 0) {
  1248. omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
  1249. udc->ep0_pending = 0;
  1250. stat = 0;
  1251. } else if (stat == 0)
  1252. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1253. omap_writew(0, UDC_EP_NUM);
  1254. /* activate status stage */
  1255. if (stat == 1) {
  1256. done(ep0, req, 0);
  1257. /* that may have STALLed ep0... */
  1258. omap_writew(UDC_EP_SEL | UDC_EP_DIR,
  1259. UDC_EP_NUM);
  1260. omap_writew(UDC_CLR_EP, UDC_CTRL);
  1261. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1262. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  1263. udc->ep0_pending = 0;
  1264. }
  1265. } else {
  1266. /* ack status stage of IN transfer */
  1267. omap_writew(0, UDC_EP_NUM);
  1268. if (req)
  1269. done(ep0, req, 0);
  1270. }
  1271. } else if (stat & UDC_STALL) {
  1272. omap_writew(UDC_CLR_HALT, UDC_CTRL);
  1273. omap_writew(0, UDC_EP_NUM);
  1274. } else {
  1275. omap_writew(0, UDC_EP_NUM);
  1276. }
  1277. }
  1278. /* SETUP starts all control transfers */
  1279. if (irq_src & UDC_SETUP) {
  1280. union u {
  1281. u16 word[4];
  1282. struct usb_ctrlrequest r;
  1283. } u;
  1284. int status = -EINVAL;
  1285. struct omap_ep *ep;
  1286. /* read the (latest) SETUP message */
  1287. do {
  1288. omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
  1289. /* two bytes at a time */
  1290. u.word[0] = omap_readw(UDC_DATA);
  1291. u.word[1] = omap_readw(UDC_DATA);
  1292. u.word[2] = omap_readw(UDC_DATA);
  1293. u.word[3] = omap_readw(UDC_DATA);
  1294. omap_writew(0, UDC_EP_NUM);
  1295. } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
  1296. #define w_value le16_to_cpu(u.r.wValue)
  1297. #define w_index le16_to_cpu(u.r.wIndex)
  1298. #define w_length le16_to_cpu(u.r.wLength)
  1299. /* Delegate almost all control requests to the gadget driver,
  1300. * except for a handful of ch9 status/feature requests that
  1301. * hardware doesn't autodecode _and_ the gadget API hides.
  1302. */
  1303. udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
  1304. udc->ep0_set_config = 0;
  1305. udc->ep0_pending = 1;
  1306. ep0->stopped = 0;
  1307. ep0->ackwait = 0;
  1308. switch (u.r.bRequest) {
  1309. case USB_REQ_SET_CONFIGURATION:
  1310. /* udc needs to know when ep != 0 is valid */
  1311. if (u.r.bRequestType != USB_RECIP_DEVICE)
  1312. goto delegate;
  1313. if (w_length != 0)
  1314. goto do_stall;
  1315. udc->ep0_set_config = 1;
  1316. udc->ep0_reset_config = (w_value == 0);
  1317. VDBG("set config %d\n", w_value);
  1318. /* update udc NOW since gadget driver may start
  1319. * queueing requests immediately; clear config
  1320. * later if it fails the request.
  1321. */
  1322. if (udc->ep0_reset_config)
  1323. omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
  1324. else
  1325. omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
  1326. update_otg(udc);
  1327. goto delegate;
  1328. case USB_REQ_CLEAR_FEATURE:
  1329. /* clear endpoint halt */
  1330. if (u.r.bRequestType != USB_RECIP_ENDPOINT)
  1331. goto delegate;
  1332. if (w_value != USB_ENDPOINT_HALT
  1333. || w_length != 0)
  1334. goto do_stall;
  1335. ep = &udc->ep[w_index & 0xf];
  1336. if (ep != ep0) {
  1337. if (w_index & USB_DIR_IN)
  1338. ep += 16;
  1339. if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
  1340. || !ep->ep.desc)
  1341. goto do_stall;
  1342. use_ep(ep, 0);
  1343. omap_writew(udc->clr_halt, UDC_CTRL);
  1344. ep->ackwait = 0;
  1345. if (!(ep->bEndpointAddress & USB_DIR_IN)) {
  1346. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1347. ep->ackwait = 1 + ep->double_buf;
  1348. }
  1349. /* NOTE: assumes the host behaves sanely,
  1350. * only clearing real halts. Else we may
  1351. * need to kill pending transfers and then
  1352. * restart the queue... very messy for DMA!
  1353. */
  1354. }
  1355. VDBG("%s halt cleared by host\n", ep->name);
  1356. goto ep0out_status_stage;
  1357. case USB_REQ_SET_FEATURE:
  1358. /* set endpoint halt */
  1359. if (u.r.bRequestType != USB_RECIP_ENDPOINT)
  1360. goto delegate;
  1361. if (w_value != USB_ENDPOINT_HALT
  1362. || w_length != 0)
  1363. goto do_stall;
  1364. ep = &udc->ep[w_index & 0xf];
  1365. if (w_index & USB_DIR_IN)
  1366. ep += 16;
  1367. if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
  1368. || ep == ep0 || !ep->ep.desc)
  1369. goto do_stall;
  1370. if (use_dma && ep->has_dma) {
  1371. /* this has rude side-effects (aborts) and
  1372. * can't really work if DMA-IN is active
  1373. */
  1374. DBG("%s host set_halt, NYET\n", ep->name);
  1375. goto do_stall;
  1376. }
  1377. use_ep(ep, 0);
  1378. /* can't halt if fifo isn't empty... */
  1379. omap_writew(UDC_CLR_EP, UDC_CTRL);
  1380. omap_writew(UDC_SET_HALT, UDC_CTRL);
  1381. VDBG("%s halted by host\n", ep->name);
  1382. ep0out_status_stage:
  1383. status = 0;
  1384. omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
  1385. omap_writew(UDC_CLR_EP, UDC_CTRL);
  1386. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1387. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  1388. udc->ep0_pending = 0;
  1389. break;
  1390. case USB_REQ_GET_STATUS:
  1391. /* USB_ENDPOINT_HALT status? */
  1392. if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
  1393. goto intf_status;
  1394. /* ep0 never stalls */
  1395. if (!(w_index & 0xf))
  1396. goto zero_status;
  1397. /* only active endpoints count */
  1398. ep = &udc->ep[w_index & 0xf];
  1399. if (w_index & USB_DIR_IN)
  1400. ep += 16;
  1401. if (!ep->ep.desc)
  1402. goto do_stall;
  1403. /* iso never stalls */
  1404. if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
  1405. goto zero_status;
  1406. /* FIXME don't assume non-halted endpoints!! */
  1407. ERR("%s status, can't report\n", ep->ep.name);
  1408. goto do_stall;
  1409. intf_status:
  1410. /* return interface status. if we were pedantic,
  1411. * we'd detect non-existent interfaces, and stall.
  1412. */
  1413. if (u.r.bRequestType
  1414. != (USB_DIR_IN|USB_RECIP_INTERFACE))
  1415. goto delegate;
  1416. zero_status:
  1417. /* return two zero bytes */
  1418. omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
  1419. omap_writew(0, UDC_DATA);
  1420. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1421. omap_writew(UDC_EP_DIR, UDC_EP_NUM);
  1422. status = 0;
  1423. VDBG("GET_STATUS, interface %d\n", w_index);
  1424. /* next, status stage */
  1425. break;
  1426. default:
  1427. delegate:
  1428. /* activate the ep0out fifo right away */
  1429. if (!udc->ep0_in && w_length) {
  1430. omap_writew(0, UDC_EP_NUM);
  1431. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1432. }
  1433. /* gadget drivers see class/vendor specific requests,
  1434. * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
  1435. * and more
  1436. */
  1437. VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
  1438. u.r.bRequestType, u.r.bRequest,
  1439. w_value, w_index, w_length);
  1440. #undef w_value
  1441. #undef w_index
  1442. #undef w_length
  1443. /* The gadget driver may return an error here,
  1444. * causing an immediate protocol stall.
  1445. *
  1446. * Else it must issue a response, either queueing a
  1447. * response buffer for the DATA stage, or halting ep0
  1448. * (causing a protocol stall, not a real halt). A
  1449. * zero length buffer means no DATA stage.
  1450. *
  1451. * It's fine to issue that response after the setup()
  1452. * call returns, and this IRQ was handled.
  1453. */
  1454. udc->ep0_setup = 1;
  1455. spin_unlock(&udc->lock);
  1456. status = udc->driver->setup(&udc->gadget, &u.r);
  1457. spin_lock(&udc->lock);
  1458. udc->ep0_setup = 0;
  1459. }
  1460. if (status < 0) {
  1461. do_stall:
  1462. VDBG("req %02x.%02x protocol STALL; stat %d\n",
  1463. u.r.bRequestType, u.r.bRequest, status);
  1464. if (udc->ep0_set_config) {
  1465. if (udc->ep0_reset_config)
  1466. WARNING("error resetting config?\n");
  1467. else
  1468. omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
  1469. }
  1470. omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
  1471. udc->ep0_pending = 0;
  1472. }
  1473. }
  1474. }
  1475. /*-------------------------------------------------------------------------*/
  1476. #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
  1477. static void devstate_irq(struct omap_udc *udc, u16 irq_src)
  1478. {
  1479. u16 devstat, change;
  1480. devstat = omap_readw(UDC_DEVSTAT);
  1481. change = devstat ^ udc->devstat;
  1482. udc->devstat = devstat;
  1483. if (change & (UDC_USB_RESET|UDC_ATT)) {
  1484. udc_quiesce(udc);
  1485. if (change & UDC_ATT) {
  1486. /* driver for any external transceiver will
  1487. * have called omap_vbus_session() already
  1488. */
  1489. if (devstat & UDC_ATT) {
  1490. udc->gadget.speed = USB_SPEED_FULL;
  1491. VDBG("connect\n");
  1492. if (IS_ERR_OR_NULL(udc->transceiver))
  1493. pullup_enable(udc);
  1494. /* if (driver->connect) call it */
  1495. } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1496. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1497. if (IS_ERR_OR_NULL(udc->transceiver))
  1498. pullup_disable(udc);
  1499. DBG("disconnect, gadget %s\n",
  1500. udc->driver->driver.name);
  1501. if (udc->driver->disconnect) {
  1502. spin_unlock(&udc->lock);
  1503. udc->driver->disconnect(&udc->gadget);
  1504. spin_lock(&udc->lock);
  1505. }
  1506. }
  1507. change &= ~UDC_ATT;
  1508. }
  1509. if (change & UDC_USB_RESET) {
  1510. if (devstat & UDC_USB_RESET) {
  1511. VDBG("RESET=1\n");
  1512. } else {
  1513. udc->gadget.speed = USB_SPEED_FULL;
  1514. INFO("USB reset done, gadget %s\n",
  1515. udc->driver->driver.name);
  1516. /* ep0 traffic is legal from now on */
  1517. omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
  1518. UDC_IRQ_EN);
  1519. }
  1520. change &= ~UDC_USB_RESET;
  1521. }
  1522. }
  1523. if (change & UDC_SUS) {
  1524. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1525. /* FIXME tell isp1301 to suspend/resume (?) */
  1526. if (devstat & UDC_SUS) {
  1527. VDBG("suspend\n");
  1528. update_otg(udc);
  1529. /* HNP could be under way already */
  1530. if (udc->gadget.speed == USB_SPEED_FULL
  1531. && udc->driver->suspend) {
  1532. spin_unlock(&udc->lock);
  1533. udc->driver->suspend(&udc->gadget);
  1534. spin_lock(&udc->lock);
  1535. }
  1536. if (!IS_ERR_OR_NULL(udc->transceiver))
  1537. usb_phy_set_suspend(
  1538. udc->transceiver, 1);
  1539. } else {
  1540. VDBG("resume\n");
  1541. if (!IS_ERR_OR_NULL(udc->transceiver))
  1542. usb_phy_set_suspend(
  1543. udc->transceiver, 0);
  1544. if (udc->gadget.speed == USB_SPEED_FULL
  1545. && udc->driver->resume) {
  1546. spin_unlock(&udc->lock);
  1547. udc->driver->resume(&udc->gadget);
  1548. spin_lock(&udc->lock);
  1549. }
  1550. }
  1551. }
  1552. change &= ~UDC_SUS;
  1553. }
  1554. if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
  1555. update_otg(udc);
  1556. change &= ~OTG_FLAGS;
  1557. }
  1558. change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
  1559. if (change)
  1560. VDBG("devstat %03x, ignore change %03x\n",
  1561. devstat, change);
  1562. omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
  1563. }
  1564. static irqreturn_t omap_udc_irq(int irq, void *_udc)
  1565. {
  1566. struct omap_udc *udc = _udc;
  1567. u16 irq_src;
  1568. irqreturn_t status = IRQ_NONE;
  1569. unsigned long flags;
  1570. spin_lock_irqsave(&udc->lock, flags);
  1571. irq_src = omap_readw(UDC_IRQ_SRC);
  1572. /* Device state change (usb ch9 stuff) */
  1573. if (irq_src & UDC_DS_CHG) {
  1574. devstate_irq(_udc, irq_src);
  1575. status = IRQ_HANDLED;
  1576. irq_src &= ~UDC_DS_CHG;
  1577. }
  1578. /* EP0 control transfers */
  1579. if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
  1580. ep0_irq(_udc, irq_src);
  1581. status = IRQ_HANDLED;
  1582. irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
  1583. }
  1584. /* DMA transfer completion */
  1585. if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
  1586. dma_irq(_udc, irq_src);
  1587. status = IRQ_HANDLED;
  1588. irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
  1589. }
  1590. irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
  1591. if (irq_src)
  1592. DBG("udc_irq, unhandled %03x\n", irq_src);
  1593. spin_unlock_irqrestore(&udc->lock, flags);
  1594. return status;
  1595. }
  1596. /* workaround for seemingly-lost IRQs for RX ACKs... */
  1597. #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
  1598. #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
  1599. static void pio_out_timer(unsigned long _ep)
  1600. {
  1601. struct omap_ep *ep = (void *) _ep;
  1602. unsigned long flags;
  1603. u16 stat_flg;
  1604. spin_lock_irqsave(&ep->udc->lock, flags);
  1605. if (!list_empty(&ep->queue) && ep->ackwait) {
  1606. use_ep(ep, UDC_EP_SEL);
  1607. stat_flg = omap_readw(UDC_STAT_FLG);
  1608. if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
  1609. || (ep->double_buf && HALF_FULL(stat_flg)))) {
  1610. struct omap_req *req;
  1611. VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
  1612. req = container_of(ep->queue.next,
  1613. struct omap_req, queue);
  1614. (void) read_fifo(ep, req);
  1615. omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
  1616. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1617. ep->ackwait = 1 + ep->double_buf;
  1618. } else
  1619. deselect_ep();
  1620. }
  1621. mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
  1622. spin_unlock_irqrestore(&ep->udc->lock, flags);
  1623. }
  1624. static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
  1625. {
  1626. u16 epn_stat, irq_src;
  1627. irqreturn_t status = IRQ_NONE;
  1628. struct omap_ep *ep;
  1629. int epnum;
  1630. struct omap_udc *udc = _dev;
  1631. struct omap_req *req;
  1632. unsigned long flags;
  1633. spin_lock_irqsave(&udc->lock, flags);
  1634. epn_stat = omap_readw(UDC_EPN_STAT);
  1635. irq_src = omap_readw(UDC_IRQ_SRC);
  1636. /* handle OUT first, to avoid some wasteful NAKs */
  1637. if (irq_src & UDC_EPN_RX) {
  1638. epnum = (epn_stat >> 8) & 0x0f;
  1639. omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
  1640. status = IRQ_HANDLED;
  1641. ep = &udc->ep[epnum];
  1642. ep->irqs++;
  1643. omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
  1644. ep->fnf = 0;
  1645. if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
  1646. ep->ackwait--;
  1647. if (!list_empty(&ep->queue)) {
  1648. int stat;
  1649. req = container_of(ep->queue.next,
  1650. struct omap_req, queue);
  1651. stat = read_fifo(ep, req);
  1652. if (!ep->double_buf)
  1653. ep->fnf = 1;
  1654. }
  1655. }
  1656. /* min 6 clock delay before clearing EP_SEL ... */
  1657. epn_stat = omap_readw(UDC_EPN_STAT);
  1658. epn_stat = omap_readw(UDC_EPN_STAT);
  1659. omap_writew(epnum, UDC_EP_NUM);
  1660. /* enabling fifo _after_ clearing ACK, contrary to docs,
  1661. * reduces lossage; timer still needed though (sigh).
  1662. */
  1663. if (ep->fnf) {
  1664. omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
  1665. ep->ackwait = 1 + ep->double_buf;
  1666. }
  1667. mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
  1668. }
  1669. /* then IN transfers */
  1670. else if (irq_src & UDC_EPN_TX) {
  1671. epnum = epn_stat & 0x0f;
  1672. omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
  1673. status = IRQ_HANDLED;
  1674. ep = &udc->ep[16 + epnum];
  1675. ep->irqs++;
  1676. omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
  1677. if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
  1678. ep->ackwait = 0;
  1679. if (!list_empty(&ep->queue)) {
  1680. req = container_of(ep->queue.next,
  1681. struct omap_req, queue);
  1682. (void) write_fifo(ep, req);
  1683. }
  1684. }
  1685. /* min 6 clock delay before clearing EP_SEL ... */
  1686. epn_stat = omap_readw(UDC_EPN_STAT);
  1687. epn_stat = omap_readw(UDC_EPN_STAT);
  1688. omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
  1689. /* then 6 clocks before it'd tx */
  1690. }
  1691. spin_unlock_irqrestore(&udc->lock, flags);
  1692. return status;
  1693. }
  1694. #ifdef USE_ISO
  1695. static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
  1696. {
  1697. struct omap_udc *udc = _dev;
  1698. struct omap_ep *ep;
  1699. int pending = 0;
  1700. unsigned long flags;
  1701. spin_lock_irqsave(&udc->lock, flags);
  1702. /* handle all non-DMA ISO transfers */
  1703. list_for_each_entry(ep, &udc->iso, iso) {
  1704. u16 stat;
  1705. struct omap_req *req;
  1706. if (ep->has_dma || list_empty(&ep->queue))
  1707. continue;
  1708. req = list_entry(ep->queue.next, struct omap_req, queue);
  1709. use_ep(ep, UDC_EP_SEL);
  1710. stat = omap_readw(UDC_STAT_FLG);
  1711. /* NOTE: like the other controller drivers, this isn't
  1712. * currently reporting lost or damaged frames.
  1713. */
  1714. if (ep->bEndpointAddress & USB_DIR_IN) {
  1715. if (stat & UDC_MISS_IN)
  1716. /* done(ep, req, -EPROTO) */;
  1717. else
  1718. write_fifo(ep, req);
  1719. } else {
  1720. int status = 0;
  1721. if (stat & UDC_NO_RXPACKET)
  1722. status = -EREMOTEIO;
  1723. else if (stat & UDC_ISO_ERR)
  1724. status = -EILSEQ;
  1725. else if (stat & UDC_DATA_FLUSH)
  1726. status = -ENOSR;
  1727. if (status)
  1728. /* done(ep, req, status) */;
  1729. else
  1730. read_fifo(ep, req);
  1731. }
  1732. deselect_ep();
  1733. /* 6 wait states before next EP */
  1734. ep->irqs++;
  1735. if (!list_empty(&ep->queue))
  1736. pending = 1;
  1737. }
  1738. if (!pending) {
  1739. u16 w;
  1740. w = omap_readw(UDC_IRQ_EN);
  1741. w &= ~UDC_SOF_IE;
  1742. omap_writew(w, UDC_IRQ_EN);
  1743. }
  1744. omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
  1745. spin_unlock_irqrestore(&udc->lock, flags);
  1746. return IRQ_HANDLED;
  1747. }
  1748. #endif
  1749. /*-------------------------------------------------------------------------*/
  1750. static inline int machine_without_vbus_sense(void)
  1751. {
  1752. return machine_is_omap_innovator()
  1753. || machine_is_omap_osk()
  1754. || machine_is_sx1()
  1755. /* No known omap7xx boards with vbus sense */
  1756. || cpu_is_omap7xx();
  1757. }
  1758. static int omap_udc_start(struct usb_gadget *g,
  1759. struct usb_gadget_driver *driver)
  1760. {
  1761. int status = -ENODEV;
  1762. struct omap_ep *ep;
  1763. unsigned long flags;
  1764. spin_lock_irqsave(&udc->lock, flags);
  1765. /* reset state */
  1766. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
  1767. ep->irqs = 0;
  1768. if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
  1769. continue;
  1770. use_ep(ep, 0);
  1771. omap_writew(UDC_SET_HALT, UDC_CTRL);
  1772. }
  1773. udc->ep0_pending = 0;
  1774. udc->ep[0].irqs = 0;
  1775. udc->softconnect = 1;
  1776. /* hook up the driver */
  1777. driver->driver.bus = NULL;
  1778. udc->driver = driver;
  1779. spin_unlock_irqrestore(&udc->lock, flags);
  1780. if (udc->dc_clk != NULL)
  1781. omap_udc_enable_clock(1);
  1782. omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
  1783. /* connect to bus through transceiver */
  1784. if (!IS_ERR_OR_NULL(udc->transceiver)) {
  1785. status = otg_set_peripheral(udc->transceiver->otg,
  1786. &udc->gadget);
  1787. if (status < 0) {
  1788. ERR("can't bind to transceiver\n");
  1789. if (driver->unbind) {
  1790. driver->unbind(&udc->gadget);
  1791. udc->driver = NULL;
  1792. }
  1793. goto done;
  1794. }
  1795. } else {
  1796. if (can_pullup(udc))
  1797. pullup_enable(udc);
  1798. else
  1799. pullup_disable(udc);
  1800. }
  1801. /* boards that don't have VBUS sensing can't autogate 48MHz;
  1802. * can't enter deep sleep while a gadget driver is active.
  1803. */
  1804. if (machine_without_vbus_sense())
  1805. omap_vbus_session(&udc->gadget, 1);
  1806. done:
  1807. if (udc->dc_clk != NULL)
  1808. omap_udc_enable_clock(0);
  1809. return status;
  1810. }
  1811. static int omap_udc_stop(struct usb_gadget *g,
  1812. struct usb_gadget_driver *driver)
  1813. {
  1814. unsigned long flags;
  1815. int status = -ENODEV;
  1816. if (udc->dc_clk != NULL)
  1817. omap_udc_enable_clock(1);
  1818. if (machine_without_vbus_sense())
  1819. omap_vbus_session(&udc->gadget, 0);
  1820. if (!IS_ERR_OR_NULL(udc->transceiver))
  1821. (void) otg_set_peripheral(udc->transceiver->otg, NULL);
  1822. else
  1823. pullup_disable(udc);
  1824. spin_lock_irqsave(&udc->lock, flags);
  1825. udc_quiesce(udc);
  1826. spin_unlock_irqrestore(&udc->lock, flags);
  1827. udc->driver = NULL;
  1828. if (udc->dc_clk != NULL)
  1829. omap_udc_enable_clock(0);
  1830. return status;
  1831. }
  1832. /*-------------------------------------------------------------------------*/
  1833. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  1834. #include <linux/seq_file.h>
  1835. static const char proc_filename[] = "driver/udc";
  1836. #define FOURBITS "%s%s%s%s"
  1837. #define EIGHTBITS "%s%s%s%s%s%s%s%s"
  1838. static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
  1839. {
  1840. u16 stat_flg;
  1841. struct omap_req *req;
  1842. char buf[20];
  1843. use_ep(ep, 0);
  1844. if (use_dma && ep->has_dma)
  1845. snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
  1846. (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
  1847. ep->dma_channel - 1, ep->lch);
  1848. else
  1849. buf[0] = 0;
  1850. stat_flg = omap_readw(UDC_STAT_FLG);
  1851. seq_printf(s,
  1852. "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
  1853. ep->name, buf,
  1854. ep->double_buf ? "dbuf " : "",
  1855. ({ char *s;
  1856. switch (ep->ackwait) {
  1857. case 0:
  1858. s = "";
  1859. break;
  1860. case 1:
  1861. s = "(ackw) ";
  1862. break;
  1863. case 2:
  1864. s = "(ackw2) ";
  1865. break;
  1866. default:
  1867. s = "(?) ";
  1868. break;
  1869. } s; }),
  1870. ep->irqs, stat_flg,
  1871. (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
  1872. (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
  1873. (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
  1874. (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
  1875. (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
  1876. (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
  1877. (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
  1878. (stat_flg & UDC_STALL) ? "STALL " : "",
  1879. (stat_flg & UDC_NAK) ? "NAK " : "",
  1880. (stat_flg & UDC_ACK) ? "ACK " : "",
  1881. (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
  1882. (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
  1883. (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
  1884. if (list_empty(&ep->queue))
  1885. seq_printf(s, "\t(queue empty)\n");
  1886. else
  1887. list_for_each_entry(req, &ep->queue, queue) {
  1888. unsigned length = req->req.actual;
  1889. if (use_dma && buf[0]) {
  1890. length += ((ep->bEndpointAddress & USB_DIR_IN)
  1891. ? dma_src_len : dma_dest_len)
  1892. (ep, req->req.dma + length);
  1893. buf[0] = 0;
  1894. }
  1895. seq_printf(s, "\treq %p len %d/%d buf %p\n",
  1896. &req->req, length,
  1897. req->req.length, req->req.buf);
  1898. }
  1899. }
  1900. static char *trx_mode(unsigned m, int enabled)
  1901. {
  1902. switch (m) {
  1903. case 0:
  1904. return enabled ? "*6wire" : "unused";
  1905. case 1:
  1906. return "4wire";
  1907. case 2:
  1908. return "3wire";
  1909. case 3:
  1910. return "6wire";
  1911. default:
  1912. return "unknown";
  1913. }
  1914. }
  1915. static int proc_otg_show(struct seq_file *s)
  1916. {
  1917. u32 tmp;
  1918. u32 trans = 0;
  1919. char *ctrl_name = "(UNKNOWN)";
  1920. tmp = omap_readl(OTG_REV);
  1921. ctrl_name = "tranceiver_ctrl";
  1922. trans = omap_readw(USB_TRANSCEIVER_CTRL);
  1923. seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
  1924. tmp >> 4, tmp & 0xf, ctrl_name, trans);
  1925. tmp = omap_readw(OTG_SYSCON_1);
  1926. seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
  1927. FOURBITS "\n", tmp,
  1928. trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
  1929. trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
  1930. (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
  1931. ? "internal"
  1932. : trx_mode(USB0_TRX_MODE(tmp), 1),
  1933. (tmp & OTG_IDLE_EN) ? " !otg" : "",
  1934. (tmp & HST_IDLE_EN) ? " !host" : "",
  1935. (tmp & DEV_IDLE_EN) ? " !dev" : "",
  1936. (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
  1937. tmp = omap_readl(OTG_SYSCON_2);
  1938. seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
  1939. " b_ase_brst=%d hmc=%d\n", tmp,
  1940. (tmp & OTG_EN) ? " otg_en" : "",
  1941. (tmp & USBX_SYNCHRO) ? " synchro" : "",
  1942. /* much more SRP stuff */
  1943. (tmp & SRP_DATA) ? " srp_data" : "",
  1944. (tmp & SRP_VBUS) ? " srp_vbus" : "",
  1945. (tmp & OTG_PADEN) ? " otg_paden" : "",
  1946. (tmp & HMC_PADEN) ? " hmc_paden" : "",
  1947. (tmp & UHOST_EN) ? " uhost_en" : "",
  1948. (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
  1949. (tmp & HMC_TLLATTACH) ? " tllattach" : "",
  1950. B_ASE_BRST(tmp),
  1951. OTG_HMC(tmp));
  1952. tmp = omap_readl(OTG_CTRL);
  1953. seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
  1954. (tmp & OTG_ASESSVLD) ? " asess" : "",
  1955. (tmp & OTG_BSESSEND) ? " bsess_end" : "",
  1956. (tmp & OTG_BSESSVLD) ? " bsess" : "",
  1957. (tmp & OTG_VBUSVLD) ? " vbus" : "",
  1958. (tmp & OTG_ID) ? " id" : "",
  1959. (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
  1960. (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
  1961. (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
  1962. (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
  1963. (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
  1964. (tmp & OTG_BUSDROP) ? " busdrop" : "",
  1965. (tmp & OTG_PULLDOWN) ? " down" : "",
  1966. (tmp & OTG_PULLUP) ? " up" : "",
  1967. (tmp & OTG_DRV_VBUS) ? " drv" : "",
  1968. (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
  1969. (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
  1970. (tmp & OTG_PU_ID) ? " pu_id" : ""
  1971. );
  1972. tmp = omap_readw(OTG_IRQ_EN);
  1973. seq_printf(s, "otg_irq_en %04x" "\n", tmp);
  1974. tmp = omap_readw(OTG_IRQ_SRC);
  1975. seq_printf(s, "otg_irq_src %04x" "\n", tmp);
  1976. tmp = omap_readw(OTG_OUTCTRL);
  1977. seq_printf(s, "otg_outctrl %04x" "\n", tmp);
  1978. tmp = omap_readw(OTG_TEST);
  1979. seq_printf(s, "otg_test %04x" "\n", tmp);
  1980. return 0;
  1981. }
  1982. static int proc_udc_show(struct seq_file *s, void *_)
  1983. {
  1984. u32 tmp;
  1985. struct omap_ep *ep;
  1986. unsigned long flags;
  1987. spin_lock_irqsave(&udc->lock, flags);
  1988. seq_printf(s, "%s, version: " DRIVER_VERSION
  1989. #ifdef USE_ISO
  1990. " (iso)"
  1991. #endif
  1992. "%s\n",
  1993. driver_desc,
  1994. use_dma ? " (dma)" : "");
  1995. tmp = omap_readw(UDC_REV) & 0xff;
  1996. seq_printf(s,
  1997. "UDC rev %d.%d, fifo mode %d, gadget %s\n"
  1998. "hmc %d, transceiver %s\n",
  1999. tmp >> 4, tmp & 0xf,
  2000. fifo_mode,
  2001. udc->driver ? udc->driver->driver.name : "(none)",
  2002. HMC,
  2003. udc->transceiver
  2004. ? udc->transceiver->label
  2005. : (cpu_is_omap1710()
  2006. ? "external" : "(none)"));
  2007. seq_printf(s, "ULPD control %04x req %04x status %04x\n",
  2008. omap_readw(ULPD_CLOCK_CTRL),
  2009. omap_readw(ULPD_SOFT_REQ),
  2010. omap_readw(ULPD_STATUS_REQ));
  2011. /* OTG controller registers */
  2012. if (!cpu_is_omap15xx())
  2013. proc_otg_show(s);
  2014. tmp = omap_readw(UDC_SYSCON1);
  2015. seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
  2016. (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
  2017. (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
  2018. (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
  2019. (tmp & UDC_NAK_EN) ? " nak" : "",
  2020. (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
  2021. (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
  2022. (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
  2023. (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
  2024. /* syscon2 is write-only */
  2025. /* UDC controller registers */
  2026. if (!(tmp & UDC_PULLUP_EN)) {
  2027. seq_printf(s, "(suspended)\n");
  2028. spin_unlock_irqrestore(&udc->lock, flags);
  2029. return 0;
  2030. }
  2031. tmp = omap_readw(UDC_DEVSTAT);
  2032. seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
  2033. (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
  2034. (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
  2035. (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
  2036. (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
  2037. (tmp & UDC_USB_RESET) ? " usb_reset" : "",
  2038. (tmp & UDC_SUS) ? " SUS" : "",
  2039. (tmp & UDC_CFG) ? " CFG" : "",
  2040. (tmp & UDC_ADD) ? " ADD" : "",
  2041. (tmp & UDC_DEF) ? " DEF" : "",
  2042. (tmp & UDC_ATT) ? " ATT" : "");
  2043. seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
  2044. tmp = omap_readw(UDC_IRQ_EN);
  2045. seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
  2046. (tmp & UDC_SOF_IE) ? " sof" : "",
  2047. (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
  2048. (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
  2049. (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
  2050. (tmp & UDC_EP0_IE) ? " ep0" : "");
  2051. tmp = omap_readw(UDC_IRQ_SRC);
  2052. seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
  2053. (tmp & UDC_TXN_DONE) ? " txn_done" : "",
  2054. (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
  2055. (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
  2056. (tmp & UDC_IRQ_SOF) ? " sof" : "",
  2057. (tmp & UDC_EPN_RX) ? " epn_rx" : "",
  2058. (tmp & UDC_EPN_TX) ? " epn_tx" : "",
  2059. (tmp & UDC_DS_CHG) ? " ds_chg" : "",
  2060. (tmp & UDC_SETUP) ? " setup" : "",
  2061. (tmp & UDC_EP0_RX) ? " ep0out" : "",
  2062. (tmp & UDC_EP0_TX) ? " ep0in" : "");
  2063. if (use_dma) {
  2064. unsigned i;
  2065. tmp = omap_readw(UDC_DMA_IRQ_EN);
  2066. seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
  2067. (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
  2068. (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
  2069. (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
  2070. (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
  2071. (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
  2072. (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
  2073. (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
  2074. (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
  2075. (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
  2076. tmp = omap_readw(UDC_RXDMA_CFG);
  2077. seq_printf(s, "rxdma_cfg %04x\n", tmp);
  2078. if (tmp) {
  2079. for (i = 0; i < 3; i++) {
  2080. if ((tmp & (0x0f << (i * 4))) == 0)
  2081. continue;
  2082. seq_printf(s, "rxdma[%d] %04x\n", i,
  2083. omap_readw(UDC_RXDMA(i + 1)));
  2084. }
  2085. }
  2086. tmp = omap_readw(UDC_TXDMA_CFG);
  2087. seq_printf(s, "txdma_cfg %04x\n", tmp);
  2088. if (tmp) {
  2089. for (i = 0; i < 3; i++) {
  2090. if (!(tmp & (0x0f << (i * 4))))
  2091. continue;
  2092. seq_printf(s, "txdma[%d] %04x\n", i,
  2093. omap_readw(UDC_TXDMA(i + 1)));
  2094. }
  2095. }
  2096. }
  2097. tmp = omap_readw(UDC_DEVSTAT);
  2098. if (tmp & UDC_ATT) {
  2099. proc_ep_show(s, &udc->ep[0]);
  2100. if (tmp & UDC_ADD) {
  2101. list_for_each_entry(ep, &udc->gadget.ep_list,
  2102. ep.ep_list) {
  2103. if (ep->ep.desc)
  2104. proc_ep_show(s, ep);
  2105. }
  2106. }
  2107. }
  2108. spin_unlock_irqrestore(&udc->lock, flags);
  2109. return 0;
  2110. }
  2111. static int proc_udc_open(struct inode *inode, struct file *file)
  2112. {
  2113. return single_open(file, proc_udc_show, NULL);
  2114. }
  2115. static const struct file_operations proc_ops = {
  2116. .owner = THIS_MODULE,
  2117. .open = proc_udc_open,
  2118. .read = seq_read,
  2119. .llseek = seq_lseek,
  2120. .release = single_release,
  2121. };
  2122. static void create_proc_file(void)
  2123. {
  2124. proc_create(proc_filename, 0, NULL, &proc_ops);
  2125. }
  2126. static void remove_proc_file(void)
  2127. {
  2128. remove_proc_entry(proc_filename, NULL);
  2129. }
  2130. #else
  2131. static inline void create_proc_file(void) {}
  2132. static inline void remove_proc_file(void) {}
  2133. #endif
  2134. /*-------------------------------------------------------------------------*/
  2135. /* Before this controller can enumerate, we need to pick an endpoint
  2136. * configuration, or "fifo_mode" That involves allocating 2KB of packet
  2137. * buffer space among the endpoints we'll be operating.
  2138. *
  2139. * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
  2140. * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
  2141. * capability yet though.
  2142. */
  2143. static unsigned
  2144. omap_ep_setup(char *name, u8 addr, u8 type,
  2145. unsigned buf, unsigned maxp, int dbuf)
  2146. {
  2147. struct omap_ep *ep;
  2148. u16 epn_rxtx = 0;
  2149. /* OUT endpoints first, then IN */
  2150. ep = &udc->ep[addr & 0xf];
  2151. if (addr & USB_DIR_IN)
  2152. ep += 16;
  2153. /* in case of ep init table bugs */
  2154. BUG_ON(ep->name[0]);
  2155. /* chip setup ... bit values are same for IN, OUT */
  2156. if (type == USB_ENDPOINT_XFER_ISOC) {
  2157. switch (maxp) {
  2158. case 8:
  2159. epn_rxtx = 0 << 12;
  2160. break;
  2161. case 16:
  2162. epn_rxtx = 1 << 12;
  2163. break;
  2164. case 32:
  2165. epn_rxtx = 2 << 12;
  2166. break;
  2167. case 64:
  2168. epn_rxtx = 3 << 12;
  2169. break;
  2170. case 128:
  2171. epn_rxtx = 4 << 12;
  2172. break;
  2173. case 256:
  2174. epn_rxtx = 5 << 12;
  2175. break;
  2176. case 512:
  2177. epn_rxtx = 6 << 12;
  2178. break;
  2179. default:
  2180. BUG();
  2181. }
  2182. epn_rxtx |= UDC_EPN_RX_ISO;
  2183. dbuf = 1;
  2184. } else {
  2185. /* double-buffering "not supported" on 15xx,
  2186. * and ignored for PIO-IN on newer chips
  2187. * (for more reliable behavior)
  2188. */
  2189. if (!use_dma || cpu_is_omap15xx())
  2190. dbuf = 0;
  2191. switch (maxp) {
  2192. case 8:
  2193. epn_rxtx = 0 << 12;
  2194. break;
  2195. case 16:
  2196. epn_rxtx = 1 << 12;
  2197. break;
  2198. case 32:
  2199. epn_rxtx = 2 << 12;
  2200. break;
  2201. case 64:
  2202. epn_rxtx = 3 << 12;
  2203. break;
  2204. default:
  2205. BUG();
  2206. }
  2207. if (dbuf && addr)
  2208. epn_rxtx |= UDC_EPN_RX_DB;
  2209. init_timer(&ep->timer);
  2210. ep->timer.function = pio_out_timer;
  2211. ep->timer.data = (unsigned long) ep;
  2212. }
  2213. if (addr)
  2214. epn_rxtx |= UDC_EPN_RX_VALID;
  2215. BUG_ON(buf & 0x07);
  2216. epn_rxtx |= buf >> 3;
  2217. DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
  2218. name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
  2219. if (addr & USB_DIR_IN)
  2220. omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
  2221. else
  2222. omap_writew(epn_rxtx, UDC_EP_RX(addr));
  2223. /* next endpoint's buffer starts after this one's */
  2224. buf += maxp;
  2225. if (dbuf)
  2226. buf += maxp;
  2227. BUG_ON(buf > 2048);
  2228. /* set up driver data structures */
  2229. BUG_ON(strlen(name) >= sizeof ep->name);
  2230. strlcpy(ep->name, name, sizeof ep->name);
  2231. INIT_LIST_HEAD(&ep->queue);
  2232. INIT_LIST_HEAD(&ep->iso);
  2233. ep->bEndpointAddress = addr;
  2234. ep->bmAttributes = type;
  2235. ep->double_buf = dbuf;
  2236. ep->udc = udc;
  2237. ep->ep.name = ep->name;
  2238. ep->ep.ops = &omap_ep_ops;
  2239. ep->ep.maxpacket = ep->maxpacket = maxp;
  2240. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  2241. return buf;
  2242. }
  2243. static void omap_udc_release(struct device *dev)
  2244. {
  2245. complete(udc->done);
  2246. kfree(udc);
  2247. udc = NULL;
  2248. }
  2249. static int
  2250. omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
  2251. {
  2252. unsigned tmp, buf;
  2253. /* abolish any previous hardware state */
  2254. omap_writew(0, UDC_SYSCON1);
  2255. omap_writew(0, UDC_IRQ_EN);
  2256. omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
  2257. omap_writew(0, UDC_DMA_IRQ_EN);
  2258. omap_writew(0, UDC_RXDMA_CFG);
  2259. omap_writew(0, UDC_TXDMA_CFG);
  2260. /* UDC_PULLUP_EN gates the chip clock */
  2261. /* OTG_SYSCON_1 |= DEV_IDLE_EN; */
  2262. udc = kzalloc(sizeof(*udc), GFP_KERNEL);
  2263. if (!udc)
  2264. return -ENOMEM;
  2265. spin_lock_init(&udc->lock);
  2266. udc->gadget.ops = &omap_gadget_ops;
  2267. udc->gadget.ep0 = &udc->ep[0].ep;
  2268. INIT_LIST_HEAD(&udc->gadget.ep_list);
  2269. INIT_LIST_HEAD(&udc->iso);
  2270. udc->gadget.speed = USB_SPEED_UNKNOWN;
  2271. udc->gadget.max_speed = USB_SPEED_FULL;
  2272. udc->gadget.name = driver_name;
  2273. udc->transceiver = xceiv;
  2274. /* ep0 is special; put it right after the SETUP buffer */
  2275. buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
  2276. 8 /* after SETUP */, 64 /* maxpacket */, 0);
  2277. list_del_init(&udc->ep[0].ep.ep_list);
  2278. /* initially disable all non-ep0 endpoints */
  2279. for (tmp = 1; tmp < 15; tmp++) {
  2280. omap_writew(0, UDC_EP_RX(tmp));
  2281. omap_writew(0, UDC_EP_TX(tmp));
  2282. }
  2283. #define OMAP_BULK_EP(name, addr) \
  2284. buf = omap_ep_setup(name "-bulk", addr, \
  2285. USB_ENDPOINT_XFER_BULK, buf, 64, 1);
  2286. #define OMAP_INT_EP(name, addr, maxp) \
  2287. buf = omap_ep_setup(name "-int", addr, \
  2288. USB_ENDPOINT_XFER_INT, buf, maxp, 0);
  2289. #define OMAP_ISO_EP(name, addr, maxp) \
  2290. buf = omap_ep_setup(name "-iso", addr, \
  2291. USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
  2292. switch (fifo_mode) {
  2293. case 0:
  2294. OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
  2295. OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
  2296. OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
  2297. break;
  2298. case 1:
  2299. OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
  2300. OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
  2301. OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
  2302. OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
  2303. OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
  2304. OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
  2305. OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
  2306. OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
  2307. OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
  2308. OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
  2309. OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
  2310. OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
  2311. OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
  2312. OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
  2313. OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
  2314. OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
  2315. OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
  2316. OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
  2317. OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
  2318. OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
  2319. OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
  2320. OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
  2321. break;
  2322. #ifdef USE_ISO
  2323. case 2: /* mixed iso/bulk */
  2324. OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
  2325. OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
  2326. OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
  2327. OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
  2328. OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
  2329. OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
  2330. OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
  2331. OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
  2332. break;
  2333. case 3: /* mixed bulk/iso */
  2334. OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
  2335. OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
  2336. OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
  2337. OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
  2338. OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
  2339. OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
  2340. OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
  2341. OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
  2342. OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
  2343. break;
  2344. #endif
  2345. /* add more modes as needed */
  2346. default:
  2347. ERR("unsupported fifo_mode #%d\n", fifo_mode);
  2348. return -ENODEV;
  2349. }
  2350. omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
  2351. INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
  2352. return 0;
  2353. }
  2354. static int omap_udc_probe(struct platform_device *pdev)
  2355. {
  2356. int status = -ENODEV;
  2357. int hmc;
  2358. struct usb_phy *xceiv = NULL;
  2359. const char *type = NULL;
  2360. struct omap_usb_config *config = pdev->dev.platform_data;
  2361. struct clk *dc_clk = NULL;
  2362. struct clk *hhc_clk = NULL;
  2363. if (cpu_is_omap7xx())
  2364. use_dma = 0;
  2365. /* NOTE: "knows" the order of the resources! */
  2366. if (!request_mem_region(pdev->resource[0].start,
  2367. pdev->resource[0].end - pdev->resource[0].start + 1,
  2368. driver_name)) {
  2369. DBG("request_mem_region failed\n");
  2370. return -EBUSY;
  2371. }
  2372. if (cpu_is_omap16xx()) {
  2373. dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
  2374. hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
  2375. BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
  2376. /* can't use omap_udc_enable_clock yet */
  2377. clk_enable(dc_clk);
  2378. clk_enable(hhc_clk);
  2379. udelay(100);
  2380. }
  2381. if (cpu_is_omap7xx()) {
  2382. dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
  2383. hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
  2384. BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
  2385. /* can't use omap_udc_enable_clock yet */
  2386. clk_enable(dc_clk);
  2387. clk_enable(hhc_clk);
  2388. udelay(100);
  2389. }
  2390. INFO("OMAP UDC rev %d.%d%s\n",
  2391. omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
  2392. config->otg ? ", Mini-AB" : "");
  2393. /* use the mode given to us by board init code */
  2394. if (cpu_is_omap15xx()) {
  2395. hmc = HMC_1510;
  2396. type = "(unknown)";
  2397. if (machine_without_vbus_sense()) {
  2398. /* just set up software VBUS detect, and then
  2399. * later rig it so we always report VBUS.
  2400. * FIXME without really sensing VBUS, we can't
  2401. * know when to turn PULLUP_EN on/off; and that
  2402. * means we always "need" the 48MHz clock.
  2403. */
  2404. u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
  2405. tmp &= ~VBUS_CTRL_1510;
  2406. omap_writel(tmp, FUNC_MUX_CTRL_0);
  2407. tmp |= VBUS_MODE_1510;
  2408. tmp &= ~VBUS_CTRL_1510;
  2409. omap_writel(tmp, FUNC_MUX_CTRL_0);
  2410. }
  2411. } else {
  2412. /* The transceiver may package some GPIO logic or handle
  2413. * loopback and/or transceiverless setup; if we find one,
  2414. * use it. Except for OTG, we don't _need_ to talk to one;
  2415. * but not having one probably means no VBUS detection.
  2416. */
  2417. xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
  2418. if (!IS_ERR_OR_NULL(xceiv))
  2419. type = xceiv->label;
  2420. else if (config->otg) {
  2421. DBG("OTG requires external transceiver!\n");
  2422. goto cleanup0;
  2423. }
  2424. hmc = HMC_1610;
  2425. switch (hmc) {
  2426. case 0: /* POWERUP DEFAULT == 0 */
  2427. case 4:
  2428. case 12:
  2429. case 20:
  2430. if (!cpu_is_omap1710()) {
  2431. type = "integrated";
  2432. break;
  2433. }
  2434. /* FALL THROUGH */
  2435. case 3:
  2436. case 11:
  2437. case 16:
  2438. case 19:
  2439. case 25:
  2440. if (IS_ERR_OR_NULL(xceiv)) {
  2441. DBG("external transceiver not registered!\n");
  2442. type = "unknown";
  2443. }
  2444. break;
  2445. case 21: /* internal loopback */
  2446. type = "loopback";
  2447. break;
  2448. case 14: /* transceiverless */
  2449. if (cpu_is_omap1710())
  2450. goto bad_on_1710;
  2451. /* FALL THROUGH */
  2452. case 13:
  2453. case 15:
  2454. type = "no";
  2455. break;
  2456. default:
  2457. bad_on_1710:
  2458. ERR("unrecognized UDC HMC mode %d\n", hmc);
  2459. goto cleanup0;
  2460. }
  2461. }
  2462. INFO("hmc mode %d, %s transceiver\n", hmc, type);
  2463. /* a "gadget" abstracts/virtualizes the controller */
  2464. status = omap_udc_setup(pdev, xceiv);
  2465. if (status)
  2466. goto cleanup0;
  2467. xceiv = NULL;
  2468. /* "udc" is now valid */
  2469. pullup_disable(udc);
  2470. #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  2471. udc->gadget.is_otg = (config->otg != 0);
  2472. #endif
  2473. /* starting with omap1710 es2.0, clear toggle is a separate bit */
  2474. if (omap_readw(UDC_REV) >= 0x61)
  2475. udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
  2476. else
  2477. udc->clr_halt = UDC_RESET_EP;
  2478. /* USB general purpose IRQ: ep0, state changes, dma, etc */
  2479. status = request_irq(pdev->resource[1].start, omap_udc_irq,
  2480. 0, driver_name, udc);
  2481. if (status != 0) {
  2482. ERR("can't get irq %d, err %d\n",
  2483. (int) pdev->resource[1].start, status);
  2484. goto cleanup1;
  2485. }
  2486. /* USB "non-iso" IRQ (PIO for all but ep0) */
  2487. status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
  2488. 0, "omap_udc pio", udc);
  2489. if (status != 0) {
  2490. ERR("can't get irq %d, err %d\n",
  2491. (int) pdev->resource[2].start, status);
  2492. goto cleanup2;
  2493. }
  2494. #ifdef USE_ISO
  2495. status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
  2496. 0, "omap_udc iso", udc);
  2497. if (status != 0) {
  2498. ERR("can't get irq %d, err %d\n",
  2499. (int) pdev->resource[3].start, status);
  2500. goto cleanup3;
  2501. }
  2502. #endif
  2503. if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
  2504. udc->dc_clk = dc_clk;
  2505. udc->hhc_clk = hhc_clk;
  2506. clk_disable(hhc_clk);
  2507. clk_disable(dc_clk);
  2508. }
  2509. create_proc_file();
  2510. status = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
  2511. omap_udc_release);
  2512. if (status)
  2513. goto cleanup4;
  2514. return 0;
  2515. cleanup4:
  2516. remove_proc_file();
  2517. #ifdef USE_ISO
  2518. cleanup3:
  2519. free_irq(pdev->resource[2].start, udc);
  2520. #endif
  2521. cleanup2:
  2522. free_irq(pdev->resource[1].start, udc);
  2523. cleanup1:
  2524. kfree(udc);
  2525. udc = NULL;
  2526. cleanup0:
  2527. if (!IS_ERR_OR_NULL(xceiv))
  2528. usb_put_phy(xceiv);
  2529. if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
  2530. clk_disable(hhc_clk);
  2531. clk_disable(dc_clk);
  2532. clk_put(hhc_clk);
  2533. clk_put(dc_clk);
  2534. }
  2535. release_mem_region(pdev->resource[0].start,
  2536. pdev->resource[0].end - pdev->resource[0].start + 1);
  2537. return status;
  2538. }
  2539. static int omap_udc_remove(struct platform_device *pdev)
  2540. {
  2541. DECLARE_COMPLETION_ONSTACK(done);
  2542. if (!udc)
  2543. return -ENODEV;
  2544. usb_del_gadget_udc(&udc->gadget);
  2545. if (udc->driver)
  2546. return -EBUSY;
  2547. udc->done = &done;
  2548. pullup_disable(udc);
  2549. if (!IS_ERR_OR_NULL(udc->transceiver)) {
  2550. usb_put_phy(udc->transceiver);
  2551. udc->transceiver = NULL;
  2552. }
  2553. omap_writew(0, UDC_SYSCON1);
  2554. remove_proc_file();
  2555. #ifdef USE_ISO
  2556. free_irq(pdev->resource[3].start, udc);
  2557. #endif
  2558. free_irq(pdev->resource[2].start, udc);
  2559. free_irq(pdev->resource[1].start, udc);
  2560. if (udc->dc_clk) {
  2561. if (udc->clk_requested)
  2562. omap_udc_enable_clock(0);
  2563. clk_put(udc->hhc_clk);
  2564. clk_put(udc->dc_clk);
  2565. }
  2566. release_mem_region(pdev->resource[0].start,
  2567. pdev->resource[0].end - pdev->resource[0].start + 1);
  2568. wait_for_completion(&done);
  2569. return 0;
  2570. }
  2571. /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
  2572. * system is forced into deep sleep
  2573. *
  2574. * REVISIT we should probably reject suspend requests when there's a host
  2575. * session active, rather than disconnecting, at least on boards that can
  2576. * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
  2577. * make host resumes and VBUS detection trigger OMAP wakeup events; that
  2578. * may involve talking to an external transceiver (e.g. isp1301).
  2579. */
  2580. static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
  2581. {
  2582. u32 devstat;
  2583. devstat = omap_readw(UDC_DEVSTAT);
  2584. /* we're requesting 48 MHz clock if the pullup is enabled
  2585. * (== we're attached to the host) and we're not suspended,
  2586. * which would prevent entry to deep sleep...
  2587. */
  2588. if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
  2589. WARNING("session active; suspend requires disconnect\n");
  2590. omap_pullup(&udc->gadget, 0);
  2591. }
  2592. return 0;
  2593. }
  2594. static int omap_udc_resume(struct platform_device *dev)
  2595. {
  2596. DBG("resume + wakeup/SRP\n");
  2597. omap_pullup(&udc->gadget, 1);
  2598. /* maybe the host would enumerate us if we nudged it */
  2599. msleep(100);
  2600. return omap_wakeup(&udc->gadget);
  2601. }
  2602. /*-------------------------------------------------------------------------*/
  2603. static struct platform_driver udc_driver = {
  2604. .probe = omap_udc_probe,
  2605. .remove = omap_udc_remove,
  2606. .suspend = omap_udc_suspend,
  2607. .resume = omap_udc_resume,
  2608. .driver = {
  2609. .owner = THIS_MODULE,
  2610. .name = (char *) driver_name,
  2611. },
  2612. };
  2613. module_platform_driver(udc_driver);
  2614. MODULE_DESCRIPTION(DRIVER_DESC);
  2615. MODULE_LICENSE("GPL");
  2616. MODULE_ALIAS("platform:omap_udc");