ep0.c 26 KB

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  1. /**
  2. * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
  3. *
  4. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5. *
  6. * Authors: Felipe Balbi <balbi@ti.com>,
  7. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8. *
  9. * Redistribution and use in source and binary forms, with or without
  10. * modification, are permitted provided that the following conditions
  11. * are met:
  12. * 1. Redistributions of source code must retain the above copyright
  13. * notice, this list of conditions, and the following disclaimer,
  14. * without modification.
  15. * 2. Redistributions in binary form must reproduce the above copyright
  16. * notice, this list of conditions and the following disclaimer in the
  17. * documentation and/or other materials provided with the distribution.
  18. * 3. The names of the above-listed copyright holders may not be used
  19. * to endorse or promote products derived from this software without
  20. * specific prior written permission.
  21. *
  22. * ALTERNATIVELY, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2, as published by the Free
  24. * Software Foundation.
  25. *
  26. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37. */
  38. #include <linux/kernel.h>
  39. #include <linux/slab.h>
  40. #include <linux/spinlock.h>
  41. #include <linux/platform_device.h>
  42. #include <linux/pm_runtime.h>
  43. #include <linux/interrupt.h>
  44. #include <linux/io.h>
  45. #include <linux/list.h>
  46. #include <linux/dma-mapping.h>
  47. #include <linux/usb/ch9.h>
  48. #include <linux/usb/gadget.h>
  49. #include <linux/usb/composite.h>
  50. #include "core.h"
  51. #include "gadget.h"
  52. #include "io.h"
  53. static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  54. static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  55. struct dwc3_ep *dep, struct dwc3_request *req);
  56. static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  57. {
  58. switch (state) {
  59. case EP0_UNCONNECTED:
  60. return "Unconnected";
  61. case EP0_SETUP_PHASE:
  62. return "Setup Phase";
  63. case EP0_DATA_PHASE:
  64. return "Data Phase";
  65. case EP0_STATUS_PHASE:
  66. return "Status Phase";
  67. default:
  68. return "UNKNOWN";
  69. }
  70. }
  71. static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  72. u32 len, u32 type)
  73. {
  74. struct dwc3_gadget_ep_cmd_params params;
  75. struct dwc3_trb *trb;
  76. struct dwc3_ep *dep;
  77. int ret;
  78. dep = dwc->eps[epnum];
  79. if (dep->flags & DWC3_EP_BUSY) {
  80. dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
  81. return 0;
  82. }
  83. trb = dwc->ep0_trb;
  84. trb->bpl = lower_32_bits(buf_dma);
  85. trb->bph = upper_32_bits(buf_dma);
  86. trb->size = len;
  87. trb->ctrl = type;
  88. trb->ctrl |= (DWC3_TRB_CTRL_HWO
  89. | DWC3_TRB_CTRL_LST
  90. | DWC3_TRB_CTRL_IOC
  91. | DWC3_TRB_CTRL_ISP_IMI);
  92. memset(&params, 0, sizeof(params));
  93. params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  94. params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  95. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
  96. DWC3_DEPCMD_STARTTRANSFER, &params);
  97. if (ret < 0) {
  98. dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
  99. return ret;
  100. }
  101. dep->flags |= DWC3_EP_BUSY;
  102. dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
  103. dep->number);
  104. dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  105. return 0;
  106. }
  107. static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
  108. struct dwc3_request *req)
  109. {
  110. struct dwc3 *dwc = dep->dwc;
  111. req->request.actual = 0;
  112. req->request.status = -EINPROGRESS;
  113. req->epnum = dep->number;
  114. list_add_tail(&req->list, &dep->request_list);
  115. /*
  116. * Gadget driver might not be quick enough to queue a request
  117. * before we get a Transfer Not Ready event on this endpoint.
  118. *
  119. * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
  120. * flag is set, it's telling us that as soon as Gadget queues the
  121. * required request, we should kick the transfer here because the
  122. * IRQ we were waiting for is long gone.
  123. */
  124. if (dep->flags & DWC3_EP_PENDING_REQUEST) {
  125. unsigned direction;
  126. direction = !!(dep->flags & DWC3_EP0_DIR_IN);
  127. if (dwc->ep0state != EP0_DATA_PHASE) {
  128. dev_WARN(dwc->dev, "Unexpected pending request\n");
  129. return 0;
  130. }
  131. __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
  132. dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
  133. DWC3_EP0_DIR_IN);
  134. return 0;
  135. }
  136. /*
  137. * In case gadget driver asked us to delay the STATUS phase,
  138. * handle it here.
  139. */
  140. if (dwc->delayed_status) {
  141. unsigned direction;
  142. direction = !dwc->ep0_expect_in;
  143. dwc->delayed_status = false;
  144. if (dwc->ep0state == EP0_STATUS_PHASE)
  145. __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
  146. else
  147. dev_dbg(dwc->dev, "too early for delayed status\n");
  148. return 0;
  149. }
  150. /*
  151. * Unfortunately we have uncovered a limitation wrt the Data Phase.
  152. *
  153. * Section 9.4 says we can wait for the XferNotReady(DATA) event to
  154. * come before issueing Start Transfer command, but if we do, we will
  155. * miss situations where the host starts another SETUP phase instead of
  156. * the DATA phase. Such cases happen at least on TD.7.6 of the Link
  157. * Layer Compliance Suite.
  158. *
  159. * The problem surfaces due to the fact that in case of back-to-back
  160. * SETUP packets there will be no XferNotReady(DATA) generated and we
  161. * will be stuck waiting for XferNotReady(DATA) forever.
  162. *
  163. * By looking at tables 9-13 and 9-14 of the Databook, we can see that
  164. * it tells us to start Data Phase right away. It also mentions that if
  165. * we receive a SETUP phase instead of the DATA phase, core will issue
  166. * XferComplete for the DATA phase, before actually initiating it in
  167. * the wire, with the TRB's status set to "SETUP_PENDING". Such status
  168. * can only be used to print some debugging logs, as the core expects
  169. * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
  170. * just so it completes right away, without transferring anything and,
  171. * only then, we can go back to the SETUP phase.
  172. *
  173. * Because of this scenario, SNPS decided to change the programming
  174. * model of control transfers and support on-demand transfers only for
  175. * the STATUS phase. To fix the issue we have now, we will always wait
  176. * for gadget driver to queue the DATA phase's struct usb_request, then
  177. * start it right away.
  178. *
  179. * If we're actually in a 2-stage transfer, we will wait for
  180. * XferNotReady(STATUS).
  181. */
  182. if (dwc->three_stage_setup) {
  183. unsigned direction;
  184. direction = dwc->ep0_expect_in;
  185. dwc->ep0state = EP0_DATA_PHASE;
  186. __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
  187. dep->flags &= ~DWC3_EP0_DIR_IN;
  188. }
  189. return 0;
  190. }
  191. int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
  192. gfp_t gfp_flags)
  193. {
  194. struct dwc3_request *req = to_dwc3_request(request);
  195. struct dwc3_ep *dep = to_dwc3_ep(ep);
  196. struct dwc3 *dwc = dep->dwc;
  197. unsigned long flags;
  198. int ret;
  199. spin_lock_irqsave(&dwc->lock, flags);
  200. if (!dep->endpoint.desc) {
  201. dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
  202. request, dep->name);
  203. ret = -ESHUTDOWN;
  204. goto out;
  205. }
  206. /* we share one TRB for ep0/1 */
  207. if (!list_empty(&dep->request_list)) {
  208. ret = -EBUSY;
  209. goto out;
  210. }
  211. dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
  212. request, dep->name, request->length,
  213. dwc3_ep0_state_string(dwc->ep0state));
  214. ret = __dwc3_gadget_ep0_queue(dep, req);
  215. out:
  216. spin_unlock_irqrestore(&dwc->lock, flags);
  217. return ret;
  218. }
  219. static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
  220. {
  221. struct dwc3_ep *dep;
  222. /* reinitialize physical ep1 */
  223. dep = dwc->eps[1];
  224. dep->flags = DWC3_EP_ENABLED;
  225. /* stall is always issued on EP0 */
  226. dep = dwc->eps[0];
  227. __dwc3_gadget_ep_set_halt(dep, 1);
  228. dep->flags = DWC3_EP_ENABLED;
  229. dwc->delayed_status = false;
  230. if (!list_empty(&dep->request_list)) {
  231. struct dwc3_request *req;
  232. req = next_request(&dep->request_list);
  233. dwc3_gadget_giveback(dep, req, -ECONNRESET);
  234. }
  235. dwc->ep0state = EP0_SETUP_PHASE;
  236. dwc3_ep0_out_start(dwc);
  237. }
  238. int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
  239. {
  240. struct dwc3_ep *dep = to_dwc3_ep(ep);
  241. struct dwc3 *dwc = dep->dwc;
  242. dwc3_ep0_stall_and_restart(dwc);
  243. return 0;
  244. }
  245. void dwc3_ep0_out_start(struct dwc3 *dwc)
  246. {
  247. int ret;
  248. ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
  249. DWC3_TRBCTL_CONTROL_SETUP);
  250. WARN_ON(ret < 0);
  251. }
  252. static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
  253. {
  254. struct dwc3_ep *dep;
  255. u32 windex = le16_to_cpu(wIndex_le);
  256. u32 epnum;
  257. epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
  258. if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
  259. epnum |= 1;
  260. dep = dwc->eps[epnum];
  261. if (dep->flags & DWC3_EP_ENABLED)
  262. return dep;
  263. return NULL;
  264. }
  265. static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
  266. {
  267. }
  268. /*
  269. * ch 9.4.5
  270. */
  271. static int dwc3_ep0_handle_status(struct dwc3 *dwc,
  272. struct usb_ctrlrequest *ctrl)
  273. {
  274. struct dwc3_ep *dep;
  275. u32 recip;
  276. u32 reg;
  277. u16 usb_status = 0;
  278. __le16 *response_pkt;
  279. recip = ctrl->bRequestType & USB_RECIP_MASK;
  280. switch (recip) {
  281. case USB_RECIP_DEVICE:
  282. /*
  283. * LTM will be set once we know how to set this in HW.
  284. */
  285. usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
  286. if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
  287. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  288. if (reg & DWC3_DCTL_INITU1ENA)
  289. usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
  290. if (reg & DWC3_DCTL_INITU2ENA)
  291. usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
  292. }
  293. break;
  294. case USB_RECIP_INTERFACE:
  295. /*
  296. * Function Remote Wake Capable D0
  297. * Function Remote Wakeup D1
  298. */
  299. break;
  300. case USB_RECIP_ENDPOINT:
  301. dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
  302. if (!dep)
  303. return -EINVAL;
  304. if (dep->flags & DWC3_EP_STALL)
  305. usb_status = 1 << USB_ENDPOINT_HALT;
  306. break;
  307. default:
  308. return -EINVAL;
  309. };
  310. response_pkt = (__le16 *) dwc->setup_buf;
  311. *response_pkt = cpu_to_le16(usb_status);
  312. dep = dwc->eps[0];
  313. dwc->ep0_usb_req.dep = dep;
  314. dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
  315. dwc->ep0_usb_req.request.buf = dwc->setup_buf;
  316. dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
  317. return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
  318. }
  319. static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
  320. struct usb_ctrlrequest *ctrl, int set)
  321. {
  322. struct dwc3_ep *dep;
  323. u32 recip;
  324. u32 wValue;
  325. u32 wIndex;
  326. u32 reg;
  327. int ret;
  328. enum usb_device_state state;
  329. wValue = le16_to_cpu(ctrl->wValue);
  330. wIndex = le16_to_cpu(ctrl->wIndex);
  331. recip = ctrl->bRequestType & USB_RECIP_MASK;
  332. state = dwc->gadget.state;
  333. switch (recip) {
  334. case USB_RECIP_DEVICE:
  335. switch (wValue) {
  336. case USB_DEVICE_REMOTE_WAKEUP:
  337. break;
  338. /*
  339. * 9.4.1 says only only for SS, in AddressState only for
  340. * default control pipe
  341. */
  342. case USB_DEVICE_U1_ENABLE:
  343. if (state != USB_STATE_CONFIGURED)
  344. return -EINVAL;
  345. if (dwc->speed != DWC3_DSTS_SUPERSPEED)
  346. return -EINVAL;
  347. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  348. if (set)
  349. reg |= DWC3_DCTL_INITU1ENA;
  350. else
  351. reg &= ~DWC3_DCTL_INITU1ENA;
  352. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  353. break;
  354. case USB_DEVICE_U2_ENABLE:
  355. if (state != USB_STATE_CONFIGURED)
  356. return -EINVAL;
  357. if (dwc->speed != DWC3_DSTS_SUPERSPEED)
  358. return -EINVAL;
  359. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  360. if (set)
  361. reg |= DWC3_DCTL_INITU2ENA;
  362. else
  363. reg &= ~DWC3_DCTL_INITU2ENA;
  364. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  365. break;
  366. case USB_DEVICE_LTM_ENABLE:
  367. return -EINVAL;
  368. break;
  369. case USB_DEVICE_TEST_MODE:
  370. if ((wIndex & 0xff) != 0)
  371. return -EINVAL;
  372. if (!set)
  373. return -EINVAL;
  374. dwc->test_mode_nr = wIndex >> 8;
  375. dwc->test_mode = true;
  376. break;
  377. default:
  378. return -EINVAL;
  379. }
  380. break;
  381. case USB_RECIP_INTERFACE:
  382. switch (wValue) {
  383. case USB_INTRF_FUNC_SUSPEND:
  384. if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
  385. /* XXX enable Low power suspend */
  386. ;
  387. if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
  388. /* XXX enable remote wakeup */
  389. ;
  390. break;
  391. default:
  392. return -EINVAL;
  393. }
  394. break;
  395. case USB_RECIP_ENDPOINT:
  396. switch (wValue) {
  397. case USB_ENDPOINT_HALT:
  398. dep = dwc3_wIndex_to_dep(dwc, wIndex);
  399. if (!dep)
  400. return -EINVAL;
  401. ret = __dwc3_gadget_ep_set_halt(dep, set);
  402. if (ret)
  403. return -EINVAL;
  404. break;
  405. default:
  406. return -EINVAL;
  407. }
  408. break;
  409. default:
  410. return -EINVAL;
  411. };
  412. return 0;
  413. }
  414. static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  415. {
  416. enum usb_device_state state = dwc->gadget.state;
  417. u32 addr;
  418. u32 reg;
  419. addr = le16_to_cpu(ctrl->wValue);
  420. if (addr > 127) {
  421. dev_dbg(dwc->dev, "invalid device address %d\n", addr);
  422. return -EINVAL;
  423. }
  424. if (state == USB_STATE_CONFIGURED) {
  425. dev_dbg(dwc->dev, "trying to set address when configured\n");
  426. return -EINVAL;
  427. }
  428. reg = dwc3_readl(dwc->regs, DWC3_DCFG);
  429. reg &= ~(DWC3_DCFG_DEVADDR_MASK);
  430. reg |= DWC3_DCFG_DEVADDR(addr);
  431. dwc3_writel(dwc->regs, DWC3_DCFG, reg);
  432. if (addr)
  433. usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
  434. else
  435. usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
  436. return 0;
  437. }
  438. static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  439. {
  440. int ret;
  441. spin_unlock(&dwc->lock);
  442. ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
  443. spin_lock(&dwc->lock);
  444. return ret;
  445. }
  446. static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  447. {
  448. enum usb_device_state state = dwc->gadget.state;
  449. u32 cfg;
  450. int ret;
  451. u32 reg;
  452. dwc->start_config_issued = false;
  453. cfg = le16_to_cpu(ctrl->wValue);
  454. switch (state) {
  455. case USB_STATE_DEFAULT:
  456. return -EINVAL;
  457. break;
  458. case USB_STATE_ADDRESS:
  459. ret = dwc3_ep0_delegate_req(dwc, ctrl);
  460. /* if the cfg matches and the cfg is non zero */
  461. if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
  462. usb_gadget_set_state(&dwc->gadget,
  463. USB_STATE_CONFIGURED);
  464. /*
  465. * Enable transition to U1/U2 state when
  466. * nothing is pending from application.
  467. */
  468. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  469. reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
  470. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  471. dwc->resize_fifos = true;
  472. dev_dbg(dwc->dev, "resize fifos flag SET\n");
  473. }
  474. break;
  475. case USB_STATE_CONFIGURED:
  476. ret = dwc3_ep0_delegate_req(dwc, ctrl);
  477. if (!cfg)
  478. usb_gadget_set_state(&dwc->gadget,
  479. USB_STATE_ADDRESS);
  480. break;
  481. default:
  482. ret = -EINVAL;
  483. }
  484. return ret;
  485. }
  486. static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
  487. {
  488. struct dwc3_ep *dep = to_dwc3_ep(ep);
  489. struct dwc3 *dwc = dep->dwc;
  490. u32 param = 0;
  491. u32 reg;
  492. struct timing {
  493. u8 u1sel;
  494. u8 u1pel;
  495. u16 u2sel;
  496. u16 u2pel;
  497. } __packed timing;
  498. int ret;
  499. memcpy(&timing, req->buf, sizeof(timing));
  500. dwc->u1sel = timing.u1sel;
  501. dwc->u1pel = timing.u1pel;
  502. dwc->u2sel = le16_to_cpu(timing.u2sel);
  503. dwc->u2pel = le16_to_cpu(timing.u2pel);
  504. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  505. if (reg & DWC3_DCTL_INITU2ENA)
  506. param = dwc->u2pel;
  507. if (reg & DWC3_DCTL_INITU1ENA)
  508. param = dwc->u1pel;
  509. /*
  510. * According to Synopsys Databook, if parameter is
  511. * greater than 125, a value of zero should be
  512. * programmed in the register.
  513. */
  514. if (param > 125)
  515. param = 0;
  516. /* now that we have the time, issue DGCMD Set Sel */
  517. ret = dwc3_send_gadget_generic_command(dwc,
  518. DWC3_DGCMD_SET_PERIODIC_PAR, param);
  519. WARN_ON(ret < 0);
  520. }
  521. static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  522. {
  523. struct dwc3_ep *dep;
  524. enum usb_device_state state = dwc->gadget.state;
  525. u16 wLength;
  526. u16 wValue;
  527. if (state == USB_STATE_DEFAULT)
  528. return -EINVAL;
  529. wValue = le16_to_cpu(ctrl->wValue);
  530. wLength = le16_to_cpu(ctrl->wLength);
  531. if (wLength != 6) {
  532. dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
  533. wLength);
  534. return -EINVAL;
  535. }
  536. /*
  537. * To handle Set SEL we need to receive 6 bytes from Host. So let's
  538. * queue a usb_request for 6 bytes.
  539. *
  540. * Remember, though, this controller can't handle non-wMaxPacketSize
  541. * aligned transfers on the OUT direction, so we queue a request for
  542. * wMaxPacketSize instead.
  543. */
  544. dep = dwc->eps[0];
  545. dwc->ep0_usb_req.dep = dep;
  546. dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
  547. dwc->ep0_usb_req.request.buf = dwc->setup_buf;
  548. dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
  549. return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
  550. }
  551. static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  552. {
  553. u16 wLength;
  554. u16 wValue;
  555. u16 wIndex;
  556. wValue = le16_to_cpu(ctrl->wValue);
  557. wLength = le16_to_cpu(ctrl->wLength);
  558. wIndex = le16_to_cpu(ctrl->wIndex);
  559. if (wIndex || wLength)
  560. return -EINVAL;
  561. /*
  562. * REVISIT It's unclear from Databook what to do with this
  563. * value. For now, just cache it.
  564. */
  565. dwc->isoch_delay = wValue;
  566. return 0;
  567. }
  568. static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  569. {
  570. int ret;
  571. switch (ctrl->bRequest) {
  572. case USB_REQ_GET_STATUS:
  573. dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
  574. ret = dwc3_ep0_handle_status(dwc, ctrl);
  575. break;
  576. case USB_REQ_CLEAR_FEATURE:
  577. dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
  578. ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
  579. break;
  580. case USB_REQ_SET_FEATURE:
  581. dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
  582. ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
  583. break;
  584. case USB_REQ_SET_ADDRESS:
  585. dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
  586. ret = dwc3_ep0_set_address(dwc, ctrl);
  587. break;
  588. case USB_REQ_SET_CONFIGURATION:
  589. dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
  590. ret = dwc3_ep0_set_config(dwc, ctrl);
  591. break;
  592. case USB_REQ_SET_SEL:
  593. dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n");
  594. ret = dwc3_ep0_set_sel(dwc, ctrl);
  595. break;
  596. case USB_REQ_SET_ISOCH_DELAY:
  597. dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
  598. ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
  599. break;
  600. default:
  601. dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
  602. ret = dwc3_ep0_delegate_req(dwc, ctrl);
  603. break;
  604. };
  605. return ret;
  606. }
  607. static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
  608. const struct dwc3_event_depevt *event)
  609. {
  610. struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
  611. int ret = -EINVAL;
  612. u32 len;
  613. if (!dwc->gadget_driver)
  614. goto out;
  615. len = le16_to_cpu(ctrl->wLength);
  616. if (!len) {
  617. dwc->three_stage_setup = false;
  618. dwc->ep0_expect_in = false;
  619. dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
  620. } else {
  621. dwc->three_stage_setup = true;
  622. dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
  623. dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
  624. }
  625. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
  626. ret = dwc3_ep0_std_request(dwc, ctrl);
  627. else
  628. ret = dwc3_ep0_delegate_req(dwc, ctrl);
  629. if (ret == USB_GADGET_DELAYED_STATUS)
  630. dwc->delayed_status = true;
  631. out:
  632. if (ret < 0)
  633. dwc3_ep0_stall_and_restart(dwc);
  634. }
  635. static void dwc3_ep0_complete_data(struct dwc3 *dwc,
  636. const struct dwc3_event_depevt *event)
  637. {
  638. struct dwc3_request *r = NULL;
  639. struct usb_request *ur;
  640. struct dwc3_trb *trb;
  641. struct dwc3_ep *ep0;
  642. u32 transferred;
  643. u32 status;
  644. u32 length;
  645. u8 epnum;
  646. epnum = event->endpoint_number;
  647. ep0 = dwc->eps[0];
  648. dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
  649. r = next_request(&ep0->request_list);
  650. ur = &r->request;
  651. trb = dwc->ep0_trb;
  652. status = DWC3_TRB_SIZE_TRBSTS(trb->size);
  653. if (status == DWC3_TRBSTS_SETUP_PENDING) {
  654. dev_dbg(dwc->dev, "Setup Pending received\n");
  655. if (r)
  656. dwc3_gadget_giveback(ep0, r, -ECONNRESET);
  657. return;
  658. }
  659. length = trb->size & DWC3_TRB_SIZE_MASK;
  660. if (dwc->ep0_bounced) {
  661. unsigned transfer_size = ur->length;
  662. unsigned maxp = ep0->endpoint.maxpacket;
  663. transfer_size += (maxp - (transfer_size % maxp));
  664. transferred = min_t(u32, ur->length,
  665. transfer_size - length);
  666. memcpy(ur->buf, dwc->ep0_bounce, transferred);
  667. } else {
  668. transferred = ur->length - length;
  669. }
  670. ur->actual += transferred;
  671. if ((epnum & 1) && ur->actual < ur->length) {
  672. /* for some reason we did not get everything out */
  673. dwc3_ep0_stall_and_restart(dwc);
  674. } else {
  675. /*
  676. * handle the case where we have to send a zero packet. This
  677. * seems to be case when req.length > maxpacket. Could it be?
  678. */
  679. if (r)
  680. dwc3_gadget_giveback(ep0, r, 0);
  681. }
  682. }
  683. static void dwc3_ep0_complete_status(struct dwc3 *dwc,
  684. const struct dwc3_event_depevt *event)
  685. {
  686. struct dwc3_request *r;
  687. struct dwc3_ep *dep;
  688. struct dwc3_trb *trb;
  689. u32 status;
  690. dep = dwc->eps[0];
  691. trb = dwc->ep0_trb;
  692. if (!list_empty(&dep->request_list)) {
  693. r = next_request(&dep->request_list);
  694. dwc3_gadget_giveback(dep, r, 0);
  695. }
  696. if (dwc->test_mode) {
  697. int ret;
  698. ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
  699. if (ret < 0) {
  700. dev_dbg(dwc->dev, "Invalid Test #%d\n",
  701. dwc->test_mode_nr);
  702. dwc3_ep0_stall_and_restart(dwc);
  703. return;
  704. }
  705. }
  706. status = DWC3_TRB_SIZE_TRBSTS(trb->size);
  707. if (status == DWC3_TRBSTS_SETUP_PENDING)
  708. dev_dbg(dwc->dev, "Setup Pending received\n");
  709. dwc->ep0state = EP0_SETUP_PHASE;
  710. dwc3_ep0_out_start(dwc);
  711. }
  712. static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
  713. const struct dwc3_event_depevt *event)
  714. {
  715. struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
  716. dep->flags &= ~DWC3_EP_BUSY;
  717. dep->resource_index = 0;
  718. dwc->setup_packet_pending = false;
  719. switch (dwc->ep0state) {
  720. case EP0_SETUP_PHASE:
  721. dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
  722. dwc3_ep0_inspect_setup(dwc, event);
  723. break;
  724. case EP0_DATA_PHASE:
  725. dev_vdbg(dwc->dev, "Data Phase\n");
  726. dwc3_ep0_complete_data(dwc, event);
  727. break;
  728. case EP0_STATUS_PHASE:
  729. dev_vdbg(dwc->dev, "Status Phase\n");
  730. dwc3_ep0_complete_status(dwc, event);
  731. break;
  732. default:
  733. WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
  734. }
  735. }
  736. static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  737. struct dwc3_ep *dep, struct dwc3_request *req)
  738. {
  739. int ret;
  740. req->direction = !!dep->number;
  741. if (req->request.length == 0) {
  742. ret = dwc3_ep0_start_trans(dwc, dep->number,
  743. dwc->ctrl_req_addr, 0,
  744. DWC3_TRBCTL_CONTROL_DATA);
  745. } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
  746. && (dep->number == 0)) {
  747. u32 transfer_size;
  748. u32 maxpacket;
  749. ret = usb_gadget_map_request(&dwc->gadget, &req->request,
  750. dep->number);
  751. if (ret) {
  752. dev_dbg(dwc->dev, "failed to map request\n");
  753. return;
  754. }
  755. WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
  756. maxpacket = dep->endpoint.maxpacket;
  757. transfer_size = roundup(req->request.length, maxpacket);
  758. dwc->ep0_bounced = true;
  759. /*
  760. * REVISIT in case request length is bigger than
  761. * DWC3_EP0_BOUNCE_SIZE we will need two chained
  762. * TRBs to handle the transfer.
  763. */
  764. ret = dwc3_ep0_start_trans(dwc, dep->number,
  765. dwc->ep0_bounce_addr, transfer_size,
  766. DWC3_TRBCTL_CONTROL_DATA);
  767. } else {
  768. ret = usb_gadget_map_request(&dwc->gadget, &req->request,
  769. dep->number);
  770. if (ret) {
  771. dev_dbg(dwc->dev, "failed to map request\n");
  772. return;
  773. }
  774. ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
  775. req->request.length, DWC3_TRBCTL_CONTROL_DATA);
  776. }
  777. WARN_ON(ret < 0);
  778. }
  779. static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
  780. {
  781. struct dwc3 *dwc = dep->dwc;
  782. u32 type;
  783. type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
  784. : DWC3_TRBCTL_CONTROL_STATUS2;
  785. return dwc3_ep0_start_trans(dwc, dep->number,
  786. dwc->ctrl_req_addr, 0, type);
  787. }
  788. static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
  789. {
  790. if (dwc->resize_fifos) {
  791. dev_dbg(dwc->dev, "starting to resize fifos\n");
  792. dwc3_gadget_resize_tx_fifos(dwc);
  793. dwc->resize_fifos = 0;
  794. }
  795. WARN_ON(dwc3_ep0_start_control_status(dep));
  796. }
  797. static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
  798. const struct dwc3_event_depevt *event)
  799. {
  800. struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
  801. __dwc3_ep0_do_control_status(dwc, dep);
  802. }
  803. static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
  804. {
  805. struct dwc3_gadget_ep_cmd_params params;
  806. u32 cmd;
  807. int ret;
  808. if (!dep->resource_index)
  809. return;
  810. cmd = DWC3_DEPCMD_ENDTRANSFER;
  811. cmd |= DWC3_DEPCMD_CMDIOC;
  812. cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
  813. memset(&params, 0, sizeof(params));
  814. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
  815. WARN_ON_ONCE(ret);
  816. dep->resource_index = 0;
  817. }
  818. static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
  819. const struct dwc3_event_depevt *event)
  820. {
  821. dwc->setup_packet_pending = true;
  822. switch (event->status) {
  823. case DEPEVT_STATUS_CONTROL_DATA:
  824. dev_vdbg(dwc->dev, "Control Data\n");
  825. /*
  826. * We already have a DATA transfer in the controller's cache,
  827. * if we receive a XferNotReady(DATA) we will ignore it, unless
  828. * it's for the wrong direction.
  829. *
  830. * In that case, we must issue END_TRANSFER command to the Data
  831. * Phase we already have started and issue SetStall on the
  832. * control endpoint.
  833. */
  834. if (dwc->ep0_expect_in != event->endpoint_number) {
  835. struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
  836. dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
  837. dwc3_ep0_end_control_data(dwc, dep);
  838. dwc3_ep0_stall_and_restart(dwc);
  839. return;
  840. }
  841. break;
  842. case DEPEVT_STATUS_CONTROL_STATUS:
  843. if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
  844. return;
  845. dev_vdbg(dwc->dev, "Control Status\n");
  846. dwc->ep0state = EP0_STATUS_PHASE;
  847. if (dwc->delayed_status) {
  848. WARN_ON_ONCE(event->endpoint_number != 1);
  849. dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
  850. return;
  851. }
  852. dwc3_ep0_do_control_status(dwc, event);
  853. }
  854. }
  855. void dwc3_ep0_interrupt(struct dwc3 *dwc,
  856. const struct dwc3_event_depevt *event)
  857. {
  858. u8 epnum = event->endpoint_number;
  859. dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
  860. dwc3_ep_event_string(event->endpoint_event),
  861. epnum >> 1, (epnum & 1) ? "in" : "out",
  862. dwc3_ep0_state_string(dwc->ep0state));
  863. switch (event->endpoint_event) {
  864. case DWC3_DEPEVT_XFERCOMPLETE:
  865. dwc3_ep0_xfer_complete(dwc, event);
  866. break;
  867. case DWC3_DEPEVT_XFERNOTREADY:
  868. dwc3_ep0_xfernotready(dwc, event);
  869. break;
  870. case DWC3_DEPEVT_XFERINPROGRESS:
  871. case DWC3_DEPEVT_RXTXFIFOEVT:
  872. case DWC3_DEPEVT_STREAMEVT:
  873. case DWC3_DEPEVT_EPCMDCMPLT:
  874. break;
  875. }
  876. }