dwc3-omap.c 16 KB

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  1. /**
  2. * dwc3-omap.c - OMAP Specific Glue layer
  3. *
  4. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5. *
  6. * Authors: Felipe Balbi <balbi@ti.com>,
  7. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8. *
  9. * Redistribution and use in source and binary forms, with or without
  10. * modification, are permitted provided that the following conditions
  11. * are met:
  12. * 1. Redistributions of source code must retain the above copyright
  13. * notice, this list of conditions, and the following disclaimer,
  14. * without modification.
  15. * 2. Redistributions in binary form must reproduce the above copyright
  16. * notice, this list of conditions and the following disclaimer in the
  17. * documentation and/or other materials provided with the distribution.
  18. * 3. The names of the above-listed copyright holders may not be used
  19. * to endorse or promote products derived from this software without
  20. * specific prior written permission.
  21. *
  22. * ALTERNATIVELY, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2, as published by the Free
  24. * Software Foundation.
  25. *
  26. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37. */
  38. #include <linux/module.h>
  39. #include <linux/kernel.h>
  40. #include <linux/slab.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/spinlock.h>
  43. #include <linux/platform_device.h>
  44. #include <linux/platform_data/dwc3-omap.h>
  45. #include <linux/usb/dwc3-omap.h>
  46. #include <linux/pm_runtime.h>
  47. #include <linux/dma-mapping.h>
  48. #include <linux/ioport.h>
  49. #include <linux/io.h>
  50. #include <linux/of.h>
  51. #include <linux/of_platform.h>
  52. #include <linux/usb/otg.h>
  53. /*
  54. * All these registers belong to OMAP's Wrapper around the
  55. * DesignWare USB3 Core.
  56. */
  57. #define USBOTGSS_REVISION 0x0000
  58. #define USBOTGSS_SYSCONFIG 0x0010
  59. #define USBOTGSS_IRQ_EOI 0x0020
  60. #define USBOTGSS_EOI_OFFSET 0x0008
  61. #define USBOTGSS_IRQSTATUS_RAW_0 0x0024
  62. #define USBOTGSS_IRQSTATUS_0 0x0028
  63. #define USBOTGSS_IRQENABLE_SET_0 0x002c
  64. #define USBOTGSS_IRQENABLE_CLR_0 0x0030
  65. #define USBOTGSS_IRQ0_OFFSET 0x0004
  66. #define USBOTGSS_IRQSTATUS_RAW_1 0x0030
  67. #define USBOTGSS_IRQSTATUS_1 0x0034
  68. #define USBOTGSS_IRQENABLE_SET_1 0x0038
  69. #define USBOTGSS_IRQENABLE_CLR_1 0x003c
  70. #define USBOTGSS_IRQSTATUS_RAW_2 0x0040
  71. #define USBOTGSS_IRQSTATUS_2 0x0044
  72. #define USBOTGSS_IRQENABLE_SET_2 0x0048
  73. #define USBOTGSS_IRQENABLE_CLR_2 0x004c
  74. #define USBOTGSS_IRQSTATUS_RAW_3 0x0050
  75. #define USBOTGSS_IRQSTATUS_3 0x0054
  76. #define USBOTGSS_IRQENABLE_SET_3 0x0058
  77. #define USBOTGSS_IRQENABLE_CLR_3 0x005c
  78. #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
  79. #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
  80. #define USBOTGSS_IRQSTATUS_MISC 0x0038
  81. #define USBOTGSS_IRQENABLE_SET_MISC 0x003c
  82. #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
  83. #define USBOTGSS_IRQMISC_OFFSET 0x03fc
  84. #define USBOTGSS_UTMI_OTG_CTRL 0x0080
  85. #define USBOTGSS_UTMI_OTG_STATUS 0x0084
  86. #define USBOTGSS_UTMI_OTG_OFFSET 0x0480
  87. #define USBOTGSS_TXFIFO_DEPTH 0x0508
  88. #define USBOTGSS_RXFIFO_DEPTH 0x050c
  89. #define USBOTGSS_MMRAM_OFFSET 0x0100
  90. #define USBOTGSS_FLADJ 0x0104
  91. #define USBOTGSS_DEBUG_CFG 0x0108
  92. #define USBOTGSS_DEBUG_DATA 0x010c
  93. #define USBOTGSS_DEV_EBC_EN 0x0110
  94. #define USBOTGSS_DEBUG_OFFSET 0x0600
  95. /* REVISION REGISTER */
  96. #define USBOTGSS_REVISION_XMAJOR(reg) ((reg >> 8) & 0x7)
  97. #define USBOTGSS_REVISION_XMAJOR1 1
  98. #define USBOTGSS_REVISION_XMAJOR2 2
  99. /* SYSCONFIG REGISTER */
  100. #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
  101. /* IRQ_EOI REGISTER */
  102. #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
  103. /* IRQS0 BITS */
  104. #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
  105. /* IRQMISC BITS */
  106. #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17)
  107. #define USBOTGSS_IRQMISC_OEVT (1 << 16)
  108. #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13)
  109. #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12)
  110. #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11)
  111. #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8)
  112. #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5)
  113. #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4)
  114. #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3)
  115. #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0)
  116. /* UTMI_OTG_CTRL REGISTER */
  117. #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
  118. #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
  119. #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
  120. #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
  121. /* UTMI_OTG_STATUS REGISTER */
  122. #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
  123. #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
  124. #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
  125. #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
  126. #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
  127. #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
  128. #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
  129. struct dwc3_omap {
  130. /* device lock */
  131. spinlock_t lock;
  132. struct device *dev;
  133. int irq;
  134. void __iomem *base;
  135. u32 utmi_otg_status;
  136. u32 utmi_otg_offset;
  137. u32 irqmisc_offset;
  138. u32 irq_eoi_offset;
  139. u32 debug_offset;
  140. u32 irq0_offset;
  141. u32 revision;
  142. u32 dma_status:1;
  143. };
  144. static struct dwc3_omap *_omap;
  145. static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
  146. {
  147. return readl(base + offset);
  148. }
  149. static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
  150. {
  151. writel(value, base + offset);
  152. }
  153. static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
  154. {
  155. return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
  156. omap->utmi_otg_offset);
  157. }
  158. static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
  159. {
  160. dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
  161. omap->utmi_otg_offset, value);
  162. }
  163. static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
  164. {
  165. return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
  166. omap->irq0_offset);
  167. }
  168. static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
  169. {
  170. dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
  171. omap->irq0_offset, value);
  172. }
  173. static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
  174. {
  175. return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
  176. omap->irqmisc_offset);
  177. }
  178. static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
  179. {
  180. dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
  181. omap->irqmisc_offset, value);
  182. }
  183. static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
  184. {
  185. dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
  186. omap->irqmisc_offset, value);
  187. }
  188. static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
  189. {
  190. dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
  191. omap->irq0_offset, value);
  192. }
  193. int dwc3_omap_mailbox(enum omap_dwc3_vbus_id_status status)
  194. {
  195. u32 val;
  196. struct dwc3_omap *omap = _omap;
  197. if (!omap)
  198. return -EPROBE_DEFER;
  199. switch (status) {
  200. case OMAP_DWC3_ID_GROUND:
  201. dev_dbg(omap->dev, "ID GND\n");
  202. val = dwc3_omap_read_utmi_status(omap);
  203. val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
  204. | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
  205. | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
  206. val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
  207. | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
  208. dwc3_omap_write_utmi_status(omap, val);
  209. break;
  210. case OMAP_DWC3_VBUS_VALID:
  211. dev_dbg(omap->dev, "VBUS Connect\n");
  212. val = dwc3_omap_read_utmi_status(omap);
  213. val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
  214. val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
  215. | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
  216. | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
  217. | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
  218. dwc3_omap_write_utmi_status(omap, val);
  219. break;
  220. case OMAP_DWC3_ID_FLOAT:
  221. case OMAP_DWC3_VBUS_OFF:
  222. dev_dbg(omap->dev, "VBUS Disconnect\n");
  223. val = dwc3_omap_read_utmi_status(omap);
  224. val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
  225. | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
  226. | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
  227. val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
  228. | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
  229. dwc3_omap_write_utmi_status(omap, val);
  230. break;
  231. default:
  232. dev_dbg(omap->dev, "ID float\n");
  233. }
  234. return 0;
  235. }
  236. EXPORT_SYMBOL_GPL(dwc3_omap_mailbox);
  237. static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
  238. {
  239. struct dwc3_omap *omap = _omap;
  240. u32 reg;
  241. spin_lock(&omap->lock);
  242. reg = dwc3_omap_read_irqmisc_status(omap);
  243. if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
  244. dev_dbg(omap->dev, "DMA Disable was Cleared\n");
  245. omap->dma_status = false;
  246. }
  247. if (reg & USBOTGSS_IRQMISC_OEVT)
  248. dev_dbg(omap->dev, "OTG Event\n");
  249. if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
  250. dev_dbg(omap->dev, "DRVVBUS Rise\n");
  251. if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
  252. dev_dbg(omap->dev, "CHRGVBUS Rise\n");
  253. if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
  254. dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
  255. if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
  256. dev_dbg(omap->dev, "IDPULLUP Rise\n");
  257. if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
  258. dev_dbg(omap->dev, "DRVVBUS Fall\n");
  259. if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
  260. dev_dbg(omap->dev, "CHRGVBUS Fall\n");
  261. if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
  262. dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
  263. if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
  264. dev_dbg(omap->dev, "IDPULLUP Fall\n");
  265. dwc3_omap_write_irqmisc_status(omap, reg);
  266. reg = dwc3_omap_read_irq0_status(omap);
  267. dwc3_omap_write_irq0_status(omap, reg);
  268. spin_unlock(&omap->lock);
  269. return IRQ_HANDLED;
  270. }
  271. static int dwc3_omap_remove_core(struct device *dev, void *c)
  272. {
  273. struct platform_device *pdev = to_platform_device(dev);
  274. platform_device_unregister(pdev);
  275. return 0;
  276. }
  277. static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
  278. {
  279. u32 reg;
  280. /* enable all IRQs */
  281. reg = USBOTGSS_IRQO_COREIRQ_ST;
  282. dwc3_omap_write_irq0_set(omap, reg);
  283. reg = (USBOTGSS_IRQMISC_OEVT |
  284. USBOTGSS_IRQMISC_DRVVBUS_RISE |
  285. USBOTGSS_IRQMISC_CHRGVBUS_RISE |
  286. USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
  287. USBOTGSS_IRQMISC_IDPULLUP_RISE |
  288. USBOTGSS_IRQMISC_DRVVBUS_FALL |
  289. USBOTGSS_IRQMISC_CHRGVBUS_FALL |
  290. USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
  291. USBOTGSS_IRQMISC_IDPULLUP_FALL);
  292. dwc3_omap_write_irqmisc_set(omap, reg);
  293. }
  294. static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
  295. {
  296. /* disable all IRQs */
  297. dwc3_omap_write_irqmisc_set(omap, 0x00);
  298. dwc3_omap_write_irq0_set(omap, 0x00);
  299. }
  300. static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
  301. static int dwc3_omap_probe(struct platform_device *pdev)
  302. {
  303. struct device_node *node = pdev->dev.of_node;
  304. struct dwc3_omap *omap;
  305. struct resource *res;
  306. struct device *dev = &pdev->dev;
  307. int ret = -ENOMEM;
  308. int irq;
  309. int utmi_mode = 0;
  310. int x_major;
  311. u32 reg;
  312. void __iomem *base;
  313. if (!node) {
  314. dev_err(dev, "device node not found\n");
  315. return -EINVAL;
  316. }
  317. omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
  318. if (!omap) {
  319. dev_err(dev, "not enough memory\n");
  320. return -ENOMEM;
  321. }
  322. platform_set_drvdata(pdev, omap);
  323. irq = platform_get_irq(pdev, 0);
  324. if (irq < 0) {
  325. dev_err(dev, "missing IRQ resource\n");
  326. return -EINVAL;
  327. }
  328. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  329. if (!res) {
  330. dev_err(dev, "missing memory base resource\n");
  331. return -EINVAL;
  332. }
  333. base = devm_ioremap_nocache(dev, res->start, resource_size(res));
  334. if (!base) {
  335. dev_err(dev, "ioremap failed\n");
  336. return -ENOMEM;
  337. }
  338. spin_lock_init(&omap->lock);
  339. omap->dev = dev;
  340. omap->irq = irq;
  341. omap->base = base;
  342. dev->dma_mask = &dwc3_omap_dma_mask;
  343. /*
  344. * REVISIT if we ever have two instances of the wrapper, we will be
  345. * in big trouble
  346. */
  347. _omap = omap;
  348. pm_runtime_enable(dev);
  349. ret = pm_runtime_get_sync(dev);
  350. if (ret < 0) {
  351. dev_err(dev, "get_sync failed with err %d\n", ret);
  352. goto err0;
  353. }
  354. reg = dwc3_omap_readl(omap->base, USBOTGSS_REVISION);
  355. omap->revision = reg;
  356. x_major = USBOTGSS_REVISION_XMAJOR(reg);
  357. /* Differentiate between OMAP5 and AM437x */
  358. switch (x_major) {
  359. case USBOTGSS_REVISION_XMAJOR1:
  360. case USBOTGSS_REVISION_XMAJOR2:
  361. omap->irq_eoi_offset = 0;
  362. omap->irq0_offset = 0;
  363. omap->irqmisc_offset = 0;
  364. omap->utmi_otg_offset = 0;
  365. omap->debug_offset = 0;
  366. break;
  367. default:
  368. /* Default to the latest revision */
  369. omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
  370. omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
  371. omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
  372. omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
  373. omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
  374. break;
  375. }
  376. /* For OMAP5(ES2.0) and AM437x x_major is 2 even though there are
  377. * changes in wrapper registers, Using dt compatible for aegis
  378. */
  379. if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
  380. omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
  381. omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
  382. omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
  383. omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
  384. omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
  385. }
  386. reg = dwc3_omap_read_utmi_status(omap);
  387. of_property_read_u32(node, "utmi-mode", &utmi_mode);
  388. switch (utmi_mode) {
  389. case DWC3_OMAP_UTMI_MODE_SW:
  390. reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
  391. break;
  392. case DWC3_OMAP_UTMI_MODE_HW:
  393. reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
  394. break;
  395. default:
  396. dev_dbg(dev, "UNKNOWN utmi mode %d\n", utmi_mode);
  397. }
  398. dwc3_omap_write_utmi_status(omap, reg);
  399. /* check the DMA Status */
  400. reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
  401. omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
  402. ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
  403. "dwc3-omap", omap);
  404. if (ret) {
  405. dev_err(dev, "failed to request IRQ #%d --> %d\n",
  406. omap->irq, ret);
  407. goto err1;
  408. }
  409. dwc3_omap_enable_irqs(omap);
  410. ret = of_platform_populate(node, NULL, NULL, dev);
  411. if (ret) {
  412. dev_err(&pdev->dev, "failed to create dwc3 core\n");
  413. goto err2;
  414. }
  415. return 0;
  416. err2:
  417. dwc3_omap_disable_irqs(omap);
  418. err1:
  419. pm_runtime_put_sync(dev);
  420. err0:
  421. pm_runtime_disable(dev);
  422. return ret;
  423. }
  424. static int dwc3_omap_remove(struct platform_device *pdev)
  425. {
  426. struct dwc3_omap *omap = platform_get_drvdata(pdev);
  427. dwc3_omap_disable_irqs(omap);
  428. pm_runtime_put_sync(&pdev->dev);
  429. pm_runtime_disable(&pdev->dev);
  430. device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
  431. return 0;
  432. }
  433. static const struct of_device_id of_dwc3_match[] = {
  434. {
  435. .compatible = "ti,dwc3"
  436. },
  437. {
  438. .compatible = "ti,am437x-dwc3"
  439. },
  440. { },
  441. };
  442. MODULE_DEVICE_TABLE(of, of_dwc3_match);
  443. #ifdef CONFIG_PM_SLEEP
  444. static int dwc3_omap_prepare(struct device *dev)
  445. {
  446. struct dwc3_omap *omap = dev_get_drvdata(dev);
  447. dwc3_omap_disable_irqs(omap);
  448. return 0;
  449. }
  450. static void dwc3_omap_complete(struct device *dev)
  451. {
  452. struct dwc3_omap *omap = dev_get_drvdata(dev);
  453. dwc3_omap_enable_irqs(omap);
  454. }
  455. static int dwc3_omap_suspend(struct device *dev)
  456. {
  457. struct dwc3_omap *omap = dev_get_drvdata(dev);
  458. omap->utmi_otg_status = dwc3_omap_read_utmi_status(omap);
  459. return 0;
  460. }
  461. static int dwc3_omap_resume(struct device *dev)
  462. {
  463. struct dwc3_omap *omap = dev_get_drvdata(dev);
  464. dwc3_omap_write_utmi_status(omap, omap->utmi_otg_status);
  465. pm_runtime_disable(dev);
  466. pm_runtime_set_active(dev);
  467. pm_runtime_enable(dev);
  468. return 0;
  469. }
  470. static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
  471. .prepare = dwc3_omap_prepare,
  472. .complete = dwc3_omap_complete,
  473. SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
  474. };
  475. #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops)
  476. #else
  477. #define DEV_PM_OPS NULL
  478. #endif /* CONFIG_PM_SLEEP */
  479. static struct platform_driver dwc3_omap_driver = {
  480. .probe = dwc3_omap_probe,
  481. .remove = dwc3_omap_remove,
  482. .driver = {
  483. .name = "omap-dwc3",
  484. .of_match_table = of_dwc3_match,
  485. .pm = DEV_PM_OPS,
  486. },
  487. };
  488. module_platform_driver(dwc3_omap_driver);
  489. MODULE_ALIAS("platform:omap-dwc3");
  490. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  491. MODULE_LICENSE("Dual BSD/GPL");
  492. MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");