core.c 19 KB

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  1. /**
  2. * core.c - DesignWare USB3 DRD Controller Core file
  3. *
  4. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5. *
  6. * Authors: Felipe Balbi <balbi@ti.com>,
  7. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8. *
  9. * Redistribution and use in source and binary forms, with or without
  10. * modification, are permitted provided that the following conditions
  11. * are met:
  12. * 1. Redistributions of source code must retain the above copyright
  13. * notice, this list of conditions, and the following disclaimer,
  14. * without modification.
  15. * 2. Redistributions in binary form must reproduce the above copyright
  16. * notice, this list of conditions and the following disclaimer in the
  17. * documentation and/or other materials provided with the distribution.
  18. * 3. The names of the above-listed copyright holders may not be used
  19. * to endorse or promote products derived from this software without
  20. * specific prior written permission.
  21. *
  22. * ALTERNATIVELY, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2, as published by the Free
  24. * Software Foundation.
  25. *
  26. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37. */
  38. #include <linux/module.h>
  39. #include <linux/kernel.h>
  40. #include <linux/slab.h>
  41. #include <linux/spinlock.h>
  42. #include <linux/platform_device.h>
  43. #include <linux/pm_runtime.h>
  44. #include <linux/interrupt.h>
  45. #include <linux/ioport.h>
  46. #include <linux/io.h>
  47. #include <linux/list.h>
  48. #include <linux/delay.h>
  49. #include <linux/dma-mapping.h>
  50. #include <linux/of.h>
  51. #include <linux/usb/otg.h>
  52. #include <linux/usb/ch9.h>
  53. #include <linux/usb/gadget.h>
  54. #include "core.h"
  55. #include "gadget.h"
  56. #include "io.h"
  57. #include "debug.h"
  58. static char *maximum_speed = "super";
  59. module_param(maximum_speed, charp, 0);
  60. MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
  61. /* -------------------------------------------------------------------------- */
  62. void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  63. {
  64. u32 reg;
  65. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  66. reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  67. reg |= DWC3_GCTL_PRTCAPDIR(mode);
  68. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  69. }
  70. /**
  71. * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  72. * @dwc: pointer to our context structure
  73. */
  74. static void dwc3_core_soft_reset(struct dwc3 *dwc)
  75. {
  76. u32 reg;
  77. /* Before Resetting PHY, put Core in Reset */
  78. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  79. reg |= DWC3_GCTL_CORESOFTRESET;
  80. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  81. /* Assert USB3 PHY reset */
  82. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  83. reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  84. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  85. /* Assert USB2 PHY reset */
  86. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  87. reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  88. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  89. usb_phy_init(dwc->usb2_phy);
  90. usb_phy_init(dwc->usb3_phy);
  91. mdelay(100);
  92. /* Clear USB3 PHY reset */
  93. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  94. reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
  95. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  96. /* Clear USB2 PHY reset */
  97. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  98. reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
  99. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  100. mdelay(100);
  101. /* After PHYs are stable we can take Core out of reset state */
  102. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  103. reg &= ~DWC3_GCTL_CORESOFTRESET;
  104. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  105. }
  106. /**
  107. * dwc3_free_one_event_buffer - Frees one event buffer
  108. * @dwc: Pointer to our controller context structure
  109. * @evt: Pointer to event buffer to be freed
  110. */
  111. static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
  112. struct dwc3_event_buffer *evt)
  113. {
  114. dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
  115. }
  116. /**
  117. * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
  118. * @dwc: Pointer to our controller context structure
  119. * @length: size of the event buffer
  120. *
  121. * Returns a pointer to the allocated event buffer structure on success
  122. * otherwise ERR_PTR(errno).
  123. */
  124. static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
  125. unsigned length)
  126. {
  127. struct dwc3_event_buffer *evt;
  128. evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
  129. if (!evt)
  130. return ERR_PTR(-ENOMEM);
  131. evt->dwc = dwc;
  132. evt->length = length;
  133. evt->buf = dma_alloc_coherent(dwc->dev, length,
  134. &evt->dma, GFP_KERNEL);
  135. if (!evt->buf)
  136. return ERR_PTR(-ENOMEM);
  137. return evt;
  138. }
  139. /**
  140. * dwc3_free_event_buffers - frees all allocated event buffers
  141. * @dwc: Pointer to our controller context structure
  142. */
  143. static void dwc3_free_event_buffers(struct dwc3 *dwc)
  144. {
  145. struct dwc3_event_buffer *evt;
  146. int i;
  147. for (i = 0; i < dwc->num_event_buffers; i++) {
  148. evt = dwc->ev_buffs[i];
  149. if (evt)
  150. dwc3_free_one_event_buffer(dwc, evt);
  151. }
  152. }
  153. /**
  154. * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
  155. * @dwc: pointer to our controller context structure
  156. * @length: size of event buffer
  157. *
  158. * Returns 0 on success otherwise negative errno. In the error case, dwc
  159. * may contain some buffers allocated but not all which were requested.
  160. */
  161. static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
  162. {
  163. int num;
  164. int i;
  165. num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
  166. dwc->num_event_buffers = num;
  167. dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
  168. GFP_KERNEL);
  169. if (!dwc->ev_buffs) {
  170. dev_err(dwc->dev, "can't allocate event buffers array\n");
  171. return -ENOMEM;
  172. }
  173. for (i = 0; i < num; i++) {
  174. struct dwc3_event_buffer *evt;
  175. evt = dwc3_alloc_one_event_buffer(dwc, length);
  176. if (IS_ERR(evt)) {
  177. dev_err(dwc->dev, "can't allocate event buffer\n");
  178. return PTR_ERR(evt);
  179. }
  180. dwc->ev_buffs[i] = evt;
  181. }
  182. return 0;
  183. }
  184. /**
  185. * dwc3_event_buffers_setup - setup our allocated event buffers
  186. * @dwc: pointer to our controller context structure
  187. *
  188. * Returns 0 on success otherwise negative errno.
  189. */
  190. static int dwc3_event_buffers_setup(struct dwc3 *dwc)
  191. {
  192. struct dwc3_event_buffer *evt;
  193. int n;
  194. for (n = 0; n < dwc->num_event_buffers; n++) {
  195. evt = dwc->ev_buffs[n];
  196. dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
  197. evt->buf, (unsigned long long) evt->dma,
  198. evt->length);
  199. evt->lpos = 0;
  200. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
  201. lower_32_bits(evt->dma));
  202. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
  203. upper_32_bits(evt->dma));
  204. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
  205. evt->length & 0xffff);
  206. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
  207. }
  208. return 0;
  209. }
  210. static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
  211. {
  212. struct dwc3_event_buffer *evt;
  213. int n;
  214. for (n = 0; n < dwc->num_event_buffers; n++) {
  215. evt = dwc->ev_buffs[n];
  216. evt->lpos = 0;
  217. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
  218. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
  219. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
  220. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
  221. }
  222. }
  223. static void dwc3_core_num_eps(struct dwc3 *dwc)
  224. {
  225. struct dwc3_hwparams *parms = &dwc->hwparams;
  226. dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
  227. dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
  228. dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
  229. dwc->num_in_eps, dwc->num_out_eps);
  230. }
  231. static void dwc3_cache_hwparams(struct dwc3 *dwc)
  232. {
  233. struct dwc3_hwparams *parms = &dwc->hwparams;
  234. parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
  235. parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
  236. parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
  237. parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
  238. parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
  239. parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
  240. parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
  241. parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
  242. parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
  243. }
  244. /**
  245. * dwc3_core_init - Low-level initialization of DWC3 Core
  246. * @dwc: Pointer to our controller context structure
  247. *
  248. * Returns 0 on success otherwise negative errno.
  249. */
  250. static int dwc3_core_init(struct dwc3 *dwc)
  251. {
  252. unsigned long timeout;
  253. u32 reg;
  254. int ret;
  255. reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
  256. /* This should read as U3 followed by revision number */
  257. if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
  258. dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
  259. ret = -ENODEV;
  260. goto err0;
  261. }
  262. dwc->revision = reg;
  263. /* issue device SoftReset too */
  264. timeout = jiffies + msecs_to_jiffies(500);
  265. dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
  266. do {
  267. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  268. if (!(reg & DWC3_DCTL_CSFTRST))
  269. break;
  270. if (time_after(jiffies, timeout)) {
  271. dev_err(dwc->dev, "Reset Timed Out\n");
  272. ret = -ETIMEDOUT;
  273. goto err0;
  274. }
  275. cpu_relax();
  276. } while (true);
  277. dwc3_core_soft_reset(dwc);
  278. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  279. reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  280. reg &= ~DWC3_GCTL_DISSCRAMBLE;
  281. switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
  282. case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  283. reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  284. break;
  285. default:
  286. dev_dbg(dwc->dev, "No power optimization available\n");
  287. }
  288. /*
  289. * WORKAROUND: DWC3 revisions <1.90a have a bug
  290. * where the device can fail to connect at SuperSpeed
  291. * and falls back to high-speed mode which causes
  292. * the device to enter a Connect/Disconnect loop
  293. */
  294. if (dwc->revision < DWC3_REVISION_190A)
  295. reg |= DWC3_GCTL_U2RSTECN;
  296. dwc3_core_num_eps(dwc);
  297. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  298. return 0;
  299. err0:
  300. return ret;
  301. }
  302. static void dwc3_core_exit(struct dwc3 *dwc)
  303. {
  304. usb_phy_shutdown(dwc->usb2_phy);
  305. usb_phy_shutdown(dwc->usb3_phy);
  306. }
  307. #define DWC3_ALIGN_MASK (16 - 1)
  308. static int dwc3_probe(struct platform_device *pdev)
  309. {
  310. struct device_node *node = pdev->dev.of_node;
  311. struct resource *res;
  312. struct dwc3 *dwc;
  313. struct device *dev = &pdev->dev;
  314. int ret = -ENOMEM;
  315. void __iomem *regs;
  316. void *mem;
  317. u8 mode;
  318. mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
  319. if (!mem) {
  320. dev_err(dev, "not enough memory\n");
  321. return -ENOMEM;
  322. }
  323. dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
  324. dwc->mem = mem;
  325. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  326. if (!res) {
  327. dev_err(dev, "missing IRQ\n");
  328. return -ENODEV;
  329. }
  330. dwc->xhci_resources[1].start = res->start;
  331. dwc->xhci_resources[1].end = res->end;
  332. dwc->xhci_resources[1].flags = res->flags;
  333. dwc->xhci_resources[1].name = res->name;
  334. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  335. if (!res) {
  336. dev_err(dev, "missing memory resource\n");
  337. return -ENODEV;
  338. }
  339. dwc->xhci_resources[0].start = res->start;
  340. dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
  341. DWC3_XHCI_REGS_END;
  342. dwc->xhci_resources[0].flags = res->flags;
  343. dwc->xhci_resources[0].name = res->name;
  344. /*
  345. * Request memory region but exclude xHCI regs,
  346. * since it will be requested by the xhci-plat driver.
  347. */
  348. res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
  349. resource_size(res) - DWC3_GLOBALS_REGS_START,
  350. dev_name(dev));
  351. if (!res) {
  352. dev_err(dev, "can't request mem region\n");
  353. return -ENOMEM;
  354. }
  355. regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
  356. if (!regs) {
  357. dev_err(dev, "ioremap failed\n");
  358. return -ENOMEM;
  359. }
  360. if (node) {
  361. dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
  362. dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
  363. } else {
  364. dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
  365. dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
  366. }
  367. if (IS_ERR(dwc->usb2_phy)) {
  368. ret = PTR_ERR(dwc->usb2_phy);
  369. /*
  370. * if -ENXIO is returned, it means PHY layer wasn't
  371. * enabled, so it makes no sense to return -EPROBE_DEFER
  372. * in that case, since no PHY driver will ever probe.
  373. */
  374. if (ret == -ENXIO)
  375. return ret;
  376. dev_err(dev, "no usb2 phy configured\n");
  377. return -EPROBE_DEFER;
  378. }
  379. if (IS_ERR(dwc->usb3_phy)) {
  380. ret = PTR_ERR(dwc->usb2_phy);
  381. /*
  382. * if -ENXIO is returned, it means PHY layer wasn't
  383. * enabled, so it makes no sense to return -EPROBE_DEFER
  384. * in that case, since no PHY driver will ever probe.
  385. */
  386. if (ret == -ENXIO)
  387. return ret;
  388. dev_err(dev, "no usb3 phy configured\n");
  389. return -EPROBE_DEFER;
  390. }
  391. usb_phy_set_suspend(dwc->usb2_phy, 0);
  392. usb_phy_set_suspend(dwc->usb3_phy, 0);
  393. spin_lock_init(&dwc->lock);
  394. platform_set_drvdata(pdev, dwc);
  395. dwc->regs = regs;
  396. dwc->regs_size = resource_size(res);
  397. dwc->dev = dev;
  398. dev->dma_mask = dev->parent->dma_mask;
  399. dev->dma_parms = dev->parent->dma_parms;
  400. dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
  401. if (!strncmp("super", maximum_speed, 5))
  402. dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
  403. else if (!strncmp("high", maximum_speed, 4))
  404. dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
  405. else if (!strncmp("full", maximum_speed, 4))
  406. dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
  407. else if (!strncmp("low", maximum_speed, 3))
  408. dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
  409. else
  410. dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
  411. dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
  412. pm_runtime_enable(dev);
  413. pm_runtime_get_sync(dev);
  414. pm_runtime_forbid(dev);
  415. dwc3_cache_hwparams(dwc);
  416. ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  417. if (ret) {
  418. dev_err(dwc->dev, "failed to allocate event buffers\n");
  419. ret = -ENOMEM;
  420. goto err0;
  421. }
  422. ret = dwc3_core_init(dwc);
  423. if (ret) {
  424. dev_err(dev, "failed to initialize core\n");
  425. goto err0;
  426. }
  427. ret = dwc3_event_buffers_setup(dwc);
  428. if (ret) {
  429. dev_err(dwc->dev, "failed to setup event buffers\n");
  430. goto err1;
  431. }
  432. if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  433. mode = DWC3_MODE_HOST;
  434. else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  435. mode = DWC3_MODE_DEVICE;
  436. else
  437. mode = DWC3_MODE_DRD;
  438. switch (mode) {
  439. case DWC3_MODE_DEVICE:
  440. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  441. ret = dwc3_gadget_init(dwc);
  442. if (ret) {
  443. dev_err(dev, "failed to initialize gadget\n");
  444. goto err2;
  445. }
  446. break;
  447. case DWC3_MODE_HOST:
  448. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
  449. ret = dwc3_host_init(dwc);
  450. if (ret) {
  451. dev_err(dev, "failed to initialize host\n");
  452. goto err2;
  453. }
  454. break;
  455. case DWC3_MODE_DRD:
  456. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
  457. ret = dwc3_host_init(dwc);
  458. if (ret) {
  459. dev_err(dev, "failed to initialize host\n");
  460. goto err2;
  461. }
  462. ret = dwc3_gadget_init(dwc);
  463. if (ret) {
  464. dev_err(dev, "failed to initialize gadget\n");
  465. goto err2;
  466. }
  467. break;
  468. default:
  469. dev_err(dev, "Unsupported mode of operation %d\n", mode);
  470. goto err2;
  471. }
  472. dwc->mode = mode;
  473. ret = dwc3_debugfs_init(dwc);
  474. if (ret) {
  475. dev_err(dev, "failed to initialize debugfs\n");
  476. goto err3;
  477. }
  478. pm_runtime_allow(dev);
  479. return 0;
  480. err3:
  481. switch (mode) {
  482. case DWC3_MODE_DEVICE:
  483. dwc3_gadget_exit(dwc);
  484. break;
  485. case DWC3_MODE_HOST:
  486. dwc3_host_exit(dwc);
  487. break;
  488. case DWC3_MODE_DRD:
  489. dwc3_host_exit(dwc);
  490. dwc3_gadget_exit(dwc);
  491. break;
  492. default:
  493. /* do nothing */
  494. break;
  495. }
  496. err2:
  497. dwc3_event_buffers_cleanup(dwc);
  498. err1:
  499. dwc3_core_exit(dwc);
  500. err0:
  501. dwc3_free_event_buffers(dwc);
  502. return ret;
  503. }
  504. static int dwc3_remove(struct platform_device *pdev)
  505. {
  506. struct dwc3 *dwc = platform_get_drvdata(pdev);
  507. usb_phy_set_suspend(dwc->usb2_phy, 1);
  508. usb_phy_set_suspend(dwc->usb3_phy, 1);
  509. pm_runtime_put(&pdev->dev);
  510. pm_runtime_disable(&pdev->dev);
  511. dwc3_debugfs_exit(dwc);
  512. switch (dwc->mode) {
  513. case DWC3_MODE_DEVICE:
  514. dwc3_gadget_exit(dwc);
  515. break;
  516. case DWC3_MODE_HOST:
  517. dwc3_host_exit(dwc);
  518. break;
  519. case DWC3_MODE_DRD:
  520. dwc3_host_exit(dwc);
  521. dwc3_gadget_exit(dwc);
  522. break;
  523. default:
  524. /* do nothing */
  525. break;
  526. }
  527. dwc3_event_buffers_cleanup(dwc);
  528. dwc3_free_event_buffers(dwc);
  529. dwc3_core_exit(dwc);
  530. return 0;
  531. }
  532. #ifdef CONFIG_PM_SLEEP
  533. static int dwc3_prepare(struct device *dev)
  534. {
  535. struct dwc3 *dwc = dev_get_drvdata(dev);
  536. unsigned long flags;
  537. spin_lock_irqsave(&dwc->lock, flags);
  538. switch (dwc->mode) {
  539. case DWC3_MODE_DEVICE:
  540. case DWC3_MODE_DRD:
  541. dwc3_gadget_prepare(dwc);
  542. /* FALLTHROUGH */
  543. case DWC3_MODE_HOST:
  544. default:
  545. dwc3_event_buffers_cleanup(dwc);
  546. break;
  547. }
  548. spin_unlock_irqrestore(&dwc->lock, flags);
  549. return 0;
  550. }
  551. static void dwc3_complete(struct device *dev)
  552. {
  553. struct dwc3 *dwc = dev_get_drvdata(dev);
  554. unsigned long flags;
  555. spin_lock_irqsave(&dwc->lock, flags);
  556. switch (dwc->mode) {
  557. case DWC3_MODE_DEVICE:
  558. case DWC3_MODE_DRD:
  559. dwc3_gadget_complete(dwc);
  560. /* FALLTHROUGH */
  561. case DWC3_MODE_HOST:
  562. default:
  563. dwc3_event_buffers_setup(dwc);
  564. break;
  565. }
  566. spin_unlock_irqrestore(&dwc->lock, flags);
  567. }
  568. static int dwc3_suspend(struct device *dev)
  569. {
  570. struct dwc3 *dwc = dev_get_drvdata(dev);
  571. unsigned long flags;
  572. spin_lock_irqsave(&dwc->lock, flags);
  573. switch (dwc->mode) {
  574. case DWC3_MODE_DEVICE:
  575. case DWC3_MODE_DRD:
  576. dwc3_gadget_suspend(dwc);
  577. /* FALLTHROUGH */
  578. case DWC3_MODE_HOST:
  579. default:
  580. /* do nothing */
  581. break;
  582. }
  583. dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
  584. spin_unlock_irqrestore(&dwc->lock, flags);
  585. usb_phy_shutdown(dwc->usb3_phy);
  586. usb_phy_shutdown(dwc->usb2_phy);
  587. return 0;
  588. }
  589. static int dwc3_resume(struct device *dev)
  590. {
  591. struct dwc3 *dwc = dev_get_drvdata(dev);
  592. unsigned long flags;
  593. usb_phy_init(dwc->usb3_phy);
  594. usb_phy_init(dwc->usb2_phy);
  595. msleep(100);
  596. spin_lock_irqsave(&dwc->lock, flags);
  597. dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
  598. switch (dwc->mode) {
  599. case DWC3_MODE_DEVICE:
  600. case DWC3_MODE_DRD:
  601. dwc3_gadget_resume(dwc);
  602. /* FALLTHROUGH */
  603. case DWC3_MODE_HOST:
  604. default:
  605. /* do nothing */
  606. break;
  607. }
  608. spin_unlock_irqrestore(&dwc->lock, flags);
  609. pm_runtime_disable(dev);
  610. pm_runtime_set_active(dev);
  611. pm_runtime_enable(dev);
  612. return 0;
  613. }
  614. static const struct dev_pm_ops dwc3_dev_pm_ops = {
  615. .prepare = dwc3_prepare,
  616. .complete = dwc3_complete,
  617. SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
  618. };
  619. #define DWC3_PM_OPS &(dwc3_dev_pm_ops)
  620. #else
  621. #define DWC3_PM_OPS NULL
  622. #endif
  623. #ifdef CONFIG_OF
  624. static const struct of_device_id of_dwc3_match[] = {
  625. {
  626. .compatible = "synopsys,dwc3"
  627. },
  628. { },
  629. };
  630. MODULE_DEVICE_TABLE(of, of_dwc3_match);
  631. #endif
  632. static struct platform_driver dwc3_driver = {
  633. .probe = dwc3_probe,
  634. .remove = dwc3_remove,
  635. .driver = {
  636. .name = "dwc3",
  637. .of_match_table = of_match_ptr(of_dwc3_match),
  638. .pm = DWC3_PM_OPS,
  639. },
  640. };
  641. module_platform_driver(dwc3_driver);
  642. MODULE_ALIAS("platform:dwc3");
  643. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  644. MODULE_LICENSE("Dual BSD/GPL");
  645. MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");