core.c 13 KB

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  1. /*
  2. * core.c - ChipIdea USB IP core family device controller
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * Description: ChipIdea USB IP core family device controller
  14. *
  15. * This driver is composed of several blocks:
  16. * - HW: hardware interface
  17. * - DBG: debug facilities (optional)
  18. * - UTIL: utilities
  19. * - ISR: interrupts handling
  20. * - ENDPT: endpoint operations (Gadget API)
  21. * - GADGET: gadget operations (Gadget API)
  22. * - BUS: bus glue code, bus abstraction layer
  23. *
  24. * Compile Options
  25. * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  26. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  27. * if defined mass storage compliance succeeds but with warnings
  28. * => case 4: Hi > Dn
  29. * => case 5: Hi > Di
  30. * => case 8: Hi <> Do
  31. * if undefined usbtest 13 fails
  32. * - TRACE: enable function tracing (depends on DEBUG)
  33. *
  34. * Main Features
  35. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  36. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  37. * - Normal & LPM support
  38. *
  39. * USBTEST Report
  40. * - OK: 0-12, 13 (STALL_IN defined) & 14
  41. * - Not Supported: 15 & 16 (ISO)
  42. *
  43. * TODO List
  44. * - OTG
  45. * - Interrupt Traffic
  46. * - GET_STATUS(device) - always reports 0
  47. * - Gadget API (majority of optional features)
  48. * - Suspend & Remote Wakeup
  49. */
  50. #include <linux/delay.h>
  51. #include <linux/device.h>
  52. #include <linux/dma-mapping.h>
  53. #include <linux/platform_device.h>
  54. #include <linux/module.h>
  55. #include <linux/idr.h>
  56. #include <linux/interrupt.h>
  57. #include <linux/io.h>
  58. #include <linux/kernel.h>
  59. #include <linux/slab.h>
  60. #include <linux/pm_runtime.h>
  61. #include <linux/usb/ch9.h>
  62. #include <linux/usb/gadget.h>
  63. #include <linux/usb/otg.h>
  64. #include <linux/usb/chipidea.h>
  65. #include <linux/usb/of.h>
  66. #include <linux/phy.h>
  67. #include "ci.h"
  68. #include "udc.h"
  69. #include "bits.h"
  70. #include "host.h"
  71. #include "debug.h"
  72. /* Controller register map */
  73. static uintptr_t ci_regs_nolpm[] = {
  74. [CAP_CAPLENGTH] = 0x000UL,
  75. [CAP_HCCPARAMS] = 0x008UL,
  76. [CAP_DCCPARAMS] = 0x024UL,
  77. [CAP_TESTMODE] = 0x038UL,
  78. [OP_USBCMD] = 0x000UL,
  79. [OP_USBSTS] = 0x004UL,
  80. [OP_USBINTR] = 0x008UL,
  81. [OP_DEVICEADDR] = 0x014UL,
  82. [OP_ENDPTLISTADDR] = 0x018UL,
  83. [OP_PORTSC] = 0x044UL,
  84. [OP_DEVLC] = 0x084UL,
  85. [OP_OTGSC] = 0x064UL,
  86. [OP_USBMODE] = 0x068UL,
  87. [OP_ENDPTSETUPSTAT] = 0x06CUL,
  88. [OP_ENDPTPRIME] = 0x070UL,
  89. [OP_ENDPTFLUSH] = 0x074UL,
  90. [OP_ENDPTSTAT] = 0x078UL,
  91. [OP_ENDPTCOMPLETE] = 0x07CUL,
  92. [OP_ENDPTCTRL] = 0x080UL,
  93. };
  94. static uintptr_t ci_regs_lpm[] = {
  95. [CAP_CAPLENGTH] = 0x000UL,
  96. [CAP_HCCPARAMS] = 0x008UL,
  97. [CAP_DCCPARAMS] = 0x024UL,
  98. [CAP_TESTMODE] = 0x0FCUL,
  99. [OP_USBCMD] = 0x000UL,
  100. [OP_USBSTS] = 0x004UL,
  101. [OP_USBINTR] = 0x008UL,
  102. [OP_DEVICEADDR] = 0x014UL,
  103. [OP_ENDPTLISTADDR] = 0x018UL,
  104. [OP_PORTSC] = 0x044UL,
  105. [OP_DEVLC] = 0x084UL,
  106. [OP_OTGSC] = 0x0C4UL,
  107. [OP_USBMODE] = 0x0C8UL,
  108. [OP_ENDPTSETUPSTAT] = 0x0D8UL,
  109. [OP_ENDPTPRIME] = 0x0DCUL,
  110. [OP_ENDPTFLUSH] = 0x0E0UL,
  111. [OP_ENDPTSTAT] = 0x0E4UL,
  112. [OP_ENDPTCOMPLETE] = 0x0E8UL,
  113. [OP_ENDPTCTRL] = 0x0ECUL,
  114. };
  115. static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
  116. {
  117. int i;
  118. kfree(ci->hw_bank.regmap);
  119. ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
  120. GFP_KERNEL);
  121. if (!ci->hw_bank.regmap)
  122. return -ENOMEM;
  123. for (i = 0; i < OP_ENDPTCTRL; i++)
  124. ci->hw_bank.regmap[i] =
  125. (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
  126. (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
  127. for (; i <= OP_LAST; i++)
  128. ci->hw_bank.regmap[i] = ci->hw_bank.op +
  129. 4 * (i - OP_ENDPTCTRL) +
  130. (is_lpm
  131. ? ci_regs_lpm[OP_ENDPTCTRL]
  132. : ci_regs_nolpm[OP_ENDPTCTRL]);
  133. return 0;
  134. }
  135. /**
  136. * hw_port_test_set: writes port test mode (execute without interruption)
  137. * @mode: new value
  138. *
  139. * This function returns an error code
  140. */
  141. int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
  142. {
  143. const u8 TEST_MODE_MAX = 7;
  144. if (mode > TEST_MODE_MAX)
  145. return -EINVAL;
  146. hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
  147. return 0;
  148. }
  149. /**
  150. * hw_port_test_get: reads port test mode value
  151. *
  152. * This function returns port test mode value
  153. */
  154. u8 hw_port_test_get(struct ci_hdrc *ci)
  155. {
  156. return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
  157. }
  158. static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
  159. {
  160. u32 reg;
  161. /* bank is a module variable */
  162. ci->hw_bank.abs = base;
  163. ci->hw_bank.cap = ci->hw_bank.abs;
  164. ci->hw_bank.cap += ci->platdata->capoffset;
  165. ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
  166. hw_alloc_regmap(ci, false);
  167. reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
  168. __ffs(HCCPARAMS_LEN);
  169. ci->hw_bank.lpm = reg;
  170. hw_alloc_regmap(ci, !!reg);
  171. ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
  172. ci->hw_bank.size += OP_LAST;
  173. ci->hw_bank.size /= sizeof(u32);
  174. reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
  175. __ffs(DCCPARAMS_DEN);
  176. ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  177. if (ci->hw_ep_max > ENDPT_MAX)
  178. return -ENODEV;
  179. dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
  180. ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
  181. /* setup lock mode ? */
  182. /* ENDPTSETUPSTAT is '0' by default */
  183. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  184. return 0;
  185. }
  186. static void hw_phymode_configure(struct ci_hdrc *ci)
  187. {
  188. u32 portsc, lpm, sts;
  189. switch (ci->platdata->phy_mode) {
  190. case USBPHY_INTERFACE_MODE_UTMI:
  191. portsc = PORTSC_PTS(PTS_UTMI);
  192. lpm = DEVLC_PTS(PTS_UTMI);
  193. break;
  194. case USBPHY_INTERFACE_MODE_UTMIW:
  195. portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
  196. lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
  197. break;
  198. case USBPHY_INTERFACE_MODE_ULPI:
  199. portsc = PORTSC_PTS(PTS_ULPI);
  200. lpm = DEVLC_PTS(PTS_ULPI);
  201. break;
  202. case USBPHY_INTERFACE_MODE_SERIAL:
  203. portsc = PORTSC_PTS(PTS_SERIAL);
  204. lpm = DEVLC_PTS(PTS_SERIAL);
  205. sts = 1;
  206. break;
  207. case USBPHY_INTERFACE_MODE_HSIC:
  208. portsc = PORTSC_PTS(PTS_HSIC);
  209. lpm = DEVLC_PTS(PTS_HSIC);
  210. break;
  211. default:
  212. return;
  213. }
  214. if (ci->hw_bank.lpm) {
  215. hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
  216. hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
  217. } else {
  218. hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
  219. hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
  220. }
  221. }
  222. /**
  223. * hw_device_reset: resets chip (execute without interruption)
  224. * @ci: the controller
  225. *
  226. * This function returns an error code
  227. */
  228. int hw_device_reset(struct ci_hdrc *ci, u32 mode)
  229. {
  230. /* should flush & stop before reset */
  231. hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
  232. hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
  233. hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
  234. while (hw_read(ci, OP_USBCMD, USBCMD_RST))
  235. udelay(10); /* not RTOS friendly */
  236. hw_phymode_configure(ci);
  237. if (ci->platdata->notify_event)
  238. ci->platdata->notify_event(ci,
  239. CI_HDRC_CONTROLLER_RESET_EVENT);
  240. if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
  241. hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
  242. /* USBMODE should be configured step by step */
  243. hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  244. hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
  245. /* HW >= 2.3 */
  246. hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
  247. if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
  248. pr_err("cannot enter in %s mode", ci_role(ci)->name);
  249. pr_err("lpm = %i", ci->hw_bank.lpm);
  250. return -ENODEV;
  251. }
  252. return 0;
  253. }
  254. /**
  255. * ci_otg_role - pick role based on ID pin state
  256. * @ci: the controller
  257. */
  258. static enum ci_role ci_otg_role(struct ci_hdrc *ci)
  259. {
  260. u32 sts = hw_read(ci, OP_OTGSC, ~0);
  261. enum ci_role role = sts & OTGSC_ID
  262. ? CI_ROLE_GADGET
  263. : CI_ROLE_HOST;
  264. return role;
  265. }
  266. /**
  267. * ci_role_work - perform role changing based on ID pin
  268. * @work: work struct
  269. */
  270. static void ci_role_work(struct work_struct *work)
  271. {
  272. struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work);
  273. enum ci_role role = ci_otg_role(ci);
  274. if (role != ci->role) {
  275. dev_dbg(ci->dev, "switching from %s to %s\n",
  276. ci_role(ci)->name, ci->roles[role]->name);
  277. ci_role_stop(ci);
  278. ci_role_start(ci, role);
  279. }
  280. enable_irq(ci->irq);
  281. }
  282. static irqreturn_t ci_irq(int irq, void *data)
  283. {
  284. struct ci_hdrc *ci = data;
  285. irqreturn_t ret = IRQ_NONE;
  286. u32 otgsc = 0;
  287. if (ci->is_otg)
  288. otgsc = hw_read(ci, OP_OTGSC, ~0);
  289. if (ci->role != CI_ROLE_END)
  290. ret = ci_role(ci)->irq(ci);
  291. if (ci->is_otg && (otgsc & OTGSC_IDIS)) {
  292. hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
  293. disable_irq_nosync(ci->irq);
  294. queue_work(ci->wq, &ci->work);
  295. ret = IRQ_HANDLED;
  296. }
  297. return ret;
  298. }
  299. static DEFINE_IDA(ci_ida);
  300. struct platform_device *ci_hdrc_add_device(struct device *dev,
  301. struct resource *res, int nres,
  302. struct ci_hdrc_platform_data *platdata)
  303. {
  304. struct platform_device *pdev;
  305. int id, ret;
  306. id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
  307. if (id < 0)
  308. return ERR_PTR(id);
  309. pdev = platform_device_alloc("ci_hdrc", id);
  310. if (!pdev) {
  311. ret = -ENOMEM;
  312. goto put_id;
  313. }
  314. pdev->dev.parent = dev;
  315. pdev->dev.dma_mask = dev->dma_mask;
  316. pdev->dev.dma_parms = dev->dma_parms;
  317. dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
  318. ret = platform_device_add_resources(pdev, res, nres);
  319. if (ret)
  320. goto err;
  321. ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
  322. if (ret)
  323. goto err;
  324. ret = platform_device_add(pdev);
  325. if (ret)
  326. goto err;
  327. return pdev;
  328. err:
  329. platform_device_put(pdev);
  330. put_id:
  331. ida_simple_remove(&ci_ida, id);
  332. return ERR_PTR(ret);
  333. }
  334. EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
  335. void ci_hdrc_remove_device(struct platform_device *pdev)
  336. {
  337. int id = pdev->id;
  338. platform_device_unregister(pdev);
  339. ida_simple_remove(&ci_ida, id);
  340. }
  341. EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
  342. static int ci_hdrc_probe(struct platform_device *pdev)
  343. {
  344. struct device *dev = &pdev->dev;
  345. struct ci_hdrc *ci;
  346. struct resource *res;
  347. void __iomem *base;
  348. int ret;
  349. enum usb_dr_mode dr_mode;
  350. if (!dev->platform_data) {
  351. dev_err(dev, "platform data missing\n");
  352. return -ENODEV;
  353. }
  354. if (!dev->of_node && dev->parent)
  355. dev->of_node = dev->parent->of_node;
  356. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  357. base = devm_ioremap_resource(dev, res);
  358. if (IS_ERR(base))
  359. return PTR_ERR(base);
  360. ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
  361. if (!ci) {
  362. dev_err(dev, "can't allocate device\n");
  363. return -ENOMEM;
  364. }
  365. ci->dev = dev;
  366. ci->platdata = dev->platform_data;
  367. if (ci->platdata->phy)
  368. ci->transceiver = ci->platdata->phy;
  369. else
  370. ci->global_phy = true;
  371. ret = hw_device_init(ci, base);
  372. if (ret < 0) {
  373. dev_err(dev, "can't initialize hardware\n");
  374. return -ENODEV;
  375. }
  376. ci->hw_bank.phys = res->start;
  377. ci->irq = platform_get_irq(pdev, 0);
  378. if (ci->irq < 0) {
  379. dev_err(dev, "missing IRQ\n");
  380. return -ENODEV;
  381. }
  382. INIT_WORK(&ci->work, ci_role_work);
  383. ci->wq = create_singlethread_workqueue("ci_otg");
  384. if (!ci->wq) {
  385. dev_err(dev, "can't create workqueue\n");
  386. return -ENODEV;
  387. }
  388. if (!ci->platdata->phy_mode)
  389. ci->platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
  390. if (!ci->platdata->dr_mode)
  391. ci->platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
  392. if (ci->platdata->dr_mode == USB_DR_MODE_UNKNOWN)
  393. ci->platdata->dr_mode = USB_DR_MODE_OTG;
  394. dr_mode = ci->platdata->dr_mode;
  395. /* initialize role(s) before the interrupt is requested */
  396. if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
  397. ret = ci_hdrc_host_init(ci);
  398. if (ret)
  399. dev_info(dev, "doesn't support host\n");
  400. }
  401. if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
  402. ret = ci_hdrc_gadget_init(ci);
  403. if (ret)
  404. dev_info(dev, "doesn't support gadget\n");
  405. }
  406. if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
  407. dev_err(dev, "no supported roles\n");
  408. ret = -ENODEV;
  409. goto rm_wq;
  410. }
  411. if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
  412. ci->is_otg = true;
  413. /* ID pin needs 1ms debouce time, we delay 2ms for safe */
  414. mdelay(2);
  415. ci->role = ci_otg_role(ci);
  416. } else {
  417. ci->role = ci->roles[CI_ROLE_HOST]
  418. ? CI_ROLE_HOST
  419. : CI_ROLE_GADGET;
  420. }
  421. ret = ci_role_start(ci, ci->role);
  422. if (ret) {
  423. dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
  424. ret = -ENODEV;
  425. goto rm_wq;
  426. }
  427. platform_set_drvdata(pdev, ci);
  428. ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
  429. ci);
  430. if (ret)
  431. goto stop;
  432. if (ci->is_otg)
  433. hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE);
  434. ret = dbg_create_files(ci);
  435. if (!ret)
  436. return 0;
  437. free_irq(ci->irq, ci);
  438. stop:
  439. ci_role_stop(ci);
  440. rm_wq:
  441. flush_workqueue(ci->wq);
  442. destroy_workqueue(ci->wq);
  443. return ret;
  444. }
  445. static int ci_hdrc_remove(struct platform_device *pdev)
  446. {
  447. struct ci_hdrc *ci = platform_get_drvdata(pdev);
  448. dbg_remove_files(ci);
  449. flush_workqueue(ci->wq);
  450. destroy_workqueue(ci->wq);
  451. free_irq(ci->irq, ci);
  452. ci_role_stop(ci);
  453. return 0;
  454. }
  455. static struct platform_driver ci_hdrc_driver = {
  456. .probe = ci_hdrc_probe,
  457. .remove = ci_hdrc_remove,
  458. .driver = {
  459. .name = "ci_hdrc",
  460. },
  461. };
  462. module_platform_driver(ci_hdrc_driver);
  463. MODULE_ALIAS("platform:ci_hdrc");
  464. MODULE_ALIAS("platform:ci13xxx");
  465. MODULE_LICENSE("GPL v2");
  466. MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
  467. MODULE_DESCRIPTION("ChipIdea HDRC Driver");