ci.h 7.4 KB

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  1. /*
  2. * ci.h - common structures, functions, and macros of the ChipIdea driver
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
  13. #define __DRIVERS_USB_CHIPIDEA_CI_H
  14. #include <linux/list.h>
  15. #include <linux/irqreturn.h>
  16. #include <linux/usb.h>
  17. #include <linux/usb/gadget.h>
  18. /******************************************************************************
  19. * DEFINE
  20. *****************************************************************************/
  21. #define TD_PAGE_COUNT 5
  22. #define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */
  23. #define ENDPT_MAX 32
  24. /******************************************************************************
  25. * STRUCTURES
  26. *****************************************************************************/
  27. /**
  28. * struct ci_hw_ep - endpoint representation
  29. * @ep: endpoint structure for gadget drivers
  30. * @dir: endpoint direction (TX/RX)
  31. * @num: endpoint number
  32. * @type: endpoint type
  33. * @name: string description of the endpoint
  34. * @qh: queue head for this endpoint
  35. * @wedge: is the endpoint wedged
  36. * @ci: pointer to the controller
  37. * @lock: pointer to controller's spinlock
  38. * @td_pool: pointer to controller's TD pool
  39. */
  40. struct ci_hw_ep {
  41. struct usb_ep ep;
  42. u8 dir;
  43. u8 num;
  44. u8 type;
  45. char name[16];
  46. struct {
  47. struct list_head queue;
  48. struct ci_hw_qh *ptr;
  49. dma_addr_t dma;
  50. } qh;
  51. int wedge;
  52. /* global resources */
  53. struct ci_hdrc *ci;
  54. spinlock_t *lock;
  55. struct dma_pool *td_pool;
  56. struct td_node *pending_td;
  57. };
  58. enum ci_role {
  59. CI_ROLE_HOST = 0,
  60. CI_ROLE_GADGET,
  61. CI_ROLE_END,
  62. };
  63. /**
  64. * struct ci_role_driver - host/gadget role driver
  65. * start: start this role
  66. * stop: stop this role
  67. * irq: irq handler for this role
  68. * name: role name string (host/gadget)
  69. */
  70. struct ci_role_driver {
  71. int (*start)(struct ci_hdrc *);
  72. void (*stop)(struct ci_hdrc *);
  73. irqreturn_t (*irq)(struct ci_hdrc *);
  74. const char *name;
  75. };
  76. /**
  77. * struct hw_bank - hardware register mapping representation
  78. * @lpm: set if the device is LPM capable
  79. * @phys: physical address of the controller's registers
  80. * @abs: absolute address of the beginning of register window
  81. * @cap: capability registers
  82. * @op: operational registers
  83. * @size: size of the register window
  84. * @regmap: register lookup table
  85. */
  86. struct hw_bank {
  87. unsigned lpm;
  88. resource_size_t phys;
  89. void __iomem *abs;
  90. void __iomem *cap;
  91. void __iomem *op;
  92. size_t size;
  93. void __iomem **regmap;
  94. };
  95. /**
  96. * struct ci_hdrc - chipidea device representation
  97. * @dev: pointer to parent device
  98. * @lock: access synchronization
  99. * @hw_bank: hardware register mapping
  100. * @irq: IRQ number
  101. * @roles: array of supported roles for this controller
  102. * @role: current role
  103. * @is_otg: if the device is otg-capable
  104. * @work: work for role changing
  105. * @wq: workqueue thread
  106. * @qh_pool: allocation pool for queue heads
  107. * @td_pool: allocation pool for transfer descriptors
  108. * @gadget: device side representation for peripheral controller
  109. * @driver: gadget driver
  110. * @hw_ep_max: total number of endpoints supported by hardware
  111. * @ci_hw_ep: array of endpoints
  112. * @ep0_dir: ep0 direction
  113. * @ep0out: pointer to ep0 OUT endpoint
  114. * @ep0in: pointer to ep0 IN endpoint
  115. * @status: ep0 status request
  116. * @setaddr: if we should set the address on status completion
  117. * @address: usb address received from the host
  118. * @remote_wakeup: host-enabled remote wakeup
  119. * @suspended: suspended by host
  120. * @test_mode: the selected test mode
  121. * @platdata: platform specific information supplied by parent device
  122. * @vbus_active: is VBUS active
  123. * @transceiver: pointer to USB PHY, if any
  124. * @hcd: pointer to usb_hcd for ehci host driver
  125. * @debugfs: root dentry for this controller in debugfs
  126. */
  127. struct ci_hdrc {
  128. struct device *dev;
  129. spinlock_t lock;
  130. struct hw_bank hw_bank;
  131. int irq;
  132. struct ci_role_driver *roles[CI_ROLE_END];
  133. enum ci_role role;
  134. bool is_otg;
  135. struct work_struct work;
  136. struct workqueue_struct *wq;
  137. struct dma_pool *qh_pool;
  138. struct dma_pool *td_pool;
  139. struct usb_gadget gadget;
  140. struct usb_gadget_driver *driver;
  141. unsigned hw_ep_max;
  142. struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
  143. u32 ep0_dir;
  144. struct ci_hw_ep *ep0out, *ep0in;
  145. struct usb_request *status;
  146. bool setaddr;
  147. u8 address;
  148. u8 remote_wakeup;
  149. u8 suspended;
  150. u8 test_mode;
  151. struct ci_hdrc_platform_data *platdata;
  152. int vbus_active;
  153. /* FIXME: some day, we'll not use global phy */
  154. bool global_phy;
  155. struct usb_phy *transceiver;
  156. struct usb_hcd *hcd;
  157. struct dentry *debugfs;
  158. };
  159. static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
  160. {
  161. BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
  162. return ci->roles[ci->role];
  163. }
  164. static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
  165. {
  166. int ret;
  167. if (role >= CI_ROLE_END)
  168. return -EINVAL;
  169. if (!ci->roles[role])
  170. return -ENXIO;
  171. ret = ci->roles[role]->start(ci);
  172. if (!ret)
  173. ci->role = role;
  174. return ret;
  175. }
  176. static inline void ci_role_stop(struct ci_hdrc *ci)
  177. {
  178. enum ci_role role = ci->role;
  179. if (role == CI_ROLE_END)
  180. return;
  181. ci->role = CI_ROLE_END;
  182. ci->roles[role]->stop(ci);
  183. }
  184. /******************************************************************************
  185. * REGISTERS
  186. *****************************************************************************/
  187. /* register size */
  188. #define REG_BITS (32)
  189. /* register indices */
  190. enum ci_hw_regs {
  191. CAP_CAPLENGTH,
  192. CAP_HCCPARAMS,
  193. CAP_DCCPARAMS,
  194. CAP_TESTMODE,
  195. CAP_LAST = CAP_TESTMODE,
  196. OP_USBCMD,
  197. OP_USBSTS,
  198. OP_USBINTR,
  199. OP_DEVICEADDR,
  200. OP_ENDPTLISTADDR,
  201. OP_PORTSC,
  202. OP_DEVLC,
  203. OP_OTGSC,
  204. OP_USBMODE,
  205. OP_ENDPTSETUPSTAT,
  206. OP_ENDPTPRIME,
  207. OP_ENDPTFLUSH,
  208. OP_ENDPTSTAT,
  209. OP_ENDPTCOMPLETE,
  210. OP_ENDPTCTRL,
  211. /* endptctrl1..15 follow */
  212. OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
  213. };
  214. /**
  215. * hw_read: reads from a hw register
  216. * @reg: register index
  217. * @mask: bitfield mask
  218. *
  219. * This function returns register contents
  220. */
  221. static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
  222. {
  223. return ioread32(ci->hw_bank.regmap[reg]) & mask;
  224. }
  225. /**
  226. * hw_write: writes to a hw register
  227. * @reg: register index
  228. * @mask: bitfield mask
  229. * @data: new value
  230. */
  231. static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
  232. u32 mask, u32 data)
  233. {
  234. if (~mask)
  235. data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
  236. | (data & mask);
  237. iowrite32(data, ci->hw_bank.regmap[reg]);
  238. }
  239. /**
  240. * hw_test_and_clear: tests & clears a hw register
  241. * @reg: register index
  242. * @mask: bitfield mask
  243. *
  244. * This function returns register contents
  245. */
  246. static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
  247. u32 mask)
  248. {
  249. u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
  250. iowrite32(val, ci->hw_bank.regmap[reg]);
  251. return val;
  252. }
  253. /**
  254. * hw_test_and_write: tests & writes a hw register
  255. * @reg: register index
  256. * @mask: bitfield mask
  257. * @data: new value
  258. *
  259. * This function returns register contents
  260. */
  261. static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
  262. u32 mask, u32 data)
  263. {
  264. u32 val = hw_read(ci, reg, ~0);
  265. hw_write(ci, reg, mask, data);
  266. return (val & mask) >> __ffs(mask);
  267. }
  268. int hw_device_reset(struct ci_hdrc *ci, u32 mode);
  269. int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
  270. u8 hw_port_test_get(struct ci_hdrc *ci);
  271. #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */