bits.h 3.0 KB

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  1. /*
  2. * bits.h - register bits of the ChipIdea USB IP core
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #ifndef __DRIVERS_USB_CHIPIDEA_BITS_H
  13. #define __DRIVERS_USB_CHIPIDEA_BITS_H
  14. #include <linux/usb/ehci_def.h>
  15. /* HCCPARAMS */
  16. #define HCCPARAMS_LEN BIT(17)
  17. /* DCCPARAMS */
  18. #define DCCPARAMS_DEN (0x1F << 0)
  19. #define DCCPARAMS_DC BIT(7)
  20. #define DCCPARAMS_HC BIT(8)
  21. /* TESTMODE */
  22. #define TESTMODE_FORCE BIT(0)
  23. /* USBCMD */
  24. #define USBCMD_RS BIT(0)
  25. #define USBCMD_RST BIT(1)
  26. #define USBCMD_SUTW BIT(13)
  27. #define USBCMD_ATDTW BIT(14)
  28. /* USBSTS & USBINTR */
  29. #define USBi_UI BIT(0)
  30. #define USBi_UEI BIT(1)
  31. #define USBi_PCI BIT(2)
  32. #define USBi_URI BIT(6)
  33. #define USBi_SLI BIT(8)
  34. /* DEVICEADDR */
  35. #define DEVICEADDR_USBADRA BIT(24)
  36. #define DEVICEADDR_USBADR (0x7FUL << 25)
  37. /* PORTSC */
  38. #define PORTSC_FPR BIT(6)
  39. #define PORTSC_SUSP BIT(7)
  40. #define PORTSC_HSP BIT(9)
  41. #define PORTSC_PTC (0x0FUL << 16)
  42. /* PTS and PTW for non lpm version only */
  43. #define PORTSC_PTS(d) \
  44. ((((d) & 0x3) << 30) | (((d) & 0x4) ? BIT(25) : 0))
  45. #define PORTSC_PTW BIT(28)
  46. #define PORTSC_STS BIT(29)
  47. /* DEVLC */
  48. #define DEVLC_PSPD (0x03UL << 25)
  49. #define DEVLC_PSPD_HS (0x02UL << 25)
  50. #define DEVLC_PTW BIT(27)
  51. #define DEVLC_STS BIT(28)
  52. #define DEVLC_PTS(d) (((d) & 0x7) << 29)
  53. /* Encoding for DEVLC_PTS and PORTSC_PTS */
  54. #define PTS_UTMI 0
  55. #define PTS_ULPI 2
  56. #define PTS_SERIAL 3
  57. #define PTS_HSIC 4
  58. /* OTGSC */
  59. #define OTGSC_IDPU BIT(5)
  60. #define OTGSC_ID BIT(8)
  61. #define OTGSC_AVV BIT(9)
  62. #define OTGSC_ASV BIT(10)
  63. #define OTGSC_BSV BIT(11)
  64. #define OTGSC_BSE BIT(12)
  65. #define OTGSC_IDIS BIT(16)
  66. #define OTGSC_AVVIS BIT(17)
  67. #define OTGSC_ASVIS BIT(18)
  68. #define OTGSC_BSVIS BIT(19)
  69. #define OTGSC_BSEIS BIT(20)
  70. #define OTGSC_IDIE BIT(24)
  71. #define OTGSC_AVVIE BIT(25)
  72. #define OTGSC_ASVIE BIT(26)
  73. #define OTGSC_BSVIE BIT(27)
  74. #define OTGSC_BSEIE BIT(28)
  75. /* USBMODE */
  76. #define USBMODE_CM (0x03UL << 0)
  77. #define USBMODE_CM_DC (0x02UL << 0)
  78. #define USBMODE_SLOM BIT(3)
  79. #define USBMODE_CI_SDIS BIT(4)
  80. /* ENDPTCTRL */
  81. #define ENDPTCTRL_RXS BIT(0)
  82. #define ENDPTCTRL_RXT (0x03UL << 2)
  83. #define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */
  84. #define ENDPTCTRL_RXE BIT(7)
  85. #define ENDPTCTRL_TXS BIT(16)
  86. #define ENDPTCTRL_TXT (0x03UL << 18)
  87. #define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */
  88. #define ENDPTCTRL_TXE BIT(23)
  89. #endif /* __DRIVERS_USB_CHIPIDEA_BITS_H */