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- Device Tree Clock bindings for Altera's SoCFPGA platform
- This binding uses the common clock binding[1].
- [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
- Required properties:
- - compatible : shall be one of the following:
- "altr,socfpga-pll-clock" - for a PLL clock
- "altr,socfpga-perip-clock" - The peripheral clock divided from the
- PLL clock.
- "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
- can get gated.
- - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
- - clocks : shall be the input parent clock phandle for the clock. This is
- either an oscillator or a pll output.
- - #clock-cells : from common clock binding, shall be set to 0.
- Optional properties:
- - fixed-divider : If clocks have a fixed divider value, use this property.
- - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
- and the bit index.
- - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
- and width.
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