sgtl5000.c 37 KB

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  1. /*
  2. * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
  3. *
  4. * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/slab.h>
  15. #include <linux/pm.h>
  16. #include <linux/i2c.h>
  17. #include <linux/clk.h>
  18. #include <linux/regulator/driver.h>
  19. #include <linux/regulator/machine.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/of_device.h>
  22. #include <sound/core.h>
  23. #include <sound/tlv.h>
  24. #include <sound/pcm.h>
  25. #include <sound/pcm_params.h>
  26. #include <sound/soc.h>
  27. #include <sound/soc-dapm.h>
  28. #include <sound/initval.h>
  29. #include "sgtl5000.h"
  30. #define SGTL5000_DAP_REG_OFFSET 0x0100
  31. #define SGTL5000_MAX_REG_OFFSET 0x013A
  32. /* default value of sgtl5000 registers */
  33. static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET] = {
  34. [SGTL5000_CHIP_CLK_CTRL] = 0x0008,
  35. [SGTL5000_CHIP_I2S_CTRL] = 0x0010,
  36. [SGTL5000_CHIP_SSS_CTRL] = 0x0008,
  37. [SGTL5000_CHIP_DAC_VOL] = 0x3c3c,
  38. [SGTL5000_CHIP_PAD_STRENGTH] = 0x015f,
  39. [SGTL5000_CHIP_ANA_HP_CTRL] = 0x1818,
  40. [SGTL5000_CHIP_ANA_CTRL] = 0x0111,
  41. [SGTL5000_CHIP_LINE_OUT_VOL] = 0x0404,
  42. [SGTL5000_CHIP_ANA_POWER] = 0x7060,
  43. [SGTL5000_CHIP_PLL_CTRL] = 0x5000,
  44. [SGTL5000_DAP_BASS_ENHANCE] = 0x0040,
  45. [SGTL5000_DAP_BASS_ENHANCE_CTRL] = 0x051f,
  46. [SGTL5000_DAP_SURROUND] = 0x0040,
  47. [SGTL5000_DAP_EQ_BASS_BAND0] = 0x002f,
  48. [SGTL5000_DAP_EQ_BASS_BAND1] = 0x002f,
  49. [SGTL5000_DAP_EQ_BASS_BAND2] = 0x002f,
  50. [SGTL5000_DAP_EQ_BASS_BAND3] = 0x002f,
  51. [SGTL5000_DAP_EQ_BASS_BAND4] = 0x002f,
  52. [SGTL5000_DAP_MAIN_CHAN] = 0x8000,
  53. [SGTL5000_DAP_AVC_CTRL] = 0x0510,
  54. [SGTL5000_DAP_AVC_THRESHOLD] = 0x1473,
  55. [SGTL5000_DAP_AVC_ATTACK] = 0x0028,
  56. [SGTL5000_DAP_AVC_DECAY] = 0x0050,
  57. };
  58. /* regulator supplies for sgtl5000, VDDD is an optional external supply */
  59. enum sgtl5000_regulator_supplies {
  60. VDDA,
  61. VDDIO,
  62. VDDD,
  63. SGTL5000_SUPPLY_NUM
  64. };
  65. /* vddd is optional supply */
  66. static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
  67. "VDDA",
  68. "VDDIO",
  69. "VDDD"
  70. };
  71. #define LDO_CONSUMER_NAME "VDDD_LDO"
  72. #define LDO_VOLTAGE 1200000
  73. static struct regulator_consumer_supply ldo_consumer[] = {
  74. REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
  75. };
  76. static struct regulator_init_data ldo_init_data = {
  77. .constraints = {
  78. .min_uV = 850000,
  79. .max_uV = 1600000,
  80. .valid_modes_mask = REGULATOR_MODE_NORMAL,
  81. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  82. },
  83. .num_consumer_supplies = 1,
  84. .consumer_supplies = &ldo_consumer[0],
  85. };
  86. /*
  87. * sgtl5000 internal ldo regulator,
  88. * enabled when VDDD not provided
  89. */
  90. struct ldo_regulator {
  91. struct regulator_desc desc;
  92. struct regulator_dev *dev;
  93. int voltage;
  94. void *codec_data;
  95. bool enabled;
  96. };
  97. /* sgtl5000 private structure in codec */
  98. struct sgtl5000_priv {
  99. int sysclk; /* sysclk rate */
  100. int master; /* i2s master or not */
  101. int fmt; /* i2s data format */
  102. struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
  103. struct ldo_regulator *ldo;
  104. };
  105. /*
  106. * mic_bias power on/off share the same register bits with
  107. * output impedance of mic bias, when power on mic bias, we
  108. * need reclaim it to impedance value.
  109. * 0x0 = Powered off
  110. * 0x1 = 2Kohm
  111. * 0x2 = 4Kohm
  112. * 0x3 = 8Kohm
  113. */
  114. static int mic_bias_event(struct snd_soc_dapm_widget *w,
  115. struct snd_kcontrol *kcontrol, int event)
  116. {
  117. switch (event) {
  118. case SND_SOC_DAPM_POST_PMU:
  119. /* change mic bias resistor to 4Kohm */
  120. snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
  121. SGTL5000_BIAS_R_MASK,
  122. SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
  123. break;
  124. case SND_SOC_DAPM_PRE_PMD:
  125. snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
  126. SGTL5000_BIAS_R_MASK, 0);
  127. break;
  128. }
  129. return 0;
  130. }
  131. /*
  132. * using codec assist to small pop, hp_powerup or lineout_powerup
  133. * should stay setting until vag_powerup is fully ramped down,
  134. * vag fully ramped down require 400ms.
  135. */
  136. static int small_pop_event(struct snd_soc_dapm_widget *w,
  137. struct snd_kcontrol *kcontrol, int event)
  138. {
  139. switch (event) {
  140. case SND_SOC_DAPM_PRE_PMU:
  141. snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
  142. SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
  143. break;
  144. case SND_SOC_DAPM_PRE_PMD:
  145. snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
  146. SGTL5000_VAG_POWERUP, 0);
  147. msleep(400);
  148. break;
  149. default:
  150. break;
  151. }
  152. return 0;
  153. }
  154. /* input sources for ADC */
  155. static const char *adc_mux_text[] = {
  156. "MIC_IN", "LINE_IN"
  157. };
  158. static const struct soc_enum adc_enum =
  159. SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text);
  160. static const struct snd_kcontrol_new adc_mux =
  161. SOC_DAPM_ENUM("Capture Mux", adc_enum);
  162. /* input sources for DAC */
  163. static const char *dac_mux_text[] = {
  164. "DAC", "LINE_IN"
  165. };
  166. static const struct soc_enum dac_enum =
  167. SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text);
  168. static const struct snd_kcontrol_new dac_mux =
  169. SOC_DAPM_ENUM("Headphone Mux", dac_enum);
  170. static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
  171. SND_SOC_DAPM_INPUT("LINE_IN"),
  172. SND_SOC_DAPM_INPUT("MIC_IN"),
  173. SND_SOC_DAPM_OUTPUT("HP_OUT"),
  174. SND_SOC_DAPM_OUTPUT("LINE_OUT"),
  175. SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
  176. mic_bias_event,
  177. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  178. SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
  179. small_pop_event,
  180. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
  181. SND_SOC_DAPM_PGA_E("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0,
  182. small_pop_event,
  183. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
  184. SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
  185. SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
  186. /* aif for i2s input */
  187. SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
  188. 0, SGTL5000_CHIP_DIG_POWER,
  189. 0, 0),
  190. /* aif for i2s output */
  191. SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
  192. 0, SGTL5000_CHIP_DIG_POWER,
  193. 1, 0),
  194. SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
  195. SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
  196. };
  197. /* routes for sgtl5000 */
  198. static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
  199. {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
  200. {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
  201. {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
  202. {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
  203. {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
  204. {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
  205. {"LO", NULL, "DAC"}, /* dac --> line_out */
  206. {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
  207. {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
  208. {"LINE_OUT", NULL, "LO"},
  209. {"HP_OUT", NULL, "HP"},
  210. };
  211. /* custom function to fetch info of PCM playback volume */
  212. static int dac_info_volsw(struct snd_kcontrol *kcontrol,
  213. struct snd_ctl_elem_info *uinfo)
  214. {
  215. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  216. uinfo->count = 2;
  217. uinfo->value.integer.min = 0;
  218. uinfo->value.integer.max = 0xfc - 0x3c;
  219. return 0;
  220. }
  221. /*
  222. * custom function to get of PCM playback volume
  223. *
  224. * dac volume register
  225. * 15-------------8-7--------------0
  226. * | R channel vol | L channel vol |
  227. * -------------------------------
  228. *
  229. * PCM volume with 0.5017 dB steps from 0 to -90 dB
  230. *
  231. * register values map to dB
  232. * 0x3B and less = Reserved
  233. * 0x3C = 0 dB
  234. * 0x3D = -0.5 dB
  235. * 0xF0 = -90 dB
  236. * 0xFC and greater = Muted
  237. *
  238. * register value map to userspace value
  239. *
  240. * register value 0x3c(0dB) 0xf0(-90dB)0xfc
  241. * ------------------------------
  242. * userspace value 0xc0 0
  243. */
  244. static int dac_get_volsw(struct snd_kcontrol *kcontrol,
  245. struct snd_ctl_elem_value *ucontrol)
  246. {
  247. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  248. int reg;
  249. int l;
  250. int r;
  251. reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
  252. /* get left channel volume */
  253. l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
  254. /* get right channel volume */
  255. r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
  256. /* make sure value fall in (0x3c,0xfc) */
  257. l = clamp(l, 0x3c, 0xfc);
  258. r = clamp(r, 0x3c, 0xfc);
  259. /* invert it and map to userspace value */
  260. l = 0xfc - l;
  261. r = 0xfc - r;
  262. ucontrol->value.integer.value[0] = l;
  263. ucontrol->value.integer.value[1] = r;
  264. return 0;
  265. }
  266. /*
  267. * custom function to put of PCM playback volume
  268. *
  269. * dac volume register
  270. * 15-------------8-7--------------0
  271. * | R channel vol | L channel vol |
  272. * -------------------------------
  273. *
  274. * PCM volume with 0.5017 dB steps from 0 to -90 dB
  275. *
  276. * register values map to dB
  277. * 0x3B and less = Reserved
  278. * 0x3C = 0 dB
  279. * 0x3D = -0.5 dB
  280. * 0xF0 = -90 dB
  281. * 0xFC and greater = Muted
  282. *
  283. * userspace value map to register value
  284. *
  285. * userspace value 0xc0 0
  286. * ------------------------------
  287. * register value 0x3c(0dB) 0xf0(-90dB)0xfc
  288. */
  289. static int dac_put_volsw(struct snd_kcontrol *kcontrol,
  290. struct snd_ctl_elem_value *ucontrol)
  291. {
  292. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  293. int reg;
  294. int l;
  295. int r;
  296. l = ucontrol->value.integer.value[0];
  297. r = ucontrol->value.integer.value[1];
  298. /* make sure userspace volume fall in (0, 0xfc-0x3c) */
  299. l = clamp(l, 0, 0xfc - 0x3c);
  300. r = clamp(r, 0, 0xfc - 0x3c);
  301. /* invert it, get the value can be set to register */
  302. l = 0xfc - l;
  303. r = 0xfc - r;
  304. /* shift to get the register value */
  305. reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
  306. r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
  307. snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
  308. return 0;
  309. }
  310. static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
  311. /* tlv for mic gain, 0db 20db 30db 40db */
  312. static const unsigned int mic_gain_tlv[] = {
  313. TLV_DB_RANGE_HEAD(2),
  314. 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  315. 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
  316. };
  317. /* tlv for hp volume, -51.5db to 12.0db, step .5db */
  318. static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
  319. static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
  320. /* SOC_DOUBLE_S8_TLV with invert */
  321. {
  322. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  323. .name = "PCM Playback Volume",
  324. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
  325. SNDRV_CTL_ELEM_ACCESS_READWRITE,
  326. .info = dac_info_volsw,
  327. .get = dac_get_volsw,
  328. .put = dac_put_volsw,
  329. },
  330. SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
  331. SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
  332. SGTL5000_CHIP_ANA_ADC_CTRL,
  333. 8, 2, 0, capture_6db_attenuate),
  334. SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
  335. SOC_DOUBLE_TLV("Headphone Playback Volume",
  336. SGTL5000_CHIP_ANA_HP_CTRL,
  337. 0, 8,
  338. 0x7f, 1,
  339. headphone_volume),
  340. SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
  341. 5, 1, 0),
  342. SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
  343. 0, 4, 0, mic_gain_tlv),
  344. };
  345. /* mute the codec used by alsa core */
  346. static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
  347. {
  348. struct snd_soc_codec *codec = codec_dai->codec;
  349. u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
  350. snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
  351. adcdac_ctrl, mute ? adcdac_ctrl : 0);
  352. return 0;
  353. }
  354. /* set codec format */
  355. static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  356. {
  357. struct snd_soc_codec *codec = codec_dai->codec;
  358. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  359. u16 i2sctl = 0;
  360. sgtl5000->master = 0;
  361. /*
  362. * i2s clock and frame master setting.
  363. * ONLY support:
  364. * - clock and frame slave,
  365. * - clock and frame master
  366. */
  367. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  368. case SND_SOC_DAIFMT_CBS_CFS:
  369. break;
  370. case SND_SOC_DAIFMT_CBM_CFM:
  371. i2sctl |= SGTL5000_I2S_MASTER;
  372. sgtl5000->master = 1;
  373. break;
  374. default:
  375. return -EINVAL;
  376. }
  377. /* setting i2s data format */
  378. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  379. case SND_SOC_DAIFMT_DSP_A:
  380. i2sctl |= SGTL5000_I2S_MODE_PCM;
  381. break;
  382. case SND_SOC_DAIFMT_DSP_B:
  383. i2sctl |= SGTL5000_I2S_MODE_PCM;
  384. i2sctl |= SGTL5000_I2S_LRALIGN;
  385. break;
  386. case SND_SOC_DAIFMT_I2S:
  387. i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
  388. break;
  389. case SND_SOC_DAIFMT_RIGHT_J:
  390. i2sctl |= SGTL5000_I2S_MODE_RJ;
  391. i2sctl |= SGTL5000_I2S_LRPOL;
  392. break;
  393. case SND_SOC_DAIFMT_LEFT_J:
  394. i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
  395. i2sctl |= SGTL5000_I2S_LRALIGN;
  396. break;
  397. default:
  398. return -EINVAL;
  399. }
  400. sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  401. /* Clock inversion */
  402. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  403. case SND_SOC_DAIFMT_NB_NF:
  404. break;
  405. case SND_SOC_DAIFMT_IB_NF:
  406. i2sctl |= SGTL5000_I2S_SCLK_INV;
  407. break;
  408. default:
  409. return -EINVAL;
  410. }
  411. snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
  412. return 0;
  413. }
  414. /* set codec sysclk */
  415. static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  416. int clk_id, unsigned int freq, int dir)
  417. {
  418. struct snd_soc_codec *codec = codec_dai->codec;
  419. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  420. switch (clk_id) {
  421. case SGTL5000_SYSCLK:
  422. sgtl5000->sysclk = freq;
  423. break;
  424. default:
  425. return -EINVAL;
  426. }
  427. return 0;
  428. }
  429. /*
  430. * set clock according to i2s frame clock,
  431. * sgtl5000 provide 2 clock sources.
  432. * 1. sys_mclk. sample freq can only configure to
  433. * 1/256, 1/384, 1/512 of sys_mclk.
  434. * 2. pll. can derive any audio clocks.
  435. *
  436. * clock setting rules:
  437. * 1. in slave mode, only sys_mclk can use.
  438. * 2. as constraint by sys_mclk, sample freq should
  439. * set to 32k, 44.1k and above.
  440. * 3. using sys_mclk prefer to pll to save power.
  441. */
  442. static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
  443. {
  444. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  445. int clk_ctl = 0;
  446. int sys_fs; /* sample freq */
  447. /*
  448. * sample freq should be divided by frame clock,
  449. * if frame clock lower than 44.1khz, sample feq should set to
  450. * 32khz or 44.1khz.
  451. */
  452. switch (frame_rate) {
  453. case 8000:
  454. case 16000:
  455. sys_fs = 32000;
  456. break;
  457. case 11025:
  458. case 22050:
  459. sys_fs = 44100;
  460. break;
  461. default:
  462. sys_fs = frame_rate;
  463. break;
  464. }
  465. /* set divided factor of frame clock */
  466. switch (sys_fs / frame_rate) {
  467. case 4:
  468. clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
  469. break;
  470. case 2:
  471. clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
  472. break;
  473. case 1:
  474. clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
  475. break;
  476. default:
  477. return -EINVAL;
  478. }
  479. /* set the sys_fs according to frame rate */
  480. switch (sys_fs) {
  481. case 32000:
  482. clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
  483. break;
  484. case 44100:
  485. clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
  486. break;
  487. case 48000:
  488. clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
  489. break;
  490. case 96000:
  491. clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
  492. break;
  493. default:
  494. dev_err(codec->dev, "frame rate %d not supported\n",
  495. frame_rate);
  496. return -EINVAL;
  497. }
  498. /*
  499. * calculate the divider of mclk/sample_freq,
  500. * factor of freq =96k can only be 256, since mclk in range (12m,27m)
  501. */
  502. switch (sgtl5000->sysclk / sys_fs) {
  503. case 256:
  504. clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
  505. SGTL5000_MCLK_FREQ_SHIFT;
  506. break;
  507. case 384:
  508. clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
  509. SGTL5000_MCLK_FREQ_SHIFT;
  510. break;
  511. case 512:
  512. clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
  513. SGTL5000_MCLK_FREQ_SHIFT;
  514. break;
  515. default:
  516. /* if mclk not satisify the divider, use pll */
  517. if (sgtl5000->master) {
  518. clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
  519. SGTL5000_MCLK_FREQ_SHIFT;
  520. } else {
  521. dev_err(codec->dev,
  522. "PLL not supported in slave mode\n");
  523. return -EINVAL;
  524. }
  525. }
  526. /* if using pll, please check manual 6.4.2 for detail */
  527. if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
  528. u64 out, t;
  529. int div2;
  530. int pll_ctl;
  531. unsigned int in, int_div, frac_div;
  532. if (sgtl5000->sysclk > 17000000) {
  533. div2 = 1;
  534. in = sgtl5000->sysclk / 2;
  535. } else {
  536. div2 = 0;
  537. in = sgtl5000->sysclk;
  538. }
  539. if (sys_fs == 44100)
  540. out = 180633600;
  541. else
  542. out = 196608000;
  543. t = do_div(out, in);
  544. int_div = out;
  545. t *= 2048;
  546. do_div(t, in);
  547. frac_div = t;
  548. pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
  549. frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
  550. snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
  551. if (div2)
  552. snd_soc_update_bits(codec,
  553. SGTL5000_CHIP_CLK_TOP_CTRL,
  554. SGTL5000_INPUT_FREQ_DIV2,
  555. SGTL5000_INPUT_FREQ_DIV2);
  556. else
  557. snd_soc_update_bits(codec,
  558. SGTL5000_CHIP_CLK_TOP_CTRL,
  559. SGTL5000_INPUT_FREQ_DIV2,
  560. 0);
  561. /* power up pll */
  562. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  563. SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
  564. SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
  565. } else {
  566. /* power down pll */
  567. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  568. SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
  569. 0);
  570. }
  571. /* if using pll, clk_ctrl must be set after pll power up */
  572. snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
  573. return 0;
  574. }
  575. /*
  576. * Set PCM DAI bit size and sample rate.
  577. * input: params_rate, params_fmt
  578. */
  579. static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
  580. struct snd_pcm_hw_params *params,
  581. struct snd_soc_dai *dai)
  582. {
  583. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  584. struct snd_soc_codec *codec = rtd->codec;
  585. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  586. int channels = params_channels(params);
  587. int i2s_ctl = 0;
  588. int stereo;
  589. int ret;
  590. /* sysclk should already set */
  591. if (!sgtl5000->sysclk) {
  592. dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
  593. return -EFAULT;
  594. }
  595. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  596. stereo = SGTL5000_DAC_STEREO;
  597. else
  598. stereo = SGTL5000_ADC_STEREO;
  599. /* set mono to save power */
  600. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
  601. channels == 1 ? 0 : stereo);
  602. /* set codec clock base on lrclk */
  603. ret = sgtl5000_set_clock(codec, params_rate(params));
  604. if (ret)
  605. return ret;
  606. /* set i2s data format */
  607. switch (params_format(params)) {
  608. case SNDRV_PCM_FORMAT_S16_LE:
  609. if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
  610. return -EINVAL;
  611. i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
  612. i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
  613. SGTL5000_I2S_SCLKFREQ_SHIFT;
  614. break;
  615. case SNDRV_PCM_FORMAT_S20_3LE:
  616. i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
  617. i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
  618. SGTL5000_I2S_SCLKFREQ_SHIFT;
  619. break;
  620. case SNDRV_PCM_FORMAT_S24_LE:
  621. i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
  622. i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
  623. SGTL5000_I2S_SCLKFREQ_SHIFT;
  624. break;
  625. case SNDRV_PCM_FORMAT_S32_LE:
  626. if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
  627. return -EINVAL;
  628. i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
  629. i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
  630. SGTL5000_I2S_SCLKFREQ_SHIFT;
  631. break;
  632. default:
  633. return -EINVAL;
  634. }
  635. snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
  636. SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
  637. i2s_ctl);
  638. return 0;
  639. }
  640. #ifdef CONFIG_REGULATOR
  641. static int ldo_regulator_is_enabled(struct regulator_dev *dev)
  642. {
  643. struct ldo_regulator *ldo = rdev_get_drvdata(dev);
  644. return ldo->enabled;
  645. }
  646. static int ldo_regulator_enable(struct regulator_dev *dev)
  647. {
  648. struct ldo_regulator *ldo = rdev_get_drvdata(dev);
  649. struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
  650. int reg;
  651. if (ldo_regulator_is_enabled(dev))
  652. return 0;
  653. /* set regulator value firstly */
  654. reg = (1600 - ldo->voltage / 1000) / 50;
  655. reg = clamp(reg, 0x0, 0xf);
  656. /* amend the voltage value, unit: uV */
  657. ldo->voltage = (1600 - reg * 50) * 1000;
  658. /* set voltage to register */
  659. snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
  660. SGTL5000_LINREG_VDDD_MASK, reg);
  661. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  662. SGTL5000_LINEREG_D_POWERUP,
  663. SGTL5000_LINEREG_D_POWERUP);
  664. /* when internal ldo enabled, simple digital power can be disabled */
  665. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  666. SGTL5000_LINREG_SIMPLE_POWERUP,
  667. 0);
  668. ldo->enabled = 1;
  669. return 0;
  670. }
  671. static int ldo_regulator_disable(struct regulator_dev *dev)
  672. {
  673. struct ldo_regulator *ldo = rdev_get_drvdata(dev);
  674. struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
  675. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  676. SGTL5000_LINEREG_D_POWERUP,
  677. 0);
  678. /* clear voltage info */
  679. snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
  680. SGTL5000_LINREG_VDDD_MASK, 0);
  681. ldo->enabled = 0;
  682. return 0;
  683. }
  684. static int ldo_regulator_get_voltage(struct regulator_dev *dev)
  685. {
  686. struct ldo_regulator *ldo = rdev_get_drvdata(dev);
  687. return ldo->voltage;
  688. }
  689. static struct regulator_ops ldo_regulator_ops = {
  690. .is_enabled = ldo_regulator_is_enabled,
  691. .enable = ldo_regulator_enable,
  692. .disable = ldo_regulator_disable,
  693. .get_voltage = ldo_regulator_get_voltage,
  694. };
  695. static int ldo_regulator_register(struct snd_soc_codec *codec,
  696. struct regulator_init_data *init_data,
  697. int voltage)
  698. {
  699. struct ldo_regulator *ldo;
  700. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  701. ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
  702. if (!ldo) {
  703. dev_err(codec->dev, "failed to allocate ldo_regulator\n");
  704. return -ENOMEM;
  705. }
  706. ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
  707. if (!ldo->desc.name) {
  708. kfree(ldo);
  709. dev_err(codec->dev, "failed to allocate decs name memory\n");
  710. return -ENOMEM;
  711. }
  712. ldo->desc.type = REGULATOR_VOLTAGE;
  713. ldo->desc.owner = THIS_MODULE;
  714. ldo->desc.ops = &ldo_regulator_ops;
  715. ldo->desc.n_voltages = 1;
  716. ldo->codec_data = codec;
  717. ldo->voltage = voltage;
  718. ldo->dev = regulator_register(&ldo->desc, codec->dev,
  719. init_data, ldo, NULL);
  720. if (IS_ERR(ldo->dev)) {
  721. int ret = PTR_ERR(ldo->dev);
  722. dev_err(codec->dev, "failed to register regulator\n");
  723. kfree(ldo->desc.name);
  724. kfree(ldo);
  725. return ret;
  726. }
  727. sgtl5000->ldo = ldo;
  728. return 0;
  729. }
  730. static int ldo_regulator_remove(struct snd_soc_codec *codec)
  731. {
  732. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  733. struct ldo_regulator *ldo = sgtl5000->ldo;
  734. if (!ldo)
  735. return 0;
  736. regulator_unregister(ldo->dev);
  737. kfree(ldo->desc.name);
  738. kfree(ldo);
  739. return 0;
  740. }
  741. #else
  742. static int ldo_regulator_register(struct snd_soc_codec *codec,
  743. struct regulator_init_data *init_data,
  744. int voltage)
  745. {
  746. dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
  747. return -EINVAL;
  748. }
  749. static int ldo_regulator_remove(struct snd_soc_codec *codec)
  750. {
  751. return 0;
  752. }
  753. #endif
  754. /*
  755. * set dac bias
  756. * common state changes:
  757. * startup:
  758. * off --> standby --> prepare --> on
  759. * standby --> prepare --> on
  760. *
  761. * stop:
  762. * on --> prepare --> standby
  763. */
  764. static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
  765. enum snd_soc_bias_level level)
  766. {
  767. int ret;
  768. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  769. switch (level) {
  770. case SND_SOC_BIAS_ON:
  771. case SND_SOC_BIAS_PREPARE:
  772. break;
  773. case SND_SOC_BIAS_STANDBY:
  774. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
  775. ret = regulator_bulk_enable(
  776. ARRAY_SIZE(sgtl5000->supplies),
  777. sgtl5000->supplies);
  778. if (ret)
  779. return ret;
  780. udelay(10);
  781. }
  782. break;
  783. case SND_SOC_BIAS_OFF:
  784. regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
  785. sgtl5000->supplies);
  786. break;
  787. }
  788. codec->dapm.bias_level = level;
  789. return 0;
  790. }
  791. #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  792. SNDRV_PCM_FMTBIT_S20_3LE |\
  793. SNDRV_PCM_FMTBIT_S24_LE |\
  794. SNDRV_PCM_FMTBIT_S32_LE)
  795. static const struct snd_soc_dai_ops sgtl5000_ops = {
  796. .hw_params = sgtl5000_pcm_hw_params,
  797. .digital_mute = sgtl5000_digital_mute,
  798. .set_fmt = sgtl5000_set_dai_fmt,
  799. .set_sysclk = sgtl5000_set_dai_sysclk,
  800. };
  801. static struct snd_soc_dai_driver sgtl5000_dai = {
  802. .name = "sgtl5000",
  803. .playback = {
  804. .stream_name = "Playback",
  805. .channels_min = 1,
  806. .channels_max = 2,
  807. /*
  808. * only support 8~48K + 96K,
  809. * TODO modify hw_param to support more
  810. */
  811. .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
  812. .formats = SGTL5000_FORMATS,
  813. },
  814. .capture = {
  815. .stream_name = "Capture",
  816. .channels_min = 1,
  817. .channels_max = 2,
  818. .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
  819. .formats = SGTL5000_FORMATS,
  820. },
  821. .ops = &sgtl5000_ops,
  822. .symmetric_rates = 1,
  823. };
  824. static int sgtl5000_volatile_register(struct snd_soc_codec *codec,
  825. unsigned int reg)
  826. {
  827. switch (reg) {
  828. case SGTL5000_CHIP_ID:
  829. case SGTL5000_CHIP_ADCDAC_CTRL:
  830. case SGTL5000_CHIP_ANA_STATUS:
  831. return 1;
  832. }
  833. return 0;
  834. }
  835. #ifdef CONFIG_SUSPEND
  836. static int sgtl5000_suspend(struct snd_soc_codec *codec)
  837. {
  838. sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
  839. return 0;
  840. }
  841. /*
  842. * restore all sgtl5000 registers,
  843. * since a big hole between dap and regular registers,
  844. * we will restore them respectively.
  845. */
  846. static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
  847. {
  848. u16 *cache = codec->reg_cache;
  849. u16 reg;
  850. /* restore regular registers */
  851. for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
  852. /* These regs should restore in particular order */
  853. if (reg == SGTL5000_CHIP_ANA_POWER ||
  854. reg == SGTL5000_CHIP_CLK_CTRL ||
  855. reg == SGTL5000_CHIP_LINREG_CTRL ||
  856. reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
  857. reg == SGTL5000_CHIP_REF_CTRL)
  858. continue;
  859. snd_soc_write(codec, reg, cache[reg]);
  860. }
  861. /* restore dap registers */
  862. for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
  863. snd_soc_write(codec, reg, cache[reg]);
  864. /*
  865. * restore these regs according to the power setting sequence in
  866. * sgtl5000_set_power_regs() and clock setting sequence in
  867. * sgtl5000_set_clock().
  868. *
  869. * The order of restore is:
  870. * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after
  871. * SGTL5000_CHIP_ANA_POWER PLL bits set
  872. * 2. SGTL5000_CHIP_LINREG_CTRL should be set before
  873. * SGTL5000_CHIP_ANA_POWER LINREG_D restored
  874. * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage,
  875. * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored
  876. */
  877. snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
  878. cache[SGTL5000_CHIP_LINREG_CTRL]);
  879. snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
  880. cache[SGTL5000_CHIP_ANA_POWER]);
  881. snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
  882. cache[SGTL5000_CHIP_CLK_CTRL]);
  883. snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
  884. cache[SGTL5000_CHIP_REF_CTRL]);
  885. snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
  886. cache[SGTL5000_CHIP_LINE_OUT_CTRL]);
  887. return 0;
  888. }
  889. static int sgtl5000_resume(struct snd_soc_codec *codec)
  890. {
  891. /* Bring the codec back up to standby to enable regulators */
  892. sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  893. /* Restore registers by cached in memory */
  894. sgtl5000_restore_regs(codec);
  895. return 0;
  896. }
  897. #else
  898. #define sgtl5000_suspend NULL
  899. #define sgtl5000_resume NULL
  900. #endif /* CONFIG_SUSPEND */
  901. /*
  902. * sgtl5000 has 3 internal power supplies:
  903. * 1. VAG, normally set to vdda/2
  904. * 2. chargepump, set to different value
  905. * according to voltage of vdda and vddio
  906. * 3. line out VAG, normally set to vddio/2
  907. *
  908. * and should be set according to:
  909. * 1. vddd provided by external or not
  910. * 2. vdda and vddio voltage value. > 3.1v or not
  911. * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
  912. */
  913. static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
  914. {
  915. int vddd;
  916. int vdda;
  917. int vddio;
  918. u16 ana_pwr;
  919. u16 lreg_ctrl;
  920. int vag;
  921. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  922. vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
  923. vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
  924. vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
  925. vdda = vdda / 1000;
  926. vddio = vddio / 1000;
  927. vddd = vddd / 1000;
  928. if (vdda <= 0 || vddio <= 0 || vddd < 0) {
  929. dev_err(codec->dev, "regulator voltage not set correctly\n");
  930. return -EINVAL;
  931. }
  932. /* according to datasheet, maximum voltage of supplies */
  933. if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
  934. dev_err(codec->dev,
  935. "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
  936. vdda, vddio, vddd);
  937. return -EINVAL;
  938. }
  939. /* reset value */
  940. ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
  941. ana_pwr |= SGTL5000_DAC_STEREO |
  942. SGTL5000_ADC_STEREO |
  943. SGTL5000_REFTOP_POWERUP;
  944. lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
  945. if (vddio < 3100 && vdda < 3100) {
  946. /* enable internal oscillator used for charge pump */
  947. snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
  948. SGTL5000_INT_OSC_EN,
  949. SGTL5000_INT_OSC_EN);
  950. /* Enable VDDC charge pump */
  951. ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
  952. } else if (vddio >= 3100 && vdda >= 3100) {
  953. /*
  954. * if vddio and vddd > 3.1v,
  955. * charge pump should be clean before set ana_pwr
  956. */
  957. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  958. SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
  959. /* VDDC use VDDIO rail */
  960. lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
  961. lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
  962. SGTL5000_VDDC_MAN_ASSN_SHIFT;
  963. }
  964. snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
  965. snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
  966. /* set voltage to register */
  967. snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
  968. SGTL5000_LINREG_VDDD_MASK, 0x8);
  969. /*
  970. * if vddd linear reg has been enabled,
  971. * simple digital supply should be clear to get
  972. * proper VDDD voltage.
  973. */
  974. if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
  975. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  976. SGTL5000_LINREG_SIMPLE_POWERUP,
  977. 0);
  978. else
  979. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  980. SGTL5000_LINREG_SIMPLE_POWERUP |
  981. SGTL5000_STARTUP_POWERUP,
  982. 0);
  983. /*
  984. * set ADC/DAC VAG to vdda / 2,
  985. * should stay in range (0.8v, 1.575v)
  986. */
  987. vag = vdda / 2;
  988. if (vag <= SGTL5000_ANA_GND_BASE)
  989. vag = 0;
  990. else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
  991. (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
  992. vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
  993. else
  994. vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
  995. snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
  996. SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
  997. /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
  998. vag = vddio / 2;
  999. if (vag <= SGTL5000_LINE_OUT_GND_BASE)
  1000. vag = 0;
  1001. else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
  1002. SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
  1003. vag = SGTL5000_LINE_OUT_GND_MAX;
  1004. else
  1005. vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
  1006. SGTL5000_LINE_OUT_GND_STP;
  1007. snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
  1008. SGTL5000_LINE_OUT_CURRENT_MASK |
  1009. SGTL5000_LINE_OUT_GND_MASK,
  1010. vag << SGTL5000_LINE_OUT_GND_SHIFT |
  1011. SGTL5000_LINE_OUT_CURRENT_360u <<
  1012. SGTL5000_LINE_OUT_CURRENT_SHIFT);
  1013. return 0;
  1014. }
  1015. static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
  1016. {
  1017. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  1018. int ret;
  1019. /* set internal ldo to 1.2v */
  1020. ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
  1021. if (ret) {
  1022. dev_err(codec->dev,
  1023. "Failed to register vddd internal supplies: %d\n", ret);
  1024. return ret;
  1025. }
  1026. sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
  1027. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
  1028. sgtl5000->supplies);
  1029. if (ret) {
  1030. ldo_regulator_remove(codec);
  1031. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  1032. return ret;
  1033. }
  1034. dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
  1035. return 0;
  1036. }
  1037. static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
  1038. {
  1039. u16 reg;
  1040. int ret;
  1041. int rev;
  1042. int i;
  1043. int external_vddd = 0;
  1044. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  1045. for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
  1046. sgtl5000->supplies[i].supply = supply_names[i];
  1047. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
  1048. sgtl5000->supplies);
  1049. if (!ret)
  1050. external_vddd = 1;
  1051. else {
  1052. ret = sgtl5000_replace_vddd_with_ldo(codec);
  1053. if (ret)
  1054. return ret;
  1055. }
  1056. ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
  1057. sgtl5000->supplies);
  1058. if (ret)
  1059. goto err_regulator_free;
  1060. /* wait for all power rails bring up */
  1061. udelay(10);
  1062. /* read chip information */
  1063. reg = snd_soc_read(codec, SGTL5000_CHIP_ID);
  1064. if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
  1065. SGTL5000_PARTID_PART_ID) {
  1066. dev_err(codec->dev,
  1067. "Device with ID register %x is not a sgtl5000\n", reg);
  1068. ret = -ENODEV;
  1069. goto err_regulator_disable;
  1070. }
  1071. rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
  1072. dev_info(codec->dev, "sgtl5000 revision 0x%x\n", rev);
  1073. /*
  1074. * workaround for revision 0x11 and later,
  1075. * roll back to use internal LDO
  1076. */
  1077. if (external_vddd && rev >= 0x11) {
  1078. /* disable all regulator first */
  1079. regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
  1080. sgtl5000->supplies);
  1081. /* free VDDD regulator */
  1082. regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
  1083. sgtl5000->supplies);
  1084. ret = sgtl5000_replace_vddd_with_ldo(codec);
  1085. if (ret)
  1086. return ret;
  1087. ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
  1088. sgtl5000->supplies);
  1089. if (ret)
  1090. goto err_regulator_free;
  1091. /* wait for all power rails bring up */
  1092. udelay(10);
  1093. }
  1094. return 0;
  1095. err_regulator_disable:
  1096. regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
  1097. sgtl5000->supplies);
  1098. err_regulator_free:
  1099. regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
  1100. sgtl5000->supplies);
  1101. if (external_vddd)
  1102. ldo_regulator_remove(codec);
  1103. return ret;
  1104. }
  1105. static int sgtl5000_probe(struct snd_soc_codec *codec)
  1106. {
  1107. int ret;
  1108. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  1109. /* setup i2c data ops */
  1110. ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
  1111. if (ret < 0) {
  1112. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  1113. return ret;
  1114. }
  1115. ret = sgtl5000_enable_regulators(codec);
  1116. if (ret)
  1117. return ret;
  1118. /* power up sgtl5000 */
  1119. ret = sgtl5000_set_power_regs(codec);
  1120. if (ret)
  1121. goto err;
  1122. /* enable small pop, introduce 400ms delay in turning off */
  1123. snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
  1124. SGTL5000_SMALL_POP,
  1125. SGTL5000_SMALL_POP);
  1126. /* disable short cut detector */
  1127. snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
  1128. /*
  1129. * set i2s as default input of sound switch
  1130. * TODO: add sound switch to control and dapm widge.
  1131. */
  1132. snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
  1133. SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
  1134. snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
  1135. SGTL5000_ADC_EN | SGTL5000_DAC_EN);
  1136. /* enable dac volume ramp by default */
  1137. snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
  1138. SGTL5000_DAC_VOL_RAMP_EN |
  1139. SGTL5000_DAC_MUTE_RIGHT |
  1140. SGTL5000_DAC_MUTE_LEFT);
  1141. snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
  1142. snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
  1143. SGTL5000_HP_ZCD_EN |
  1144. SGTL5000_ADC_ZCD_EN);
  1145. snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 0);
  1146. /*
  1147. * disable DAP
  1148. * TODO:
  1149. * Enable DAP in kcontrol and dapm.
  1150. */
  1151. snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
  1152. /* leading to standby state */
  1153. ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1154. if (ret)
  1155. goto err;
  1156. snd_soc_dapm_new_widgets(&codec->dapm);
  1157. return 0;
  1158. err:
  1159. regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
  1160. sgtl5000->supplies);
  1161. regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
  1162. sgtl5000->supplies);
  1163. ldo_regulator_remove(codec);
  1164. return ret;
  1165. }
  1166. static int sgtl5000_remove(struct snd_soc_codec *codec)
  1167. {
  1168. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  1169. sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1170. regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
  1171. sgtl5000->supplies);
  1172. regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
  1173. sgtl5000->supplies);
  1174. ldo_regulator_remove(codec);
  1175. return 0;
  1176. }
  1177. static struct snd_soc_codec_driver sgtl5000_driver = {
  1178. .probe = sgtl5000_probe,
  1179. .remove = sgtl5000_remove,
  1180. .suspend = sgtl5000_suspend,
  1181. .resume = sgtl5000_resume,
  1182. .set_bias_level = sgtl5000_set_bias_level,
  1183. .reg_cache_size = ARRAY_SIZE(sgtl5000_regs),
  1184. .reg_word_size = sizeof(u16),
  1185. .reg_cache_step = 2,
  1186. .reg_cache_default = sgtl5000_regs,
  1187. .volatile_register = sgtl5000_volatile_register,
  1188. .controls = sgtl5000_snd_controls,
  1189. .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
  1190. .dapm_widgets = sgtl5000_dapm_widgets,
  1191. .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
  1192. .dapm_routes = sgtl5000_dapm_routes,
  1193. .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
  1194. };
  1195. static __devinit int sgtl5000_i2c_probe(struct i2c_client *client,
  1196. const struct i2c_device_id *id)
  1197. {
  1198. struct sgtl5000_priv *sgtl5000;
  1199. int ret;
  1200. sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv),
  1201. GFP_KERNEL);
  1202. if (!sgtl5000)
  1203. return -ENOMEM;
  1204. i2c_set_clientdata(client, sgtl5000);
  1205. ret = snd_soc_register_codec(&client->dev,
  1206. &sgtl5000_driver, &sgtl5000_dai, 1);
  1207. return ret;
  1208. }
  1209. static __devexit int sgtl5000_i2c_remove(struct i2c_client *client)
  1210. {
  1211. snd_soc_unregister_codec(&client->dev);
  1212. return 0;
  1213. }
  1214. static const struct i2c_device_id sgtl5000_id[] = {
  1215. {"sgtl5000", 0},
  1216. {},
  1217. };
  1218. MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
  1219. static const struct of_device_id sgtl5000_dt_ids[] = {
  1220. { .compatible = "fsl,sgtl5000", },
  1221. { /* sentinel */ }
  1222. };
  1223. MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
  1224. static struct i2c_driver sgtl5000_i2c_driver = {
  1225. .driver = {
  1226. .name = "sgtl5000",
  1227. .owner = THIS_MODULE,
  1228. .of_match_table = sgtl5000_dt_ids,
  1229. },
  1230. .probe = sgtl5000_i2c_probe,
  1231. .remove = __devexit_p(sgtl5000_i2c_remove),
  1232. .id_table = sgtl5000_id,
  1233. };
  1234. static int __init sgtl5000_modinit(void)
  1235. {
  1236. return i2c_add_driver(&sgtl5000_i2c_driver);
  1237. }
  1238. module_init(sgtl5000_modinit);
  1239. static void __exit sgtl5000_exit(void)
  1240. {
  1241. i2c_del_driver(&sgtl5000_i2c_driver);
  1242. }
  1243. module_exit(sgtl5000_exit);
  1244. MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
  1245. MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
  1246. MODULE_LICENSE("GPL");