langwell_udc.c 85 KB

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  1. /*
  2. * Intel Langwell USB Device Controller driver
  3. * Copyright (C) 2008-2009, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. */
  9. /* #undef DEBUG */
  10. /* #undef VERBOSE_DEBUG */
  11. #include <linux/module.h>
  12. #include <linux/pci.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/kernel.h>
  15. #include <linux/delay.h>
  16. #include <linux/ioport.h>
  17. #include <linux/sched.h>
  18. #include <linux/slab.h>
  19. #include <linux/errno.h>
  20. #include <linux/init.h>
  21. #include <linux/timer.h>
  22. #include <linux/list.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/device.h>
  26. #include <linux/usb/ch9.h>
  27. #include <linux/usb/gadget.h>
  28. #include <linux/usb/otg.h>
  29. #include <linux/pm.h>
  30. #include <linux/io.h>
  31. #include <linux/irq.h>
  32. #include <asm/system.h>
  33. #include <asm/unaligned.h>
  34. #include "langwell_udc.h"
  35. #define DRIVER_DESC "Intel Langwell USB Device Controller driver"
  36. #define DRIVER_VERSION "16 May 2009"
  37. static const char driver_name[] = "langwell_udc";
  38. static const char driver_desc[] = DRIVER_DESC;
  39. /* for endpoint 0 operations */
  40. static const struct usb_endpoint_descriptor
  41. langwell_ep0_desc = {
  42. .bLength = USB_DT_ENDPOINT_SIZE,
  43. .bDescriptorType = USB_DT_ENDPOINT,
  44. .bEndpointAddress = 0,
  45. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  46. .wMaxPacketSize = EP0_MAX_PKT_SIZE,
  47. };
  48. /*-------------------------------------------------------------------------*/
  49. /* debugging */
  50. #ifdef VERBOSE_DEBUG
  51. static inline void print_all_registers(struct langwell_udc *dev)
  52. {
  53. int i;
  54. /* Capability Registers */
  55. dev_dbg(&dev->pdev->dev,
  56. "Capability Registers (offset: 0x%04x, length: 0x%08x)\n",
  57. CAP_REG_OFFSET, (u32)sizeof(struct langwell_cap_regs));
  58. dev_dbg(&dev->pdev->dev, "caplength=0x%02x\n",
  59. readb(&dev->cap_regs->caplength));
  60. dev_dbg(&dev->pdev->dev, "hciversion=0x%04x\n",
  61. readw(&dev->cap_regs->hciversion));
  62. dev_dbg(&dev->pdev->dev, "hcsparams=0x%08x\n",
  63. readl(&dev->cap_regs->hcsparams));
  64. dev_dbg(&dev->pdev->dev, "hccparams=0x%08x\n",
  65. readl(&dev->cap_regs->hccparams));
  66. dev_dbg(&dev->pdev->dev, "dciversion=0x%04x\n",
  67. readw(&dev->cap_regs->dciversion));
  68. dev_dbg(&dev->pdev->dev, "dccparams=0x%08x\n",
  69. readl(&dev->cap_regs->dccparams));
  70. /* Operational Registers */
  71. dev_dbg(&dev->pdev->dev,
  72. "Operational Registers (offset: 0x%04x, length: 0x%08x)\n",
  73. OP_REG_OFFSET, (u32)sizeof(struct langwell_op_regs));
  74. dev_dbg(&dev->pdev->dev, "extsts=0x%08x\n",
  75. readl(&dev->op_regs->extsts));
  76. dev_dbg(&dev->pdev->dev, "extintr=0x%08x\n",
  77. readl(&dev->op_regs->extintr));
  78. dev_dbg(&dev->pdev->dev, "usbcmd=0x%08x\n",
  79. readl(&dev->op_regs->usbcmd));
  80. dev_dbg(&dev->pdev->dev, "usbsts=0x%08x\n",
  81. readl(&dev->op_regs->usbsts));
  82. dev_dbg(&dev->pdev->dev, "usbintr=0x%08x\n",
  83. readl(&dev->op_regs->usbintr));
  84. dev_dbg(&dev->pdev->dev, "frindex=0x%08x\n",
  85. readl(&dev->op_regs->frindex));
  86. dev_dbg(&dev->pdev->dev, "ctrldssegment=0x%08x\n",
  87. readl(&dev->op_regs->ctrldssegment));
  88. dev_dbg(&dev->pdev->dev, "deviceaddr=0x%08x\n",
  89. readl(&dev->op_regs->deviceaddr));
  90. dev_dbg(&dev->pdev->dev, "endpointlistaddr=0x%08x\n",
  91. readl(&dev->op_regs->endpointlistaddr));
  92. dev_dbg(&dev->pdev->dev, "ttctrl=0x%08x\n",
  93. readl(&dev->op_regs->ttctrl));
  94. dev_dbg(&dev->pdev->dev, "burstsize=0x%08x\n",
  95. readl(&dev->op_regs->burstsize));
  96. dev_dbg(&dev->pdev->dev, "txfilltuning=0x%08x\n",
  97. readl(&dev->op_regs->txfilltuning));
  98. dev_dbg(&dev->pdev->dev, "txttfilltuning=0x%08x\n",
  99. readl(&dev->op_regs->txttfilltuning));
  100. dev_dbg(&dev->pdev->dev, "ic_usb=0x%08x\n",
  101. readl(&dev->op_regs->ic_usb));
  102. dev_dbg(&dev->pdev->dev, "ulpi_viewport=0x%08x\n",
  103. readl(&dev->op_regs->ulpi_viewport));
  104. dev_dbg(&dev->pdev->dev, "configflag=0x%08x\n",
  105. readl(&dev->op_regs->configflag));
  106. dev_dbg(&dev->pdev->dev, "portsc1=0x%08x\n",
  107. readl(&dev->op_regs->portsc1));
  108. dev_dbg(&dev->pdev->dev, "devlc=0x%08x\n",
  109. readl(&dev->op_regs->devlc));
  110. dev_dbg(&dev->pdev->dev, "otgsc=0x%08x\n",
  111. readl(&dev->op_regs->otgsc));
  112. dev_dbg(&dev->pdev->dev, "usbmode=0x%08x\n",
  113. readl(&dev->op_regs->usbmode));
  114. dev_dbg(&dev->pdev->dev, "endptnak=0x%08x\n",
  115. readl(&dev->op_regs->endptnak));
  116. dev_dbg(&dev->pdev->dev, "endptnaken=0x%08x\n",
  117. readl(&dev->op_regs->endptnaken));
  118. dev_dbg(&dev->pdev->dev, "endptsetupstat=0x%08x\n",
  119. readl(&dev->op_regs->endptsetupstat));
  120. dev_dbg(&dev->pdev->dev, "endptprime=0x%08x\n",
  121. readl(&dev->op_regs->endptprime));
  122. dev_dbg(&dev->pdev->dev, "endptflush=0x%08x\n",
  123. readl(&dev->op_regs->endptflush));
  124. dev_dbg(&dev->pdev->dev, "endptstat=0x%08x\n",
  125. readl(&dev->op_regs->endptstat));
  126. dev_dbg(&dev->pdev->dev, "endptcomplete=0x%08x\n",
  127. readl(&dev->op_regs->endptcomplete));
  128. for (i = 0; i < dev->ep_max / 2; i++) {
  129. dev_dbg(&dev->pdev->dev, "endptctrl[%d]=0x%08x\n",
  130. i, readl(&dev->op_regs->endptctrl[i]));
  131. }
  132. }
  133. #else
  134. #define print_all_registers(dev) do { } while (0)
  135. #endif /* VERBOSE_DEBUG */
  136. /*-------------------------------------------------------------------------*/
  137. #define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \
  138. USB_DIR_IN) : (usb_endpoint_dir_in((ep)->desc)))
  139. #define DIR_STRING(ep) (is_in(ep) ? "in" : "out")
  140. static char *type_string(const struct usb_endpoint_descriptor *desc)
  141. {
  142. switch (usb_endpoint_type(desc)) {
  143. case USB_ENDPOINT_XFER_BULK:
  144. return "bulk";
  145. case USB_ENDPOINT_XFER_ISOC:
  146. return "iso";
  147. case USB_ENDPOINT_XFER_INT:
  148. return "int";
  149. };
  150. return "control";
  151. }
  152. /* configure endpoint control registers */
  153. static void ep_reset(struct langwell_ep *ep, unsigned char ep_num,
  154. unsigned char is_in, unsigned char ep_type)
  155. {
  156. struct langwell_udc *dev;
  157. u32 endptctrl;
  158. dev = ep->dev;
  159. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  160. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  161. if (is_in) { /* TX */
  162. if (ep_num)
  163. endptctrl |= EPCTRL_TXR;
  164. endptctrl |= EPCTRL_TXE;
  165. endptctrl |= ep_type << EPCTRL_TXT_SHIFT;
  166. } else { /* RX */
  167. if (ep_num)
  168. endptctrl |= EPCTRL_RXR;
  169. endptctrl |= EPCTRL_RXE;
  170. endptctrl |= ep_type << EPCTRL_RXT_SHIFT;
  171. }
  172. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  173. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  174. }
  175. /* reset ep0 dQH and endptctrl */
  176. static void ep0_reset(struct langwell_udc *dev)
  177. {
  178. struct langwell_ep *ep;
  179. int i;
  180. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  181. /* ep0 in and out */
  182. for (i = 0; i < 2; i++) {
  183. ep = &dev->ep[i];
  184. ep->dev = dev;
  185. /* ep0 dQH */
  186. ep->dqh = &dev->ep_dqh[i];
  187. /* configure ep0 endpoint capabilities in dQH */
  188. ep->dqh->dqh_ios = 1;
  189. ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE;
  190. /* enable ep0-in HW zero length termination select */
  191. if (is_in(ep))
  192. ep->dqh->dqh_zlt = 0;
  193. ep->dqh->dqh_mult = 0;
  194. ep->dqh->dtd_next = DTD_TERM;
  195. /* configure ep0 control registers */
  196. ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL);
  197. }
  198. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  199. }
  200. /*-------------------------------------------------------------------------*/
  201. /* endpoints operations */
  202. /* configure endpoint, making it usable */
  203. static int langwell_ep_enable(struct usb_ep *_ep,
  204. const struct usb_endpoint_descriptor *desc)
  205. {
  206. struct langwell_udc *dev;
  207. struct langwell_ep *ep;
  208. u16 max = 0;
  209. unsigned long flags;
  210. int i, retval = 0;
  211. unsigned char zlt, ios = 0, mult = 0;
  212. ep = container_of(_ep, struct langwell_ep, ep);
  213. dev = ep->dev;
  214. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  215. if (!_ep || !desc || ep->desc
  216. || desc->bDescriptorType != USB_DT_ENDPOINT)
  217. return -EINVAL;
  218. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  219. return -ESHUTDOWN;
  220. max = usb_endpoint_maxp(desc);
  221. /*
  222. * disable HW zero length termination select
  223. * driver handles zero length packet through req->req.zero
  224. */
  225. zlt = 1;
  226. /*
  227. * sanity check type, direction, address, and then
  228. * initialize the endpoint capabilities fields in dQH
  229. */
  230. switch (usb_endpoint_type(desc)) {
  231. case USB_ENDPOINT_XFER_CONTROL:
  232. ios = 1;
  233. break;
  234. case USB_ENDPOINT_XFER_BULK:
  235. if ((dev->gadget.speed == USB_SPEED_HIGH
  236. && max != 512)
  237. || (dev->gadget.speed == USB_SPEED_FULL
  238. && max > 64)) {
  239. goto done;
  240. }
  241. break;
  242. case USB_ENDPOINT_XFER_INT:
  243. if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
  244. goto done;
  245. switch (dev->gadget.speed) {
  246. case USB_SPEED_HIGH:
  247. if (max <= 1024)
  248. break;
  249. case USB_SPEED_FULL:
  250. if (max <= 64)
  251. break;
  252. default:
  253. if (max <= 8)
  254. break;
  255. goto done;
  256. }
  257. break;
  258. case USB_ENDPOINT_XFER_ISOC:
  259. if (strstr(ep->ep.name, "-bulk")
  260. || strstr(ep->ep.name, "-int"))
  261. goto done;
  262. switch (dev->gadget.speed) {
  263. case USB_SPEED_HIGH:
  264. if (max <= 1024)
  265. break;
  266. case USB_SPEED_FULL:
  267. if (max <= 1023)
  268. break;
  269. default:
  270. goto done;
  271. }
  272. /*
  273. * FIXME:
  274. * calculate transactions needed for high bandwidth iso
  275. */
  276. mult = (unsigned char)(1 + ((max >> 11) & 0x03));
  277. max = max & 0x8ff; /* bit 0~10 */
  278. /* 3 transactions at most */
  279. if (mult > 3)
  280. goto done;
  281. break;
  282. default:
  283. goto done;
  284. }
  285. spin_lock_irqsave(&dev->lock, flags);
  286. ep->ep.maxpacket = max;
  287. ep->desc = desc;
  288. ep->stopped = 0;
  289. ep->ep_num = usb_endpoint_num(desc);
  290. /* ep_type */
  291. ep->ep_type = usb_endpoint_type(desc);
  292. /* configure endpoint control registers */
  293. ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type);
  294. /* configure endpoint capabilities in dQH */
  295. i = ep->ep_num * 2 + is_in(ep);
  296. ep->dqh = &dev->ep_dqh[i];
  297. ep->dqh->dqh_ios = ios;
  298. ep->dqh->dqh_mpl = cpu_to_le16(max);
  299. ep->dqh->dqh_zlt = zlt;
  300. ep->dqh->dqh_mult = mult;
  301. ep->dqh->dtd_next = DTD_TERM;
  302. dev_dbg(&dev->pdev->dev, "enabled %s (ep%d%s-%s), max %04x\n",
  303. _ep->name,
  304. ep->ep_num,
  305. DIR_STRING(ep),
  306. type_string(desc),
  307. max);
  308. spin_unlock_irqrestore(&dev->lock, flags);
  309. done:
  310. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  311. return retval;
  312. }
  313. /*-------------------------------------------------------------------------*/
  314. /* retire a request */
  315. static void done(struct langwell_ep *ep, struct langwell_request *req,
  316. int status)
  317. {
  318. struct langwell_udc *dev = ep->dev;
  319. unsigned stopped = ep->stopped;
  320. struct langwell_dtd *curr_dtd, *next_dtd;
  321. int i;
  322. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  323. /* remove the req from ep->queue */
  324. list_del_init(&req->queue);
  325. if (req->req.status == -EINPROGRESS)
  326. req->req.status = status;
  327. else
  328. status = req->req.status;
  329. /* free dTD for the request */
  330. next_dtd = req->head;
  331. for (i = 0; i < req->dtd_count; i++) {
  332. curr_dtd = next_dtd;
  333. if (i != req->dtd_count - 1)
  334. next_dtd = curr_dtd->next_dtd_virt;
  335. dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma);
  336. }
  337. usb_gadget_unmap_request(&dev->gadget, &req->req, is_in(ep));
  338. if (status != -ESHUTDOWN)
  339. dev_dbg(&dev->pdev->dev,
  340. "complete %s, req %p, stat %d, len %u/%u\n",
  341. ep->ep.name, &req->req, status,
  342. req->req.actual, req->req.length);
  343. /* don't modify queue heads during completion callback */
  344. ep->stopped = 1;
  345. spin_unlock(&dev->lock);
  346. /* complete routine from gadget driver */
  347. if (req->req.complete)
  348. req->req.complete(&ep->ep, &req->req);
  349. spin_lock(&dev->lock);
  350. ep->stopped = stopped;
  351. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  352. }
  353. static void langwell_ep_fifo_flush(struct usb_ep *_ep);
  354. /* delete all endpoint requests, called with spinlock held */
  355. static void nuke(struct langwell_ep *ep, int status)
  356. {
  357. /* called with spinlock held */
  358. ep->stopped = 1;
  359. /* endpoint fifo flush */
  360. if (&ep->ep && ep->desc)
  361. langwell_ep_fifo_flush(&ep->ep);
  362. while (!list_empty(&ep->queue)) {
  363. struct langwell_request *req = NULL;
  364. req = list_entry(ep->queue.next, struct langwell_request,
  365. queue);
  366. done(ep, req, status);
  367. }
  368. }
  369. /*-------------------------------------------------------------------------*/
  370. /* endpoint is no longer usable */
  371. static int langwell_ep_disable(struct usb_ep *_ep)
  372. {
  373. struct langwell_ep *ep;
  374. unsigned long flags;
  375. struct langwell_udc *dev;
  376. int ep_num;
  377. u32 endptctrl;
  378. ep = container_of(_ep, struct langwell_ep, ep);
  379. dev = ep->dev;
  380. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  381. if (!_ep || !ep->desc)
  382. return -EINVAL;
  383. spin_lock_irqsave(&dev->lock, flags);
  384. /* disable endpoint control register */
  385. ep_num = ep->ep_num;
  386. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  387. if (is_in(ep))
  388. endptctrl &= ~EPCTRL_TXE;
  389. else
  390. endptctrl &= ~EPCTRL_RXE;
  391. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  392. /* nuke all pending requests (does flush) */
  393. nuke(ep, -ESHUTDOWN);
  394. ep->desc = NULL;
  395. ep->ep.desc = NULL;
  396. ep->stopped = 1;
  397. spin_unlock_irqrestore(&dev->lock, flags);
  398. dev_dbg(&dev->pdev->dev, "disabled %s\n", _ep->name);
  399. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  400. return 0;
  401. }
  402. /* allocate a request object to use with this endpoint */
  403. static struct usb_request *langwell_alloc_request(struct usb_ep *_ep,
  404. gfp_t gfp_flags)
  405. {
  406. struct langwell_ep *ep;
  407. struct langwell_udc *dev;
  408. struct langwell_request *req = NULL;
  409. if (!_ep)
  410. return NULL;
  411. ep = container_of(_ep, struct langwell_ep, ep);
  412. dev = ep->dev;
  413. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  414. req = kzalloc(sizeof(*req), gfp_flags);
  415. if (!req)
  416. return NULL;
  417. req->req.dma = DMA_ADDR_INVALID;
  418. INIT_LIST_HEAD(&req->queue);
  419. dev_vdbg(&dev->pdev->dev, "alloc request for %s\n", _ep->name);
  420. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  421. return &req->req;
  422. }
  423. /* free a request object */
  424. static void langwell_free_request(struct usb_ep *_ep,
  425. struct usb_request *_req)
  426. {
  427. struct langwell_ep *ep;
  428. struct langwell_udc *dev;
  429. struct langwell_request *req = NULL;
  430. ep = container_of(_ep, struct langwell_ep, ep);
  431. dev = ep->dev;
  432. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  433. if (!_ep || !_req)
  434. return;
  435. req = container_of(_req, struct langwell_request, req);
  436. WARN_ON(!list_empty(&req->queue));
  437. if (_req)
  438. kfree(req);
  439. dev_vdbg(&dev->pdev->dev, "free request for %s\n", _ep->name);
  440. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  441. }
  442. /*-------------------------------------------------------------------------*/
  443. /* queue dTD and PRIME endpoint */
  444. static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req)
  445. {
  446. u32 bit_mask, usbcmd, endptstat, dtd_dma;
  447. u8 dtd_status;
  448. int i;
  449. struct langwell_dqh *dqh;
  450. struct langwell_udc *dev;
  451. dev = ep->dev;
  452. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  453. i = ep->ep_num * 2 + is_in(ep);
  454. dqh = &dev->ep_dqh[i];
  455. if (ep->ep_num)
  456. dev_vdbg(&dev->pdev->dev, "%s\n", ep->name);
  457. else
  458. /* ep0 */
  459. dev_vdbg(&dev->pdev->dev, "%s-%s\n", ep->name, DIR_STRING(ep));
  460. dev_vdbg(&dev->pdev->dev, "ep_dqh[%d] addr: 0x%p\n",
  461. i, &(dev->ep_dqh[i]));
  462. bit_mask = is_in(ep) ?
  463. (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num));
  464. dev_vdbg(&dev->pdev->dev, "bit_mask = 0x%08x\n", bit_mask);
  465. /* check if the pipe is empty */
  466. if (!(list_empty(&ep->queue))) {
  467. /* add dTD to the end of linked list */
  468. struct langwell_request *lastreq;
  469. lastreq = list_entry(ep->queue.prev,
  470. struct langwell_request, queue);
  471. lastreq->tail->dtd_next =
  472. cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK);
  473. /* read prime bit, if 1 goto out */
  474. if (readl(&dev->op_regs->endptprime) & bit_mask)
  475. goto out;
  476. do {
  477. /* set ATDTW bit in USBCMD */
  478. usbcmd = readl(&dev->op_regs->usbcmd);
  479. writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd);
  480. /* read correct status bit */
  481. endptstat = readl(&dev->op_regs->endptstat) & bit_mask;
  482. } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW));
  483. /* write ATDTW bit to 0 */
  484. usbcmd = readl(&dev->op_regs->usbcmd);
  485. writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd);
  486. if (endptstat)
  487. goto out;
  488. }
  489. /* write dQH next pointer and terminate bit to 0 */
  490. dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK;
  491. dqh->dtd_next = cpu_to_le32(dtd_dma);
  492. /* clear active and halt bit */
  493. dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED);
  494. dqh->dtd_status &= dtd_status;
  495. dev_vdbg(&dev->pdev->dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status);
  496. /* ensure that updates to the dQH will occur before priming */
  497. wmb();
  498. /* write 1 to endptprime register to PRIME endpoint */
  499. bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num);
  500. dev_vdbg(&dev->pdev->dev, "endprime bit_mask = 0x%08x\n", bit_mask);
  501. writel(bit_mask, &dev->op_regs->endptprime);
  502. out:
  503. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  504. return 0;
  505. }
  506. /* fill in the dTD structure to build a transfer descriptor */
  507. static struct langwell_dtd *build_dtd(struct langwell_request *req,
  508. unsigned *length, dma_addr_t *dma, int *is_last)
  509. {
  510. u32 buf_ptr;
  511. struct langwell_dtd *dtd;
  512. struct langwell_udc *dev;
  513. int i;
  514. dev = req->ep->dev;
  515. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  516. /* the maximum transfer length, up to 16k bytes */
  517. *length = min(req->req.length - req->req.actual,
  518. (unsigned)DTD_MAX_TRANSFER_LENGTH);
  519. /* create dTD dma_pool resource */
  520. dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma);
  521. if (dtd == NULL)
  522. return dtd;
  523. dtd->dtd_dma = *dma;
  524. /* initialize buffer page pointers */
  525. buf_ptr = (u32)(req->req.dma + req->req.actual);
  526. for (i = 0; i < 5; i++)
  527. dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE);
  528. req->req.actual += *length;
  529. /* fill in total bytes with transfer size */
  530. dtd->dtd_total = cpu_to_le16(*length);
  531. dev_vdbg(&dev->pdev->dev, "dtd->dtd_total = %d\n", dtd->dtd_total);
  532. /* set is_last flag if req->req.zero is set or not */
  533. if (req->req.zero) {
  534. if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
  535. *is_last = 1;
  536. else
  537. *is_last = 0;
  538. } else if (req->req.length == req->req.actual) {
  539. *is_last = 1;
  540. } else
  541. *is_last = 0;
  542. if (*is_last == 0)
  543. dev_vdbg(&dev->pdev->dev, "multi-dtd request!\n");
  544. /* set interrupt on complete bit for the last dTD */
  545. if (*is_last && !req->req.no_interrupt)
  546. dtd->dtd_ioc = 1;
  547. /* set multiplier override 0 for non-ISO and non-TX endpoint */
  548. dtd->dtd_multo = 0;
  549. /* set the active bit of status field to 1 */
  550. dtd->dtd_status = DTD_STS_ACTIVE;
  551. dev_vdbg(&dev->pdev->dev, "dtd->dtd_status = 0x%02x\n",
  552. dtd->dtd_status);
  553. dev_vdbg(&dev->pdev->dev, "length = %d, dma addr= 0x%08x\n",
  554. *length, (int)*dma);
  555. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  556. return dtd;
  557. }
  558. /* generate dTD linked list for a request */
  559. static int req_to_dtd(struct langwell_request *req)
  560. {
  561. unsigned count;
  562. int is_last, is_first = 1;
  563. struct langwell_dtd *dtd, *last_dtd = NULL;
  564. struct langwell_udc *dev;
  565. dma_addr_t dma;
  566. dev = req->ep->dev;
  567. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  568. do {
  569. dtd = build_dtd(req, &count, &dma, &is_last);
  570. if (dtd == NULL)
  571. return -ENOMEM;
  572. if (is_first) {
  573. is_first = 0;
  574. req->head = dtd;
  575. } else {
  576. last_dtd->dtd_next = cpu_to_le32(dma);
  577. last_dtd->next_dtd_virt = dtd;
  578. }
  579. last_dtd = dtd;
  580. req->dtd_count++;
  581. } while (!is_last);
  582. /* set terminate bit to 1 for the last dTD */
  583. dtd->dtd_next = DTD_TERM;
  584. req->tail = dtd;
  585. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  586. return 0;
  587. }
  588. /*-------------------------------------------------------------------------*/
  589. /* queue (submits) an I/O requests to an endpoint */
  590. static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
  591. gfp_t gfp_flags)
  592. {
  593. struct langwell_request *req;
  594. struct langwell_ep *ep;
  595. struct langwell_udc *dev;
  596. unsigned long flags;
  597. int is_iso = 0;
  598. int ret;
  599. /* always require a cpu-view buffer */
  600. req = container_of(_req, struct langwell_request, req);
  601. ep = container_of(_ep, struct langwell_ep, ep);
  602. if (!_req || !_req->complete || !_req->buf
  603. || !list_empty(&req->queue)) {
  604. return -EINVAL;
  605. }
  606. if (unlikely(!_ep || !ep->desc))
  607. return -EINVAL;
  608. dev = ep->dev;
  609. req->ep = ep;
  610. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  611. if (usb_endpoint_xfer_isoc(ep->desc)) {
  612. if (req->req.length > ep->ep.maxpacket)
  613. return -EMSGSIZE;
  614. is_iso = 1;
  615. }
  616. if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN))
  617. return -ESHUTDOWN;
  618. /* set up dma mapping */
  619. ret = usb_gadget_map_request(&dev->gadget, &req->req, is_in(ep));
  620. if (ret)
  621. return ret;
  622. dev_dbg(&dev->pdev->dev,
  623. "%s queue req %p, len %u, buf %p, dma 0x%08x\n",
  624. _ep->name,
  625. _req, _req->length, _req->buf, (int)_req->dma);
  626. _req->status = -EINPROGRESS;
  627. _req->actual = 0;
  628. req->dtd_count = 0;
  629. spin_lock_irqsave(&dev->lock, flags);
  630. /* build and put dTDs to endpoint queue */
  631. if (!req_to_dtd(req)) {
  632. queue_dtd(ep, req);
  633. } else {
  634. spin_unlock_irqrestore(&dev->lock, flags);
  635. return -ENOMEM;
  636. }
  637. /* update ep0 state */
  638. if (ep->ep_num == 0)
  639. dev->ep0_state = DATA_STATE_XMIT;
  640. if (likely(req != NULL)) {
  641. list_add_tail(&req->queue, &ep->queue);
  642. dev_vdbg(&dev->pdev->dev, "list_add_tail()\n");
  643. }
  644. spin_unlock_irqrestore(&dev->lock, flags);
  645. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  646. return 0;
  647. }
  648. /* dequeue (cancels, unlinks) an I/O request from an endpoint */
  649. static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  650. {
  651. struct langwell_ep *ep;
  652. struct langwell_udc *dev;
  653. struct langwell_request *req;
  654. unsigned long flags;
  655. int stopped, ep_num, retval = 0;
  656. u32 endptctrl;
  657. ep = container_of(_ep, struct langwell_ep, ep);
  658. dev = ep->dev;
  659. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  660. if (!_ep || !ep->desc || !_req)
  661. return -EINVAL;
  662. if (!dev->driver)
  663. return -ESHUTDOWN;
  664. spin_lock_irqsave(&dev->lock, flags);
  665. stopped = ep->stopped;
  666. /* quiesce dma while we patch the queue */
  667. ep->stopped = 1;
  668. ep_num = ep->ep_num;
  669. /* disable endpoint control register */
  670. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  671. if (is_in(ep))
  672. endptctrl &= ~EPCTRL_TXE;
  673. else
  674. endptctrl &= ~EPCTRL_RXE;
  675. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  676. /* make sure it's still queued on this endpoint */
  677. list_for_each_entry(req, &ep->queue, queue) {
  678. if (&req->req == _req)
  679. break;
  680. }
  681. if (&req->req != _req) {
  682. retval = -EINVAL;
  683. goto done;
  684. }
  685. /* queue head may be partially complete. */
  686. if (ep->queue.next == &req->queue) {
  687. dev_dbg(&dev->pdev->dev, "unlink (%s) dma\n", _ep->name);
  688. _req->status = -ECONNRESET;
  689. langwell_ep_fifo_flush(&ep->ep);
  690. /* not the last request in endpoint queue */
  691. if (likely(ep->queue.next == &req->queue)) {
  692. struct langwell_dqh *dqh;
  693. struct langwell_request *next_req;
  694. dqh = ep->dqh;
  695. next_req = list_entry(req->queue.next,
  696. struct langwell_request, queue);
  697. /* point the dQH to the first dTD of next request */
  698. writel((u32) next_req->head, &dqh->dqh_current);
  699. }
  700. } else {
  701. struct langwell_request *prev_req;
  702. prev_req = list_entry(req->queue.prev,
  703. struct langwell_request, queue);
  704. writel(readl(&req->tail->dtd_next),
  705. &prev_req->tail->dtd_next);
  706. }
  707. done(ep, req, -ECONNRESET);
  708. done:
  709. /* enable endpoint again */
  710. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  711. if (is_in(ep))
  712. endptctrl |= EPCTRL_TXE;
  713. else
  714. endptctrl |= EPCTRL_RXE;
  715. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  716. ep->stopped = stopped;
  717. spin_unlock_irqrestore(&dev->lock, flags);
  718. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  719. return retval;
  720. }
  721. /*-------------------------------------------------------------------------*/
  722. /* endpoint set/clear halt */
  723. static void ep_set_halt(struct langwell_ep *ep, int value)
  724. {
  725. u32 endptctrl = 0;
  726. int ep_num;
  727. struct langwell_udc *dev = ep->dev;
  728. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  729. ep_num = ep->ep_num;
  730. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  731. /* value: 1 - set halt, 0 - clear halt */
  732. if (value) {
  733. /* set the stall bit */
  734. if (is_in(ep))
  735. endptctrl |= EPCTRL_TXS;
  736. else
  737. endptctrl |= EPCTRL_RXS;
  738. } else {
  739. /* clear the stall bit and reset data toggle */
  740. if (is_in(ep)) {
  741. endptctrl &= ~EPCTRL_TXS;
  742. endptctrl |= EPCTRL_TXR;
  743. } else {
  744. endptctrl &= ~EPCTRL_RXS;
  745. endptctrl |= EPCTRL_RXR;
  746. }
  747. }
  748. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  749. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  750. }
  751. /* set the endpoint halt feature */
  752. static int langwell_ep_set_halt(struct usb_ep *_ep, int value)
  753. {
  754. struct langwell_ep *ep;
  755. struct langwell_udc *dev;
  756. unsigned long flags;
  757. int retval = 0;
  758. ep = container_of(_ep, struct langwell_ep, ep);
  759. dev = ep->dev;
  760. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  761. if (!_ep || !ep->desc)
  762. return -EINVAL;
  763. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  764. return -ESHUTDOWN;
  765. if (usb_endpoint_xfer_isoc(ep->desc))
  766. return -EOPNOTSUPP;
  767. spin_lock_irqsave(&dev->lock, flags);
  768. /*
  769. * attempt to halt IN ep will fail if any transfer requests
  770. * are still queue
  771. */
  772. if (!list_empty(&ep->queue) && is_in(ep) && value) {
  773. /* IN endpoint FIFO holds bytes */
  774. dev_dbg(&dev->pdev->dev, "%s FIFO holds bytes\n", _ep->name);
  775. retval = -EAGAIN;
  776. goto done;
  777. }
  778. /* endpoint set/clear halt */
  779. if (ep->ep_num) {
  780. ep_set_halt(ep, value);
  781. } else { /* endpoint 0 */
  782. dev->ep0_state = WAIT_FOR_SETUP;
  783. dev->ep0_dir = USB_DIR_OUT;
  784. }
  785. done:
  786. spin_unlock_irqrestore(&dev->lock, flags);
  787. dev_dbg(&dev->pdev->dev, "%s %s halt\n",
  788. _ep->name, value ? "set" : "clear");
  789. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  790. return retval;
  791. }
  792. /* set the halt feature and ignores clear requests */
  793. static int langwell_ep_set_wedge(struct usb_ep *_ep)
  794. {
  795. struct langwell_ep *ep;
  796. struct langwell_udc *dev;
  797. ep = container_of(_ep, struct langwell_ep, ep);
  798. dev = ep->dev;
  799. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  800. if (!_ep || !ep->desc)
  801. return -EINVAL;
  802. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  803. return usb_ep_set_halt(_ep);
  804. }
  805. /* flush contents of a fifo */
  806. static void langwell_ep_fifo_flush(struct usb_ep *_ep)
  807. {
  808. struct langwell_ep *ep;
  809. struct langwell_udc *dev;
  810. u32 flush_bit;
  811. unsigned long timeout;
  812. ep = container_of(_ep, struct langwell_ep, ep);
  813. dev = ep->dev;
  814. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  815. if (!_ep || !ep->desc) {
  816. dev_vdbg(&dev->pdev->dev, "ep or ep->desc is NULL\n");
  817. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  818. return;
  819. }
  820. dev_vdbg(&dev->pdev->dev, "%s-%s fifo flush\n",
  821. _ep->name, DIR_STRING(ep));
  822. /* flush endpoint buffer */
  823. if (ep->ep_num == 0)
  824. flush_bit = (1 << 16) | 1;
  825. else if (is_in(ep))
  826. flush_bit = 1 << (ep->ep_num + 16); /* TX */
  827. else
  828. flush_bit = 1 << ep->ep_num; /* RX */
  829. /* wait until flush complete */
  830. timeout = jiffies + FLUSH_TIMEOUT;
  831. do {
  832. writel(flush_bit, &dev->op_regs->endptflush);
  833. while (readl(&dev->op_regs->endptflush)) {
  834. if (time_after(jiffies, timeout)) {
  835. dev_err(&dev->pdev->dev, "ep flush timeout\n");
  836. goto done;
  837. }
  838. cpu_relax();
  839. }
  840. } while (readl(&dev->op_regs->endptstat) & flush_bit);
  841. done:
  842. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  843. }
  844. /* endpoints operations structure */
  845. static const struct usb_ep_ops langwell_ep_ops = {
  846. /* configure endpoint, making it usable */
  847. .enable = langwell_ep_enable,
  848. /* endpoint is no longer usable */
  849. .disable = langwell_ep_disable,
  850. /* allocate a request object to use with this endpoint */
  851. .alloc_request = langwell_alloc_request,
  852. /* free a request object */
  853. .free_request = langwell_free_request,
  854. /* queue (submits) an I/O requests to an endpoint */
  855. .queue = langwell_ep_queue,
  856. /* dequeue (cancels, unlinks) an I/O request from an endpoint */
  857. .dequeue = langwell_ep_dequeue,
  858. /* set the endpoint halt feature */
  859. .set_halt = langwell_ep_set_halt,
  860. /* set the halt feature and ignores clear requests */
  861. .set_wedge = langwell_ep_set_wedge,
  862. /* flush contents of a fifo */
  863. .fifo_flush = langwell_ep_fifo_flush,
  864. };
  865. /*-------------------------------------------------------------------------*/
  866. /* device controller usb_gadget_ops structure */
  867. /* returns the current frame number */
  868. static int langwell_get_frame(struct usb_gadget *_gadget)
  869. {
  870. struct langwell_udc *dev;
  871. u16 retval;
  872. if (!_gadget)
  873. return -ENODEV;
  874. dev = container_of(_gadget, struct langwell_udc, gadget);
  875. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  876. retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK;
  877. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  878. return retval;
  879. }
  880. /* enter or exit PHY low power state */
  881. static void langwell_phy_low_power(struct langwell_udc *dev, bool flag)
  882. {
  883. u32 devlc;
  884. u8 devlc_byte2;
  885. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  886. devlc = readl(&dev->op_regs->devlc);
  887. dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
  888. if (flag)
  889. devlc |= LPM_PHCD;
  890. else
  891. devlc &= ~LPM_PHCD;
  892. /* FIXME: workaround for Langwell A1/A2/A3 sighting */
  893. devlc_byte2 = (devlc >> 16) & 0xff;
  894. writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
  895. devlc = readl(&dev->op_regs->devlc);
  896. dev_vdbg(&dev->pdev->dev,
  897. "%s PHY low power suspend, devlc = 0x%08x\n",
  898. flag ? "enter" : "exit", devlc);
  899. }
  900. /* tries to wake up the host connected to this gadget */
  901. static int langwell_wakeup(struct usb_gadget *_gadget)
  902. {
  903. struct langwell_udc *dev;
  904. u32 portsc1;
  905. unsigned long flags;
  906. if (!_gadget)
  907. return 0;
  908. dev = container_of(_gadget, struct langwell_udc, gadget);
  909. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  910. /* remote wakeup feature not enabled by host */
  911. if (!dev->remote_wakeup) {
  912. dev_info(&dev->pdev->dev, "remote wakeup is disabled\n");
  913. return -ENOTSUPP;
  914. }
  915. spin_lock_irqsave(&dev->lock, flags);
  916. portsc1 = readl(&dev->op_regs->portsc1);
  917. if (!(portsc1 & PORTS_SUSP)) {
  918. spin_unlock_irqrestore(&dev->lock, flags);
  919. return 0;
  920. }
  921. /* LPM L1 to L0 or legacy remote wakeup */
  922. if (dev->lpm && dev->lpm_state == LPM_L1)
  923. dev_info(&dev->pdev->dev, "LPM L1 to L0 remote wakeup\n");
  924. else
  925. dev_info(&dev->pdev->dev, "device remote wakeup\n");
  926. /* exit PHY low power suspend */
  927. if (dev->pdev->device != 0x0829)
  928. langwell_phy_low_power(dev, 0);
  929. /* force port resume */
  930. portsc1 |= PORTS_FPR;
  931. writel(portsc1, &dev->op_regs->portsc1);
  932. spin_unlock_irqrestore(&dev->lock, flags);
  933. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  934. return 0;
  935. }
  936. /* notify controller that VBUS is powered or not */
  937. static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active)
  938. {
  939. struct langwell_udc *dev;
  940. unsigned long flags;
  941. u32 usbcmd;
  942. if (!_gadget)
  943. return -ENODEV;
  944. dev = container_of(_gadget, struct langwell_udc, gadget);
  945. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  946. spin_lock_irqsave(&dev->lock, flags);
  947. dev_vdbg(&dev->pdev->dev, "VBUS status: %s\n",
  948. is_active ? "on" : "off");
  949. dev->vbus_active = (is_active != 0);
  950. if (dev->driver && dev->softconnected && dev->vbus_active) {
  951. usbcmd = readl(&dev->op_regs->usbcmd);
  952. usbcmd |= CMD_RUNSTOP;
  953. writel(usbcmd, &dev->op_regs->usbcmd);
  954. } else {
  955. usbcmd = readl(&dev->op_regs->usbcmd);
  956. usbcmd &= ~CMD_RUNSTOP;
  957. writel(usbcmd, &dev->op_regs->usbcmd);
  958. }
  959. spin_unlock_irqrestore(&dev->lock, flags);
  960. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  961. return 0;
  962. }
  963. /* constrain controller's VBUS power usage */
  964. static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  965. {
  966. struct langwell_udc *dev;
  967. if (!_gadget)
  968. return -ENODEV;
  969. dev = container_of(_gadget, struct langwell_udc, gadget);
  970. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  971. if (dev->transceiver) {
  972. dev_vdbg(&dev->pdev->dev, "usb_phy_set_power\n");
  973. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  974. return usb_phy_set_power(dev->transceiver, mA);
  975. }
  976. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  977. return -ENOTSUPP;
  978. }
  979. /* D+ pullup, software-controlled connect/disconnect to USB host */
  980. static int langwell_pullup(struct usb_gadget *_gadget, int is_on)
  981. {
  982. struct langwell_udc *dev;
  983. u32 usbcmd;
  984. unsigned long flags;
  985. if (!_gadget)
  986. return -ENODEV;
  987. dev = container_of(_gadget, struct langwell_udc, gadget);
  988. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  989. spin_lock_irqsave(&dev->lock, flags);
  990. dev->softconnected = (is_on != 0);
  991. if (dev->driver && dev->softconnected && dev->vbus_active) {
  992. usbcmd = readl(&dev->op_regs->usbcmd);
  993. usbcmd |= CMD_RUNSTOP;
  994. writel(usbcmd, &dev->op_regs->usbcmd);
  995. } else {
  996. usbcmd = readl(&dev->op_regs->usbcmd);
  997. usbcmd &= ~CMD_RUNSTOP;
  998. writel(usbcmd, &dev->op_regs->usbcmd);
  999. }
  1000. spin_unlock_irqrestore(&dev->lock, flags);
  1001. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1002. return 0;
  1003. }
  1004. static int langwell_start(struct usb_gadget *g,
  1005. struct usb_gadget_driver *driver);
  1006. static int langwell_stop(struct usb_gadget *g,
  1007. struct usb_gadget_driver *driver);
  1008. /* device controller usb_gadget_ops structure */
  1009. static const struct usb_gadget_ops langwell_ops = {
  1010. /* returns the current frame number */
  1011. .get_frame = langwell_get_frame,
  1012. /* tries to wake up the host connected to this gadget */
  1013. .wakeup = langwell_wakeup,
  1014. /* set the device selfpowered feature, always selfpowered */
  1015. /* .set_selfpowered = langwell_set_selfpowered, */
  1016. /* notify controller that VBUS is powered or not */
  1017. .vbus_session = langwell_vbus_session,
  1018. /* constrain controller's VBUS power usage */
  1019. .vbus_draw = langwell_vbus_draw,
  1020. /* D+ pullup, software-controlled connect/disconnect to USB host */
  1021. .pullup = langwell_pullup,
  1022. .udc_start = langwell_start,
  1023. .udc_stop = langwell_stop,
  1024. };
  1025. /*-------------------------------------------------------------------------*/
  1026. /* device controller operations */
  1027. /* reset device controller */
  1028. static int langwell_udc_reset(struct langwell_udc *dev)
  1029. {
  1030. u32 usbcmd, usbmode, devlc, endpointlistaddr;
  1031. u8 devlc_byte0, devlc_byte2;
  1032. unsigned long timeout;
  1033. if (!dev)
  1034. return -EINVAL;
  1035. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1036. /* set controller to stop state */
  1037. usbcmd = readl(&dev->op_regs->usbcmd);
  1038. usbcmd &= ~CMD_RUNSTOP;
  1039. writel(usbcmd, &dev->op_regs->usbcmd);
  1040. /* reset device controller */
  1041. usbcmd = readl(&dev->op_regs->usbcmd);
  1042. usbcmd |= CMD_RST;
  1043. writel(usbcmd, &dev->op_regs->usbcmd);
  1044. /* wait for reset to complete */
  1045. timeout = jiffies + RESET_TIMEOUT;
  1046. while (readl(&dev->op_regs->usbcmd) & CMD_RST) {
  1047. if (time_after(jiffies, timeout)) {
  1048. dev_err(&dev->pdev->dev, "device reset timeout\n");
  1049. return -ETIMEDOUT;
  1050. }
  1051. cpu_relax();
  1052. }
  1053. /* set controller to device mode */
  1054. usbmode = readl(&dev->op_regs->usbmode);
  1055. usbmode |= MODE_DEVICE;
  1056. /* turn setup lockout off, require setup tripwire in usbcmd */
  1057. usbmode |= MODE_SLOM;
  1058. writel(usbmode, &dev->op_regs->usbmode);
  1059. usbmode = readl(&dev->op_regs->usbmode);
  1060. dev_vdbg(&dev->pdev->dev, "usbmode=0x%08x\n", usbmode);
  1061. /* Write-Clear setup status */
  1062. writel(0, &dev->op_regs->usbsts);
  1063. /* if support USB LPM, ACK all LPM token */
  1064. if (dev->lpm) {
  1065. devlc = readl(&dev->op_regs->devlc);
  1066. dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
  1067. /* FIXME: workaround for Langwell A1/A2/A3 sighting */
  1068. devlc &= ~LPM_STL; /* don't STALL LPM token */
  1069. devlc &= ~LPM_NYT_ACK; /* ACK LPM token */
  1070. devlc_byte0 = devlc & 0xff;
  1071. devlc_byte2 = (devlc >> 16) & 0xff;
  1072. writeb(devlc_byte0, (u8 *)&dev->op_regs->devlc);
  1073. writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
  1074. devlc = readl(&dev->op_regs->devlc);
  1075. dev_vdbg(&dev->pdev->dev,
  1076. "ACK LPM token, devlc = 0x%08x\n", devlc);
  1077. }
  1078. /* fill endpointlistaddr register */
  1079. endpointlistaddr = dev->ep_dqh_dma;
  1080. endpointlistaddr &= ENDPOINTLISTADDR_MASK;
  1081. writel(endpointlistaddr, &dev->op_regs->endpointlistaddr);
  1082. dev_vdbg(&dev->pdev->dev,
  1083. "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n",
  1084. dev->ep_dqh, endpointlistaddr,
  1085. readl(&dev->op_regs->endpointlistaddr));
  1086. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1087. return 0;
  1088. }
  1089. /* reinitialize device controller endpoints */
  1090. static int eps_reinit(struct langwell_udc *dev)
  1091. {
  1092. struct langwell_ep *ep;
  1093. char name[14];
  1094. int i;
  1095. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1096. /* initialize ep0 */
  1097. ep = &dev->ep[0];
  1098. ep->dev = dev;
  1099. strncpy(ep->name, "ep0", sizeof(ep->name));
  1100. ep->ep.name = ep->name;
  1101. ep->ep.ops = &langwell_ep_ops;
  1102. ep->stopped = 0;
  1103. ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
  1104. ep->ep_num = 0;
  1105. ep->desc = &langwell_ep0_desc;
  1106. INIT_LIST_HEAD(&ep->queue);
  1107. ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
  1108. /* initialize other endpoints */
  1109. for (i = 2; i < dev->ep_max; i++) {
  1110. ep = &dev->ep[i];
  1111. if (i % 2)
  1112. snprintf(name, sizeof(name), "ep%din", i / 2);
  1113. else
  1114. snprintf(name, sizeof(name), "ep%dout", i / 2);
  1115. ep->dev = dev;
  1116. strncpy(ep->name, name, sizeof(ep->name));
  1117. ep->ep.name = ep->name;
  1118. ep->ep.ops = &langwell_ep_ops;
  1119. ep->stopped = 0;
  1120. ep->ep.maxpacket = (unsigned short) ~0;
  1121. ep->ep_num = i / 2;
  1122. INIT_LIST_HEAD(&ep->queue);
  1123. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  1124. }
  1125. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1126. return 0;
  1127. }
  1128. /* enable interrupt and set controller to run state */
  1129. static void langwell_udc_start(struct langwell_udc *dev)
  1130. {
  1131. u32 usbintr, usbcmd;
  1132. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1133. /* enable interrupts */
  1134. usbintr = INTR_ULPIE /* ULPI */
  1135. | INTR_SLE /* suspend */
  1136. /* | INTR_SRE SOF received */
  1137. | INTR_URE /* USB reset */
  1138. | INTR_AAE /* async advance */
  1139. | INTR_SEE /* system error */
  1140. | INTR_FRE /* frame list rollover */
  1141. | INTR_PCE /* port change detect */
  1142. | INTR_UEE /* USB error interrupt */
  1143. | INTR_UE; /* USB interrupt */
  1144. writel(usbintr, &dev->op_regs->usbintr);
  1145. /* clear stopped bit */
  1146. dev->stopped = 0;
  1147. /* set controller to run */
  1148. usbcmd = readl(&dev->op_regs->usbcmd);
  1149. usbcmd |= CMD_RUNSTOP;
  1150. writel(usbcmd, &dev->op_regs->usbcmd);
  1151. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1152. }
  1153. /* disable interrupt and set controller to stop state */
  1154. static void langwell_udc_stop(struct langwell_udc *dev)
  1155. {
  1156. u32 usbcmd;
  1157. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1158. /* disable all interrupts */
  1159. writel(0, &dev->op_regs->usbintr);
  1160. /* set stopped bit */
  1161. dev->stopped = 1;
  1162. /* set controller to stop state */
  1163. usbcmd = readl(&dev->op_regs->usbcmd);
  1164. usbcmd &= ~CMD_RUNSTOP;
  1165. writel(usbcmd, &dev->op_regs->usbcmd);
  1166. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1167. }
  1168. /* stop all USB activities */
  1169. static void stop_activity(struct langwell_udc *dev)
  1170. {
  1171. struct langwell_ep *ep;
  1172. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1173. nuke(&dev->ep[0], -ESHUTDOWN);
  1174. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1175. nuke(ep, -ESHUTDOWN);
  1176. }
  1177. /* report disconnect; the driver is already quiesced */
  1178. if (dev->driver) {
  1179. spin_unlock(&dev->lock);
  1180. dev->driver->disconnect(&dev->gadget);
  1181. spin_lock(&dev->lock);
  1182. }
  1183. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1184. }
  1185. /*-------------------------------------------------------------------------*/
  1186. /* device "function" sysfs attribute file */
  1187. static ssize_t show_function(struct device *_dev,
  1188. struct device_attribute *attr, char *buf)
  1189. {
  1190. struct langwell_udc *dev = dev_get_drvdata(_dev);
  1191. if (!dev->driver || !dev->driver->function
  1192. || strlen(dev->driver->function) > PAGE_SIZE)
  1193. return 0;
  1194. return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
  1195. }
  1196. static DEVICE_ATTR(function, S_IRUGO, show_function, NULL);
  1197. static inline enum usb_device_speed lpm_device_speed(u32 reg)
  1198. {
  1199. switch (LPM_PSPD(reg)) {
  1200. case LPM_SPEED_HIGH:
  1201. return USB_SPEED_HIGH;
  1202. case LPM_SPEED_FULL:
  1203. return USB_SPEED_FULL;
  1204. case LPM_SPEED_LOW:
  1205. return USB_SPEED_LOW;
  1206. default:
  1207. return USB_SPEED_UNKNOWN;
  1208. }
  1209. }
  1210. /* device "langwell_udc" sysfs attribute file */
  1211. static ssize_t show_langwell_udc(struct device *_dev,
  1212. struct device_attribute *attr, char *buf)
  1213. {
  1214. struct langwell_udc *dev = dev_get_drvdata(_dev);
  1215. struct langwell_request *req;
  1216. struct langwell_ep *ep = NULL;
  1217. char *next;
  1218. unsigned size;
  1219. unsigned t;
  1220. unsigned i;
  1221. unsigned long flags;
  1222. u32 tmp_reg;
  1223. next = buf;
  1224. size = PAGE_SIZE;
  1225. spin_lock_irqsave(&dev->lock, flags);
  1226. /* driver basic information */
  1227. t = scnprintf(next, size,
  1228. DRIVER_DESC "\n"
  1229. "%s version: %s\n"
  1230. "Gadget driver: %s\n\n",
  1231. driver_name, DRIVER_VERSION,
  1232. dev->driver ? dev->driver->driver.name : "(none)");
  1233. size -= t;
  1234. next += t;
  1235. /* device registers */
  1236. tmp_reg = readl(&dev->op_regs->usbcmd);
  1237. t = scnprintf(next, size,
  1238. "USBCMD reg:\n"
  1239. "SetupTW: %d\n"
  1240. "Run/Stop: %s\n\n",
  1241. (tmp_reg & CMD_SUTW) ? 1 : 0,
  1242. (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop");
  1243. size -= t;
  1244. next += t;
  1245. tmp_reg = readl(&dev->op_regs->usbsts);
  1246. t = scnprintf(next, size,
  1247. "USB Status Reg:\n"
  1248. "Device Suspend: %d\n"
  1249. "Reset Received: %d\n"
  1250. "System Error: %s\n"
  1251. "USB Error Interrupt: %s\n\n",
  1252. (tmp_reg & STS_SLI) ? 1 : 0,
  1253. (tmp_reg & STS_URI) ? 1 : 0,
  1254. (tmp_reg & STS_SEI) ? "Error" : "No error",
  1255. (tmp_reg & STS_UEI) ? "Error detected" : "No error");
  1256. size -= t;
  1257. next += t;
  1258. tmp_reg = readl(&dev->op_regs->usbintr);
  1259. t = scnprintf(next, size,
  1260. "USB Intrrupt Enable Reg:\n"
  1261. "Sleep Enable: %d\n"
  1262. "SOF Received Enable: %d\n"
  1263. "Reset Enable: %d\n"
  1264. "System Error Enable: %d\n"
  1265. "Port Change Dectected Enable: %d\n"
  1266. "USB Error Intr Enable: %d\n"
  1267. "USB Intr Enable: %d\n\n",
  1268. (tmp_reg & INTR_SLE) ? 1 : 0,
  1269. (tmp_reg & INTR_SRE) ? 1 : 0,
  1270. (tmp_reg & INTR_URE) ? 1 : 0,
  1271. (tmp_reg & INTR_SEE) ? 1 : 0,
  1272. (tmp_reg & INTR_PCE) ? 1 : 0,
  1273. (tmp_reg & INTR_UEE) ? 1 : 0,
  1274. (tmp_reg & INTR_UE) ? 1 : 0);
  1275. size -= t;
  1276. next += t;
  1277. tmp_reg = readl(&dev->op_regs->frindex);
  1278. t = scnprintf(next, size,
  1279. "USB Frame Index Reg:\n"
  1280. "Frame Number is 0x%08x\n\n",
  1281. (tmp_reg & FRINDEX_MASK));
  1282. size -= t;
  1283. next += t;
  1284. tmp_reg = readl(&dev->op_regs->deviceaddr);
  1285. t = scnprintf(next, size,
  1286. "USB Device Address Reg:\n"
  1287. "Device Addr is 0x%x\n\n",
  1288. USBADR(tmp_reg));
  1289. size -= t;
  1290. next += t;
  1291. tmp_reg = readl(&dev->op_regs->endpointlistaddr);
  1292. t = scnprintf(next, size,
  1293. "USB Endpoint List Address Reg:\n"
  1294. "Endpoint List Pointer is 0x%x\n\n",
  1295. EPBASE(tmp_reg));
  1296. size -= t;
  1297. next += t;
  1298. tmp_reg = readl(&dev->op_regs->portsc1);
  1299. t = scnprintf(next, size,
  1300. "USB Port Status & Control Reg:\n"
  1301. "Port Reset: %s\n"
  1302. "Port Suspend Mode: %s\n"
  1303. "Over-current Change: %s\n"
  1304. "Port Enable/Disable Change: %s\n"
  1305. "Port Enabled/Disabled: %s\n"
  1306. "Current Connect Status: %s\n"
  1307. "LPM Suspend Status: %s\n\n",
  1308. (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset",
  1309. (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend",
  1310. (tmp_reg & PORTS_OCC) ? "Detected" : "No",
  1311. (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed",
  1312. (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct",
  1313. (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached",
  1314. (tmp_reg & PORTS_SLP) ? "LPM L1" : "LPM L0");
  1315. size -= t;
  1316. next += t;
  1317. tmp_reg = readl(&dev->op_regs->devlc);
  1318. t = scnprintf(next, size,
  1319. "Device LPM Control Reg:\n"
  1320. "Parallel Transceiver : %d\n"
  1321. "Serial Transceiver : %d\n"
  1322. "Port Speed: %s\n"
  1323. "Port Force Full Speed Connenct: %s\n"
  1324. "PHY Low Power Suspend Clock: %s\n"
  1325. "BmAttributes: %d\n\n",
  1326. LPM_PTS(tmp_reg),
  1327. (tmp_reg & LPM_STS) ? 1 : 0,
  1328. usb_speed_string(lpm_device_speed(tmp_reg)),
  1329. (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force",
  1330. (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled",
  1331. LPM_BA(tmp_reg));
  1332. size -= t;
  1333. next += t;
  1334. tmp_reg = readl(&dev->op_regs->usbmode);
  1335. t = scnprintf(next, size,
  1336. "USB Mode Reg:\n"
  1337. "Controller Mode is : %s\n\n", ({
  1338. char *s;
  1339. switch (MODE_CM(tmp_reg)) {
  1340. case MODE_IDLE:
  1341. s = "Idle"; break;
  1342. case MODE_DEVICE:
  1343. s = "Device Controller"; break;
  1344. case MODE_HOST:
  1345. s = "Host Controller"; break;
  1346. default:
  1347. s = "None"; break;
  1348. }
  1349. s;
  1350. }));
  1351. size -= t;
  1352. next += t;
  1353. tmp_reg = readl(&dev->op_regs->endptsetupstat);
  1354. t = scnprintf(next, size,
  1355. "Endpoint Setup Status Reg:\n"
  1356. "SETUP on ep 0x%04x\n\n",
  1357. tmp_reg & SETUPSTAT_MASK);
  1358. size -= t;
  1359. next += t;
  1360. for (i = 0; i < dev->ep_max / 2; i++) {
  1361. tmp_reg = readl(&dev->op_regs->endptctrl[i]);
  1362. t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n",
  1363. i, tmp_reg);
  1364. size -= t;
  1365. next += t;
  1366. }
  1367. tmp_reg = readl(&dev->op_regs->endptprime);
  1368. t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg);
  1369. size -= t;
  1370. next += t;
  1371. /* langwell_udc, langwell_ep, langwell_request structure information */
  1372. ep = &dev->ep[0];
  1373. t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n",
  1374. ep->ep.name, ep->ep.maxpacket, ep->ep_num);
  1375. size -= t;
  1376. next += t;
  1377. if (list_empty(&ep->queue)) {
  1378. t = scnprintf(next, size, "its req queue is empty\n\n");
  1379. size -= t;
  1380. next += t;
  1381. } else {
  1382. list_for_each_entry(req, &ep->queue, queue) {
  1383. t = scnprintf(next, size,
  1384. "req %p actual 0x%x length 0x%x buf %p\n",
  1385. &req->req, req->req.actual,
  1386. req->req.length, req->req.buf);
  1387. size -= t;
  1388. next += t;
  1389. }
  1390. }
  1391. /* other gadget->eplist ep */
  1392. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1393. if (ep->desc) {
  1394. t = scnprintf(next, size,
  1395. "\n%s MaxPacketSize: 0x%x, "
  1396. "ep_num: %d\n",
  1397. ep->ep.name, ep->ep.maxpacket,
  1398. ep->ep_num);
  1399. size -= t;
  1400. next += t;
  1401. if (list_empty(&ep->queue)) {
  1402. t = scnprintf(next, size,
  1403. "its req queue is empty\n\n");
  1404. size -= t;
  1405. next += t;
  1406. } else {
  1407. list_for_each_entry(req, &ep->queue, queue) {
  1408. t = scnprintf(next, size,
  1409. "req %p actual 0x%x length "
  1410. "0x%x buf %p\n",
  1411. &req->req, req->req.actual,
  1412. req->req.length, req->req.buf);
  1413. size -= t;
  1414. next += t;
  1415. }
  1416. }
  1417. }
  1418. }
  1419. spin_unlock_irqrestore(&dev->lock, flags);
  1420. return PAGE_SIZE - size;
  1421. }
  1422. static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL);
  1423. /* device "remote_wakeup" sysfs attribute file */
  1424. static ssize_t store_remote_wakeup(struct device *_dev,
  1425. struct device_attribute *attr, const char *buf, size_t count)
  1426. {
  1427. struct langwell_udc *dev = dev_get_drvdata(_dev);
  1428. unsigned long flags;
  1429. ssize_t rc = count;
  1430. if (count > 2)
  1431. return -EINVAL;
  1432. if (count > 0 && buf[count-1] == '\n')
  1433. ((char *) buf)[count-1] = 0;
  1434. if (buf[0] != '1')
  1435. return -EINVAL;
  1436. /* force remote wakeup enabled in case gadget driver doesn't support */
  1437. spin_lock_irqsave(&dev->lock, flags);
  1438. dev->remote_wakeup = 1;
  1439. dev->dev_status |= (1 << USB_DEVICE_REMOTE_WAKEUP);
  1440. spin_unlock_irqrestore(&dev->lock, flags);
  1441. langwell_wakeup(&dev->gadget);
  1442. return rc;
  1443. }
  1444. static DEVICE_ATTR(remote_wakeup, S_IWUSR, NULL, store_remote_wakeup);
  1445. /*-------------------------------------------------------------------------*/
  1446. /*
  1447. * when a driver is successfully registered, it will receive
  1448. * control requests including set_configuration(), which enables
  1449. * non-control requests. then usb traffic follows until a
  1450. * disconnect is reported. then a host may connect again, or
  1451. * the driver might get unbound.
  1452. */
  1453. static int langwell_start(struct usb_gadget *g,
  1454. struct usb_gadget_driver *driver)
  1455. {
  1456. struct langwell_udc *dev = gadget_to_langwell(g);
  1457. unsigned long flags;
  1458. int retval;
  1459. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1460. spin_lock_irqsave(&dev->lock, flags);
  1461. /* hook up the driver ... */
  1462. driver->driver.bus = NULL;
  1463. dev->driver = driver;
  1464. dev->gadget.dev.driver = &driver->driver;
  1465. spin_unlock_irqrestore(&dev->lock, flags);
  1466. retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
  1467. if (retval)
  1468. goto err;
  1469. dev->usb_state = USB_STATE_ATTACHED;
  1470. dev->ep0_state = WAIT_FOR_SETUP;
  1471. dev->ep0_dir = USB_DIR_OUT;
  1472. /* enable interrupt and set controller to run state */
  1473. if (dev->got_irq)
  1474. langwell_udc_start(dev);
  1475. dev_vdbg(&dev->pdev->dev,
  1476. "After langwell_udc_start(), print all registers:\n");
  1477. print_all_registers(dev);
  1478. dev_info(&dev->pdev->dev, "register driver: %s\n",
  1479. driver->driver.name);
  1480. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1481. return 0;
  1482. err:
  1483. dev->gadget.dev.driver = NULL;
  1484. dev->driver = NULL;
  1485. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1486. return retval;
  1487. }
  1488. /* unregister gadget driver */
  1489. static int langwell_stop(struct usb_gadget *g,
  1490. struct usb_gadget_driver *driver)
  1491. {
  1492. struct langwell_udc *dev = gadget_to_langwell(g);
  1493. unsigned long flags;
  1494. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1495. /* exit PHY low power suspend */
  1496. if (dev->pdev->device != 0x0829)
  1497. langwell_phy_low_power(dev, 0);
  1498. /* unbind OTG transceiver */
  1499. if (dev->transceiver)
  1500. (void)otg_set_peripheral(dev->transceiver->otg, 0);
  1501. /* disable interrupt and set controller to stop state */
  1502. langwell_udc_stop(dev);
  1503. dev->usb_state = USB_STATE_ATTACHED;
  1504. dev->ep0_state = WAIT_FOR_SETUP;
  1505. dev->ep0_dir = USB_DIR_OUT;
  1506. spin_lock_irqsave(&dev->lock, flags);
  1507. /* stop all usb activities */
  1508. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1509. dev->gadget.dev.driver = NULL;
  1510. dev->driver = NULL;
  1511. stop_activity(dev);
  1512. spin_unlock_irqrestore(&dev->lock, flags);
  1513. device_remove_file(&dev->pdev->dev, &dev_attr_function);
  1514. dev_info(&dev->pdev->dev, "unregistered driver '%s'\n",
  1515. driver->driver.name);
  1516. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1517. return 0;
  1518. }
  1519. /*-------------------------------------------------------------------------*/
  1520. /*
  1521. * setup tripwire is used as a semaphore to ensure that the setup data
  1522. * payload is extracted from a dQH without being corrupted
  1523. */
  1524. static void setup_tripwire(struct langwell_udc *dev)
  1525. {
  1526. u32 usbcmd,
  1527. endptsetupstat;
  1528. unsigned long timeout;
  1529. struct langwell_dqh *dqh;
  1530. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1531. /* ep0 OUT dQH */
  1532. dqh = &dev->ep_dqh[EP_DIR_OUT];
  1533. /* Write-Clear endptsetupstat */
  1534. endptsetupstat = readl(&dev->op_regs->endptsetupstat);
  1535. writel(endptsetupstat, &dev->op_regs->endptsetupstat);
  1536. /* wait until endptsetupstat is cleared */
  1537. timeout = jiffies + SETUPSTAT_TIMEOUT;
  1538. while (readl(&dev->op_regs->endptsetupstat)) {
  1539. if (time_after(jiffies, timeout)) {
  1540. dev_err(&dev->pdev->dev, "setup_tripwire timeout\n");
  1541. break;
  1542. }
  1543. cpu_relax();
  1544. }
  1545. /* while a hazard exists when setup packet arrives */
  1546. do {
  1547. /* set setup tripwire bit */
  1548. usbcmd = readl(&dev->op_regs->usbcmd);
  1549. writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd);
  1550. /* copy the setup packet to local buffer */
  1551. memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8);
  1552. } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW));
  1553. /* Write-Clear setup tripwire bit */
  1554. usbcmd = readl(&dev->op_regs->usbcmd);
  1555. writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd);
  1556. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1557. }
  1558. /* protocol ep0 stall, will automatically be cleared on new transaction */
  1559. static void ep0_stall(struct langwell_udc *dev)
  1560. {
  1561. u32 endptctrl;
  1562. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1563. /* set TX and RX to stall */
  1564. endptctrl = readl(&dev->op_regs->endptctrl[0]);
  1565. endptctrl |= EPCTRL_TXS | EPCTRL_RXS;
  1566. writel(endptctrl, &dev->op_regs->endptctrl[0]);
  1567. /* update ep0 state */
  1568. dev->ep0_state = WAIT_FOR_SETUP;
  1569. dev->ep0_dir = USB_DIR_OUT;
  1570. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1571. }
  1572. /* PRIME a status phase for ep0 */
  1573. static int prime_status_phase(struct langwell_udc *dev, int dir)
  1574. {
  1575. struct langwell_request *req;
  1576. struct langwell_ep *ep;
  1577. int status = 0;
  1578. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1579. if (dir == EP_DIR_IN)
  1580. dev->ep0_dir = USB_DIR_IN;
  1581. else
  1582. dev->ep0_dir = USB_DIR_OUT;
  1583. ep = &dev->ep[0];
  1584. dev->ep0_state = WAIT_FOR_OUT_STATUS;
  1585. req = dev->status_req;
  1586. req->ep = ep;
  1587. req->req.length = 0;
  1588. req->req.status = -EINPROGRESS;
  1589. req->req.actual = 0;
  1590. req->req.complete = NULL;
  1591. req->dtd_count = 0;
  1592. if (!req_to_dtd(req))
  1593. status = queue_dtd(ep, req);
  1594. else
  1595. return -ENOMEM;
  1596. if (status)
  1597. dev_err(&dev->pdev->dev, "can't queue ep0 status request\n");
  1598. list_add_tail(&req->queue, &ep->queue);
  1599. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1600. return status;
  1601. }
  1602. /* SET_ADDRESS request routine */
  1603. static void set_address(struct langwell_udc *dev, u16 value,
  1604. u16 index, u16 length)
  1605. {
  1606. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1607. /* save the new address to device struct */
  1608. dev->dev_addr = (u8) value;
  1609. dev_vdbg(&dev->pdev->dev, "dev->dev_addr = %d\n", dev->dev_addr);
  1610. /* update usb state */
  1611. dev->usb_state = USB_STATE_ADDRESS;
  1612. /* STATUS phase */
  1613. if (prime_status_phase(dev, EP_DIR_IN))
  1614. ep0_stall(dev);
  1615. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1616. }
  1617. /* return endpoint by windex */
  1618. static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev,
  1619. u16 wIndex)
  1620. {
  1621. struct langwell_ep *ep;
  1622. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1623. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  1624. return &dev->ep[0];
  1625. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1626. u8 bEndpointAddress;
  1627. if (!ep->desc)
  1628. continue;
  1629. bEndpointAddress = ep->desc->bEndpointAddress;
  1630. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  1631. continue;
  1632. if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
  1633. == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
  1634. return ep;
  1635. }
  1636. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1637. return NULL;
  1638. }
  1639. /* return whether endpoint is stalled, 0: not stalled; 1: stalled */
  1640. static int ep_is_stall(struct langwell_ep *ep)
  1641. {
  1642. struct langwell_udc *dev = ep->dev;
  1643. u32 endptctrl;
  1644. int retval;
  1645. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1646. endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]);
  1647. if (is_in(ep))
  1648. retval = endptctrl & EPCTRL_TXS ? 1 : 0;
  1649. else
  1650. retval = endptctrl & EPCTRL_RXS ? 1 : 0;
  1651. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1652. return retval;
  1653. }
  1654. /* GET_STATUS request routine */
  1655. static void get_status(struct langwell_udc *dev, u8 request_type, u16 value,
  1656. u16 index, u16 length)
  1657. {
  1658. struct langwell_request *req;
  1659. struct langwell_ep *ep;
  1660. u16 status_data = 0; /* 16 bits cpu view status data */
  1661. int status = 0;
  1662. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1663. ep = &dev->ep[0];
  1664. if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1665. /* get device status */
  1666. status_data = dev->dev_status;
  1667. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
  1668. /* get interface status */
  1669. status_data = 0;
  1670. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
  1671. /* get endpoint status */
  1672. struct langwell_ep *epn;
  1673. epn = get_ep_by_windex(dev, index);
  1674. /* stall if endpoint doesn't exist */
  1675. if (!epn)
  1676. goto stall;
  1677. status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT;
  1678. }
  1679. dev_dbg(&dev->pdev->dev, "get status data: 0x%04x\n", status_data);
  1680. dev->ep0_dir = USB_DIR_IN;
  1681. /* borrow the per device status_req */
  1682. req = dev->status_req;
  1683. /* fill in the reqest structure */
  1684. *((u16 *) req->req.buf) = cpu_to_le16(status_data);
  1685. req->ep = ep;
  1686. req->req.length = 2;
  1687. req->req.status = -EINPROGRESS;
  1688. req->req.actual = 0;
  1689. req->req.complete = NULL;
  1690. req->dtd_count = 0;
  1691. /* prime the data phase */
  1692. if (!req_to_dtd(req))
  1693. status = queue_dtd(ep, req);
  1694. else /* no mem */
  1695. goto stall;
  1696. if (status) {
  1697. dev_err(&dev->pdev->dev,
  1698. "response error on GET_STATUS request\n");
  1699. goto stall;
  1700. }
  1701. list_add_tail(&req->queue, &ep->queue);
  1702. dev->ep0_state = DATA_STATE_XMIT;
  1703. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1704. return;
  1705. stall:
  1706. ep0_stall(dev);
  1707. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1708. }
  1709. /* setup packet interrupt handler */
  1710. static void handle_setup_packet(struct langwell_udc *dev,
  1711. struct usb_ctrlrequest *setup)
  1712. {
  1713. u16 wValue = le16_to_cpu(setup->wValue);
  1714. u16 wIndex = le16_to_cpu(setup->wIndex);
  1715. u16 wLength = le16_to_cpu(setup->wLength);
  1716. u32 portsc1;
  1717. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1718. /* ep0 fifo flush */
  1719. nuke(&dev->ep[0], -ESHUTDOWN);
  1720. dev_dbg(&dev->pdev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
  1721. setup->bRequestType, setup->bRequest,
  1722. wValue, wIndex, wLength);
  1723. /* RNDIS gadget delegate */
  1724. if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) {
  1725. /* USB_CDC_SEND_ENCAPSULATED_COMMAND */
  1726. goto delegate;
  1727. }
  1728. /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
  1729. if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) {
  1730. /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
  1731. goto delegate;
  1732. }
  1733. /* We process some stardard setup requests here */
  1734. switch (setup->bRequest) {
  1735. case USB_REQ_GET_STATUS:
  1736. dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_GET_STATUS\n");
  1737. /* get status, DATA and STATUS phase */
  1738. if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
  1739. != (USB_DIR_IN | USB_TYPE_STANDARD))
  1740. break;
  1741. get_status(dev, setup->bRequestType, wValue, wIndex, wLength);
  1742. goto end;
  1743. case USB_REQ_SET_ADDRESS:
  1744. dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_SET_ADDRESS\n");
  1745. /* STATUS phase */
  1746. if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
  1747. | USB_RECIP_DEVICE))
  1748. break;
  1749. set_address(dev, wValue, wIndex, wLength);
  1750. goto end;
  1751. case USB_REQ_CLEAR_FEATURE:
  1752. case USB_REQ_SET_FEATURE:
  1753. /* STATUS phase */
  1754. {
  1755. int rc = -EOPNOTSUPP;
  1756. if (setup->bRequest == USB_REQ_SET_FEATURE)
  1757. dev_dbg(&dev->pdev->dev,
  1758. "SETUP: USB_REQ_SET_FEATURE\n");
  1759. else if (setup->bRequest == USB_REQ_CLEAR_FEATURE)
  1760. dev_dbg(&dev->pdev->dev,
  1761. "SETUP: USB_REQ_CLEAR_FEATURE\n");
  1762. if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
  1763. == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
  1764. struct langwell_ep *epn;
  1765. epn = get_ep_by_windex(dev, wIndex);
  1766. /* stall if endpoint doesn't exist */
  1767. if (!epn) {
  1768. ep0_stall(dev);
  1769. goto end;
  1770. }
  1771. if (wValue != 0 || wLength != 0
  1772. || epn->ep_num > dev->ep_max)
  1773. break;
  1774. spin_unlock(&dev->lock);
  1775. rc = langwell_ep_set_halt(&epn->ep,
  1776. (setup->bRequest == USB_REQ_SET_FEATURE)
  1777. ? 1 : 0);
  1778. spin_lock(&dev->lock);
  1779. } else if ((setup->bRequestType & (USB_RECIP_MASK
  1780. | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
  1781. | USB_TYPE_STANDARD)) {
  1782. rc = 0;
  1783. switch (wValue) {
  1784. case USB_DEVICE_REMOTE_WAKEUP:
  1785. if (setup->bRequest == USB_REQ_SET_FEATURE) {
  1786. dev->remote_wakeup = 1;
  1787. dev->dev_status |= (1 << wValue);
  1788. } else {
  1789. dev->remote_wakeup = 0;
  1790. dev->dev_status &= ~(1 << wValue);
  1791. }
  1792. break;
  1793. case USB_DEVICE_TEST_MODE:
  1794. dev_dbg(&dev->pdev->dev, "SETUP: TEST MODE\n");
  1795. if ((wIndex & 0xff) ||
  1796. (dev->gadget.speed != USB_SPEED_HIGH))
  1797. ep0_stall(dev);
  1798. switch (wIndex >> 8) {
  1799. case TEST_J:
  1800. case TEST_K:
  1801. case TEST_SE0_NAK:
  1802. case TEST_PACKET:
  1803. case TEST_FORCE_EN:
  1804. if (prime_status_phase(dev, EP_DIR_IN))
  1805. ep0_stall(dev);
  1806. portsc1 = readl(&dev->op_regs->portsc1);
  1807. portsc1 |= (wIndex & 0xf00) << 8;
  1808. writel(portsc1, &dev->op_regs->portsc1);
  1809. goto end;
  1810. default:
  1811. rc = -EOPNOTSUPP;
  1812. }
  1813. break;
  1814. default:
  1815. rc = -EOPNOTSUPP;
  1816. break;
  1817. }
  1818. if (!gadget_is_otg(&dev->gadget))
  1819. break;
  1820. else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE)
  1821. dev->gadget.b_hnp_enable = 1;
  1822. else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
  1823. dev->gadget.a_hnp_support = 1;
  1824. else if (setup->bRequest ==
  1825. USB_DEVICE_A_ALT_HNP_SUPPORT)
  1826. dev->gadget.a_alt_hnp_support = 1;
  1827. else
  1828. break;
  1829. } else
  1830. break;
  1831. if (rc == 0) {
  1832. if (prime_status_phase(dev, EP_DIR_IN))
  1833. ep0_stall(dev);
  1834. }
  1835. goto end;
  1836. }
  1837. case USB_REQ_GET_DESCRIPTOR:
  1838. dev_dbg(&dev->pdev->dev,
  1839. "SETUP: USB_REQ_GET_DESCRIPTOR\n");
  1840. goto delegate;
  1841. case USB_REQ_SET_DESCRIPTOR:
  1842. dev_dbg(&dev->pdev->dev,
  1843. "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n");
  1844. goto delegate;
  1845. case USB_REQ_GET_CONFIGURATION:
  1846. dev_dbg(&dev->pdev->dev,
  1847. "SETUP: USB_REQ_GET_CONFIGURATION\n");
  1848. goto delegate;
  1849. case USB_REQ_SET_CONFIGURATION:
  1850. dev_dbg(&dev->pdev->dev,
  1851. "SETUP: USB_REQ_SET_CONFIGURATION\n");
  1852. goto delegate;
  1853. case USB_REQ_GET_INTERFACE:
  1854. dev_dbg(&dev->pdev->dev,
  1855. "SETUP: USB_REQ_GET_INTERFACE\n");
  1856. goto delegate;
  1857. case USB_REQ_SET_INTERFACE:
  1858. dev_dbg(&dev->pdev->dev,
  1859. "SETUP: USB_REQ_SET_INTERFACE\n");
  1860. goto delegate;
  1861. case USB_REQ_SYNCH_FRAME:
  1862. dev_dbg(&dev->pdev->dev,
  1863. "SETUP: USB_REQ_SYNCH_FRAME unsupported\n");
  1864. goto delegate;
  1865. default:
  1866. /* delegate USB standard requests to the gadget driver */
  1867. goto delegate;
  1868. delegate:
  1869. /* USB requests handled by gadget */
  1870. if (wLength) {
  1871. /* DATA phase from gadget, STATUS phase from udc */
  1872. dev->ep0_dir = (setup->bRequestType & USB_DIR_IN)
  1873. ? USB_DIR_IN : USB_DIR_OUT;
  1874. dev_vdbg(&dev->pdev->dev,
  1875. "dev->ep0_dir = 0x%x, wLength = %d\n",
  1876. dev->ep0_dir, wLength);
  1877. spin_unlock(&dev->lock);
  1878. if (dev->driver->setup(&dev->gadget,
  1879. &dev->local_setup_buff) < 0)
  1880. ep0_stall(dev);
  1881. spin_lock(&dev->lock);
  1882. dev->ep0_state = (setup->bRequestType & USB_DIR_IN)
  1883. ? DATA_STATE_XMIT : DATA_STATE_RECV;
  1884. } else {
  1885. /* no DATA phase, IN STATUS phase from gadget */
  1886. dev->ep0_dir = USB_DIR_IN;
  1887. dev_vdbg(&dev->pdev->dev,
  1888. "dev->ep0_dir = 0x%x, wLength = %d\n",
  1889. dev->ep0_dir, wLength);
  1890. spin_unlock(&dev->lock);
  1891. if (dev->driver->setup(&dev->gadget,
  1892. &dev->local_setup_buff) < 0)
  1893. ep0_stall(dev);
  1894. spin_lock(&dev->lock);
  1895. dev->ep0_state = WAIT_FOR_OUT_STATUS;
  1896. }
  1897. break;
  1898. }
  1899. end:
  1900. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1901. }
  1902. /* transfer completion, process endpoint request and free the completed dTDs
  1903. * for this request
  1904. */
  1905. static int process_ep_req(struct langwell_udc *dev, int index,
  1906. struct langwell_request *curr_req)
  1907. {
  1908. struct langwell_dtd *curr_dtd;
  1909. struct langwell_dqh *curr_dqh;
  1910. int td_complete, actual, remaining_length;
  1911. int i, dir;
  1912. u8 dtd_status = 0;
  1913. int retval = 0;
  1914. curr_dqh = &dev->ep_dqh[index];
  1915. dir = index % 2;
  1916. curr_dtd = curr_req->head;
  1917. td_complete = 0;
  1918. actual = curr_req->req.length;
  1919. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1920. for (i = 0; i < curr_req->dtd_count; i++) {
  1921. /* command execution states by dTD */
  1922. dtd_status = curr_dtd->dtd_status;
  1923. barrier();
  1924. remaining_length = le16_to_cpu(curr_dtd->dtd_total);
  1925. actual -= remaining_length;
  1926. if (!dtd_status) {
  1927. /* transfers completed successfully */
  1928. if (!remaining_length) {
  1929. td_complete++;
  1930. dev_vdbg(&dev->pdev->dev,
  1931. "dTD transmitted successfully\n");
  1932. } else {
  1933. if (dir) {
  1934. dev_vdbg(&dev->pdev->dev,
  1935. "TX dTD remains data\n");
  1936. retval = -EPROTO;
  1937. break;
  1938. } else {
  1939. td_complete++;
  1940. break;
  1941. }
  1942. }
  1943. } else {
  1944. /* transfers completed with errors */
  1945. if (dtd_status & DTD_STS_ACTIVE) {
  1946. dev_dbg(&dev->pdev->dev,
  1947. "dTD status ACTIVE dQH[%d]\n", index);
  1948. retval = 1;
  1949. return retval;
  1950. } else if (dtd_status & DTD_STS_HALTED) {
  1951. dev_err(&dev->pdev->dev,
  1952. "dTD error %08x dQH[%d]\n",
  1953. dtd_status, index);
  1954. /* clear the errors and halt condition */
  1955. curr_dqh->dtd_status = 0;
  1956. retval = -EPIPE;
  1957. break;
  1958. } else if (dtd_status & DTD_STS_DBE) {
  1959. dev_dbg(&dev->pdev->dev,
  1960. "data buffer (overflow) error\n");
  1961. retval = -EPROTO;
  1962. break;
  1963. } else if (dtd_status & DTD_STS_TRE) {
  1964. dev_dbg(&dev->pdev->dev,
  1965. "transaction(ISO) error\n");
  1966. retval = -EILSEQ;
  1967. break;
  1968. } else
  1969. dev_err(&dev->pdev->dev,
  1970. "unknown error (0x%x)!\n",
  1971. dtd_status);
  1972. }
  1973. if (i != curr_req->dtd_count - 1)
  1974. curr_dtd = (struct langwell_dtd *)
  1975. curr_dtd->next_dtd_virt;
  1976. }
  1977. if (retval)
  1978. return retval;
  1979. curr_req->req.actual = actual;
  1980. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1981. return 0;
  1982. }
  1983. /* complete DATA or STATUS phase of ep0 prime status phase if needed */
  1984. static void ep0_req_complete(struct langwell_udc *dev,
  1985. struct langwell_ep *ep0, struct langwell_request *req)
  1986. {
  1987. u32 new_addr;
  1988. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1989. if (dev->usb_state == USB_STATE_ADDRESS) {
  1990. /* set the new address */
  1991. new_addr = (u32)dev->dev_addr;
  1992. writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr);
  1993. new_addr = USBADR(readl(&dev->op_regs->deviceaddr));
  1994. dev_vdbg(&dev->pdev->dev, "new_addr = %d\n", new_addr);
  1995. }
  1996. done(ep0, req, 0);
  1997. switch (dev->ep0_state) {
  1998. case DATA_STATE_XMIT:
  1999. /* receive status phase */
  2000. if (prime_status_phase(dev, EP_DIR_OUT))
  2001. ep0_stall(dev);
  2002. break;
  2003. case DATA_STATE_RECV:
  2004. /* send status phase */
  2005. if (prime_status_phase(dev, EP_DIR_IN))
  2006. ep0_stall(dev);
  2007. break;
  2008. case WAIT_FOR_OUT_STATUS:
  2009. dev->ep0_state = WAIT_FOR_SETUP;
  2010. break;
  2011. case WAIT_FOR_SETUP:
  2012. dev_err(&dev->pdev->dev, "unexpect ep0 packets\n");
  2013. break;
  2014. default:
  2015. ep0_stall(dev);
  2016. break;
  2017. }
  2018. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2019. }
  2020. /* USB transfer completion interrupt */
  2021. static void handle_trans_complete(struct langwell_udc *dev)
  2022. {
  2023. u32 complete_bits;
  2024. int i, ep_num, dir, bit_mask, status;
  2025. struct langwell_ep *epn;
  2026. struct langwell_request *curr_req, *temp_req;
  2027. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2028. complete_bits = readl(&dev->op_regs->endptcomplete);
  2029. dev_vdbg(&dev->pdev->dev, "endptcomplete register: 0x%08x\n",
  2030. complete_bits);
  2031. /* Write-Clear the bits in endptcomplete register */
  2032. writel(complete_bits, &dev->op_regs->endptcomplete);
  2033. if (!complete_bits) {
  2034. dev_dbg(&dev->pdev->dev, "complete_bits = 0\n");
  2035. goto done;
  2036. }
  2037. for (i = 0; i < dev->ep_max; i++) {
  2038. ep_num = i / 2;
  2039. dir = i % 2;
  2040. bit_mask = 1 << (ep_num + 16 * dir);
  2041. if (!(complete_bits & bit_mask))
  2042. continue;
  2043. /* ep0 */
  2044. if (i == 1)
  2045. epn = &dev->ep[0];
  2046. else
  2047. epn = &dev->ep[i];
  2048. if (epn->name == NULL) {
  2049. dev_warn(&dev->pdev->dev, "invalid endpoint\n");
  2050. continue;
  2051. }
  2052. if (i < 2)
  2053. /* ep0 in and out */
  2054. dev_dbg(&dev->pdev->dev, "%s-%s transfer completed\n",
  2055. epn->name,
  2056. is_in(epn) ? "in" : "out");
  2057. else
  2058. dev_dbg(&dev->pdev->dev, "%s transfer completed\n",
  2059. epn->name);
  2060. /* process the req queue until an uncomplete request */
  2061. list_for_each_entry_safe(curr_req, temp_req,
  2062. &epn->queue, queue) {
  2063. status = process_ep_req(dev, i, curr_req);
  2064. dev_vdbg(&dev->pdev->dev, "%s req status: %d\n",
  2065. epn->name, status);
  2066. if (status)
  2067. break;
  2068. /* write back status to req */
  2069. curr_req->req.status = status;
  2070. /* ep0 request completion */
  2071. if (ep_num == 0) {
  2072. ep0_req_complete(dev, epn, curr_req);
  2073. break;
  2074. } else {
  2075. done(epn, curr_req, status);
  2076. }
  2077. }
  2078. }
  2079. done:
  2080. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2081. }
  2082. /* port change detect interrupt handler */
  2083. static void handle_port_change(struct langwell_udc *dev)
  2084. {
  2085. u32 portsc1, devlc;
  2086. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2087. if (dev->bus_reset)
  2088. dev->bus_reset = 0;
  2089. portsc1 = readl(&dev->op_regs->portsc1);
  2090. devlc = readl(&dev->op_regs->devlc);
  2091. dev_vdbg(&dev->pdev->dev, "portsc1 = 0x%08x, devlc = 0x%08x\n",
  2092. portsc1, devlc);
  2093. /* bus reset is finished */
  2094. if (!(portsc1 & PORTS_PR)) {
  2095. /* get the speed */
  2096. dev->gadget.speed = lpm_device_speed(devlc);
  2097. dev_vdbg(&dev->pdev->dev, "dev->gadget.speed = %d\n",
  2098. dev->gadget.speed);
  2099. }
  2100. /* LPM L0 to L1 */
  2101. if (dev->lpm && dev->lpm_state == LPM_L0)
  2102. if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) {
  2103. dev_info(&dev->pdev->dev, "LPM L0 to L1\n");
  2104. dev->lpm_state = LPM_L1;
  2105. }
  2106. /* LPM L1 to L0, force resume or remote wakeup finished */
  2107. if (dev->lpm && dev->lpm_state == LPM_L1)
  2108. if (!(portsc1 & PORTS_SUSP)) {
  2109. dev_info(&dev->pdev->dev, "LPM L1 to L0\n");
  2110. dev->lpm_state = LPM_L0;
  2111. }
  2112. /* update USB state */
  2113. if (!dev->resume_state)
  2114. dev->usb_state = USB_STATE_DEFAULT;
  2115. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2116. }
  2117. /* USB reset interrupt handler */
  2118. static void handle_usb_reset(struct langwell_udc *dev)
  2119. {
  2120. u32 deviceaddr,
  2121. endptsetupstat,
  2122. endptcomplete;
  2123. unsigned long timeout;
  2124. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2125. /* Write-Clear the device address */
  2126. deviceaddr = readl(&dev->op_regs->deviceaddr);
  2127. writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr);
  2128. dev->dev_addr = 0;
  2129. /* clear usb state */
  2130. dev->resume_state = 0;
  2131. /* LPM L1 to L0, reset */
  2132. if (dev->lpm)
  2133. dev->lpm_state = LPM_L0;
  2134. dev->ep0_dir = USB_DIR_OUT;
  2135. dev->ep0_state = WAIT_FOR_SETUP;
  2136. /* remote wakeup reset to 0 when the device is reset */
  2137. dev->remote_wakeup = 0;
  2138. dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
  2139. dev->gadget.b_hnp_enable = 0;
  2140. dev->gadget.a_hnp_support = 0;
  2141. dev->gadget.a_alt_hnp_support = 0;
  2142. /* Write-Clear all the setup token semaphores */
  2143. endptsetupstat = readl(&dev->op_regs->endptsetupstat);
  2144. writel(endptsetupstat, &dev->op_regs->endptsetupstat);
  2145. /* Write-Clear all the endpoint complete status bits */
  2146. endptcomplete = readl(&dev->op_regs->endptcomplete);
  2147. writel(endptcomplete, &dev->op_regs->endptcomplete);
  2148. /* wait until all endptprime bits cleared */
  2149. timeout = jiffies + PRIME_TIMEOUT;
  2150. while (readl(&dev->op_regs->endptprime)) {
  2151. if (time_after(jiffies, timeout)) {
  2152. dev_err(&dev->pdev->dev, "USB reset timeout\n");
  2153. break;
  2154. }
  2155. cpu_relax();
  2156. }
  2157. /* write 1s to endptflush register to clear any primed buffers */
  2158. writel((u32) ~0, &dev->op_regs->endptflush);
  2159. if (readl(&dev->op_regs->portsc1) & PORTS_PR) {
  2160. dev_vdbg(&dev->pdev->dev, "USB bus reset\n");
  2161. /* bus is reseting */
  2162. dev->bus_reset = 1;
  2163. /* reset all the queues, stop all USB activities */
  2164. stop_activity(dev);
  2165. dev->usb_state = USB_STATE_DEFAULT;
  2166. } else {
  2167. dev_vdbg(&dev->pdev->dev, "device controller reset\n");
  2168. /* controller reset */
  2169. langwell_udc_reset(dev);
  2170. /* reset all the queues, stop all USB activities */
  2171. stop_activity(dev);
  2172. /* reset ep0 dQH and endptctrl */
  2173. ep0_reset(dev);
  2174. /* enable interrupt and set controller to run state */
  2175. langwell_udc_start(dev);
  2176. dev->usb_state = USB_STATE_ATTACHED;
  2177. }
  2178. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2179. }
  2180. /* USB bus suspend/resume interrupt */
  2181. static void handle_bus_suspend(struct langwell_udc *dev)
  2182. {
  2183. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2184. dev->resume_state = dev->usb_state;
  2185. dev->usb_state = USB_STATE_SUSPENDED;
  2186. /* report suspend to the driver */
  2187. if (dev->driver) {
  2188. if (dev->driver->suspend) {
  2189. spin_unlock(&dev->lock);
  2190. dev->driver->suspend(&dev->gadget);
  2191. spin_lock(&dev->lock);
  2192. dev_dbg(&dev->pdev->dev, "suspend %s\n",
  2193. dev->driver->driver.name);
  2194. }
  2195. }
  2196. /* enter PHY low power suspend */
  2197. if (dev->pdev->device != 0x0829)
  2198. langwell_phy_low_power(dev, 0);
  2199. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2200. }
  2201. static void handle_bus_resume(struct langwell_udc *dev)
  2202. {
  2203. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2204. dev->usb_state = dev->resume_state;
  2205. dev->resume_state = 0;
  2206. /* exit PHY low power suspend */
  2207. if (dev->pdev->device != 0x0829)
  2208. langwell_phy_low_power(dev, 0);
  2209. /* report resume to the driver */
  2210. if (dev->driver) {
  2211. if (dev->driver->resume) {
  2212. spin_unlock(&dev->lock);
  2213. dev->driver->resume(&dev->gadget);
  2214. spin_lock(&dev->lock);
  2215. dev_dbg(&dev->pdev->dev, "resume %s\n",
  2216. dev->driver->driver.name);
  2217. }
  2218. }
  2219. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2220. }
  2221. /* USB device controller interrupt handler */
  2222. static irqreturn_t langwell_irq(int irq, void *_dev)
  2223. {
  2224. struct langwell_udc *dev = _dev;
  2225. u32 usbsts,
  2226. usbintr,
  2227. irq_sts,
  2228. portsc1;
  2229. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2230. if (dev->stopped) {
  2231. dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
  2232. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2233. return IRQ_NONE;
  2234. }
  2235. spin_lock(&dev->lock);
  2236. /* USB status */
  2237. usbsts = readl(&dev->op_regs->usbsts);
  2238. /* USB interrupt enable */
  2239. usbintr = readl(&dev->op_regs->usbintr);
  2240. irq_sts = usbsts & usbintr;
  2241. dev_vdbg(&dev->pdev->dev,
  2242. "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n",
  2243. usbsts, usbintr, irq_sts);
  2244. if (!irq_sts) {
  2245. dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
  2246. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2247. spin_unlock(&dev->lock);
  2248. return IRQ_NONE;
  2249. }
  2250. /* Write-Clear interrupt status bits */
  2251. writel(irq_sts, &dev->op_regs->usbsts);
  2252. /* resume from suspend */
  2253. portsc1 = readl(&dev->op_regs->portsc1);
  2254. if (dev->usb_state == USB_STATE_SUSPENDED)
  2255. if (!(portsc1 & PORTS_SUSP))
  2256. handle_bus_resume(dev);
  2257. /* USB interrupt */
  2258. if (irq_sts & STS_UI) {
  2259. dev_vdbg(&dev->pdev->dev, "USB interrupt\n");
  2260. /* setup packet received from ep0 */
  2261. if (readl(&dev->op_regs->endptsetupstat)
  2262. & EP0SETUPSTAT_MASK) {
  2263. dev_vdbg(&dev->pdev->dev,
  2264. "USB SETUP packet received interrupt\n");
  2265. /* setup tripwire semaphone */
  2266. setup_tripwire(dev);
  2267. handle_setup_packet(dev, &dev->local_setup_buff);
  2268. }
  2269. /* USB transfer completion */
  2270. if (readl(&dev->op_regs->endptcomplete)) {
  2271. dev_vdbg(&dev->pdev->dev,
  2272. "USB transfer completion interrupt\n");
  2273. handle_trans_complete(dev);
  2274. }
  2275. }
  2276. /* SOF received interrupt (for ISO transfer) */
  2277. if (irq_sts & STS_SRI) {
  2278. /* FIXME */
  2279. /* dev_vdbg(&dev->pdev->dev, "SOF received interrupt\n"); */
  2280. }
  2281. /* port change detect interrupt */
  2282. if (irq_sts & STS_PCI) {
  2283. dev_vdbg(&dev->pdev->dev, "port change detect interrupt\n");
  2284. handle_port_change(dev);
  2285. }
  2286. /* suspend interrupt */
  2287. if (irq_sts & STS_SLI) {
  2288. dev_vdbg(&dev->pdev->dev, "suspend interrupt\n");
  2289. handle_bus_suspend(dev);
  2290. }
  2291. /* USB reset interrupt */
  2292. if (irq_sts & STS_URI) {
  2293. dev_vdbg(&dev->pdev->dev, "USB reset interrupt\n");
  2294. handle_usb_reset(dev);
  2295. }
  2296. /* USB error or system error interrupt */
  2297. if (irq_sts & (STS_UEI | STS_SEI)) {
  2298. /* FIXME */
  2299. dev_warn(&dev->pdev->dev, "error IRQ, irq_sts: %x\n", irq_sts);
  2300. }
  2301. spin_unlock(&dev->lock);
  2302. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2303. return IRQ_HANDLED;
  2304. }
  2305. /*-------------------------------------------------------------------------*/
  2306. /* release device structure */
  2307. static void gadget_release(struct device *_dev)
  2308. {
  2309. struct langwell_udc *dev = dev_get_drvdata(_dev);
  2310. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2311. complete(dev->done);
  2312. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2313. kfree(dev);
  2314. }
  2315. /* enable SRAM caching if SRAM detected */
  2316. static void sram_init(struct langwell_udc *dev)
  2317. {
  2318. struct pci_dev *pdev = dev->pdev;
  2319. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2320. dev->sram_addr = pci_resource_start(pdev, 1);
  2321. dev->sram_size = pci_resource_len(pdev, 1);
  2322. dev_info(&dev->pdev->dev, "Found private SRAM at %x size:%x\n",
  2323. dev->sram_addr, dev->sram_size);
  2324. dev->got_sram = 1;
  2325. if (pci_request_region(pdev, 1, kobject_name(&pdev->dev.kobj))) {
  2326. dev_warn(&dev->pdev->dev, "SRAM request failed\n");
  2327. dev->got_sram = 0;
  2328. } else if (!dma_declare_coherent_memory(&pdev->dev, dev->sram_addr,
  2329. dev->sram_addr, dev->sram_size, DMA_MEMORY_MAP)) {
  2330. dev_warn(&dev->pdev->dev, "SRAM DMA declare failed\n");
  2331. pci_release_region(pdev, 1);
  2332. dev->got_sram = 0;
  2333. }
  2334. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2335. }
  2336. /* release SRAM caching */
  2337. static void sram_deinit(struct langwell_udc *dev)
  2338. {
  2339. struct pci_dev *pdev = dev->pdev;
  2340. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2341. dma_release_declared_memory(&pdev->dev);
  2342. pci_release_region(pdev, 1);
  2343. dev->got_sram = 0;
  2344. dev_info(&dev->pdev->dev, "release SRAM caching\n");
  2345. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2346. }
  2347. /* tear down the binding between this driver and the pci device */
  2348. static void langwell_udc_remove(struct pci_dev *pdev)
  2349. {
  2350. struct langwell_udc *dev = pci_get_drvdata(pdev);
  2351. DECLARE_COMPLETION(done);
  2352. BUG_ON(dev->driver);
  2353. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2354. dev->done = &done;
  2355. /* free dTD dma_pool and dQH */
  2356. if (dev->dtd_pool)
  2357. dma_pool_destroy(dev->dtd_pool);
  2358. if (dev->ep_dqh)
  2359. dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
  2360. dev->ep_dqh, dev->ep_dqh_dma);
  2361. /* release SRAM caching */
  2362. if (dev->has_sram && dev->got_sram)
  2363. sram_deinit(dev);
  2364. if (dev->status_req) {
  2365. kfree(dev->status_req->req.buf);
  2366. kfree(dev->status_req);
  2367. }
  2368. kfree(dev->ep);
  2369. /* disable IRQ handler */
  2370. if (dev->got_irq)
  2371. free_irq(pdev->irq, dev);
  2372. if (dev->cap_regs)
  2373. iounmap(dev->cap_regs);
  2374. if (dev->region)
  2375. release_mem_region(pci_resource_start(pdev, 0),
  2376. pci_resource_len(pdev, 0));
  2377. if (dev->enabled)
  2378. pci_disable_device(pdev);
  2379. dev->cap_regs = NULL;
  2380. dev_info(&dev->pdev->dev, "unbind\n");
  2381. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2382. device_unregister(&dev->gadget.dev);
  2383. device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
  2384. device_remove_file(&pdev->dev, &dev_attr_remote_wakeup);
  2385. pci_set_drvdata(pdev, NULL);
  2386. /* free dev, wait for the release() finished */
  2387. wait_for_completion(&done);
  2388. }
  2389. /*
  2390. * wrap this driver around the specified device, but
  2391. * don't respond over USB until a gadget driver binds to us.
  2392. */
  2393. static int langwell_udc_probe(struct pci_dev *pdev,
  2394. const struct pci_device_id *id)
  2395. {
  2396. struct langwell_udc *dev;
  2397. unsigned long resource, len;
  2398. void __iomem *base = NULL;
  2399. size_t size;
  2400. int retval;
  2401. /* alloc, and start init */
  2402. dev = kzalloc(sizeof *dev, GFP_KERNEL);
  2403. if (dev == NULL) {
  2404. retval = -ENOMEM;
  2405. goto error;
  2406. }
  2407. /* initialize device spinlock */
  2408. spin_lock_init(&dev->lock);
  2409. dev->pdev = pdev;
  2410. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2411. pci_set_drvdata(pdev, dev);
  2412. /* now all the pci goodies ... */
  2413. if (pci_enable_device(pdev) < 0) {
  2414. retval = -ENODEV;
  2415. goto error;
  2416. }
  2417. dev->enabled = 1;
  2418. /* control register: BAR 0 */
  2419. resource = pci_resource_start(pdev, 0);
  2420. len = pci_resource_len(pdev, 0);
  2421. if (!request_mem_region(resource, len, driver_name)) {
  2422. dev_err(&dev->pdev->dev, "controller already in use\n");
  2423. retval = -EBUSY;
  2424. goto error;
  2425. }
  2426. dev->region = 1;
  2427. base = ioremap_nocache(resource, len);
  2428. if (base == NULL) {
  2429. dev_err(&dev->pdev->dev, "can't map memory\n");
  2430. retval = -EFAULT;
  2431. goto error;
  2432. }
  2433. dev->cap_regs = (struct langwell_cap_regs __iomem *) base;
  2434. dev_vdbg(&dev->pdev->dev, "dev->cap_regs: %p\n", dev->cap_regs);
  2435. dev->op_regs = (struct langwell_op_regs __iomem *)
  2436. (base + OP_REG_OFFSET);
  2437. dev_vdbg(&dev->pdev->dev, "dev->op_regs: %p\n", dev->op_regs);
  2438. /* irq setup after old hardware is cleaned up */
  2439. if (!pdev->irq) {
  2440. dev_err(&dev->pdev->dev, "No IRQ. Check PCI setup!\n");
  2441. retval = -ENODEV;
  2442. goto error;
  2443. }
  2444. dev->has_sram = 1;
  2445. dev->got_sram = 0;
  2446. dev_vdbg(&dev->pdev->dev, "dev->has_sram: %d\n", dev->has_sram);
  2447. /* enable SRAM caching if detected */
  2448. if (dev->has_sram && !dev->got_sram)
  2449. sram_init(dev);
  2450. dev_info(&dev->pdev->dev,
  2451. "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n",
  2452. pdev->irq, resource, len, base);
  2453. /* enables bus-mastering for device dev */
  2454. pci_set_master(pdev);
  2455. if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
  2456. driver_name, dev) != 0) {
  2457. dev_err(&dev->pdev->dev,
  2458. "request interrupt %d failed\n", pdev->irq);
  2459. retval = -EBUSY;
  2460. goto error;
  2461. }
  2462. dev->got_irq = 1;
  2463. /* set stopped bit */
  2464. dev->stopped = 1;
  2465. /* capabilities and endpoint number */
  2466. dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0;
  2467. dev->dciversion = readw(&dev->cap_regs->dciversion);
  2468. dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0;
  2469. dev_vdbg(&dev->pdev->dev, "dev->lpm: %d\n", dev->lpm);
  2470. dev_vdbg(&dev->pdev->dev, "dev->dciversion: 0x%04x\n",
  2471. dev->dciversion);
  2472. dev_vdbg(&dev->pdev->dev, "dccparams: 0x%08x\n",
  2473. readl(&dev->cap_regs->dccparams));
  2474. dev_vdbg(&dev->pdev->dev, "dev->devcap: %d\n", dev->devcap);
  2475. if (!dev->devcap) {
  2476. dev_err(&dev->pdev->dev, "can't support device mode\n");
  2477. retval = -ENODEV;
  2478. goto error;
  2479. }
  2480. /* a pair of endpoints (out/in) for each address */
  2481. dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2;
  2482. dev_vdbg(&dev->pdev->dev, "dev->ep_max: %d\n", dev->ep_max);
  2483. /* allocate endpoints memory */
  2484. dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max,
  2485. GFP_KERNEL);
  2486. if (!dev->ep) {
  2487. dev_err(&dev->pdev->dev, "allocate endpoints memory failed\n");
  2488. retval = -ENOMEM;
  2489. goto error;
  2490. }
  2491. /* allocate device dQH memory */
  2492. size = dev->ep_max * sizeof(struct langwell_dqh);
  2493. dev_vdbg(&dev->pdev->dev, "orig size = %zd\n", size);
  2494. if (size < DQH_ALIGNMENT)
  2495. size = DQH_ALIGNMENT;
  2496. else if ((size % DQH_ALIGNMENT) != 0) {
  2497. size += DQH_ALIGNMENT + 1;
  2498. size &= ~(DQH_ALIGNMENT - 1);
  2499. }
  2500. dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
  2501. &dev->ep_dqh_dma, GFP_KERNEL);
  2502. if (!dev->ep_dqh) {
  2503. dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
  2504. retval = -ENOMEM;
  2505. goto error;
  2506. }
  2507. dev->ep_dqh_size = size;
  2508. dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %zd\n", dev->ep_dqh_size);
  2509. /* initialize ep0 status request structure */
  2510. dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL);
  2511. if (!dev->status_req) {
  2512. dev_err(&dev->pdev->dev,
  2513. "allocate status_req memory failed\n");
  2514. retval = -ENOMEM;
  2515. goto error;
  2516. }
  2517. INIT_LIST_HEAD(&dev->status_req->queue);
  2518. /* allocate a small amount of memory to get valid address */
  2519. dev->status_req->req.buf = kmalloc(8, GFP_KERNEL);
  2520. dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf);
  2521. dev->resume_state = USB_STATE_NOTATTACHED;
  2522. dev->usb_state = USB_STATE_POWERED;
  2523. dev->ep0_dir = USB_DIR_OUT;
  2524. /* remote wakeup reset to 0 when the device is reset */
  2525. dev->remote_wakeup = 0;
  2526. dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
  2527. /* reset device controller */
  2528. langwell_udc_reset(dev);
  2529. /* initialize gadget structure */
  2530. dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */
  2531. dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */
  2532. INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */
  2533. dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
  2534. dev->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
  2535. /* the "gadget" abstracts/virtualizes the controller */
  2536. dev_set_name(&dev->gadget.dev, "gadget");
  2537. dev->gadget.dev.parent = &pdev->dev;
  2538. dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
  2539. dev->gadget.dev.release = gadget_release;
  2540. dev->gadget.name = driver_name; /* gadget name */
  2541. /* controller endpoints reinit */
  2542. eps_reinit(dev);
  2543. /* reset ep0 dQH and endptctrl */
  2544. ep0_reset(dev);
  2545. /* create dTD dma_pool resource */
  2546. dev->dtd_pool = dma_pool_create("langwell_dtd",
  2547. &dev->pdev->dev,
  2548. sizeof(struct langwell_dtd),
  2549. DTD_ALIGNMENT,
  2550. DMA_BOUNDARY);
  2551. if (!dev->dtd_pool) {
  2552. retval = -ENOMEM;
  2553. goto error;
  2554. }
  2555. /* done */
  2556. dev_info(&dev->pdev->dev, "%s\n", driver_desc);
  2557. dev_info(&dev->pdev->dev, "irq %d, pci mem %p\n", pdev->irq, base);
  2558. dev_info(&dev->pdev->dev, "Driver version: " DRIVER_VERSION "\n");
  2559. dev_info(&dev->pdev->dev, "Support (max) %d endpoints\n", dev->ep_max);
  2560. dev_info(&dev->pdev->dev, "Device interface version: 0x%04x\n",
  2561. dev->dciversion);
  2562. dev_info(&dev->pdev->dev, "Controller mode: %s\n",
  2563. dev->devcap ? "Device" : "Host");
  2564. dev_info(&dev->pdev->dev, "Support USB LPM: %s\n",
  2565. dev->lpm ? "Yes" : "No");
  2566. dev_vdbg(&dev->pdev->dev,
  2567. "After langwell_udc_probe(), print all registers:\n");
  2568. print_all_registers(dev);
  2569. retval = device_register(&dev->gadget.dev);
  2570. if (retval)
  2571. goto error;
  2572. retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
  2573. if (retval)
  2574. goto error;
  2575. retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc);
  2576. if (retval)
  2577. goto error;
  2578. retval = device_create_file(&pdev->dev, &dev_attr_remote_wakeup);
  2579. if (retval)
  2580. goto error_attr1;
  2581. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2582. return 0;
  2583. error_attr1:
  2584. device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
  2585. error:
  2586. if (dev) {
  2587. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2588. langwell_udc_remove(pdev);
  2589. }
  2590. return retval;
  2591. }
  2592. /* device controller suspend */
  2593. static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
  2594. {
  2595. struct langwell_udc *dev = pci_get_drvdata(pdev);
  2596. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2597. usb_del_gadget_udc(&dev->gadget);
  2598. /* disable interrupt and set controller to stop state */
  2599. langwell_udc_stop(dev);
  2600. /* disable IRQ handler */
  2601. if (dev->got_irq)
  2602. free_irq(pdev->irq, dev);
  2603. dev->got_irq = 0;
  2604. /* save PCI state */
  2605. pci_save_state(pdev);
  2606. spin_lock_irq(&dev->lock);
  2607. /* stop all usb activities */
  2608. stop_activity(dev);
  2609. spin_unlock_irq(&dev->lock);
  2610. /* free dTD dma_pool and dQH */
  2611. if (dev->dtd_pool)
  2612. dma_pool_destroy(dev->dtd_pool);
  2613. if (dev->ep_dqh)
  2614. dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
  2615. dev->ep_dqh, dev->ep_dqh_dma);
  2616. /* release SRAM caching */
  2617. if (dev->has_sram && dev->got_sram)
  2618. sram_deinit(dev);
  2619. /* set device power state */
  2620. pci_set_power_state(pdev, PCI_D3hot);
  2621. /* enter PHY low power suspend */
  2622. if (dev->pdev->device != 0x0829)
  2623. langwell_phy_low_power(dev, 1);
  2624. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2625. return 0;
  2626. }
  2627. /* device controller resume */
  2628. static int langwell_udc_resume(struct pci_dev *pdev)
  2629. {
  2630. struct langwell_udc *dev = pci_get_drvdata(pdev);
  2631. size_t size;
  2632. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2633. /* exit PHY low power suspend */
  2634. if (dev->pdev->device != 0x0829)
  2635. langwell_phy_low_power(dev, 0);
  2636. /* set device D0 power state */
  2637. pci_set_power_state(pdev, PCI_D0);
  2638. /* enable SRAM caching if detected */
  2639. if (dev->has_sram && !dev->got_sram)
  2640. sram_init(dev);
  2641. /* allocate device dQH memory */
  2642. size = dev->ep_max * sizeof(struct langwell_dqh);
  2643. dev_vdbg(&dev->pdev->dev, "orig size = %zd\n", size);
  2644. if (size < DQH_ALIGNMENT)
  2645. size = DQH_ALIGNMENT;
  2646. else if ((size % DQH_ALIGNMENT) != 0) {
  2647. size += DQH_ALIGNMENT + 1;
  2648. size &= ~(DQH_ALIGNMENT - 1);
  2649. }
  2650. dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
  2651. &dev->ep_dqh_dma, GFP_KERNEL);
  2652. if (!dev->ep_dqh) {
  2653. dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
  2654. return -ENOMEM;
  2655. }
  2656. dev->ep_dqh_size = size;
  2657. dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %zd\n", dev->ep_dqh_size);
  2658. /* create dTD dma_pool resource */
  2659. dev->dtd_pool = dma_pool_create("langwell_dtd",
  2660. &dev->pdev->dev,
  2661. sizeof(struct langwell_dtd),
  2662. DTD_ALIGNMENT,
  2663. DMA_BOUNDARY);
  2664. if (!dev->dtd_pool)
  2665. return -ENOMEM;
  2666. /* restore PCI state */
  2667. pci_restore_state(pdev);
  2668. /* enable IRQ handler */
  2669. if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
  2670. driver_name, dev) != 0) {
  2671. dev_err(&dev->pdev->dev, "request interrupt %d failed\n",
  2672. pdev->irq);
  2673. return -EBUSY;
  2674. }
  2675. dev->got_irq = 1;
  2676. /* reset and start controller to run state */
  2677. if (dev->stopped) {
  2678. /* reset device controller */
  2679. langwell_udc_reset(dev);
  2680. /* reset ep0 dQH and endptctrl */
  2681. ep0_reset(dev);
  2682. /* start device if gadget is loaded */
  2683. if (dev->driver)
  2684. langwell_udc_start(dev);
  2685. }
  2686. /* reset USB status */
  2687. dev->usb_state = USB_STATE_ATTACHED;
  2688. dev->ep0_state = WAIT_FOR_SETUP;
  2689. dev->ep0_dir = USB_DIR_OUT;
  2690. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2691. return 0;
  2692. }
  2693. /* pci driver shutdown */
  2694. static void langwell_udc_shutdown(struct pci_dev *pdev)
  2695. {
  2696. struct langwell_udc *dev = pci_get_drvdata(pdev);
  2697. u32 usbmode;
  2698. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2699. /* reset controller mode to IDLE */
  2700. usbmode = readl(&dev->op_regs->usbmode);
  2701. dev_dbg(&dev->pdev->dev, "usbmode = 0x%08x\n", usbmode);
  2702. usbmode &= (~3 | MODE_IDLE);
  2703. writel(usbmode, &dev->op_regs->usbmode);
  2704. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2705. }
  2706. /*-------------------------------------------------------------------------*/
  2707. static const struct pci_device_id pci_ids[] = { {
  2708. .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
  2709. .class_mask = ~0,
  2710. .vendor = 0x8086,
  2711. .device = 0x0811,
  2712. .subvendor = PCI_ANY_ID,
  2713. .subdevice = PCI_ANY_ID,
  2714. }, { /* end: all zeroes */ }
  2715. };
  2716. MODULE_DEVICE_TABLE(pci, pci_ids);
  2717. static struct pci_driver langwell_pci_driver = {
  2718. .name = (char *) driver_name,
  2719. .id_table = pci_ids,
  2720. .probe = langwell_udc_probe,
  2721. .remove = langwell_udc_remove,
  2722. /* device controller suspend/resume */
  2723. .suspend = langwell_udc_suspend,
  2724. .resume = langwell_udc_resume,
  2725. .shutdown = langwell_udc_shutdown,
  2726. };
  2727. static int __init init(void)
  2728. {
  2729. return pci_register_driver(&langwell_pci_driver);
  2730. }
  2731. module_init(init);
  2732. static void __exit cleanup(void)
  2733. {
  2734. pci_unregister_driver(&langwell_pci_driver);
  2735. }
  2736. module_exit(cleanup);
  2737. MODULE_DESCRIPTION(DRIVER_DESC);
  2738. MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>");
  2739. MODULE_VERSION(DRIVER_VERSION);
  2740. MODULE_LICENSE("GPL");