dev.c 48 KB

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  1. /*
  2. * Linux device driver for RTL8187
  3. *
  4. * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
  5. * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
  6. *
  7. * Based on the r8187 driver, which is:
  8. * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
  9. *
  10. * The driver was extended to the RTL8187B in 2008 by:
  11. * Herton Ronaldo Krzesinski <herton@mandriva.com.br>
  12. * Hin-Tak Leung <htl10@users.sourceforge.net>
  13. * Larry Finger <Larry.Finger@lwfinger.net>
  14. *
  15. * Magic delays and register offsets below are taken from the original
  16. * r8187 driver sources. Thanks to Realtek for their support!
  17. *
  18. * This program is free software; you can redistribute it and/or modify
  19. * it under the terms of the GNU General Public License version 2 as
  20. * published by the Free Software Foundation.
  21. */
  22. #include <linux/init.h>
  23. #include <linux/usb.h>
  24. #include <linux/slab.h>
  25. #include <linux/delay.h>
  26. #include <linux/etherdevice.h>
  27. #include <linux/eeprom_93cx6.h>
  28. #include <linux/module.h>
  29. #include <net/mac80211.h>
  30. #include "rtl8187.h"
  31. #include "rtl8225.h"
  32. #ifdef CONFIG_RTL8187_LEDS
  33. #include "leds.h"
  34. #endif
  35. #include "rfkill.h"
  36. MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  37. MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
  38. MODULE_AUTHOR("Herton Ronaldo Krzesinski <herton@mandriva.com.br>");
  39. MODULE_AUTHOR("Hin-Tak Leung <htl10@users.sourceforge.net>");
  40. MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
  41. MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
  42. MODULE_LICENSE("GPL");
  43. static struct usb_device_id rtl8187_table[] __devinitdata = {
  44. /* Asus */
  45. {USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187},
  46. /* Belkin */
  47. {USB_DEVICE(0x050d, 0x705e), .driver_info = DEVICE_RTL8187B},
  48. /* Realtek */
  49. {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
  50. {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
  51. {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
  52. {USB_DEVICE(0x0bda, 0x8198), .driver_info = DEVICE_RTL8187B},
  53. /* Surecom */
  54. {USB_DEVICE(0x0769, 0x11F2), .driver_info = DEVICE_RTL8187},
  55. /* Logitech */
  56. {USB_DEVICE(0x0789, 0x010C), .driver_info = DEVICE_RTL8187},
  57. /* Netgear */
  58. {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
  59. {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
  60. {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
  61. /* HP */
  62. {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
  63. /* Sitecom */
  64. {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
  65. {USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B},
  66. {USB_DEVICE(0x0df6, 0x0029), .driver_info = DEVICE_RTL8187B},
  67. /* Sphairon Access Systems GmbH */
  68. {USB_DEVICE(0x114B, 0x0150), .driver_info = DEVICE_RTL8187},
  69. /* Dick Smith Electronics */
  70. {USB_DEVICE(0x1371, 0x9401), .driver_info = DEVICE_RTL8187},
  71. /* Abocom */
  72. {USB_DEVICE(0x13d1, 0xabe6), .driver_info = DEVICE_RTL8187},
  73. /* Qcom */
  74. {USB_DEVICE(0x18E8, 0x6232), .driver_info = DEVICE_RTL8187},
  75. /* AirLive */
  76. {USB_DEVICE(0x1b75, 0x8187), .driver_info = DEVICE_RTL8187},
  77. /* Linksys */
  78. {USB_DEVICE(0x1737, 0x0073), .driver_info = DEVICE_RTL8187B},
  79. {}
  80. };
  81. MODULE_DEVICE_TABLE(usb, rtl8187_table);
  82. static const struct ieee80211_rate rtl818x_rates[] = {
  83. { .bitrate = 10, .hw_value = 0, },
  84. { .bitrate = 20, .hw_value = 1, },
  85. { .bitrate = 55, .hw_value = 2, },
  86. { .bitrate = 110, .hw_value = 3, },
  87. { .bitrate = 60, .hw_value = 4, },
  88. { .bitrate = 90, .hw_value = 5, },
  89. { .bitrate = 120, .hw_value = 6, },
  90. { .bitrate = 180, .hw_value = 7, },
  91. { .bitrate = 240, .hw_value = 8, },
  92. { .bitrate = 360, .hw_value = 9, },
  93. { .bitrate = 480, .hw_value = 10, },
  94. { .bitrate = 540, .hw_value = 11, },
  95. };
  96. static const struct ieee80211_channel rtl818x_channels[] = {
  97. { .center_freq = 2412 },
  98. { .center_freq = 2417 },
  99. { .center_freq = 2422 },
  100. { .center_freq = 2427 },
  101. { .center_freq = 2432 },
  102. { .center_freq = 2437 },
  103. { .center_freq = 2442 },
  104. { .center_freq = 2447 },
  105. { .center_freq = 2452 },
  106. { .center_freq = 2457 },
  107. { .center_freq = 2462 },
  108. { .center_freq = 2467 },
  109. { .center_freq = 2472 },
  110. { .center_freq = 2484 },
  111. };
  112. static void rtl8187_iowrite_async_cb(struct urb *urb)
  113. {
  114. kfree(urb->context);
  115. }
  116. static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
  117. void *data, u16 len)
  118. {
  119. struct usb_ctrlrequest *dr;
  120. struct urb *urb;
  121. struct rtl8187_async_write_data {
  122. u8 data[4];
  123. struct usb_ctrlrequest dr;
  124. } *buf;
  125. int rc;
  126. buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
  127. if (!buf)
  128. return;
  129. urb = usb_alloc_urb(0, GFP_ATOMIC);
  130. if (!urb) {
  131. kfree(buf);
  132. return;
  133. }
  134. dr = &buf->dr;
  135. dr->bRequestType = RTL8187_REQT_WRITE;
  136. dr->bRequest = RTL8187_REQ_SET_REG;
  137. dr->wValue = addr;
  138. dr->wIndex = 0;
  139. dr->wLength = cpu_to_le16(len);
  140. memcpy(buf, data, len);
  141. usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
  142. (unsigned char *)dr, buf, len,
  143. rtl8187_iowrite_async_cb, buf);
  144. usb_anchor_urb(urb, &priv->anchored);
  145. rc = usb_submit_urb(urb, GFP_ATOMIC);
  146. if (rc < 0) {
  147. kfree(buf);
  148. usb_unanchor_urb(urb);
  149. }
  150. usb_free_urb(urb);
  151. }
  152. static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
  153. __le32 *addr, u32 val)
  154. {
  155. __le32 buf = cpu_to_le32(val);
  156. rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
  157. &buf, sizeof(buf));
  158. }
  159. void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
  160. {
  161. struct rtl8187_priv *priv = dev->priv;
  162. data <<= 8;
  163. data |= addr | 0x80;
  164. rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
  165. rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
  166. rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
  167. rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
  168. }
  169. static void rtl8187_tx_cb(struct urb *urb)
  170. {
  171. struct sk_buff *skb = (struct sk_buff *)urb->context;
  172. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  173. struct ieee80211_hw *hw = info->rate_driver_data[0];
  174. struct rtl8187_priv *priv = hw->priv;
  175. skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
  176. sizeof(struct rtl8187_tx_hdr));
  177. ieee80211_tx_info_clear_status(info);
  178. if (!(urb->status) && !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  179. if (priv->is_rtl8187b) {
  180. skb_queue_tail(&priv->b_tx_status.queue, skb);
  181. /* queue is "full", discard last items */
  182. while (skb_queue_len(&priv->b_tx_status.queue) > 5) {
  183. struct sk_buff *old_skb;
  184. dev_dbg(&priv->udev->dev,
  185. "transmit status queue full\n");
  186. old_skb = skb_dequeue(&priv->b_tx_status.queue);
  187. ieee80211_tx_status_irqsafe(hw, old_skb);
  188. }
  189. return;
  190. } else {
  191. info->flags |= IEEE80211_TX_STAT_ACK;
  192. }
  193. }
  194. if (priv->is_rtl8187b)
  195. ieee80211_tx_status_irqsafe(hw, skb);
  196. else {
  197. /* Retry information for the RTI8187 is only available by
  198. * reading a register in the device. We are in interrupt mode
  199. * here, thus queue the skb and finish on a work queue. */
  200. skb_queue_tail(&priv->b_tx_status.queue, skb);
  201. ieee80211_queue_delayed_work(hw, &priv->work, 0);
  202. }
  203. }
  204. static void rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
  205. {
  206. struct rtl8187_priv *priv = dev->priv;
  207. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  208. struct ieee80211_hdr *tx_hdr = (struct ieee80211_hdr *)(skb->data);
  209. unsigned int ep;
  210. void *buf;
  211. struct urb *urb;
  212. __le16 rts_dur = 0;
  213. u32 flags;
  214. int rc;
  215. urb = usb_alloc_urb(0, GFP_ATOMIC);
  216. if (!urb) {
  217. kfree_skb(skb);
  218. return;
  219. }
  220. flags = skb->len;
  221. flags |= RTL818X_TX_DESC_FLAG_NO_ENC;
  222. flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
  223. if (ieee80211_has_morefrags(tx_hdr->frame_control))
  224. flags |= RTL818X_TX_DESC_FLAG_MOREFRAG;
  225. if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  226. flags |= RTL818X_TX_DESC_FLAG_RTS;
  227. flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
  228. rts_dur = ieee80211_rts_duration(dev, priv->vif,
  229. skb->len, info);
  230. } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  231. flags |= RTL818X_TX_DESC_FLAG_CTS;
  232. flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
  233. }
  234. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  235. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  236. priv->seqno += 0x10;
  237. tx_hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  238. tx_hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
  239. }
  240. if (!priv->is_rtl8187b) {
  241. struct rtl8187_tx_hdr *hdr =
  242. (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
  243. hdr->flags = cpu_to_le32(flags);
  244. hdr->len = 0;
  245. hdr->rts_duration = rts_dur;
  246. hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
  247. buf = hdr;
  248. ep = 2;
  249. } else {
  250. /* fc needs to be calculated before skb_push() */
  251. unsigned int epmap[4] = { 6, 7, 5, 4 };
  252. u16 fc = le16_to_cpu(tx_hdr->frame_control);
  253. struct rtl8187b_tx_hdr *hdr =
  254. (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
  255. struct ieee80211_rate *txrate =
  256. ieee80211_get_tx_rate(dev, info);
  257. memset(hdr, 0, sizeof(*hdr));
  258. hdr->flags = cpu_to_le32(flags);
  259. hdr->rts_duration = rts_dur;
  260. hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
  261. hdr->tx_duration =
  262. ieee80211_generic_frame_duration(dev, priv->vif,
  263. skb->len, txrate);
  264. buf = hdr;
  265. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
  266. ep = 12;
  267. else
  268. ep = epmap[skb_get_queue_mapping(skb)];
  269. }
  270. info->rate_driver_data[0] = dev;
  271. info->rate_driver_data[1] = urb;
  272. usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
  273. buf, skb->len, rtl8187_tx_cb, skb);
  274. urb->transfer_flags |= URB_ZERO_PACKET;
  275. usb_anchor_urb(urb, &priv->anchored);
  276. rc = usb_submit_urb(urb, GFP_ATOMIC);
  277. if (rc < 0) {
  278. usb_unanchor_urb(urb);
  279. kfree_skb(skb);
  280. }
  281. usb_free_urb(urb);
  282. }
  283. static void rtl8187_rx_cb(struct urb *urb)
  284. {
  285. struct sk_buff *skb = (struct sk_buff *)urb->context;
  286. struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
  287. struct ieee80211_hw *dev = info->dev;
  288. struct rtl8187_priv *priv = dev->priv;
  289. struct ieee80211_rx_status rx_status = { 0 };
  290. int rate, signal;
  291. u32 flags;
  292. unsigned long f;
  293. spin_lock_irqsave(&priv->rx_queue.lock, f);
  294. __skb_unlink(skb, &priv->rx_queue);
  295. spin_unlock_irqrestore(&priv->rx_queue.lock, f);
  296. skb_put(skb, urb->actual_length);
  297. if (unlikely(urb->status)) {
  298. dev_kfree_skb_irq(skb);
  299. return;
  300. }
  301. if (!priv->is_rtl8187b) {
  302. struct rtl8187_rx_hdr *hdr =
  303. (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
  304. flags = le32_to_cpu(hdr->flags);
  305. /* As with the RTL8187B below, the AGC is used to calculate
  306. * signal strength. In this case, the scaling
  307. * constants are derived from the output of p54usb.
  308. */
  309. signal = -4 - ((27 * hdr->agc) >> 6);
  310. rx_status.antenna = (hdr->signal >> 7) & 1;
  311. rx_status.mactime = le64_to_cpu(hdr->mac_time);
  312. } else {
  313. struct rtl8187b_rx_hdr *hdr =
  314. (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
  315. /* The Realtek datasheet for the RTL8187B shows that the RX
  316. * header contains the following quantities: signal quality,
  317. * RSSI, AGC, the received power in dB, and the measured SNR.
  318. * In testing, none of these quantities show qualitative
  319. * agreement with AP signal strength, except for the AGC,
  320. * which is inversely proportional to the strength of the
  321. * signal. In the following, the signal strength
  322. * is derived from the AGC. The arbitrary scaling constants
  323. * are chosen to make the results close to the values obtained
  324. * for a BCM4312 using b43 as the driver. The noise is ignored
  325. * for now.
  326. */
  327. flags = le32_to_cpu(hdr->flags);
  328. signal = 14 - hdr->agc / 2;
  329. rx_status.antenna = (hdr->rssi >> 7) & 1;
  330. rx_status.mactime = le64_to_cpu(hdr->mac_time);
  331. }
  332. rx_status.signal = signal;
  333. priv->signal = signal;
  334. rate = (flags >> 20) & 0xF;
  335. skb_trim(skb, flags & 0x0FFF);
  336. rx_status.rate_idx = rate;
  337. rx_status.freq = dev->conf.channel->center_freq;
  338. rx_status.band = dev->conf.channel->band;
  339. rx_status.flag |= RX_FLAG_MACTIME_MPDU;
  340. if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
  341. rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
  342. memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
  343. ieee80211_rx_irqsafe(dev, skb);
  344. skb = dev_alloc_skb(RTL8187_MAX_RX);
  345. if (unlikely(!skb)) {
  346. /* TODO check rx queue length and refill *somewhere* */
  347. return;
  348. }
  349. info = (struct rtl8187_rx_info *)skb->cb;
  350. info->urb = urb;
  351. info->dev = dev;
  352. urb->transfer_buffer = skb_tail_pointer(skb);
  353. urb->context = skb;
  354. skb_queue_tail(&priv->rx_queue, skb);
  355. usb_anchor_urb(urb, &priv->anchored);
  356. if (usb_submit_urb(urb, GFP_ATOMIC)) {
  357. usb_unanchor_urb(urb);
  358. skb_unlink(skb, &priv->rx_queue);
  359. dev_kfree_skb_irq(skb);
  360. }
  361. }
  362. static int rtl8187_init_urbs(struct ieee80211_hw *dev)
  363. {
  364. struct rtl8187_priv *priv = dev->priv;
  365. struct urb *entry = NULL;
  366. struct sk_buff *skb;
  367. struct rtl8187_rx_info *info;
  368. int ret = 0;
  369. while (skb_queue_len(&priv->rx_queue) < 16) {
  370. skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
  371. if (!skb) {
  372. ret = -ENOMEM;
  373. goto err;
  374. }
  375. entry = usb_alloc_urb(0, GFP_KERNEL);
  376. if (!entry) {
  377. ret = -ENOMEM;
  378. goto err;
  379. }
  380. usb_fill_bulk_urb(entry, priv->udev,
  381. usb_rcvbulkpipe(priv->udev,
  382. priv->is_rtl8187b ? 3 : 1),
  383. skb_tail_pointer(skb),
  384. RTL8187_MAX_RX, rtl8187_rx_cb, skb);
  385. info = (struct rtl8187_rx_info *)skb->cb;
  386. info->urb = entry;
  387. info->dev = dev;
  388. skb_queue_tail(&priv->rx_queue, skb);
  389. usb_anchor_urb(entry, &priv->anchored);
  390. ret = usb_submit_urb(entry, GFP_KERNEL);
  391. if (ret) {
  392. skb_unlink(skb, &priv->rx_queue);
  393. usb_unanchor_urb(entry);
  394. goto err;
  395. }
  396. usb_free_urb(entry);
  397. }
  398. return ret;
  399. err:
  400. usb_free_urb(entry);
  401. kfree_skb(skb);
  402. usb_kill_anchored_urbs(&priv->anchored);
  403. return ret;
  404. }
  405. static void rtl8187b_status_cb(struct urb *urb)
  406. {
  407. struct ieee80211_hw *hw = (struct ieee80211_hw *)urb->context;
  408. struct rtl8187_priv *priv = hw->priv;
  409. u64 val;
  410. unsigned int cmd_type;
  411. if (unlikely(urb->status))
  412. return;
  413. /*
  414. * Read from status buffer:
  415. *
  416. * bits [30:31] = cmd type:
  417. * - 0 indicates tx beacon interrupt
  418. * - 1 indicates tx close descriptor
  419. *
  420. * In the case of tx beacon interrupt:
  421. * [0:9] = Last Beacon CW
  422. * [10:29] = reserved
  423. * [30:31] = 00b
  424. * [32:63] = Last Beacon TSF
  425. *
  426. * If it's tx close descriptor:
  427. * [0:7] = Packet Retry Count
  428. * [8:14] = RTS Retry Count
  429. * [15] = TOK
  430. * [16:27] = Sequence No
  431. * [28] = LS
  432. * [29] = FS
  433. * [30:31] = 01b
  434. * [32:47] = unused (reserved?)
  435. * [48:63] = MAC Used Time
  436. */
  437. val = le64_to_cpu(priv->b_tx_status.buf);
  438. cmd_type = (val >> 30) & 0x3;
  439. if (cmd_type == 1) {
  440. unsigned int pkt_rc, seq_no;
  441. bool tok;
  442. struct sk_buff *skb;
  443. struct ieee80211_hdr *ieee80211hdr;
  444. unsigned long flags;
  445. pkt_rc = val & 0xFF;
  446. tok = val & (1 << 15);
  447. seq_no = (val >> 16) & 0xFFF;
  448. spin_lock_irqsave(&priv->b_tx_status.queue.lock, flags);
  449. skb_queue_reverse_walk(&priv->b_tx_status.queue, skb) {
  450. ieee80211hdr = (struct ieee80211_hdr *)skb->data;
  451. /*
  452. * While testing, it was discovered that the seq_no
  453. * doesn't actually contains the sequence number.
  454. * Instead of returning just the 12 bits of sequence
  455. * number, hardware is returning entire sequence control
  456. * (fragment number plus sequence number) in a 12 bit
  457. * only field overflowing after some time. As a
  458. * workaround, just consider the lower bits, and expect
  459. * it's unlikely we wrongly ack some sent data
  460. */
  461. if ((le16_to_cpu(ieee80211hdr->seq_ctrl)
  462. & 0xFFF) == seq_no)
  463. break;
  464. }
  465. if (skb != (struct sk_buff *) &priv->b_tx_status.queue) {
  466. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  467. __skb_unlink(skb, &priv->b_tx_status.queue);
  468. if (tok)
  469. info->flags |= IEEE80211_TX_STAT_ACK;
  470. info->status.rates[0].count = pkt_rc + 1;
  471. ieee80211_tx_status_irqsafe(hw, skb);
  472. }
  473. spin_unlock_irqrestore(&priv->b_tx_status.queue.lock, flags);
  474. }
  475. usb_anchor_urb(urb, &priv->anchored);
  476. if (usb_submit_urb(urb, GFP_ATOMIC))
  477. usb_unanchor_urb(urb);
  478. }
  479. static int rtl8187b_init_status_urb(struct ieee80211_hw *dev)
  480. {
  481. struct rtl8187_priv *priv = dev->priv;
  482. struct urb *entry;
  483. int ret = 0;
  484. entry = usb_alloc_urb(0, GFP_KERNEL);
  485. if (!entry)
  486. return -ENOMEM;
  487. usb_fill_bulk_urb(entry, priv->udev, usb_rcvbulkpipe(priv->udev, 9),
  488. &priv->b_tx_status.buf, sizeof(priv->b_tx_status.buf),
  489. rtl8187b_status_cb, dev);
  490. usb_anchor_urb(entry, &priv->anchored);
  491. ret = usb_submit_urb(entry, GFP_KERNEL);
  492. if (ret)
  493. usb_unanchor_urb(entry);
  494. usb_free_urb(entry);
  495. return ret;
  496. }
  497. static void rtl8187_set_anaparam(struct rtl8187_priv *priv, bool rfon)
  498. {
  499. u32 anaparam, anaparam2;
  500. u8 anaparam3, reg;
  501. if (!priv->is_rtl8187b) {
  502. if (rfon) {
  503. anaparam = RTL8187_RTL8225_ANAPARAM_ON;
  504. anaparam2 = RTL8187_RTL8225_ANAPARAM2_ON;
  505. } else {
  506. anaparam = RTL8187_RTL8225_ANAPARAM_OFF;
  507. anaparam2 = RTL8187_RTL8225_ANAPARAM2_OFF;
  508. }
  509. } else {
  510. if (rfon) {
  511. anaparam = RTL8187B_RTL8225_ANAPARAM_ON;
  512. anaparam2 = RTL8187B_RTL8225_ANAPARAM2_ON;
  513. anaparam3 = RTL8187B_RTL8225_ANAPARAM3_ON;
  514. } else {
  515. anaparam = RTL8187B_RTL8225_ANAPARAM_OFF;
  516. anaparam2 = RTL8187B_RTL8225_ANAPARAM2_OFF;
  517. anaparam3 = RTL8187B_RTL8225_ANAPARAM3_OFF;
  518. }
  519. }
  520. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
  521. RTL818X_EEPROM_CMD_CONFIG);
  522. reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
  523. reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
  524. rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
  525. rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
  526. rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, anaparam2);
  527. if (priv->is_rtl8187b)
  528. rtl818x_iowrite8(priv, &priv->map->ANAPARAM3, anaparam3);
  529. reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
  530. rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
  531. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
  532. RTL818X_EEPROM_CMD_NORMAL);
  533. }
  534. static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
  535. {
  536. struct rtl8187_priv *priv = dev->priv;
  537. u8 reg;
  538. int i;
  539. reg = rtl818x_ioread8(priv, &priv->map->CMD);
  540. reg &= (1 << 1);
  541. reg |= RTL818X_CMD_RESET;
  542. rtl818x_iowrite8(priv, &priv->map->CMD, reg);
  543. i = 10;
  544. do {
  545. msleep(2);
  546. if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
  547. RTL818X_CMD_RESET))
  548. break;
  549. } while (--i);
  550. if (!i) {
  551. wiphy_err(dev->wiphy, "Reset timeout!\n");
  552. return -ETIMEDOUT;
  553. }
  554. /* reload registers from eeprom */
  555. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
  556. i = 10;
  557. do {
  558. msleep(4);
  559. if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
  560. RTL818X_EEPROM_CMD_CONFIG))
  561. break;
  562. } while (--i);
  563. if (!i) {
  564. wiphy_err(dev->wiphy, "eeprom reset timeout!\n");
  565. return -ETIMEDOUT;
  566. }
  567. return 0;
  568. }
  569. static int rtl8187_init_hw(struct ieee80211_hw *dev)
  570. {
  571. struct rtl8187_priv *priv = dev->priv;
  572. u8 reg;
  573. int res;
  574. /* reset */
  575. rtl8187_set_anaparam(priv, true);
  576. rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
  577. msleep(200);
  578. rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
  579. rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
  580. rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
  581. msleep(200);
  582. res = rtl8187_cmd_reset(dev);
  583. if (res)
  584. return res;
  585. rtl8187_set_anaparam(priv, true);
  586. /* setup card */
  587. rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
  588. rtl818x_iowrite8(priv, &priv->map->GPIO0, 0);
  589. rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
  590. rtl818x_iowrite8(priv, &priv->map->GPIO0, 1);
  591. rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
  592. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
  593. rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
  594. reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
  595. reg &= 0x3F;
  596. reg |= 0x80;
  597. rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
  598. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
  599. rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
  600. rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
  601. rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0);
  602. // TODO: set RESP_RATE and BRSR properly
  603. rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
  604. rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
  605. /* host_usb_init */
  606. rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
  607. rtl818x_iowrite8(priv, &priv->map->GPIO0, 0);
  608. reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
  609. rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
  610. rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
  611. rtl818x_iowrite8(priv, &priv->map->GPIO0, 0x20);
  612. rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
  613. rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
  614. rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
  615. rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
  616. msleep(100);
  617. rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
  618. rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
  619. rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
  620. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
  621. RTL818X_EEPROM_CMD_CONFIG);
  622. rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
  623. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
  624. RTL818X_EEPROM_CMD_NORMAL);
  625. rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
  626. msleep(100);
  627. priv->rf->init(dev);
  628. rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
  629. reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
  630. rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
  631. rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
  632. rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
  633. rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
  634. rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
  635. return 0;
  636. }
  637. static const u8 rtl8187b_reg_table[][3] = {
  638. {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
  639. {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
  640. {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
  641. {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
  642. {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
  643. {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
  644. {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1},
  645. {0xF2, 0x02, 1}, {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1},
  646. {0xF6, 0x06, 1}, {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
  647. {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
  648. {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
  649. {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
  650. {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
  651. {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
  652. {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
  653. {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2},
  654. {0x5B, 0x40, 0}, {0x84, 0x88, 0}, {0x85, 0x24, 0}, {0x88, 0x54, 0},
  655. {0x8B, 0xB8, 0}, {0x8C, 0x07, 0}, {0x8D, 0x00, 0}, {0x94, 0x1B, 0},
  656. {0x95, 0x12, 0}, {0x96, 0x00, 0}, {0x97, 0x06, 0}, {0x9D, 0x1A, 0},
  657. {0x9F, 0x10, 0}, {0xB4, 0x22, 0}, {0xBE, 0x80, 0}, {0xDB, 0x00, 0},
  658. {0xEE, 0x00, 0}, {0x4C, 0x00, 2},
  659. {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0}, {0x8E, 0x08, 0},
  660. {0x8F, 0x00, 0}
  661. };
  662. static int rtl8187b_init_hw(struct ieee80211_hw *dev)
  663. {
  664. struct rtl8187_priv *priv = dev->priv;
  665. int res, i;
  666. u8 reg;
  667. rtl8187_set_anaparam(priv, true);
  668. /* Reset PLL sequence on 8187B. Realtek note: reduces power
  669. * consumption about 30 mA */
  670. rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
  671. reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
  672. rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
  673. rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
  674. res = rtl8187_cmd_reset(dev);
  675. if (res)
  676. return res;
  677. rtl8187_set_anaparam(priv, true);
  678. /* BRSR (Basic Rate Set Register) on 8187B looks to be the same as
  679. * RESP_RATE on 8187L in Realtek sources: each bit should be each
  680. * one of the 12 rates, all are enabled */
  681. rtl818x_iowrite16(priv, (__le16 *)0xFF34, 0x0FFF);
  682. reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
  683. reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
  684. rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
  685. /* Auto Rate Fallback Register (ARFR): 1M-54M setting */
  686. rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
  687. rtl818x_iowrite8_idx(priv, (u8 *)0xFFE2, 0x00, 1);
  688. rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
  689. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
  690. RTL818X_EEPROM_CMD_CONFIG);
  691. reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
  692. rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
  693. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
  694. RTL818X_EEPROM_CMD_NORMAL);
  695. rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
  696. for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
  697. rtl818x_iowrite8_idx(priv,
  698. (u8 *)(uintptr_t)
  699. (rtl8187b_reg_table[i][0] | 0xFF00),
  700. rtl8187b_reg_table[i][1],
  701. rtl8187b_reg_table[i][2]);
  702. }
  703. rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
  704. rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
  705. rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
  706. rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
  707. rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
  708. rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
  709. /* RFSW_CTRL register */
  710. rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
  711. rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
  712. rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
  713. rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
  714. msleep(100);
  715. priv->rf->init(dev);
  716. reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
  717. rtl818x_iowrite8(priv, &priv->map->CMD, reg);
  718. rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
  719. rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
  720. rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
  721. rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
  722. rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
  723. rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
  724. rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
  725. rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
  726. reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
  727. rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
  728. rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
  729. rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
  730. rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
  731. rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
  732. rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
  733. rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
  734. rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
  735. rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
  736. rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
  737. rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
  738. rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
  739. rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
  740. rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
  741. priv->slot_time = 0x9;
  742. priv->aifsn[0] = 2; /* AIFSN[AC_VO] */
  743. priv->aifsn[1] = 2; /* AIFSN[AC_VI] */
  744. priv->aifsn[2] = 7; /* AIFSN[AC_BK] */
  745. priv->aifsn[3] = 3; /* AIFSN[AC_BE] */
  746. rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0);
  747. /* ENEDCA flag must always be set, transmit issues? */
  748. rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_ENEDCA);
  749. return 0;
  750. }
  751. static void rtl8187_work(struct work_struct *work)
  752. {
  753. /* The RTL8187 returns the retry count through register 0xFFFA. In
  754. * addition, it appears to be a cumulative retry count, not the
  755. * value for the current TX packet. When multiple TX entries are
  756. * waiting in the queue, the retry count will be the total for all.
  757. * The "error" may matter for purposes of rate setting, but there is
  758. * no other choice with this hardware.
  759. */
  760. struct rtl8187_priv *priv = container_of(work, struct rtl8187_priv,
  761. work.work);
  762. struct ieee80211_tx_info *info;
  763. struct ieee80211_hw *dev = priv->dev;
  764. static u16 retry;
  765. u16 tmp;
  766. u16 avg_retry;
  767. int length;
  768. mutex_lock(&priv->conf_mutex);
  769. tmp = rtl818x_ioread16(priv, (__le16 *)0xFFFA);
  770. length = skb_queue_len(&priv->b_tx_status.queue);
  771. if (unlikely(!length))
  772. length = 1;
  773. if (unlikely(tmp < retry))
  774. tmp = retry;
  775. avg_retry = (tmp - retry) / length;
  776. while (skb_queue_len(&priv->b_tx_status.queue) > 0) {
  777. struct sk_buff *old_skb;
  778. old_skb = skb_dequeue(&priv->b_tx_status.queue);
  779. info = IEEE80211_SKB_CB(old_skb);
  780. info->status.rates[0].count = avg_retry + 1;
  781. if (info->status.rates[0].count > RETRY_COUNT)
  782. info->flags &= ~IEEE80211_TX_STAT_ACK;
  783. ieee80211_tx_status_irqsafe(dev, old_skb);
  784. }
  785. retry = tmp;
  786. mutex_unlock(&priv->conf_mutex);
  787. }
  788. static int rtl8187_start(struct ieee80211_hw *dev)
  789. {
  790. struct rtl8187_priv *priv = dev->priv;
  791. u32 reg;
  792. int ret;
  793. mutex_lock(&priv->conf_mutex);
  794. ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
  795. rtl8187b_init_hw(dev);
  796. if (ret)
  797. goto rtl8187_start_exit;
  798. init_usb_anchor(&priv->anchored);
  799. priv->dev = dev;
  800. if (priv->is_rtl8187b) {
  801. reg = RTL818X_RX_CONF_MGMT |
  802. RTL818X_RX_CONF_DATA |
  803. RTL818X_RX_CONF_BROADCAST |
  804. RTL818X_RX_CONF_NICMAC |
  805. RTL818X_RX_CONF_BSSID |
  806. (7 << 13 /* RX FIFO threshold NONE */) |
  807. (7 << 10 /* MAX RX DMA */) |
  808. RTL818X_RX_CONF_RX_AUTORESETPHY |
  809. RTL818X_RX_CONF_ONLYERLPKT |
  810. RTL818X_RX_CONF_MULTICAST;
  811. priv->rx_conf = reg;
  812. rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
  813. reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
  814. reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
  815. reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
  816. reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
  817. rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
  818. rtl818x_iowrite32(priv, &priv->map->TX_CONF,
  819. RTL818X_TX_CONF_HW_SEQNUM |
  820. RTL818X_TX_CONF_DISREQQSIZE |
  821. (RETRY_COUNT << 8 /* short retry limit */) |
  822. (RETRY_COUNT << 0 /* long retry limit */) |
  823. (7 << 21 /* MAX TX DMA */));
  824. rtl8187_init_urbs(dev);
  825. rtl8187b_init_status_urb(dev);
  826. goto rtl8187_start_exit;
  827. }
  828. rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
  829. rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
  830. rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
  831. rtl8187_init_urbs(dev);
  832. reg = RTL818X_RX_CONF_ONLYERLPKT |
  833. RTL818X_RX_CONF_RX_AUTORESETPHY |
  834. RTL818X_RX_CONF_BSSID |
  835. RTL818X_RX_CONF_MGMT |
  836. RTL818X_RX_CONF_DATA |
  837. (7 << 13 /* RX FIFO threshold NONE */) |
  838. (7 << 10 /* MAX RX DMA */) |
  839. RTL818X_RX_CONF_BROADCAST |
  840. RTL818X_RX_CONF_NICMAC;
  841. priv->rx_conf = reg;
  842. rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
  843. reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
  844. reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
  845. reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
  846. rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
  847. reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
  848. reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
  849. reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
  850. reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
  851. rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
  852. reg = RTL818X_TX_CONF_CW_MIN |
  853. (7 << 21 /* MAX TX DMA */) |
  854. RTL818X_TX_CONF_NO_ICV;
  855. rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
  856. reg = rtl818x_ioread8(priv, &priv->map->CMD);
  857. reg |= RTL818X_CMD_TX_ENABLE;
  858. reg |= RTL818X_CMD_RX_ENABLE;
  859. rtl818x_iowrite8(priv, &priv->map->CMD, reg);
  860. INIT_DELAYED_WORK(&priv->work, rtl8187_work);
  861. rtl8187_start_exit:
  862. mutex_unlock(&priv->conf_mutex);
  863. return ret;
  864. }
  865. static void rtl8187_stop(struct ieee80211_hw *dev)
  866. {
  867. struct rtl8187_priv *priv = dev->priv;
  868. struct sk_buff *skb;
  869. u32 reg;
  870. mutex_lock(&priv->conf_mutex);
  871. rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
  872. reg = rtl818x_ioread8(priv, &priv->map->CMD);
  873. reg &= ~RTL818X_CMD_TX_ENABLE;
  874. reg &= ~RTL818X_CMD_RX_ENABLE;
  875. rtl818x_iowrite8(priv, &priv->map->CMD, reg);
  876. priv->rf->stop(dev);
  877. rtl8187_set_anaparam(priv, false);
  878. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
  879. reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
  880. rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
  881. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
  882. while ((skb = skb_dequeue(&priv->b_tx_status.queue)))
  883. dev_kfree_skb_any(skb);
  884. usb_kill_anchored_urbs(&priv->anchored);
  885. mutex_unlock(&priv->conf_mutex);
  886. if (!priv->is_rtl8187b)
  887. cancel_delayed_work_sync(&priv->work);
  888. }
  889. static u64 rtl8187_get_tsf(struct ieee80211_hw *dev, struct ieee80211_vif *vif)
  890. {
  891. struct rtl8187_priv *priv = dev->priv;
  892. return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
  893. (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
  894. }
  895. static void rtl8187_beacon_work(struct work_struct *work)
  896. {
  897. struct rtl8187_vif *vif_priv =
  898. container_of(work, struct rtl8187_vif, beacon_work.work);
  899. struct ieee80211_vif *vif =
  900. container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
  901. struct ieee80211_hw *dev = vif_priv->dev;
  902. struct ieee80211_mgmt *mgmt;
  903. struct sk_buff *skb;
  904. /* don't overflow the tx ring */
  905. if (ieee80211_queue_stopped(dev, 0))
  906. goto resched;
  907. /* grab a fresh beacon */
  908. skb = ieee80211_beacon_get(dev, vif);
  909. if (!skb)
  910. goto resched;
  911. /*
  912. * update beacon timestamp w/ TSF value
  913. * TODO: make hardware update beacon timestamp
  914. */
  915. mgmt = (struct ieee80211_mgmt *)skb->data;
  916. mgmt->u.beacon.timestamp = cpu_to_le64(rtl8187_get_tsf(dev, vif));
  917. /* TODO: use actual beacon queue */
  918. skb_set_queue_mapping(skb, 0);
  919. rtl8187_tx(dev, skb);
  920. resched:
  921. /*
  922. * schedule next beacon
  923. * TODO: use hardware support for beacon timing
  924. */
  925. schedule_delayed_work(&vif_priv->beacon_work,
  926. usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
  927. }
  928. static int rtl8187_add_interface(struct ieee80211_hw *dev,
  929. struct ieee80211_vif *vif)
  930. {
  931. struct rtl8187_priv *priv = dev->priv;
  932. struct rtl8187_vif *vif_priv;
  933. int i;
  934. int ret = -EOPNOTSUPP;
  935. mutex_lock(&priv->conf_mutex);
  936. if (priv->vif)
  937. goto exit;
  938. switch (vif->type) {
  939. case NL80211_IFTYPE_STATION:
  940. case NL80211_IFTYPE_ADHOC:
  941. break;
  942. default:
  943. goto exit;
  944. }
  945. ret = 0;
  946. priv->vif = vif;
  947. /* Initialize driver private area */
  948. vif_priv = (struct rtl8187_vif *)&vif->drv_priv;
  949. vif_priv->dev = dev;
  950. INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8187_beacon_work);
  951. vif_priv->enable_beacon = false;
  952. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
  953. for (i = 0; i < ETH_ALEN; i++)
  954. rtl818x_iowrite8(priv, &priv->map->MAC[i],
  955. ((u8 *)vif->addr)[i]);
  956. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
  957. exit:
  958. mutex_unlock(&priv->conf_mutex);
  959. return ret;
  960. }
  961. static void rtl8187_remove_interface(struct ieee80211_hw *dev,
  962. struct ieee80211_vif *vif)
  963. {
  964. struct rtl8187_priv *priv = dev->priv;
  965. mutex_lock(&priv->conf_mutex);
  966. priv->vif = NULL;
  967. mutex_unlock(&priv->conf_mutex);
  968. }
  969. static int rtl8187_config(struct ieee80211_hw *dev, u32 changed)
  970. {
  971. struct rtl8187_priv *priv = dev->priv;
  972. struct ieee80211_conf *conf = &dev->conf;
  973. u32 reg;
  974. mutex_lock(&priv->conf_mutex);
  975. reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
  976. /* Enable TX loopback on MAC level to avoid TX during channel
  977. * changes, as this has be seen to causes problems and the
  978. * card will stop work until next reset
  979. */
  980. rtl818x_iowrite32(priv, &priv->map->TX_CONF,
  981. reg | RTL818X_TX_CONF_LOOPBACK_MAC);
  982. priv->rf->set_chan(dev, conf);
  983. msleep(10);
  984. rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
  985. rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
  986. rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
  987. rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
  988. rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
  989. mutex_unlock(&priv->conf_mutex);
  990. return 0;
  991. }
  992. /*
  993. * With 8187B, AC_*_PARAM clashes with FEMR definition in struct rtl818x_csr for
  994. * example. Thus we have to use raw values for AC_*_PARAM register addresses.
  995. */
  996. static __le32 *rtl8187b_ac_addr[4] = {
  997. (__le32 *) 0xFFF0, /* AC_VO */
  998. (__le32 *) 0xFFF4, /* AC_VI */
  999. (__le32 *) 0xFFFC, /* AC_BK */
  1000. (__le32 *) 0xFFF8, /* AC_BE */
  1001. };
  1002. #define SIFS_TIME 0xa
  1003. static void rtl8187_conf_erp(struct rtl8187_priv *priv, bool use_short_slot,
  1004. bool use_short_preamble)
  1005. {
  1006. if (priv->is_rtl8187b) {
  1007. u8 difs, eifs;
  1008. u16 ack_timeout;
  1009. int queue;
  1010. if (use_short_slot) {
  1011. priv->slot_time = 0x9;
  1012. difs = 0x1c;
  1013. eifs = 0x53;
  1014. } else {
  1015. priv->slot_time = 0x14;
  1016. difs = 0x32;
  1017. eifs = 0x5b;
  1018. }
  1019. rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
  1020. rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
  1021. rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
  1022. /*
  1023. * BRSR+1 on 8187B is in fact EIFS register
  1024. * Value in units of 4 us
  1025. */
  1026. rtl818x_iowrite8(priv, (u8 *)&priv->map->BRSR + 1, eifs);
  1027. /*
  1028. * For 8187B, CARRIER_SENSE_COUNTER is in fact ack timeout
  1029. * register. In units of 4 us like eifs register
  1030. * ack_timeout = ack duration + plcp + difs + preamble
  1031. */
  1032. ack_timeout = 112 + 48 + difs;
  1033. if (use_short_preamble)
  1034. ack_timeout += 72;
  1035. else
  1036. ack_timeout += 144;
  1037. rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER,
  1038. DIV_ROUND_UP(ack_timeout, 4));
  1039. for (queue = 0; queue < 4; queue++)
  1040. rtl818x_iowrite8(priv, (u8 *) rtl8187b_ac_addr[queue],
  1041. priv->aifsn[queue] * priv->slot_time +
  1042. SIFS_TIME);
  1043. } else {
  1044. rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
  1045. if (use_short_slot) {
  1046. rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
  1047. rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
  1048. rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
  1049. } else {
  1050. rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
  1051. rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
  1052. rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
  1053. }
  1054. }
  1055. }
  1056. static void rtl8187_bss_info_changed(struct ieee80211_hw *dev,
  1057. struct ieee80211_vif *vif,
  1058. struct ieee80211_bss_conf *info,
  1059. u32 changed)
  1060. {
  1061. struct rtl8187_priv *priv = dev->priv;
  1062. struct rtl8187_vif *vif_priv;
  1063. int i;
  1064. u8 reg;
  1065. vif_priv = (struct rtl8187_vif *)&vif->drv_priv;
  1066. if (changed & BSS_CHANGED_BSSID) {
  1067. mutex_lock(&priv->conf_mutex);
  1068. for (i = 0; i < ETH_ALEN; i++)
  1069. rtl818x_iowrite8(priv, &priv->map->BSSID[i],
  1070. info->bssid[i]);
  1071. if (priv->is_rtl8187b)
  1072. reg = RTL818X_MSR_ENEDCA;
  1073. else
  1074. reg = 0;
  1075. if (is_valid_ether_addr(info->bssid)) {
  1076. if (vif->type == NL80211_IFTYPE_ADHOC)
  1077. reg |= RTL818X_MSR_ADHOC;
  1078. else
  1079. reg |= RTL818X_MSR_INFRA;
  1080. }
  1081. else
  1082. reg |= RTL818X_MSR_NO_LINK;
  1083. rtl818x_iowrite8(priv, &priv->map->MSR, reg);
  1084. mutex_unlock(&priv->conf_mutex);
  1085. }
  1086. if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE))
  1087. rtl8187_conf_erp(priv, info->use_short_slot,
  1088. info->use_short_preamble);
  1089. if (changed & BSS_CHANGED_BEACON_ENABLED)
  1090. vif_priv->enable_beacon = info->enable_beacon;
  1091. if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
  1092. cancel_delayed_work_sync(&vif_priv->beacon_work);
  1093. if (vif_priv->enable_beacon)
  1094. schedule_work(&vif_priv->beacon_work.work);
  1095. }
  1096. }
  1097. static u64 rtl8187_prepare_multicast(struct ieee80211_hw *dev,
  1098. struct netdev_hw_addr_list *mc_list)
  1099. {
  1100. return netdev_hw_addr_list_count(mc_list);
  1101. }
  1102. static void rtl8187_configure_filter(struct ieee80211_hw *dev,
  1103. unsigned int changed_flags,
  1104. unsigned int *total_flags,
  1105. u64 multicast)
  1106. {
  1107. struct rtl8187_priv *priv = dev->priv;
  1108. if (changed_flags & FIF_FCSFAIL)
  1109. priv->rx_conf ^= RTL818X_RX_CONF_FCS;
  1110. if (changed_flags & FIF_CONTROL)
  1111. priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
  1112. if (changed_flags & FIF_OTHER_BSS)
  1113. priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
  1114. if (*total_flags & FIF_ALLMULTI || multicast > 0)
  1115. priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
  1116. else
  1117. priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
  1118. *total_flags = 0;
  1119. if (priv->rx_conf & RTL818X_RX_CONF_FCS)
  1120. *total_flags |= FIF_FCSFAIL;
  1121. if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
  1122. *total_flags |= FIF_CONTROL;
  1123. if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
  1124. *total_flags |= FIF_OTHER_BSS;
  1125. if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
  1126. *total_flags |= FIF_ALLMULTI;
  1127. rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
  1128. }
  1129. static int rtl8187_conf_tx(struct ieee80211_hw *dev,
  1130. struct ieee80211_vif *vif, u16 queue,
  1131. const struct ieee80211_tx_queue_params *params)
  1132. {
  1133. struct rtl8187_priv *priv = dev->priv;
  1134. u8 cw_min, cw_max;
  1135. if (queue > 3)
  1136. return -EINVAL;
  1137. cw_min = fls(params->cw_min);
  1138. cw_max = fls(params->cw_max);
  1139. if (priv->is_rtl8187b) {
  1140. priv->aifsn[queue] = params->aifs;
  1141. /*
  1142. * This is the structure of AC_*_PARAM registers in 8187B:
  1143. * - TXOP limit field, bit offset = 16
  1144. * - ECWmax, bit offset = 12
  1145. * - ECWmin, bit offset = 8
  1146. * - AIFS, bit offset = 0
  1147. */
  1148. rtl818x_iowrite32(priv, rtl8187b_ac_addr[queue],
  1149. (params->txop << 16) | (cw_max << 12) |
  1150. (cw_min << 8) | (params->aifs *
  1151. priv->slot_time + SIFS_TIME));
  1152. } else {
  1153. if (queue != 0)
  1154. return -EINVAL;
  1155. rtl818x_iowrite8(priv, &priv->map->CW_VAL,
  1156. cw_min | (cw_max << 4));
  1157. }
  1158. return 0;
  1159. }
  1160. static const struct ieee80211_ops rtl8187_ops = {
  1161. .tx = rtl8187_tx,
  1162. .start = rtl8187_start,
  1163. .stop = rtl8187_stop,
  1164. .add_interface = rtl8187_add_interface,
  1165. .remove_interface = rtl8187_remove_interface,
  1166. .config = rtl8187_config,
  1167. .bss_info_changed = rtl8187_bss_info_changed,
  1168. .prepare_multicast = rtl8187_prepare_multicast,
  1169. .configure_filter = rtl8187_configure_filter,
  1170. .conf_tx = rtl8187_conf_tx,
  1171. .rfkill_poll = rtl8187_rfkill_poll,
  1172. .get_tsf = rtl8187_get_tsf,
  1173. };
  1174. static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
  1175. {
  1176. struct ieee80211_hw *dev = eeprom->data;
  1177. struct rtl8187_priv *priv = dev->priv;
  1178. u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
  1179. eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
  1180. eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
  1181. eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
  1182. eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
  1183. }
  1184. static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
  1185. {
  1186. struct ieee80211_hw *dev = eeprom->data;
  1187. struct rtl8187_priv *priv = dev->priv;
  1188. u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
  1189. if (eeprom->reg_data_in)
  1190. reg |= RTL818X_EEPROM_CMD_WRITE;
  1191. if (eeprom->reg_data_out)
  1192. reg |= RTL818X_EEPROM_CMD_READ;
  1193. if (eeprom->reg_data_clock)
  1194. reg |= RTL818X_EEPROM_CMD_CK;
  1195. if (eeprom->reg_chip_select)
  1196. reg |= RTL818X_EEPROM_CMD_CS;
  1197. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
  1198. udelay(10);
  1199. }
  1200. static int __devinit rtl8187_probe(struct usb_interface *intf,
  1201. const struct usb_device_id *id)
  1202. {
  1203. struct usb_device *udev = interface_to_usbdev(intf);
  1204. struct ieee80211_hw *dev;
  1205. struct rtl8187_priv *priv;
  1206. struct eeprom_93cx6 eeprom;
  1207. struct ieee80211_channel *channel;
  1208. const char *chip_name;
  1209. u16 txpwr, reg;
  1210. u16 product_id = le16_to_cpu(udev->descriptor.idProduct);
  1211. int err, i;
  1212. u8 mac_addr[ETH_ALEN];
  1213. dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
  1214. if (!dev) {
  1215. printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
  1216. return -ENOMEM;
  1217. }
  1218. priv = dev->priv;
  1219. priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
  1220. /* allocate "DMA aware" buffer for register accesses */
  1221. priv->io_dmabuf = kmalloc(sizeof(*priv->io_dmabuf), GFP_KERNEL);
  1222. if (!priv->io_dmabuf) {
  1223. err = -ENOMEM;
  1224. goto err_free_dev;
  1225. }
  1226. mutex_init(&priv->io_mutex);
  1227. SET_IEEE80211_DEV(dev, &intf->dev);
  1228. usb_set_intfdata(intf, dev);
  1229. priv->udev = udev;
  1230. usb_get_dev(udev);
  1231. skb_queue_head_init(&priv->rx_queue);
  1232. BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
  1233. BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
  1234. memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
  1235. memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
  1236. priv->map = (struct rtl818x_csr *)0xFF00;
  1237. priv->band.band = IEEE80211_BAND_2GHZ;
  1238. priv->band.channels = priv->channels;
  1239. priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
  1240. priv->band.bitrates = priv->rates;
  1241. priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
  1242. dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
  1243. dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  1244. IEEE80211_HW_SIGNAL_DBM |
  1245. IEEE80211_HW_RX_INCLUDES_FCS;
  1246. /* Initialize rate-control variables */
  1247. dev->max_rates = 1;
  1248. dev->max_rate_tries = RETRY_COUNT;
  1249. eeprom.data = dev;
  1250. eeprom.register_read = rtl8187_eeprom_register_read;
  1251. eeprom.register_write = rtl8187_eeprom_register_write;
  1252. if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
  1253. eeprom.width = PCI_EEPROM_WIDTH_93C66;
  1254. else
  1255. eeprom.width = PCI_EEPROM_WIDTH_93C46;
  1256. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
  1257. udelay(10);
  1258. eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
  1259. (__le16 __force *)mac_addr, 3);
  1260. if (!is_valid_ether_addr(mac_addr)) {
  1261. printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
  1262. "generated MAC address\n");
  1263. random_ether_addr(mac_addr);
  1264. }
  1265. SET_IEEE80211_PERM_ADDR(dev, mac_addr);
  1266. channel = priv->channels;
  1267. for (i = 0; i < 3; i++) {
  1268. eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
  1269. &txpwr);
  1270. (*channel++).hw_value = txpwr & 0xFF;
  1271. (*channel++).hw_value = txpwr >> 8;
  1272. }
  1273. for (i = 0; i < 2; i++) {
  1274. eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
  1275. &txpwr);
  1276. (*channel++).hw_value = txpwr & 0xFF;
  1277. (*channel++).hw_value = txpwr >> 8;
  1278. }
  1279. eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
  1280. &priv->txpwr_base);
  1281. reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
  1282. rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
  1283. /* 0 means asic B-cut, we should use SW 3 wire
  1284. * bit-by-bit banging for radio. 1 means we can use
  1285. * USB specific request to write radio registers */
  1286. priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
  1287. rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
  1288. rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
  1289. if (!priv->is_rtl8187b) {
  1290. u32 reg32;
  1291. reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
  1292. reg32 &= RTL818X_TX_CONF_HWVER_MASK;
  1293. switch (reg32) {
  1294. case RTL818X_TX_CONF_R8187vD_B:
  1295. /* Some RTL8187B devices have a USB ID of 0x8187
  1296. * detect them here */
  1297. chip_name = "RTL8187BvB(early)";
  1298. priv->is_rtl8187b = 1;
  1299. priv->hw_rev = RTL8187BvB;
  1300. break;
  1301. case RTL818X_TX_CONF_R8187vD:
  1302. chip_name = "RTL8187vD";
  1303. break;
  1304. default:
  1305. chip_name = "RTL8187vB (default)";
  1306. }
  1307. } else {
  1308. /*
  1309. * Force USB request to write radio registers for 8187B, Realtek
  1310. * only uses it in their sources
  1311. */
  1312. /*if (priv->asic_rev == 0) {
  1313. printk(KERN_WARNING "rtl8187: Forcing use of USB "
  1314. "requests to write to radio registers\n");
  1315. priv->asic_rev = 1;
  1316. }*/
  1317. switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
  1318. case RTL818X_R8187B_B:
  1319. chip_name = "RTL8187BvB";
  1320. priv->hw_rev = RTL8187BvB;
  1321. break;
  1322. case RTL818X_R8187B_D:
  1323. chip_name = "RTL8187BvD";
  1324. priv->hw_rev = RTL8187BvD;
  1325. break;
  1326. case RTL818X_R8187B_E:
  1327. chip_name = "RTL8187BvE";
  1328. priv->hw_rev = RTL8187BvE;
  1329. break;
  1330. default:
  1331. chip_name = "RTL8187BvB (default)";
  1332. priv->hw_rev = RTL8187BvB;
  1333. }
  1334. }
  1335. if (!priv->is_rtl8187b) {
  1336. for (i = 0; i < 2; i++) {
  1337. eeprom_93cx6_read(&eeprom,
  1338. RTL8187_EEPROM_TXPWR_CHAN_6 + i,
  1339. &txpwr);
  1340. (*channel++).hw_value = txpwr & 0xFF;
  1341. (*channel++).hw_value = txpwr >> 8;
  1342. }
  1343. } else {
  1344. eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
  1345. &txpwr);
  1346. (*channel++).hw_value = txpwr & 0xFF;
  1347. eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
  1348. (*channel++).hw_value = txpwr & 0xFF;
  1349. eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
  1350. (*channel++).hw_value = txpwr & 0xFF;
  1351. (*channel++).hw_value = txpwr >> 8;
  1352. }
  1353. /* Handle the differing rfkill GPIO bit in different models */
  1354. priv->rfkill_mask = RFKILL_MASK_8187_89_97;
  1355. if (product_id == 0x8197 || product_id == 0x8198) {
  1356. eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_SELECT_GPIO, &reg);
  1357. if (reg & 0xFF00)
  1358. priv->rfkill_mask = RFKILL_MASK_8198;
  1359. }
  1360. dev->vif_data_size = sizeof(struct rtl8187_vif);
  1361. dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
  1362. BIT(NL80211_IFTYPE_ADHOC) ;
  1363. if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
  1364. printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
  1365. " info!\n");
  1366. priv->rf = rtl8187_detect_rf(dev);
  1367. dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
  1368. sizeof(struct rtl8187_tx_hdr) :
  1369. sizeof(struct rtl8187b_tx_hdr);
  1370. if (!priv->is_rtl8187b)
  1371. dev->queues = 1;
  1372. else
  1373. dev->queues = 4;
  1374. err = ieee80211_register_hw(dev);
  1375. if (err) {
  1376. printk(KERN_ERR "rtl8187: Cannot register device\n");
  1377. goto err_free_dmabuf;
  1378. }
  1379. mutex_init(&priv->conf_mutex);
  1380. skb_queue_head_init(&priv->b_tx_status.queue);
  1381. wiphy_info(dev->wiphy, "hwaddr %pM, %s V%d + %s, rfkill mask %d\n",
  1382. mac_addr, chip_name, priv->asic_rev, priv->rf->name,
  1383. priv->rfkill_mask);
  1384. #ifdef CONFIG_RTL8187_LEDS
  1385. eeprom_93cx6_read(&eeprom, 0x3F, &reg);
  1386. reg &= 0xFF;
  1387. rtl8187_leds_init(dev, reg);
  1388. #endif
  1389. rtl8187_rfkill_init(dev);
  1390. return 0;
  1391. err_free_dmabuf:
  1392. kfree(priv->io_dmabuf);
  1393. err_free_dev:
  1394. ieee80211_free_hw(dev);
  1395. usb_set_intfdata(intf, NULL);
  1396. usb_put_dev(udev);
  1397. return err;
  1398. }
  1399. static void __devexit rtl8187_disconnect(struct usb_interface *intf)
  1400. {
  1401. struct ieee80211_hw *dev = usb_get_intfdata(intf);
  1402. struct rtl8187_priv *priv;
  1403. if (!dev)
  1404. return;
  1405. #ifdef CONFIG_RTL8187_LEDS
  1406. rtl8187_leds_exit(dev);
  1407. #endif
  1408. rtl8187_rfkill_exit(dev);
  1409. ieee80211_unregister_hw(dev);
  1410. priv = dev->priv;
  1411. usb_reset_device(priv->udev);
  1412. usb_put_dev(interface_to_usbdev(intf));
  1413. kfree(priv->io_dmabuf);
  1414. ieee80211_free_hw(dev);
  1415. }
  1416. static struct usb_driver rtl8187_driver = {
  1417. .name = KBUILD_MODNAME,
  1418. .id_table = rtl8187_table,
  1419. .probe = rtl8187_probe,
  1420. .disconnect = __devexit_p(rtl8187_disconnect),
  1421. };
  1422. module_usb_driver(rtl8187_driver);