htc_drv_init.c 25 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "htc.h"
  17. MODULE_AUTHOR("Atheros Communications");
  18. MODULE_LICENSE("Dual BSD/GPL");
  19. MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
  20. static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
  21. module_param_named(debug, ath9k_debug, uint, 0);
  22. MODULE_PARM_DESC(debug, "Debugging mask");
  23. int htc_modparam_nohwcrypt;
  24. module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
  25. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  26. #define CHAN2G(_freq, _idx) { \
  27. .center_freq = (_freq), \
  28. .hw_value = (_idx), \
  29. .max_power = 20, \
  30. }
  31. #define CHAN5G(_freq, _idx) { \
  32. .band = IEEE80211_BAND_5GHZ, \
  33. .center_freq = (_freq), \
  34. .hw_value = (_idx), \
  35. .max_power = 20, \
  36. }
  37. static struct ieee80211_channel ath9k_2ghz_channels[] = {
  38. CHAN2G(2412, 0), /* Channel 1 */
  39. CHAN2G(2417, 1), /* Channel 2 */
  40. CHAN2G(2422, 2), /* Channel 3 */
  41. CHAN2G(2427, 3), /* Channel 4 */
  42. CHAN2G(2432, 4), /* Channel 5 */
  43. CHAN2G(2437, 5), /* Channel 6 */
  44. CHAN2G(2442, 6), /* Channel 7 */
  45. CHAN2G(2447, 7), /* Channel 8 */
  46. CHAN2G(2452, 8), /* Channel 9 */
  47. CHAN2G(2457, 9), /* Channel 10 */
  48. CHAN2G(2462, 10), /* Channel 11 */
  49. CHAN2G(2467, 11), /* Channel 12 */
  50. CHAN2G(2472, 12), /* Channel 13 */
  51. CHAN2G(2484, 13), /* Channel 14 */
  52. };
  53. static struct ieee80211_channel ath9k_5ghz_channels[] = {
  54. /* _We_ call this UNII 1 */
  55. CHAN5G(5180, 14), /* Channel 36 */
  56. CHAN5G(5200, 15), /* Channel 40 */
  57. CHAN5G(5220, 16), /* Channel 44 */
  58. CHAN5G(5240, 17), /* Channel 48 */
  59. /* _We_ call this UNII 2 */
  60. CHAN5G(5260, 18), /* Channel 52 */
  61. CHAN5G(5280, 19), /* Channel 56 */
  62. CHAN5G(5300, 20), /* Channel 60 */
  63. CHAN5G(5320, 21), /* Channel 64 */
  64. /* _We_ call this "Middle band" */
  65. CHAN5G(5500, 22), /* Channel 100 */
  66. CHAN5G(5520, 23), /* Channel 104 */
  67. CHAN5G(5540, 24), /* Channel 108 */
  68. CHAN5G(5560, 25), /* Channel 112 */
  69. CHAN5G(5580, 26), /* Channel 116 */
  70. CHAN5G(5600, 27), /* Channel 120 */
  71. CHAN5G(5620, 28), /* Channel 124 */
  72. CHAN5G(5640, 29), /* Channel 128 */
  73. CHAN5G(5660, 30), /* Channel 132 */
  74. CHAN5G(5680, 31), /* Channel 136 */
  75. CHAN5G(5700, 32), /* Channel 140 */
  76. /* _We_ call this UNII 3 */
  77. CHAN5G(5745, 33), /* Channel 149 */
  78. CHAN5G(5765, 34), /* Channel 153 */
  79. CHAN5G(5785, 35), /* Channel 157 */
  80. CHAN5G(5805, 36), /* Channel 161 */
  81. CHAN5G(5825, 37), /* Channel 165 */
  82. };
  83. /* Atheros hardware rate code addition for short premble */
  84. #define SHPCHECK(__hw_rate, __flags) \
  85. ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
  86. #define RATE(_bitrate, _hw_rate, _flags) { \
  87. .bitrate = (_bitrate), \
  88. .flags = (_flags), \
  89. .hw_value = (_hw_rate), \
  90. .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
  91. }
  92. static struct ieee80211_rate ath9k_legacy_rates[] = {
  93. RATE(10, 0x1b, 0),
  94. RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
  95. RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
  96. RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
  97. RATE(60, 0x0b, 0),
  98. RATE(90, 0x0f, 0),
  99. RATE(120, 0x0a, 0),
  100. RATE(180, 0x0e, 0),
  101. RATE(240, 0x09, 0),
  102. RATE(360, 0x0d, 0),
  103. RATE(480, 0x08, 0),
  104. RATE(540, 0x0c, 0),
  105. };
  106. #ifdef CONFIG_MAC80211_LEDS
  107. static const struct ieee80211_tpt_blink ath9k_htc_tpt_blink[] = {
  108. { .throughput = 0 * 1024, .blink_time = 334 },
  109. { .throughput = 1 * 1024, .blink_time = 260 },
  110. { .throughput = 5 * 1024, .blink_time = 220 },
  111. { .throughput = 10 * 1024, .blink_time = 190 },
  112. { .throughput = 20 * 1024, .blink_time = 170 },
  113. { .throughput = 50 * 1024, .blink_time = 150 },
  114. { .throughput = 70 * 1024, .blink_time = 130 },
  115. { .throughput = 100 * 1024, .blink_time = 110 },
  116. { .throughput = 200 * 1024, .blink_time = 80 },
  117. { .throughput = 300 * 1024, .blink_time = 50 },
  118. };
  119. #endif
  120. static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
  121. {
  122. int time_left;
  123. if (atomic_read(&priv->htc->tgt_ready) > 0) {
  124. atomic_dec(&priv->htc->tgt_ready);
  125. return 0;
  126. }
  127. /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
  128. time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
  129. if (!time_left) {
  130. dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
  131. return -ETIMEDOUT;
  132. }
  133. atomic_dec(&priv->htc->tgt_ready);
  134. return 0;
  135. }
  136. static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
  137. {
  138. ath9k_hw_deinit(priv->ah);
  139. kfree(priv->ah);
  140. priv->ah = NULL;
  141. }
  142. static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
  143. {
  144. struct ieee80211_hw *hw = priv->hw;
  145. wiphy_rfkill_stop_polling(hw->wiphy);
  146. ath9k_deinit_leds(priv);
  147. ieee80211_unregister_hw(hw);
  148. ath9k_rx_cleanup(priv);
  149. ath9k_tx_cleanup(priv);
  150. ath9k_deinit_priv(priv);
  151. }
  152. static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
  153. u16 service_id,
  154. void (*tx) (void *,
  155. struct sk_buff *,
  156. enum htc_endpoint_id,
  157. bool txok),
  158. enum htc_endpoint_id *ep_id)
  159. {
  160. struct htc_service_connreq req;
  161. memset(&req, 0, sizeof(struct htc_service_connreq));
  162. req.service_id = service_id;
  163. req.ep_callbacks.priv = priv;
  164. req.ep_callbacks.rx = ath9k_htc_rxep;
  165. req.ep_callbacks.tx = tx;
  166. return htc_connect_service(priv->htc, &req, ep_id);
  167. }
  168. static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
  169. u32 drv_info)
  170. {
  171. int ret;
  172. /* WMI CMD*/
  173. ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
  174. if (ret)
  175. goto err;
  176. /* Beacon */
  177. ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
  178. &priv->beacon_ep);
  179. if (ret)
  180. goto err;
  181. /* CAB */
  182. ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
  183. &priv->cab_ep);
  184. if (ret)
  185. goto err;
  186. /* UAPSD */
  187. ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
  188. &priv->uapsd_ep);
  189. if (ret)
  190. goto err;
  191. /* MGMT */
  192. ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
  193. &priv->mgmt_ep);
  194. if (ret)
  195. goto err;
  196. /* DATA BE */
  197. ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
  198. &priv->data_be_ep);
  199. if (ret)
  200. goto err;
  201. /* DATA BK */
  202. ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
  203. &priv->data_bk_ep);
  204. if (ret)
  205. goto err;
  206. /* DATA VI */
  207. ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
  208. &priv->data_vi_ep);
  209. if (ret)
  210. goto err;
  211. /* DATA VO */
  212. ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
  213. &priv->data_vo_ep);
  214. if (ret)
  215. goto err;
  216. /*
  217. * Setup required credits before initializing HTC.
  218. * This is a bit hacky, but, since queuing is done in
  219. * the HIF layer, shouldn't matter much.
  220. */
  221. if (IS_AR7010_DEVICE(drv_info))
  222. priv->htc->credits = 45;
  223. else
  224. priv->htc->credits = 33;
  225. ret = htc_init(priv->htc);
  226. if (ret)
  227. goto err;
  228. dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
  229. priv->htc->credits);
  230. return 0;
  231. err:
  232. dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
  233. return ret;
  234. }
  235. static int ath9k_reg_notifier(struct wiphy *wiphy,
  236. struct regulatory_request *request)
  237. {
  238. struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
  239. struct ath9k_htc_priv *priv = hw->priv;
  240. return ath_reg_notifier_apply(wiphy, request,
  241. ath9k_hw_regulatory(priv->ah));
  242. }
  243. static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
  244. {
  245. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  246. struct ath_common *common = ath9k_hw_common(ah);
  247. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  248. __be32 val, reg = cpu_to_be32(reg_offset);
  249. int r;
  250. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
  251. (u8 *) &reg, sizeof(reg),
  252. (u8 *) &val, sizeof(val),
  253. 100);
  254. if (unlikely(r)) {
  255. ath_dbg(common, WMI, "REGISTER READ FAILED: (0x%04x, %d)\n",
  256. reg_offset, r);
  257. return -EIO;
  258. }
  259. return be32_to_cpu(val);
  260. }
  261. static void ath9k_multi_regread(void *hw_priv, u32 *addr,
  262. u32 *val, u16 count)
  263. {
  264. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  265. struct ath_common *common = ath9k_hw_common(ah);
  266. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  267. __be32 tmpaddr[8];
  268. __be32 tmpval[8];
  269. int i, ret;
  270. for (i = 0; i < count; i++) {
  271. tmpaddr[i] = cpu_to_be32(addr[i]);
  272. }
  273. ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
  274. (u8 *)tmpaddr , sizeof(u32) * count,
  275. (u8 *)tmpval, sizeof(u32) * count,
  276. 100);
  277. if (unlikely(ret)) {
  278. ath_dbg(common, WMI,
  279. "Multiple REGISTER READ FAILED (count: %d)\n", count);
  280. }
  281. for (i = 0; i < count; i++) {
  282. val[i] = be32_to_cpu(tmpval[i]);
  283. }
  284. }
  285. static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
  286. {
  287. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  288. struct ath_common *common = ath9k_hw_common(ah);
  289. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  290. const __be32 buf[2] = {
  291. cpu_to_be32(reg_offset),
  292. cpu_to_be32(val),
  293. };
  294. int r;
  295. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  296. (u8 *) &buf, sizeof(buf),
  297. (u8 *) &val, sizeof(val),
  298. 100);
  299. if (unlikely(r)) {
  300. ath_dbg(common, WMI, "REGISTER WRITE FAILED:(0x%04x, %d)\n",
  301. reg_offset, r);
  302. }
  303. }
  304. static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
  305. {
  306. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  307. struct ath_common *common = ath9k_hw_common(ah);
  308. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  309. u32 rsp_status;
  310. int r;
  311. mutex_lock(&priv->wmi->multi_write_mutex);
  312. /* Store the register/value */
  313. priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
  314. cpu_to_be32(reg_offset);
  315. priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
  316. cpu_to_be32(val);
  317. priv->wmi->multi_write_idx++;
  318. /* If the buffer is full, send it out. */
  319. if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
  320. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  321. (u8 *) &priv->wmi->multi_write,
  322. sizeof(struct register_write) * priv->wmi->multi_write_idx,
  323. (u8 *) &rsp_status, sizeof(rsp_status),
  324. 100);
  325. if (unlikely(r)) {
  326. ath_dbg(common, WMI,
  327. "REGISTER WRITE FAILED, multi len: %d\n",
  328. priv->wmi->multi_write_idx);
  329. }
  330. priv->wmi->multi_write_idx = 0;
  331. }
  332. mutex_unlock(&priv->wmi->multi_write_mutex);
  333. }
  334. static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
  335. {
  336. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  337. struct ath_common *common = ath9k_hw_common(ah);
  338. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  339. if (atomic_read(&priv->wmi->mwrite_cnt))
  340. ath9k_regwrite_buffer(hw_priv, val, reg_offset);
  341. else
  342. ath9k_regwrite_single(hw_priv, val, reg_offset);
  343. }
  344. static void ath9k_enable_regwrite_buffer(void *hw_priv)
  345. {
  346. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  347. struct ath_common *common = ath9k_hw_common(ah);
  348. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  349. atomic_inc(&priv->wmi->mwrite_cnt);
  350. }
  351. static void ath9k_regwrite_flush(void *hw_priv)
  352. {
  353. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  354. struct ath_common *common = ath9k_hw_common(ah);
  355. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  356. u32 rsp_status;
  357. int r;
  358. atomic_dec(&priv->wmi->mwrite_cnt);
  359. mutex_lock(&priv->wmi->multi_write_mutex);
  360. if (priv->wmi->multi_write_idx) {
  361. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  362. (u8 *) &priv->wmi->multi_write,
  363. sizeof(struct register_write) * priv->wmi->multi_write_idx,
  364. (u8 *) &rsp_status, sizeof(rsp_status),
  365. 100);
  366. if (unlikely(r)) {
  367. ath_dbg(common, WMI,
  368. "REGISTER WRITE FAILED, multi len: %d\n",
  369. priv->wmi->multi_write_idx);
  370. }
  371. priv->wmi->multi_write_idx = 0;
  372. }
  373. mutex_unlock(&priv->wmi->multi_write_mutex);
  374. }
  375. static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
  376. {
  377. u32 val;
  378. val = ath9k_regread(hw_priv, reg_offset);
  379. val &= ~clr;
  380. val |= set;
  381. ath9k_regwrite(hw_priv, val, reg_offset);
  382. return val;
  383. }
  384. static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
  385. {
  386. *csz = L1_CACHE_BYTES >> 2;
  387. }
  388. static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
  389. {
  390. struct ath_hw *ah = (struct ath_hw *) common->ah;
  391. (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
  392. if (!ath9k_hw_wait(ah,
  393. AR_EEPROM_STATUS_DATA,
  394. AR_EEPROM_STATUS_DATA_BUSY |
  395. AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
  396. AH_WAIT_TIMEOUT))
  397. return false;
  398. *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
  399. AR_EEPROM_STATUS_DATA_VAL);
  400. return true;
  401. }
  402. static const struct ath_bus_ops ath9k_usb_bus_ops = {
  403. .ath_bus_type = ATH_USB,
  404. .read_cachesize = ath_usb_read_cachesize,
  405. .eeprom_read = ath_usb_eeprom_read,
  406. };
  407. static void setup_ht_cap(struct ath9k_htc_priv *priv,
  408. struct ieee80211_sta_ht_cap *ht_info)
  409. {
  410. struct ath_common *common = ath9k_hw_common(priv->ah);
  411. u8 tx_streams, rx_streams;
  412. int i;
  413. ht_info->ht_supported = true;
  414. ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  415. IEEE80211_HT_CAP_SM_PS |
  416. IEEE80211_HT_CAP_SGI_40 |
  417. IEEE80211_HT_CAP_DSSSCCK40;
  418. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
  419. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  420. ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
  421. ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  422. ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
  423. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  424. /* ath9k_htc supports only 1 or 2 stream devices */
  425. tx_streams = ath9k_cmn_count_streams(priv->ah->txchainmask, 2);
  426. rx_streams = ath9k_cmn_count_streams(priv->ah->rxchainmask, 2);
  427. ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
  428. tx_streams, rx_streams);
  429. if (tx_streams != rx_streams) {
  430. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  431. ht_info->mcs.tx_params |= ((tx_streams - 1) <<
  432. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  433. }
  434. for (i = 0; i < rx_streams; i++)
  435. ht_info->mcs.rx_mask[i] = 0xff;
  436. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
  437. }
  438. static int ath9k_init_queues(struct ath9k_htc_priv *priv)
  439. {
  440. struct ath_common *common = ath9k_hw_common(priv->ah);
  441. int i;
  442. for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
  443. priv->hwq_map[i] = -1;
  444. priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
  445. if (priv->beaconq == -1) {
  446. ath_err(common, "Unable to setup BEACON xmit queue\n");
  447. goto err;
  448. }
  449. priv->cabq = ath9k_htc_cabq_setup(priv);
  450. if (priv->cabq == -1) {
  451. ath_err(common, "Unable to setup CAB xmit queue\n");
  452. goto err;
  453. }
  454. if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
  455. ath_err(common, "Unable to setup xmit queue for BE traffic\n");
  456. goto err;
  457. }
  458. if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
  459. ath_err(common, "Unable to setup xmit queue for BK traffic\n");
  460. goto err;
  461. }
  462. if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
  463. ath_err(common, "Unable to setup xmit queue for VI traffic\n");
  464. goto err;
  465. }
  466. if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
  467. ath_err(common, "Unable to setup xmit queue for VO traffic\n");
  468. goto err;
  469. }
  470. return 0;
  471. err:
  472. return -EINVAL;
  473. }
  474. static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
  475. {
  476. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
  477. priv->sbands[IEEE80211_BAND_2GHZ].channels =
  478. ath9k_2ghz_channels;
  479. priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
  480. priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
  481. ARRAY_SIZE(ath9k_2ghz_channels);
  482. priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
  483. priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
  484. ARRAY_SIZE(ath9k_legacy_rates);
  485. }
  486. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
  487. priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
  488. priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
  489. priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
  490. ARRAY_SIZE(ath9k_5ghz_channels);
  491. priv->sbands[IEEE80211_BAND_5GHZ].bitrates =
  492. ath9k_legacy_rates + 4;
  493. priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
  494. ARRAY_SIZE(ath9k_legacy_rates) - 4;
  495. }
  496. }
  497. static void ath9k_init_misc(struct ath9k_htc_priv *priv)
  498. {
  499. struct ath_common *common = ath9k_hw_common(priv->ah);
  500. memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
  501. priv->ah->opmode = NL80211_IFTYPE_STATION;
  502. }
  503. static int ath9k_init_priv(struct ath9k_htc_priv *priv,
  504. u16 devid, char *product,
  505. u32 drv_info)
  506. {
  507. struct ath_hw *ah = NULL;
  508. struct ath_common *common;
  509. int i, ret = 0, csz = 0;
  510. priv->op_flags |= OP_INVALID;
  511. ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
  512. if (!ah)
  513. return -ENOMEM;
  514. ah->hw_version.devid = devid;
  515. ah->hw_version.usbdev = drv_info;
  516. ah->ah_flags |= AH_USE_EEPROM;
  517. ah->reg_ops.read = ath9k_regread;
  518. ah->reg_ops.multi_read = ath9k_multi_regread;
  519. ah->reg_ops.write = ath9k_regwrite;
  520. ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
  521. ah->reg_ops.write_flush = ath9k_regwrite_flush;
  522. ah->reg_ops.rmw = ath9k_reg_rmw;
  523. priv->ah = ah;
  524. common = ath9k_hw_common(ah);
  525. common->ops = &ah->reg_ops;
  526. common->bus_ops = &ath9k_usb_bus_ops;
  527. common->ah = ah;
  528. common->hw = priv->hw;
  529. common->priv = priv;
  530. common->debug_mask = ath9k_debug;
  531. spin_lock_init(&priv->beacon_lock);
  532. spin_lock_init(&priv->tx.tx_lock);
  533. mutex_init(&priv->mutex);
  534. mutex_init(&priv->htc_pm_lock);
  535. tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
  536. (unsigned long)priv);
  537. tasklet_init(&priv->tx_failed_tasklet, ath9k_tx_failed_tasklet,
  538. (unsigned long)priv);
  539. INIT_DELAYED_WORK(&priv->ani_work, ath9k_htc_ani_work);
  540. INIT_WORK(&priv->ps_work, ath9k_ps_work);
  541. INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
  542. setup_timer(&priv->tx.cleanup_timer, ath9k_htc_tx_cleanup_timer,
  543. (unsigned long)priv);
  544. /*
  545. * Cache line size is used to size and align various
  546. * structures used to communicate with the hardware.
  547. */
  548. ath_read_cachesize(common, &csz);
  549. common->cachelsz = csz << 2; /* convert to bytes */
  550. ret = ath9k_hw_init(ah);
  551. if (ret) {
  552. ath_err(common,
  553. "Unable to initialize hardware; initialization status: %d\n",
  554. ret);
  555. goto err_hw;
  556. }
  557. ret = ath9k_init_queues(priv);
  558. if (ret)
  559. goto err_queues;
  560. for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++)
  561. priv->cur_beacon_conf.bslot[i] = NULL;
  562. ath9k_cmn_init_crypto(ah);
  563. ath9k_init_channels_rates(priv);
  564. ath9k_init_misc(priv);
  565. ath9k_htc_init_btcoex(priv, product);
  566. return 0;
  567. err_queues:
  568. ath9k_hw_deinit(ah);
  569. err_hw:
  570. kfree(ah);
  571. priv->ah = NULL;
  572. return ret;
  573. }
  574. static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
  575. struct ieee80211_hw *hw)
  576. {
  577. struct ath_common *common = ath9k_hw_common(priv->ah);
  578. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  579. IEEE80211_HW_AMPDU_AGGREGATION |
  580. IEEE80211_HW_SPECTRUM_MGMT |
  581. IEEE80211_HW_HAS_RATE_CONTROL |
  582. IEEE80211_HW_RX_INCLUDES_FCS |
  583. IEEE80211_HW_SUPPORTS_PS |
  584. IEEE80211_HW_PS_NULLFUNC_STACK |
  585. IEEE80211_HW_REPORTS_TX_ACK_STATUS |
  586. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
  587. hw->wiphy->interface_modes =
  588. BIT(NL80211_IFTYPE_STATION) |
  589. BIT(NL80211_IFTYPE_ADHOC) |
  590. BIT(NL80211_IFTYPE_AP) |
  591. BIT(NL80211_IFTYPE_P2P_GO) |
  592. BIT(NL80211_IFTYPE_P2P_CLIENT);
  593. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  594. hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
  595. hw->queues = 4;
  596. hw->channel_change_time = 5000;
  597. hw->max_listen_interval = 10;
  598. hw->vif_data_size = sizeof(struct ath9k_htc_vif);
  599. hw->sta_data_size = sizeof(struct ath9k_htc_sta);
  600. /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
  601. hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
  602. sizeof(struct htc_frame_hdr) + 4;
  603. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
  604. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  605. &priv->sbands[IEEE80211_BAND_2GHZ];
  606. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
  607. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  608. &priv->sbands[IEEE80211_BAND_5GHZ];
  609. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  610. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
  611. setup_ht_cap(priv,
  612. &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
  613. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
  614. setup_ht_cap(priv,
  615. &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
  616. }
  617. SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
  618. }
  619. static int ath9k_init_firmware_version(struct ath9k_htc_priv *priv)
  620. {
  621. struct ieee80211_hw *hw = priv->hw;
  622. struct wmi_fw_version cmd_rsp;
  623. int ret;
  624. memset(&cmd_rsp, 0, sizeof(cmd_rsp));
  625. WMI_CMD(WMI_GET_FW_VERSION);
  626. if (ret)
  627. return -EINVAL;
  628. priv->fw_version_major = be16_to_cpu(cmd_rsp.major);
  629. priv->fw_version_minor = be16_to_cpu(cmd_rsp.minor);
  630. snprintf(hw->wiphy->fw_version, ETHTOOL_BUSINFO_LEN, "%d.%d",
  631. priv->fw_version_major,
  632. priv->fw_version_minor);
  633. dev_info(priv->dev, "ath9k_htc: FW Version: %d.%d\n",
  634. priv->fw_version_major,
  635. priv->fw_version_minor);
  636. /*
  637. * Check if the available FW matches the driver's
  638. * required version.
  639. */
  640. if (priv->fw_version_major != MAJOR_VERSION_REQ ||
  641. priv->fw_version_minor != MINOR_VERSION_REQ) {
  642. dev_err(priv->dev, "ath9k_htc: Please upgrade to FW version %d.%d\n",
  643. MAJOR_VERSION_REQ, MINOR_VERSION_REQ);
  644. return -EINVAL;
  645. }
  646. return 0;
  647. }
  648. static int ath9k_init_device(struct ath9k_htc_priv *priv,
  649. u16 devid, char *product, u32 drv_info)
  650. {
  651. struct ieee80211_hw *hw = priv->hw;
  652. struct ath_common *common;
  653. struct ath_hw *ah;
  654. int error = 0;
  655. struct ath_regulatory *reg;
  656. char hw_name[64];
  657. /* Bring up device */
  658. error = ath9k_init_priv(priv, devid, product, drv_info);
  659. if (error != 0)
  660. goto err_init;
  661. ah = priv->ah;
  662. common = ath9k_hw_common(ah);
  663. ath9k_set_hw_capab(priv, hw);
  664. error = ath9k_init_firmware_version(priv);
  665. if (error != 0)
  666. goto err_fw;
  667. /* Initialize regulatory */
  668. error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
  669. ath9k_reg_notifier);
  670. if (error)
  671. goto err_regd;
  672. reg = &common->regulatory;
  673. /* Setup TX */
  674. error = ath9k_tx_init(priv);
  675. if (error != 0)
  676. goto err_tx;
  677. /* Setup RX */
  678. error = ath9k_rx_init(priv);
  679. if (error != 0)
  680. goto err_rx;
  681. #ifdef CONFIG_MAC80211_LEDS
  682. /* must be initialized before ieee80211_register_hw */
  683. priv->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(priv->hw,
  684. IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_htc_tpt_blink,
  685. ARRAY_SIZE(ath9k_htc_tpt_blink));
  686. #endif
  687. /* Register with mac80211 */
  688. error = ieee80211_register_hw(hw);
  689. if (error)
  690. goto err_register;
  691. /* Handle world regulatory */
  692. if (!ath_is_world_regd(reg)) {
  693. error = regulatory_hint(hw->wiphy, reg->alpha2);
  694. if (error)
  695. goto err_world;
  696. }
  697. error = ath9k_htc_init_debug(priv->ah);
  698. if (error) {
  699. ath_err(common, "Unable to create debugfs files\n");
  700. goto err_world;
  701. }
  702. ath_dbg(common, CONFIG,
  703. "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, BE:%d, BK:%d, VI:%d, VO:%d\n",
  704. priv->wmi_cmd_ep,
  705. priv->beacon_ep,
  706. priv->cab_ep,
  707. priv->uapsd_ep,
  708. priv->mgmt_ep,
  709. priv->data_be_ep,
  710. priv->data_bk_ep,
  711. priv->data_vi_ep,
  712. priv->data_vo_ep);
  713. ath9k_hw_name(priv->ah, hw_name, sizeof(hw_name));
  714. wiphy_info(hw->wiphy, "%s\n", hw_name);
  715. ath9k_init_leds(priv);
  716. ath9k_start_rfkill_poll(priv);
  717. return 0;
  718. err_world:
  719. ieee80211_unregister_hw(hw);
  720. err_register:
  721. ath9k_rx_cleanup(priv);
  722. err_rx:
  723. ath9k_tx_cleanup(priv);
  724. err_tx:
  725. /* Nothing */
  726. err_regd:
  727. /* Nothing */
  728. err_fw:
  729. ath9k_deinit_priv(priv);
  730. err_init:
  731. return error;
  732. }
  733. int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
  734. u16 devid, char *product, u32 drv_info)
  735. {
  736. struct ieee80211_hw *hw;
  737. struct ath9k_htc_priv *priv;
  738. int ret;
  739. hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
  740. if (!hw)
  741. return -ENOMEM;
  742. priv = hw->priv;
  743. priv->hw = hw;
  744. priv->htc = htc_handle;
  745. priv->dev = dev;
  746. htc_handle->drv_priv = priv;
  747. SET_IEEE80211_DEV(hw, priv->dev);
  748. ret = ath9k_htc_wait_for_target(priv);
  749. if (ret)
  750. goto err_free;
  751. priv->wmi = ath9k_init_wmi(priv);
  752. if (!priv->wmi) {
  753. ret = -EINVAL;
  754. goto err_free;
  755. }
  756. ret = ath9k_init_htc_services(priv, devid, drv_info);
  757. if (ret)
  758. goto err_init;
  759. ret = ath9k_init_device(priv, devid, product, drv_info);
  760. if (ret)
  761. goto err_init;
  762. return 0;
  763. err_init:
  764. ath9k_deinit_wmi(priv);
  765. err_free:
  766. ieee80211_free_hw(hw);
  767. return ret;
  768. }
  769. void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
  770. {
  771. if (htc_handle->drv_priv) {
  772. /* Check if the device has been yanked out. */
  773. if (hotunplug)
  774. htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
  775. ath9k_deinit_device(htc_handle->drv_priv);
  776. ath9k_deinit_wmi(htc_handle->drv_priv);
  777. ieee80211_free_hw(htc_handle->drv_priv->hw);
  778. }
  779. }
  780. #ifdef CONFIG_PM
  781. void ath9k_htc_suspend(struct htc_target *htc_handle)
  782. {
  783. ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
  784. }
  785. int ath9k_htc_resume(struct htc_target *htc_handle)
  786. {
  787. struct ath9k_htc_priv *priv = htc_handle->drv_priv;
  788. int ret;
  789. ret = ath9k_htc_wait_for_target(priv);
  790. if (ret)
  791. return ret;
  792. ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
  793. priv->ah->hw_version.usbdev);
  794. return ret;
  795. }
  796. #endif
  797. static int __init ath9k_htc_init(void)
  798. {
  799. if (ath9k_hif_usb_init() < 0) {
  800. printk(KERN_ERR
  801. "ath9k_htc: No USB devices found,"
  802. " driver not installed.\n");
  803. return -ENODEV;
  804. }
  805. return 0;
  806. }
  807. module_init(ath9k_htc_init);
  808. static void __exit ath9k_htc_exit(void)
  809. {
  810. ath9k_hif_usb_exit();
  811. printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
  812. }
  813. module_exit(ath9k_htc_exit);