siena_sriov.c 45 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2010-2011 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/pci.h>
  10. #include <linux/module.h>
  11. #include "net_driver.h"
  12. #include "efx.h"
  13. #include "nic.h"
  14. #include "io.h"
  15. #include "mcdi.h"
  16. #include "filter.h"
  17. #include "mcdi_pcol.h"
  18. #include "regs.h"
  19. #include "vfdi.h"
  20. /* Number of longs required to track all the VIs in a VF */
  21. #define VI_MASK_LENGTH BITS_TO_LONGS(1 << EFX_VI_SCALE_MAX)
  22. /**
  23. * enum efx_vf_tx_filter_mode - TX MAC filtering behaviour
  24. * @VF_TX_FILTER_OFF: Disabled
  25. * @VF_TX_FILTER_AUTO: Enabled if MAC address assigned to VF and only
  26. * 2 TX queues allowed per VF.
  27. * @VF_TX_FILTER_ON: Enabled
  28. */
  29. enum efx_vf_tx_filter_mode {
  30. VF_TX_FILTER_OFF,
  31. VF_TX_FILTER_AUTO,
  32. VF_TX_FILTER_ON,
  33. };
  34. /**
  35. * struct efx_vf - Back-end resource and protocol state for a PCI VF
  36. * @efx: The Efx NIC owning this VF
  37. * @pci_rid: The PCI requester ID for this VF
  38. * @pci_name: The PCI name (formatted address) of this VF
  39. * @index: Index of VF within its port and PF.
  40. * @req: VFDI incoming request work item. Incoming USR_EV events are received
  41. * by the NAPI handler, but must be handled by executing MCDI requests
  42. * inside a work item.
  43. * @req_addr: VFDI incoming request DMA address (in VF's PCI address space).
  44. * @req_type: Expected next incoming (from VF) %VFDI_EV_TYPE member.
  45. * @req_seqno: Expected next incoming (from VF) %VFDI_EV_SEQ member.
  46. * @msg_seqno: Next %VFDI_EV_SEQ member to reply to VF. Protected by
  47. * @status_lock
  48. * @busy: VFDI request queued to be processed or being processed. Receiving
  49. * a VFDI request when @busy is set is an error condition.
  50. * @buf: Incoming VFDI requests are DMA from the VF into this buffer.
  51. * @buftbl_base: Buffer table entries for this VF start at this index.
  52. * @rx_filtering: Receive filtering has been requested by the VF driver.
  53. * @rx_filter_flags: The flags sent in the %VFDI_OP_INSERT_FILTER request.
  54. * @rx_filter_qid: VF relative qid for RX filter requested by VF.
  55. * @rx_filter_id: Receive MAC filter ID. Only one filter per VF is supported.
  56. * @tx_filter_mode: Transmit MAC filtering mode.
  57. * @tx_filter_id: Transmit MAC filter ID.
  58. * @addr: The MAC address and outer vlan tag of the VF.
  59. * @status_addr: VF DMA address of page for &struct vfdi_status updates.
  60. * @status_lock: Mutex protecting @msg_seqno, @status_addr, @addr,
  61. * @peer_page_addrs and @peer_page_count from simultaneous
  62. * updates by the VM and consumption by
  63. * efx_sriov_update_vf_addr()
  64. * @peer_page_addrs: Pointer to an array of guest pages for local addresses.
  65. * @peer_page_count: Number of entries in @peer_page_count.
  66. * @evq0_addrs: Array of guest pages backing evq0.
  67. * @evq0_count: Number of entries in @evq0_addrs.
  68. * @flush_waitq: wait queue used by %VFDI_OP_FINI_ALL_QUEUES handler
  69. * to wait for flush completions.
  70. * @txq_lock: Mutex for TX queue allocation.
  71. * @txq_mask: Mask of initialized transmit queues.
  72. * @txq_count: Number of initialized transmit queues.
  73. * @rxq_mask: Mask of initialized receive queues.
  74. * @rxq_count: Number of initialized receive queues.
  75. * @rxq_retry_mask: Mask or receive queues that need to be flushed again
  76. * due to flush failure.
  77. * @rxq_retry_count: Number of receive queues in @rxq_retry_mask.
  78. * @reset_work: Work item to schedule a VF reset.
  79. */
  80. struct efx_vf {
  81. struct efx_nic *efx;
  82. unsigned int pci_rid;
  83. char pci_name[13]; /* dddd:bb:dd.f */
  84. unsigned int index;
  85. struct work_struct req;
  86. u64 req_addr;
  87. int req_type;
  88. unsigned req_seqno;
  89. unsigned msg_seqno;
  90. bool busy;
  91. struct efx_buffer buf;
  92. unsigned buftbl_base;
  93. bool rx_filtering;
  94. enum efx_filter_flags rx_filter_flags;
  95. unsigned rx_filter_qid;
  96. int rx_filter_id;
  97. enum efx_vf_tx_filter_mode tx_filter_mode;
  98. int tx_filter_id;
  99. struct vfdi_endpoint addr;
  100. u64 status_addr;
  101. struct mutex status_lock;
  102. u64 *peer_page_addrs;
  103. unsigned peer_page_count;
  104. u64 evq0_addrs[EFX_MAX_VF_EVQ_SIZE * sizeof(efx_qword_t) /
  105. EFX_BUF_SIZE];
  106. unsigned evq0_count;
  107. wait_queue_head_t flush_waitq;
  108. struct mutex txq_lock;
  109. unsigned long txq_mask[VI_MASK_LENGTH];
  110. unsigned txq_count;
  111. unsigned long rxq_mask[VI_MASK_LENGTH];
  112. unsigned rxq_count;
  113. unsigned long rxq_retry_mask[VI_MASK_LENGTH];
  114. atomic_t rxq_retry_count;
  115. struct work_struct reset_work;
  116. };
  117. struct efx_memcpy_req {
  118. unsigned int from_rid;
  119. void *from_buf;
  120. u64 from_addr;
  121. unsigned int to_rid;
  122. u64 to_addr;
  123. unsigned length;
  124. };
  125. /**
  126. * struct efx_local_addr - A MAC address on the vswitch without a VF.
  127. *
  128. * Siena does not have a switch, so VFs can't transmit data to each
  129. * other. Instead the VFs must be made aware of the local addresses
  130. * on the vswitch, so that they can arrange for an alternative
  131. * software datapath to be used.
  132. *
  133. * @link: List head for insertion into efx->local_addr_list.
  134. * @addr: Ethernet address
  135. */
  136. struct efx_local_addr {
  137. struct list_head link;
  138. u8 addr[ETH_ALEN];
  139. };
  140. /**
  141. * struct efx_endpoint_page - Page of vfdi_endpoint structures
  142. *
  143. * @link: List head for insertion into efx->local_page_list.
  144. * @ptr: Pointer to page.
  145. * @addr: DMA address of page.
  146. */
  147. struct efx_endpoint_page {
  148. struct list_head link;
  149. void *ptr;
  150. dma_addr_t addr;
  151. };
  152. /* Buffer table entries are reserved txq0,rxq0,evq0,txq1,rxq1,evq1 */
  153. #define EFX_BUFTBL_TXQ_BASE(_vf, _qid) \
  154. ((_vf)->buftbl_base + EFX_VF_BUFTBL_PER_VI * (_qid))
  155. #define EFX_BUFTBL_RXQ_BASE(_vf, _qid) \
  156. (EFX_BUFTBL_TXQ_BASE(_vf, _qid) + \
  157. (EFX_MAX_DMAQ_SIZE * sizeof(efx_qword_t) / EFX_BUF_SIZE))
  158. #define EFX_BUFTBL_EVQ_BASE(_vf, _qid) \
  159. (EFX_BUFTBL_TXQ_BASE(_vf, _qid) + \
  160. (2 * EFX_MAX_DMAQ_SIZE * sizeof(efx_qword_t) / EFX_BUF_SIZE))
  161. #define EFX_FIELD_MASK(_field) \
  162. ((1 << _field ## _WIDTH) - 1)
  163. /* VFs can only use this many transmit channels */
  164. static unsigned int vf_max_tx_channels = 2;
  165. module_param(vf_max_tx_channels, uint, 0444);
  166. MODULE_PARM_DESC(vf_max_tx_channels,
  167. "Limit the number of TX channels VFs can use");
  168. static int max_vfs = -1;
  169. module_param(max_vfs, int, 0444);
  170. MODULE_PARM_DESC(max_vfs,
  171. "Reduce the number of VFs initialized by the driver");
  172. /* Workqueue used by VFDI communication. We can't use the global
  173. * workqueue because it may be running the VF driver's probe()
  174. * routine, which will be blocked there waiting for a VFDI response.
  175. */
  176. static struct workqueue_struct *vfdi_workqueue;
  177. static unsigned abs_index(struct efx_vf *vf, unsigned index)
  178. {
  179. return EFX_VI_BASE + vf->index * efx_vf_size(vf->efx) + index;
  180. }
  181. static int efx_sriov_cmd(struct efx_nic *efx, bool enable,
  182. unsigned *vi_scale_out, unsigned *vf_total_out)
  183. {
  184. u8 inbuf[MC_CMD_SRIOV_IN_LEN];
  185. u8 outbuf[MC_CMD_SRIOV_OUT_LEN];
  186. unsigned vi_scale, vf_total;
  187. size_t outlen;
  188. int rc;
  189. MCDI_SET_DWORD(inbuf, SRIOV_IN_ENABLE, enable ? 1 : 0);
  190. MCDI_SET_DWORD(inbuf, SRIOV_IN_VI_BASE, EFX_VI_BASE);
  191. MCDI_SET_DWORD(inbuf, SRIOV_IN_VF_COUNT, efx->vf_count);
  192. rc = efx_mcdi_rpc(efx, MC_CMD_SRIOV, inbuf, MC_CMD_SRIOV_IN_LEN,
  193. outbuf, MC_CMD_SRIOV_OUT_LEN, &outlen);
  194. if (rc)
  195. return rc;
  196. if (outlen < MC_CMD_SRIOV_OUT_LEN)
  197. return -EIO;
  198. vf_total = MCDI_DWORD(outbuf, SRIOV_OUT_VF_TOTAL);
  199. vi_scale = MCDI_DWORD(outbuf, SRIOV_OUT_VI_SCALE);
  200. if (vi_scale > EFX_VI_SCALE_MAX)
  201. return -EOPNOTSUPP;
  202. if (vi_scale_out)
  203. *vi_scale_out = vi_scale;
  204. if (vf_total_out)
  205. *vf_total_out = vf_total;
  206. return 0;
  207. }
  208. static void efx_sriov_usrev(struct efx_nic *efx, bool enabled)
  209. {
  210. efx_oword_t reg;
  211. EFX_POPULATE_OWORD_2(reg,
  212. FRF_CZ_USREV_DIS, enabled ? 0 : 1,
  213. FRF_CZ_DFLT_EVQ, efx->vfdi_channel->channel);
  214. efx_writeo(efx, &reg, FR_CZ_USR_EV_CFG);
  215. }
  216. static int efx_sriov_memcpy(struct efx_nic *efx, struct efx_memcpy_req *req,
  217. unsigned int count)
  218. {
  219. u8 *inbuf, *record;
  220. unsigned int used;
  221. u32 from_rid, from_hi, from_lo;
  222. int rc;
  223. mb(); /* Finish writing source/reading dest before DMA starts */
  224. used = MC_CMD_MEMCPY_IN_LEN(count);
  225. if (WARN_ON(used > MCDI_CTL_SDU_LEN_MAX))
  226. return -ENOBUFS;
  227. /* Allocate room for the largest request */
  228. inbuf = kzalloc(MCDI_CTL_SDU_LEN_MAX, GFP_KERNEL);
  229. if (inbuf == NULL)
  230. return -ENOMEM;
  231. record = inbuf;
  232. MCDI_SET_DWORD(record, MEMCPY_IN_RECORD, count);
  233. while (count-- > 0) {
  234. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_TO_RID,
  235. req->to_rid);
  236. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO,
  237. (u32)req->to_addr);
  238. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI,
  239. (u32)(req->to_addr >> 32));
  240. if (req->from_buf == NULL) {
  241. from_rid = req->from_rid;
  242. from_lo = (u32)req->from_addr;
  243. from_hi = (u32)(req->from_addr >> 32);
  244. } else {
  245. if (WARN_ON(used + req->length > MCDI_CTL_SDU_LEN_MAX)) {
  246. rc = -ENOBUFS;
  247. goto out;
  248. }
  249. from_rid = MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE;
  250. from_lo = used;
  251. from_hi = 0;
  252. memcpy(inbuf + used, req->from_buf, req->length);
  253. used += req->length;
  254. }
  255. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_RID, from_rid);
  256. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO,
  257. from_lo);
  258. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI,
  259. from_hi);
  260. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_LENGTH,
  261. req->length);
  262. ++req;
  263. record += MC_CMD_MEMCPY_IN_RECORD_LEN;
  264. }
  265. rc = efx_mcdi_rpc(efx, MC_CMD_MEMCPY, inbuf, used, NULL, 0, NULL);
  266. out:
  267. kfree(inbuf);
  268. mb(); /* Don't write source/read dest before DMA is complete */
  269. return rc;
  270. }
  271. /* The TX filter is entirely controlled by this driver, and is modified
  272. * underneath the feet of the VF
  273. */
  274. static void efx_sriov_reset_tx_filter(struct efx_vf *vf)
  275. {
  276. struct efx_nic *efx = vf->efx;
  277. struct efx_filter_spec filter;
  278. u16 vlan;
  279. int rc;
  280. if (vf->tx_filter_id != -1) {
  281. efx_filter_remove_id_safe(efx, EFX_FILTER_PRI_REQUIRED,
  282. vf->tx_filter_id);
  283. netif_dbg(efx, hw, efx->net_dev, "Removed vf %s tx filter %d\n",
  284. vf->pci_name, vf->tx_filter_id);
  285. vf->tx_filter_id = -1;
  286. }
  287. if (is_zero_ether_addr(vf->addr.mac_addr))
  288. return;
  289. /* Turn on TX filtering automatically if not explicitly
  290. * enabled or disabled.
  291. */
  292. if (vf->tx_filter_mode == VF_TX_FILTER_AUTO && vf_max_tx_channels <= 2)
  293. vf->tx_filter_mode = VF_TX_FILTER_ON;
  294. vlan = ntohs(vf->addr.tci) & VLAN_VID_MASK;
  295. efx_filter_init_tx(&filter, abs_index(vf, 0));
  296. rc = efx_filter_set_eth_local(&filter,
  297. vlan ? vlan : EFX_FILTER_VID_UNSPEC,
  298. vf->addr.mac_addr);
  299. BUG_ON(rc);
  300. rc = efx_filter_insert_filter(efx, &filter, true);
  301. if (rc < 0) {
  302. netif_warn(efx, hw, efx->net_dev,
  303. "Unable to migrate tx filter for vf %s\n",
  304. vf->pci_name);
  305. } else {
  306. netif_dbg(efx, hw, efx->net_dev, "Inserted vf %s tx filter %d\n",
  307. vf->pci_name, rc);
  308. vf->tx_filter_id = rc;
  309. }
  310. }
  311. /* The RX filter is managed here on behalf of the VF driver */
  312. static void efx_sriov_reset_rx_filter(struct efx_vf *vf)
  313. {
  314. struct efx_nic *efx = vf->efx;
  315. struct efx_filter_spec filter;
  316. u16 vlan;
  317. int rc;
  318. if (vf->rx_filter_id != -1) {
  319. efx_filter_remove_id_safe(efx, EFX_FILTER_PRI_REQUIRED,
  320. vf->rx_filter_id);
  321. netif_dbg(efx, hw, efx->net_dev, "Removed vf %s rx filter %d\n",
  322. vf->pci_name, vf->rx_filter_id);
  323. vf->rx_filter_id = -1;
  324. }
  325. if (!vf->rx_filtering || is_zero_ether_addr(vf->addr.mac_addr))
  326. return;
  327. vlan = ntohs(vf->addr.tci) & VLAN_VID_MASK;
  328. efx_filter_init_rx(&filter, EFX_FILTER_PRI_REQUIRED,
  329. vf->rx_filter_flags,
  330. abs_index(vf, vf->rx_filter_qid));
  331. rc = efx_filter_set_eth_local(&filter,
  332. vlan ? vlan : EFX_FILTER_VID_UNSPEC,
  333. vf->addr.mac_addr);
  334. BUG_ON(rc);
  335. rc = efx_filter_insert_filter(efx, &filter, true);
  336. if (rc < 0) {
  337. netif_warn(efx, hw, efx->net_dev,
  338. "Unable to insert rx filter for vf %s\n",
  339. vf->pci_name);
  340. } else {
  341. netif_dbg(efx, hw, efx->net_dev, "Inserted vf %s rx filter %d\n",
  342. vf->pci_name, rc);
  343. vf->rx_filter_id = rc;
  344. }
  345. }
  346. static void __efx_sriov_update_vf_addr(struct efx_vf *vf)
  347. {
  348. efx_sriov_reset_tx_filter(vf);
  349. efx_sriov_reset_rx_filter(vf);
  350. queue_work(vfdi_workqueue, &vf->efx->peer_work);
  351. }
  352. /* Push the peer list to this VF. The caller must hold status_lock to interlock
  353. * with VFDI requests, and they must be serialised against manipulation of
  354. * local_page_list, either by acquiring local_lock or by running from
  355. * efx_sriov_peer_work()
  356. */
  357. static void __efx_sriov_push_vf_status(struct efx_vf *vf)
  358. {
  359. struct efx_nic *efx = vf->efx;
  360. struct vfdi_status *status = efx->vfdi_status.addr;
  361. struct efx_memcpy_req copy[4];
  362. struct efx_endpoint_page *epp;
  363. unsigned int pos, count;
  364. unsigned data_offset;
  365. efx_qword_t event;
  366. WARN_ON(!mutex_is_locked(&vf->status_lock));
  367. WARN_ON(!vf->status_addr);
  368. status->local = vf->addr;
  369. status->generation_end = ++status->generation_start;
  370. memset(copy, '\0', sizeof(copy));
  371. /* Write generation_start */
  372. copy[0].from_buf = &status->generation_start;
  373. copy[0].to_rid = vf->pci_rid;
  374. copy[0].to_addr = vf->status_addr + offsetof(struct vfdi_status,
  375. generation_start);
  376. copy[0].length = sizeof(status->generation_start);
  377. /* DMA the rest of the structure (excluding the generations). This
  378. * assumes that the non-generation portion of vfdi_status is in
  379. * one chunk starting at the version member.
  380. */
  381. data_offset = offsetof(struct vfdi_status, version);
  382. copy[1].from_rid = efx->pci_dev->devfn;
  383. copy[1].from_addr = efx->vfdi_status.dma_addr + data_offset;
  384. copy[1].to_rid = vf->pci_rid;
  385. copy[1].to_addr = vf->status_addr + data_offset;
  386. copy[1].length = status->length - data_offset;
  387. /* Copy the peer pages */
  388. pos = 2;
  389. count = 0;
  390. list_for_each_entry(epp, &efx->local_page_list, link) {
  391. if (count == vf->peer_page_count) {
  392. /* The VF driver will know they need to provide more
  393. * pages because peer_addr_count is too large.
  394. */
  395. break;
  396. }
  397. copy[pos].from_buf = NULL;
  398. copy[pos].from_rid = efx->pci_dev->devfn;
  399. copy[pos].from_addr = epp->addr;
  400. copy[pos].to_rid = vf->pci_rid;
  401. copy[pos].to_addr = vf->peer_page_addrs[count];
  402. copy[pos].length = EFX_PAGE_SIZE;
  403. if (++pos == ARRAY_SIZE(copy)) {
  404. efx_sriov_memcpy(efx, copy, ARRAY_SIZE(copy));
  405. pos = 0;
  406. }
  407. ++count;
  408. }
  409. /* Write generation_end */
  410. copy[pos].from_buf = &status->generation_end;
  411. copy[pos].to_rid = vf->pci_rid;
  412. copy[pos].to_addr = vf->status_addr + offsetof(struct vfdi_status,
  413. generation_end);
  414. copy[pos].length = sizeof(status->generation_end);
  415. efx_sriov_memcpy(efx, copy, pos + 1);
  416. /* Notify the guest */
  417. EFX_POPULATE_QWORD_3(event,
  418. FSF_AZ_EV_CODE, FSE_CZ_EV_CODE_USER_EV,
  419. VFDI_EV_SEQ, (vf->msg_seqno & 0xff),
  420. VFDI_EV_TYPE, VFDI_EV_TYPE_STATUS);
  421. ++vf->msg_seqno;
  422. efx_generate_event(efx, EFX_VI_BASE + vf->index * efx_vf_size(efx),
  423. &event);
  424. }
  425. static void efx_sriov_bufs(struct efx_nic *efx, unsigned offset,
  426. u64 *addr, unsigned count)
  427. {
  428. efx_qword_t buf;
  429. unsigned pos;
  430. for (pos = 0; pos < count; ++pos) {
  431. EFX_POPULATE_QWORD_3(buf,
  432. FRF_AZ_BUF_ADR_REGION, 0,
  433. FRF_AZ_BUF_ADR_FBUF,
  434. addr ? addr[pos] >> 12 : 0,
  435. FRF_AZ_BUF_OWNER_ID_FBUF, 0);
  436. efx_sram_writeq(efx, efx->membase + FR_BZ_BUF_FULL_TBL,
  437. &buf, offset + pos);
  438. }
  439. }
  440. static bool bad_vf_index(struct efx_nic *efx, unsigned index)
  441. {
  442. return index >= efx_vf_size(efx);
  443. }
  444. static bool bad_buf_count(unsigned buf_count, unsigned max_entry_count)
  445. {
  446. unsigned max_buf_count = max_entry_count *
  447. sizeof(efx_qword_t) / EFX_BUF_SIZE;
  448. return ((buf_count & (buf_count - 1)) || buf_count > max_buf_count);
  449. }
  450. /* Check that VI specified by per-port index belongs to a VF.
  451. * Optionally set VF index and VI index within the VF.
  452. */
  453. static bool map_vi_index(struct efx_nic *efx, unsigned abs_index,
  454. struct efx_vf **vf_out, unsigned *rel_index_out)
  455. {
  456. unsigned vf_i;
  457. if (abs_index < EFX_VI_BASE)
  458. return true;
  459. vf_i = (abs_index - EFX_VI_BASE) / efx_vf_size(efx);
  460. if (vf_i >= efx->vf_init_count)
  461. return true;
  462. if (vf_out)
  463. *vf_out = efx->vf + vf_i;
  464. if (rel_index_out)
  465. *rel_index_out = abs_index % efx_vf_size(efx);
  466. return false;
  467. }
  468. static int efx_vfdi_init_evq(struct efx_vf *vf)
  469. {
  470. struct efx_nic *efx = vf->efx;
  471. struct vfdi_req *req = vf->buf.addr;
  472. unsigned vf_evq = req->u.init_evq.index;
  473. unsigned buf_count = req->u.init_evq.buf_count;
  474. unsigned abs_evq = abs_index(vf, vf_evq);
  475. unsigned buftbl = EFX_BUFTBL_EVQ_BASE(vf, vf_evq);
  476. efx_oword_t reg;
  477. if (bad_vf_index(efx, vf_evq) ||
  478. bad_buf_count(buf_count, EFX_MAX_VF_EVQ_SIZE)) {
  479. if (net_ratelimit())
  480. netif_err(efx, hw, efx->net_dev,
  481. "ERROR: Invalid INIT_EVQ from %s: evq %d bufs %d\n",
  482. vf->pci_name, vf_evq, buf_count);
  483. return VFDI_RC_EINVAL;
  484. }
  485. efx_sriov_bufs(efx, buftbl, req->u.init_evq.addr, buf_count);
  486. EFX_POPULATE_OWORD_3(reg,
  487. FRF_CZ_TIMER_Q_EN, 1,
  488. FRF_CZ_HOST_NOTIFY_MODE, 0,
  489. FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
  490. efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, abs_evq);
  491. EFX_POPULATE_OWORD_3(reg,
  492. FRF_AZ_EVQ_EN, 1,
  493. FRF_AZ_EVQ_SIZE, __ffs(buf_count),
  494. FRF_AZ_EVQ_BUF_BASE_ID, buftbl);
  495. efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL, abs_evq);
  496. if (vf_evq == 0) {
  497. memcpy(vf->evq0_addrs, req->u.init_evq.addr,
  498. buf_count * sizeof(u64));
  499. vf->evq0_count = buf_count;
  500. }
  501. return VFDI_RC_SUCCESS;
  502. }
  503. static int efx_vfdi_init_rxq(struct efx_vf *vf)
  504. {
  505. struct efx_nic *efx = vf->efx;
  506. struct vfdi_req *req = vf->buf.addr;
  507. unsigned vf_rxq = req->u.init_rxq.index;
  508. unsigned vf_evq = req->u.init_rxq.evq;
  509. unsigned buf_count = req->u.init_rxq.buf_count;
  510. unsigned buftbl = EFX_BUFTBL_RXQ_BASE(vf, vf_rxq);
  511. unsigned label;
  512. efx_oword_t reg;
  513. if (bad_vf_index(efx, vf_evq) || bad_vf_index(efx, vf_rxq) ||
  514. bad_buf_count(buf_count, EFX_MAX_DMAQ_SIZE)) {
  515. if (net_ratelimit())
  516. netif_err(efx, hw, efx->net_dev,
  517. "ERROR: Invalid INIT_RXQ from %s: rxq %d evq %d "
  518. "buf_count %d\n", vf->pci_name, vf_rxq,
  519. vf_evq, buf_count);
  520. return VFDI_RC_EINVAL;
  521. }
  522. if (__test_and_set_bit(req->u.init_rxq.index, vf->rxq_mask))
  523. ++vf->rxq_count;
  524. efx_sriov_bufs(efx, buftbl, req->u.init_rxq.addr, buf_count);
  525. label = req->u.init_rxq.label & EFX_FIELD_MASK(FRF_AZ_RX_DESCQ_LABEL);
  526. EFX_POPULATE_OWORD_6(reg,
  527. FRF_AZ_RX_DESCQ_BUF_BASE_ID, buftbl,
  528. FRF_AZ_RX_DESCQ_EVQ_ID, abs_index(vf, vf_evq),
  529. FRF_AZ_RX_DESCQ_LABEL, label,
  530. FRF_AZ_RX_DESCQ_SIZE, __ffs(buf_count),
  531. FRF_AZ_RX_DESCQ_JUMBO,
  532. !!(req->u.init_rxq.flags &
  533. VFDI_RXQ_FLAG_SCATTER_EN),
  534. FRF_AZ_RX_DESCQ_EN, 1);
  535. efx_writeo_table(efx, &reg, FR_BZ_RX_DESC_PTR_TBL,
  536. abs_index(vf, vf_rxq));
  537. return VFDI_RC_SUCCESS;
  538. }
  539. static int efx_vfdi_init_txq(struct efx_vf *vf)
  540. {
  541. struct efx_nic *efx = vf->efx;
  542. struct vfdi_req *req = vf->buf.addr;
  543. unsigned vf_txq = req->u.init_txq.index;
  544. unsigned vf_evq = req->u.init_txq.evq;
  545. unsigned buf_count = req->u.init_txq.buf_count;
  546. unsigned buftbl = EFX_BUFTBL_TXQ_BASE(vf, vf_txq);
  547. unsigned label, eth_filt_en;
  548. efx_oword_t reg;
  549. if (bad_vf_index(efx, vf_evq) || bad_vf_index(efx, vf_txq) ||
  550. vf_txq >= vf_max_tx_channels ||
  551. bad_buf_count(buf_count, EFX_MAX_DMAQ_SIZE)) {
  552. if (net_ratelimit())
  553. netif_err(efx, hw, efx->net_dev,
  554. "ERROR: Invalid INIT_TXQ from %s: txq %d evq %d "
  555. "buf_count %d\n", vf->pci_name, vf_txq,
  556. vf_evq, buf_count);
  557. return VFDI_RC_EINVAL;
  558. }
  559. mutex_lock(&vf->txq_lock);
  560. if (__test_and_set_bit(req->u.init_txq.index, vf->txq_mask))
  561. ++vf->txq_count;
  562. mutex_unlock(&vf->txq_lock);
  563. efx_sriov_bufs(efx, buftbl, req->u.init_txq.addr, buf_count);
  564. eth_filt_en = vf->tx_filter_mode == VF_TX_FILTER_ON;
  565. label = req->u.init_txq.label & EFX_FIELD_MASK(FRF_AZ_TX_DESCQ_LABEL);
  566. EFX_POPULATE_OWORD_8(reg,
  567. FRF_CZ_TX_DPT_Q_MASK_WIDTH, min(efx->vi_scale, 1U),
  568. FRF_CZ_TX_DPT_ETH_FILT_EN, eth_filt_en,
  569. FRF_AZ_TX_DESCQ_EN, 1,
  570. FRF_AZ_TX_DESCQ_BUF_BASE_ID, buftbl,
  571. FRF_AZ_TX_DESCQ_EVQ_ID, abs_index(vf, vf_evq),
  572. FRF_AZ_TX_DESCQ_LABEL, label,
  573. FRF_AZ_TX_DESCQ_SIZE, __ffs(buf_count),
  574. FRF_BZ_TX_NON_IP_DROP_DIS, 1);
  575. efx_writeo_table(efx, &reg, FR_BZ_TX_DESC_PTR_TBL,
  576. abs_index(vf, vf_txq));
  577. return VFDI_RC_SUCCESS;
  578. }
  579. /* Returns true when efx_vfdi_fini_all_queues should wake */
  580. static bool efx_vfdi_flush_wake(struct efx_vf *vf)
  581. {
  582. /* Ensure that all updates are visible to efx_vfdi_fini_all_queues() */
  583. smp_mb();
  584. return (!vf->txq_count && !vf->rxq_count) ||
  585. atomic_read(&vf->rxq_retry_count);
  586. }
  587. static void efx_vfdi_flush_clear(struct efx_vf *vf)
  588. {
  589. memset(vf->txq_mask, 0, sizeof(vf->txq_mask));
  590. vf->txq_count = 0;
  591. memset(vf->rxq_mask, 0, sizeof(vf->rxq_mask));
  592. vf->rxq_count = 0;
  593. memset(vf->rxq_retry_mask, 0, sizeof(vf->rxq_retry_mask));
  594. atomic_set(&vf->rxq_retry_count, 0);
  595. }
  596. static int efx_vfdi_fini_all_queues(struct efx_vf *vf)
  597. {
  598. struct efx_nic *efx = vf->efx;
  599. efx_oword_t reg;
  600. unsigned count = efx_vf_size(efx);
  601. unsigned vf_offset = EFX_VI_BASE + vf->index * efx_vf_size(efx);
  602. unsigned timeout = HZ;
  603. unsigned index, rxqs_count;
  604. __le32 *rxqs;
  605. int rc;
  606. rxqs = kmalloc(count * sizeof(*rxqs), GFP_KERNEL);
  607. if (rxqs == NULL)
  608. return VFDI_RC_ENOMEM;
  609. rtnl_lock();
  610. if (efx->fc_disable++ == 0)
  611. efx_mcdi_set_mac(efx);
  612. rtnl_unlock();
  613. /* Flush all the initialized queues */
  614. rxqs_count = 0;
  615. for (index = 0; index < count; ++index) {
  616. if (test_bit(index, vf->txq_mask)) {
  617. EFX_POPULATE_OWORD_2(reg,
  618. FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
  619. FRF_AZ_TX_FLUSH_DESCQ,
  620. vf_offset + index);
  621. efx_writeo(efx, &reg, FR_AZ_TX_FLUSH_DESCQ);
  622. }
  623. if (test_bit(index, vf->rxq_mask))
  624. rxqs[rxqs_count++] = cpu_to_le32(vf_offset + index);
  625. }
  626. atomic_set(&vf->rxq_retry_count, 0);
  627. while (timeout && (vf->rxq_count || vf->txq_count)) {
  628. rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, (u8 *)rxqs,
  629. rxqs_count * sizeof(*rxqs), NULL, 0, NULL);
  630. WARN_ON(rc < 0);
  631. timeout = wait_event_timeout(vf->flush_waitq,
  632. efx_vfdi_flush_wake(vf),
  633. timeout);
  634. rxqs_count = 0;
  635. for (index = 0; index < count; ++index) {
  636. if (test_and_clear_bit(index, vf->rxq_retry_mask)) {
  637. atomic_dec(&vf->rxq_retry_count);
  638. rxqs[rxqs_count++] =
  639. cpu_to_le32(vf_offset + index);
  640. }
  641. }
  642. }
  643. rtnl_lock();
  644. if (--efx->fc_disable == 0)
  645. efx_mcdi_set_mac(efx);
  646. rtnl_unlock();
  647. /* Irrespective of success/failure, fini the queues */
  648. EFX_ZERO_OWORD(reg);
  649. for (index = 0; index < count; ++index) {
  650. efx_writeo_table(efx, &reg, FR_BZ_RX_DESC_PTR_TBL,
  651. vf_offset + index);
  652. efx_writeo_table(efx, &reg, FR_BZ_TX_DESC_PTR_TBL,
  653. vf_offset + index);
  654. efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL,
  655. vf_offset + index);
  656. efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL,
  657. vf_offset + index);
  658. }
  659. efx_sriov_bufs(efx, vf->buftbl_base, NULL,
  660. EFX_VF_BUFTBL_PER_VI * efx_vf_size(efx));
  661. kfree(rxqs);
  662. efx_vfdi_flush_clear(vf);
  663. vf->evq0_count = 0;
  664. return timeout ? 0 : VFDI_RC_ETIMEDOUT;
  665. }
  666. static int efx_vfdi_insert_filter(struct efx_vf *vf)
  667. {
  668. struct efx_nic *efx = vf->efx;
  669. struct vfdi_req *req = vf->buf.addr;
  670. unsigned vf_rxq = req->u.mac_filter.rxq;
  671. unsigned flags;
  672. if (bad_vf_index(efx, vf_rxq) || vf->rx_filtering) {
  673. if (net_ratelimit())
  674. netif_err(efx, hw, efx->net_dev,
  675. "ERROR: Invalid INSERT_FILTER from %s: rxq %d "
  676. "flags 0x%x\n", vf->pci_name, vf_rxq,
  677. req->u.mac_filter.flags);
  678. return VFDI_RC_EINVAL;
  679. }
  680. flags = 0;
  681. if (req->u.mac_filter.flags & VFDI_MAC_FILTER_FLAG_RSS)
  682. flags |= EFX_FILTER_FLAG_RX_RSS;
  683. if (req->u.mac_filter.flags & VFDI_MAC_FILTER_FLAG_SCATTER)
  684. flags |= EFX_FILTER_FLAG_RX_SCATTER;
  685. vf->rx_filter_flags = flags;
  686. vf->rx_filter_qid = vf_rxq;
  687. vf->rx_filtering = true;
  688. efx_sriov_reset_rx_filter(vf);
  689. queue_work(vfdi_workqueue, &efx->peer_work);
  690. return VFDI_RC_SUCCESS;
  691. }
  692. static int efx_vfdi_remove_all_filters(struct efx_vf *vf)
  693. {
  694. vf->rx_filtering = false;
  695. efx_sriov_reset_rx_filter(vf);
  696. queue_work(vfdi_workqueue, &vf->efx->peer_work);
  697. return VFDI_RC_SUCCESS;
  698. }
  699. static int efx_vfdi_set_status_page(struct efx_vf *vf)
  700. {
  701. struct efx_nic *efx = vf->efx;
  702. struct vfdi_req *req = vf->buf.addr;
  703. u64 page_count = req->u.set_status_page.peer_page_count;
  704. u64 max_page_count =
  705. (EFX_PAGE_SIZE -
  706. offsetof(struct vfdi_req, u.set_status_page.peer_page_addr[0]))
  707. / sizeof(req->u.set_status_page.peer_page_addr[0]);
  708. if (!req->u.set_status_page.dma_addr || page_count > max_page_count) {
  709. if (net_ratelimit())
  710. netif_err(efx, hw, efx->net_dev,
  711. "ERROR: Invalid SET_STATUS_PAGE from %s\n",
  712. vf->pci_name);
  713. return VFDI_RC_EINVAL;
  714. }
  715. mutex_lock(&efx->local_lock);
  716. mutex_lock(&vf->status_lock);
  717. vf->status_addr = req->u.set_status_page.dma_addr;
  718. kfree(vf->peer_page_addrs);
  719. vf->peer_page_addrs = NULL;
  720. vf->peer_page_count = 0;
  721. if (page_count) {
  722. vf->peer_page_addrs = kcalloc(page_count, sizeof(u64),
  723. GFP_KERNEL);
  724. if (vf->peer_page_addrs) {
  725. memcpy(vf->peer_page_addrs,
  726. req->u.set_status_page.peer_page_addr,
  727. page_count * sizeof(u64));
  728. vf->peer_page_count = page_count;
  729. }
  730. }
  731. __efx_sriov_push_vf_status(vf);
  732. mutex_unlock(&vf->status_lock);
  733. mutex_unlock(&efx->local_lock);
  734. return VFDI_RC_SUCCESS;
  735. }
  736. static int efx_vfdi_clear_status_page(struct efx_vf *vf)
  737. {
  738. mutex_lock(&vf->status_lock);
  739. vf->status_addr = 0;
  740. mutex_unlock(&vf->status_lock);
  741. return VFDI_RC_SUCCESS;
  742. }
  743. typedef int (*efx_vfdi_op_t)(struct efx_vf *vf);
  744. static const efx_vfdi_op_t vfdi_ops[VFDI_OP_LIMIT] = {
  745. [VFDI_OP_INIT_EVQ] = efx_vfdi_init_evq,
  746. [VFDI_OP_INIT_TXQ] = efx_vfdi_init_txq,
  747. [VFDI_OP_INIT_RXQ] = efx_vfdi_init_rxq,
  748. [VFDI_OP_FINI_ALL_QUEUES] = efx_vfdi_fini_all_queues,
  749. [VFDI_OP_INSERT_FILTER] = efx_vfdi_insert_filter,
  750. [VFDI_OP_REMOVE_ALL_FILTERS] = efx_vfdi_remove_all_filters,
  751. [VFDI_OP_SET_STATUS_PAGE] = efx_vfdi_set_status_page,
  752. [VFDI_OP_CLEAR_STATUS_PAGE] = efx_vfdi_clear_status_page,
  753. };
  754. static void efx_sriov_vfdi(struct work_struct *work)
  755. {
  756. struct efx_vf *vf = container_of(work, struct efx_vf, req);
  757. struct efx_nic *efx = vf->efx;
  758. struct vfdi_req *req = vf->buf.addr;
  759. struct efx_memcpy_req copy[2];
  760. int rc;
  761. /* Copy this page into the local address space */
  762. memset(copy, '\0', sizeof(copy));
  763. copy[0].from_rid = vf->pci_rid;
  764. copy[0].from_addr = vf->req_addr;
  765. copy[0].to_rid = efx->pci_dev->devfn;
  766. copy[0].to_addr = vf->buf.dma_addr;
  767. copy[0].length = EFX_PAGE_SIZE;
  768. rc = efx_sriov_memcpy(efx, copy, 1);
  769. if (rc) {
  770. /* If we can't get the request, we can't reply to the caller */
  771. if (net_ratelimit())
  772. netif_err(efx, hw, efx->net_dev,
  773. "ERROR: Unable to fetch VFDI request from %s rc %d\n",
  774. vf->pci_name, -rc);
  775. vf->busy = false;
  776. return;
  777. }
  778. if (req->op < VFDI_OP_LIMIT && vfdi_ops[req->op] != NULL) {
  779. rc = vfdi_ops[req->op](vf);
  780. if (rc == 0) {
  781. netif_dbg(efx, hw, efx->net_dev,
  782. "vfdi request %d from %s ok\n",
  783. req->op, vf->pci_name);
  784. }
  785. } else {
  786. netif_dbg(efx, hw, efx->net_dev,
  787. "ERROR: Unrecognised request %d from VF %s addr "
  788. "%llx\n", req->op, vf->pci_name,
  789. (unsigned long long)vf->req_addr);
  790. rc = VFDI_RC_EOPNOTSUPP;
  791. }
  792. /* Allow subsequent VF requests */
  793. vf->busy = false;
  794. smp_wmb();
  795. /* Respond to the request */
  796. req->rc = rc;
  797. req->op = VFDI_OP_RESPONSE;
  798. memset(copy, '\0', sizeof(copy));
  799. copy[0].from_buf = &req->rc;
  800. copy[0].to_rid = vf->pci_rid;
  801. copy[0].to_addr = vf->req_addr + offsetof(struct vfdi_req, rc);
  802. copy[0].length = sizeof(req->rc);
  803. copy[1].from_buf = &req->op;
  804. copy[1].to_rid = vf->pci_rid;
  805. copy[1].to_addr = vf->req_addr + offsetof(struct vfdi_req, op);
  806. copy[1].length = sizeof(req->op);
  807. (void) efx_sriov_memcpy(efx, copy, ARRAY_SIZE(copy));
  808. }
  809. /* After a reset the event queues inside the guests no longer exist. Fill the
  810. * event ring in guest memory with VFDI reset events, then (re-initialise) the
  811. * event queue to raise an interrupt. The guest driver will then recover.
  812. */
  813. static void efx_sriov_reset_vf(struct efx_vf *vf, struct efx_buffer *buffer)
  814. {
  815. struct efx_nic *efx = vf->efx;
  816. struct efx_memcpy_req copy_req[4];
  817. efx_qword_t event;
  818. unsigned int pos, count, k, buftbl, abs_evq;
  819. efx_oword_t reg;
  820. efx_dword_t ptr;
  821. int rc;
  822. BUG_ON(buffer->len != EFX_PAGE_SIZE);
  823. if (!vf->evq0_count)
  824. return;
  825. BUG_ON(vf->evq0_count & (vf->evq0_count - 1));
  826. mutex_lock(&vf->status_lock);
  827. EFX_POPULATE_QWORD_3(event,
  828. FSF_AZ_EV_CODE, FSE_CZ_EV_CODE_USER_EV,
  829. VFDI_EV_SEQ, vf->msg_seqno,
  830. VFDI_EV_TYPE, VFDI_EV_TYPE_RESET);
  831. vf->msg_seqno++;
  832. for (pos = 0; pos < EFX_PAGE_SIZE; pos += sizeof(event))
  833. memcpy(buffer->addr + pos, &event, sizeof(event));
  834. for (pos = 0; pos < vf->evq0_count; pos += count) {
  835. count = min_t(unsigned, vf->evq0_count - pos,
  836. ARRAY_SIZE(copy_req));
  837. for (k = 0; k < count; k++) {
  838. copy_req[k].from_buf = NULL;
  839. copy_req[k].from_rid = efx->pci_dev->devfn;
  840. copy_req[k].from_addr = buffer->dma_addr;
  841. copy_req[k].to_rid = vf->pci_rid;
  842. copy_req[k].to_addr = vf->evq0_addrs[pos + k];
  843. copy_req[k].length = EFX_PAGE_SIZE;
  844. }
  845. rc = efx_sriov_memcpy(efx, copy_req, count);
  846. if (rc) {
  847. if (net_ratelimit())
  848. netif_err(efx, hw, efx->net_dev,
  849. "ERROR: Unable to notify %s of reset"
  850. ": %d\n", vf->pci_name, -rc);
  851. break;
  852. }
  853. }
  854. /* Reinitialise, arm and trigger evq0 */
  855. abs_evq = abs_index(vf, 0);
  856. buftbl = EFX_BUFTBL_EVQ_BASE(vf, 0);
  857. efx_sriov_bufs(efx, buftbl, vf->evq0_addrs, vf->evq0_count);
  858. EFX_POPULATE_OWORD_3(reg,
  859. FRF_CZ_TIMER_Q_EN, 1,
  860. FRF_CZ_HOST_NOTIFY_MODE, 0,
  861. FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
  862. efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, abs_evq);
  863. EFX_POPULATE_OWORD_3(reg,
  864. FRF_AZ_EVQ_EN, 1,
  865. FRF_AZ_EVQ_SIZE, __ffs(vf->evq0_count),
  866. FRF_AZ_EVQ_BUF_BASE_ID, buftbl);
  867. efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL, abs_evq);
  868. EFX_POPULATE_DWORD_1(ptr, FRF_AZ_EVQ_RPTR, 0);
  869. efx_writed_table(efx, &ptr, FR_BZ_EVQ_RPTR, abs_evq);
  870. mutex_unlock(&vf->status_lock);
  871. }
  872. static void efx_sriov_reset_vf_work(struct work_struct *work)
  873. {
  874. struct efx_vf *vf = container_of(work, struct efx_vf, req);
  875. struct efx_nic *efx = vf->efx;
  876. struct efx_buffer buf;
  877. if (!efx_nic_alloc_buffer(efx, &buf, EFX_PAGE_SIZE)) {
  878. efx_sriov_reset_vf(vf, &buf);
  879. efx_nic_free_buffer(efx, &buf);
  880. }
  881. }
  882. static void efx_sriov_handle_no_channel(struct efx_nic *efx)
  883. {
  884. netif_err(efx, drv, efx->net_dev,
  885. "ERROR: IOV requires MSI-X and 1 additional interrupt"
  886. "vector. IOV disabled\n");
  887. efx->vf_count = 0;
  888. }
  889. static int efx_sriov_probe_channel(struct efx_channel *channel)
  890. {
  891. channel->efx->vfdi_channel = channel;
  892. return 0;
  893. }
  894. static void
  895. efx_sriov_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
  896. {
  897. snprintf(buf, len, "%s-iov", channel->efx->name);
  898. }
  899. static const struct efx_channel_type efx_sriov_channel_type = {
  900. .handle_no_channel = efx_sriov_handle_no_channel,
  901. .pre_probe = efx_sriov_probe_channel,
  902. .get_name = efx_sriov_get_channel_name,
  903. /* no copy operation; channel must not be reallocated */
  904. .keep_eventq = true,
  905. };
  906. void efx_sriov_probe(struct efx_nic *efx)
  907. {
  908. unsigned count;
  909. if (!max_vfs)
  910. return;
  911. if (efx_sriov_cmd(efx, false, &efx->vi_scale, &count))
  912. return;
  913. if (count > 0 && count > max_vfs)
  914. count = max_vfs;
  915. /* efx_nic_dimension_resources() will reduce vf_count as appopriate */
  916. efx->vf_count = count;
  917. efx->extra_channel_type[EFX_EXTRA_CHANNEL_IOV] = &efx_sriov_channel_type;
  918. }
  919. /* Copy the list of individual addresses into the vfdi_status.peers
  920. * array and auxillary pages, protected by %local_lock. Drop that lock
  921. * and then broadcast the address list to every VF.
  922. */
  923. static void efx_sriov_peer_work(struct work_struct *data)
  924. {
  925. struct efx_nic *efx = container_of(data, struct efx_nic, peer_work);
  926. struct vfdi_status *vfdi_status = efx->vfdi_status.addr;
  927. struct efx_vf *vf;
  928. struct efx_local_addr *local_addr;
  929. struct vfdi_endpoint *peer;
  930. struct efx_endpoint_page *epp;
  931. struct list_head pages;
  932. unsigned int peer_space;
  933. unsigned int peer_count;
  934. unsigned int pos;
  935. mutex_lock(&efx->local_lock);
  936. /* Move the existing peer pages off %local_page_list */
  937. INIT_LIST_HEAD(&pages);
  938. list_splice_tail_init(&efx->local_page_list, &pages);
  939. /* Populate the VF addresses starting from entry 1 (entry 0 is
  940. * the PF address)
  941. */
  942. peer = vfdi_status->peers + 1;
  943. peer_space = ARRAY_SIZE(vfdi_status->peers) - 1;
  944. peer_count = 1;
  945. for (pos = 0; pos < efx->vf_count; ++pos) {
  946. vf = efx->vf + pos;
  947. mutex_lock(&vf->status_lock);
  948. if (vf->rx_filtering && !is_zero_ether_addr(vf->addr.mac_addr)) {
  949. *peer++ = vf->addr;
  950. ++peer_count;
  951. --peer_space;
  952. BUG_ON(peer_space == 0);
  953. }
  954. mutex_unlock(&vf->status_lock);
  955. }
  956. /* Fill the remaining addresses */
  957. list_for_each_entry(local_addr, &efx->local_addr_list, link) {
  958. memcpy(peer->mac_addr, local_addr->addr, ETH_ALEN);
  959. peer->tci = 0;
  960. ++peer;
  961. ++peer_count;
  962. if (--peer_space == 0) {
  963. if (list_empty(&pages)) {
  964. epp = kmalloc(sizeof(*epp), GFP_KERNEL);
  965. if (!epp)
  966. break;
  967. epp->ptr = dma_alloc_coherent(
  968. &efx->pci_dev->dev, EFX_PAGE_SIZE,
  969. &epp->addr, GFP_KERNEL);
  970. if (!epp->ptr) {
  971. kfree(epp);
  972. break;
  973. }
  974. } else {
  975. epp = list_first_entry(
  976. &pages, struct efx_endpoint_page, link);
  977. list_del(&epp->link);
  978. }
  979. list_add_tail(&epp->link, &efx->local_page_list);
  980. peer = (struct vfdi_endpoint *)epp->ptr;
  981. peer_space = EFX_PAGE_SIZE / sizeof(struct vfdi_endpoint);
  982. }
  983. }
  984. vfdi_status->peer_count = peer_count;
  985. mutex_unlock(&efx->local_lock);
  986. /* Free any now unused endpoint pages */
  987. while (!list_empty(&pages)) {
  988. epp = list_first_entry(
  989. &pages, struct efx_endpoint_page, link);
  990. list_del(&epp->link);
  991. dma_free_coherent(&efx->pci_dev->dev, EFX_PAGE_SIZE,
  992. epp->ptr, epp->addr);
  993. kfree(epp);
  994. }
  995. /* Finally, push the pages */
  996. for (pos = 0; pos < efx->vf_count; ++pos) {
  997. vf = efx->vf + pos;
  998. mutex_lock(&vf->status_lock);
  999. if (vf->status_addr)
  1000. __efx_sriov_push_vf_status(vf);
  1001. mutex_unlock(&vf->status_lock);
  1002. }
  1003. }
  1004. static void efx_sriov_free_local(struct efx_nic *efx)
  1005. {
  1006. struct efx_local_addr *local_addr;
  1007. struct efx_endpoint_page *epp;
  1008. while (!list_empty(&efx->local_addr_list)) {
  1009. local_addr = list_first_entry(&efx->local_addr_list,
  1010. struct efx_local_addr, link);
  1011. list_del(&local_addr->link);
  1012. kfree(local_addr);
  1013. }
  1014. while (!list_empty(&efx->local_page_list)) {
  1015. epp = list_first_entry(&efx->local_page_list,
  1016. struct efx_endpoint_page, link);
  1017. list_del(&epp->link);
  1018. dma_free_coherent(&efx->pci_dev->dev, EFX_PAGE_SIZE,
  1019. epp->ptr, epp->addr);
  1020. kfree(epp);
  1021. }
  1022. }
  1023. static int efx_sriov_vf_alloc(struct efx_nic *efx)
  1024. {
  1025. unsigned index;
  1026. struct efx_vf *vf;
  1027. efx->vf = kzalloc(sizeof(struct efx_vf) * efx->vf_count, GFP_KERNEL);
  1028. if (!efx->vf)
  1029. return -ENOMEM;
  1030. for (index = 0; index < efx->vf_count; ++index) {
  1031. vf = efx->vf + index;
  1032. vf->efx = efx;
  1033. vf->index = index;
  1034. vf->rx_filter_id = -1;
  1035. vf->tx_filter_mode = VF_TX_FILTER_AUTO;
  1036. vf->tx_filter_id = -1;
  1037. INIT_WORK(&vf->req, efx_sriov_vfdi);
  1038. INIT_WORK(&vf->reset_work, efx_sriov_reset_vf_work);
  1039. init_waitqueue_head(&vf->flush_waitq);
  1040. mutex_init(&vf->status_lock);
  1041. mutex_init(&vf->txq_lock);
  1042. }
  1043. return 0;
  1044. }
  1045. static void efx_sriov_vfs_fini(struct efx_nic *efx)
  1046. {
  1047. struct efx_vf *vf;
  1048. unsigned int pos;
  1049. for (pos = 0; pos < efx->vf_count; ++pos) {
  1050. vf = efx->vf + pos;
  1051. efx_nic_free_buffer(efx, &vf->buf);
  1052. kfree(vf->peer_page_addrs);
  1053. vf->peer_page_addrs = NULL;
  1054. vf->peer_page_count = 0;
  1055. vf->evq0_count = 0;
  1056. }
  1057. }
  1058. static int efx_sriov_vfs_init(struct efx_nic *efx)
  1059. {
  1060. struct pci_dev *pci_dev = efx->pci_dev;
  1061. unsigned index, devfn, sriov, buftbl_base;
  1062. u16 offset, stride;
  1063. struct efx_vf *vf;
  1064. int rc;
  1065. sriov = pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_SRIOV);
  1066. if (!sriov)
  1067. return -ENOENT;
  1068. pci_read_config_word(pci_dev, sriov + PCI_SRIOV_VF_OFFSET, &offset);
  1069. pci_read_config_word(pci_dev, sriov + PCI_SRIOV_VF_STRIDE, &stride);
  1070. buftbl_base = efx->vf_buftbl_base;
  1071. devfn = pci_dev->devfn + offset;
  1072. for (index = 0; index < efx->vf_count; ++index) {
  1073. vf = efx->vf + index;
  1074. /* Reserve buffer entries */
  1075. vf->buftbl_base = buftbl_base;
  1076. buftbl_base += EFX_VF_BUFTBL_PER_VI * efx_vf_size(efx);
  1077. vf->pci_rid = devfn;
  1078. snprintf(vf->pci_name, sizeof(vf->pci_name),
  1079. "%04x:%02x:%02x.%d",
  1080. pci_domain_nr(pci_dev->bus), pci_dev->bus->number,
  1081. PCI_SLOT(devfn), PCI_FUNC(devfn));
  1082. rc = efx_nic_alloc_buffer(efx, &vf->buf, EFX_PAGE_SIZE);
  1083. if (rc)
  1084. goto fail;
  1085. devfn += stride;
  1086. }
  1087. return 0;
  1088. fail:
  1089. efx_sriov_vfs_fini(efx);
  1090. return rc;
  1091. }
  1092. int efx_sriov_init(struct efx_nic *efx)
  1093. {
  1094. struct net_device *net_dev = efx->net_dev;
  1095. struct vfdi_status *vfdi_status;
  1096. int rc;
  1097. /* Ensure there's room for vf_channel */
  1098. BUILD_BUG_ON(EFX_MAX_CHANNELS + 1 >= EFX_VI_BASE);
  1099. /* Ensure that VI_BASE is aligned on VI_SCALE */
  1100. BUILD_BUG_ON(EFX_VI_BASE & ((1 << EFX_VI_SCALE_MAX) - 1));
  1101. if (efx->vf_count == 0)
  1102. return 0;
  1103. rc = efx_sriov_cmd(efx, true, NULL, NULL);
  1104. if (rc)
  1105. goto fail_cmd;
  1106. rc = efx_nic_alloc_buffer(efx, &efx->vfdi_status, sizeof(*vfdi_status));
  1107. if (rc)
  1108. goto fail_status;
  1109. vfdi_status = efx->vfdi_status.addr;
  1110. memset(vfdi_status, 0, sizeof(*vfdi_status));
  1111. vfdi_status->version = 1;
  1112. vfdi_status->length = sizeof(*vfdi_status);
  1113. vfdi_status->max_tx_channels = vf_max_tx_channels;
  1114. vfdi_status->vi_scale = efx->vi_scale;
  1115. vfdi_status->rss_rxq_count = efx->rss_spread;
  1116. vfdi_status->peer_count = 1 + efx->vf_count;
  1117. vfdi_status->timer_quantum_ns = efx->timer_quantum_ns;
  1118. rc = efx_sriov_vf_alloc(efx);
  1119. if (rc)
  1120. goto fail_alloc;
  1121. mutex_init(&efx->local_lock);
  1122. INIT_WORK(&efx->peer_work, efx_sriov_peer_work);
  1123. INIT_LIST_HEAD(&efx->local_addr_list);
  1124. INIT_LIST_HEAD(&efx->local_page_list);
  1125. rc = efx_sriov_vfs_init(efx);
  1126. if (rc)
  1127. goto fail_vfs;
  1128. rtnl_lock();
  1129. memcpy(vfdi_status->peers[0].mac_addr,
  1130. net_dev->dev_addr, ETH_ALEN);
  1131. efx->vf_init_count = efx->vf_count;
  1132. rtnl_unlock();
  1133. efx_sriov_usrev(efx, true);
  1134. /* At this point we must be ready to accept VFDI requests */
  1135. rc = pci_enable_sriov(efx->pci_dev, efx->vf_count);
  1136. if (rc)
  1137. goto fail_pci;
  1138. netif_info(efx, probe, net_dev,
  1139. "enabled SR-IOV for %d VFs, %d VI per VF\n",
  1140. efx->vf_count, efx_vf_size(efx));
  1141. return 0;
  1142. fail_pci:
  1143. efx_sriov_usrev(efx, false);
  1144. rtnl_lock();
  1145. efx->vf_init_count = 0;
  1146. rtnl_unlock();
  1147. efx_sriov_vfs_fini(efx);
  1148. fail_vfs:
  1149. cancel_work_sync(&efx->peer_work);
  1150. efx_sriov_free_local(efx);
  1151. kfree(efx->vf);
  1152. fail_alloc:
  1153. efx_nic_free_buffer(efx, &efx->vfdi_status);
  1154. fail_status:
  1155. efx_sriov_cmd(efx, false, NULL, NULL);
  1156. fail_cmd:
  1157. return rc;
  1158. }
  1159. void efx_sriov_fini(struct efx_nic *efx)
  1160. {
  1161. struct efx_vf *vf;
  1162. unsigned int pos;
  1163. if (efx->vf_init_count == 0)
  1164. return;
  1165. /* Disable all interfaces to reconfiguration */
  1166. BUG_ON(efx->vfdi_channel->enabled);
  1167. efx_sriov_usrev(efx, false);
  1168. rtnl_lock();
  1169. efx->vf_init_count = 0;
  1170. rtnl_unlock();
  1171. /* Flush all reconfiguration work */
  1172. for (pos = 0; pos < efx->vf_count; ++pos) {
  1173. vf = efx->vf + pos;
  1174. cancel_work_sync(&vf->req);
  1175. cancel_work_sync(&vf->reset_work);
  1176. }
  1177. cancel_work_sync(&efx->peer_work);
  1178. pci_disable_sriov(efx->pci_dev);
  1179. /* Tear down back-end state */
  1180. efx_sriov_vfs_fini(efx);
  1181. efx_sriov_free_local(efx);
  1182. kfree(efx->vf);
  1183. efx_nic_free_buffer(efx, &efx->vfdi_status);
  1184. efx_sriov_cmd(efx, false, NULL, NULL);
  1185. }
  1186. void efx_sriov_event(struct efx_channel *channel, efx_qword_t *event)
  1187. {
  1188. struct efx_nic *efx = channel->efx;
  1189. struct efx_vf *vf;
  1190. unsigned qid, seq, type, data;
  1191. qid = EFX_QWORD_FIELD(*event, FSF_CZ_USER_QID);
  1192. /* USR_EV_REG_VALUE is dword0, so access the VFDI_EV fields directly */
  1193. BUILD_BUG_ON(FSF_CZ_USER_EV_REG_VALUE_LBN != 0);
  1194. seq = EFX_QWORD_FIELD(*event, VFDI_EV_SEQ);
  1195. type = EFX_QWORD_FIELD(*event, VFDI_EV_TYPE);
  1196. data = EFX_QWORD_FIELD(*event, VFDI_EV_DATA);
  1197. netif_vdbg(efx, hw, efx->net_dev,
  1198. "USR_EV event from qid %d seq 0x%x type %d data 0x%x\n",
  1199. qid, seq, type, data);
  1200. if (map_vi_index(efx, qid, &vf, NULL))
  1201. return;
  1202. if (vf->busy)
  1203. goto error;
  1204. if (type == VFDI_EV_TYPE_REQ_WORD0) {
  1205. /* Resynchronise */
  1206. vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
  1207. vf->req_seqno = seq + 1;
  1208. vf->req_addr = 0;
  1209. } else if (seq != (vf->req_seqno++ & 0xff) || type != vf->req_type)
  1210. goto error;
  1211. switch (vf->req_type) {
  1212. case VFDI_EV_TYPE_REQ_WORD0:
  1213. case VFDI_EV_TYPE_REQ_WORD1:
  1214. case VFDI_EV_TYPE_REQ_WORD2:
  1215. vf->req_addr |= (u64)data << (vf->req_type << 4);
  1216. ++vf->req_type;
  1217. return;
  1218. case VFDI_EV_TYPE_REQ_WORD3:
  1219. vf->req_addr |= (u64)data << 48;
  1220. vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
  1221. vf->busy = true;
  1222. queue_work(vfdi_workqueue, &vf->req);
  1223. return;
  1224. }
  1225. error:
  1226. if (net_ratelimit())
  1227. netif_err(efx, hw, efx->net_dev,
  1228. "ERROR: Screaming VFDI request from %s\n",
  1229. vf->pci_name);
  1230. /* Reset the request and sequence number */
  1231. vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
  1232. vf->req_seqno = seq + 1;
  1233. }
  1234. void efx_sriov_flr(struct efx_nic *efx, unsigned vf_i)
  1235. {
  1236. struct efx_vf *vf;
  1237. if (vf_i > efx->vf_init_count)
  1238. return;
  1239. vf = efx->vf + vf_i;
  1240. netif_info(efx, hw, efx->net_dev,
  1241. "FLR on VF %s\n", vf->pci_name);
  1242. vf->status_addr = 0;
  1243. efx_vfdi_remove_all_filters(vf);
  1244. efx_vfdi_flush_clear(vf);
  1245. vf->evq0_count = 0;
  1246. }
  1247. void efx_sriov_mac_address_changed(struct efx_nic *efx)
  1248. {
  1249. struct vfdi_status *vfdi_status = efx->vfdi_status.addr;
  1250. if (!efx->vf_init_count)
  1251. return;
  1252. memcpy(vfdi_status->peers[0].mac_addr,
  1253. efx->net_dev->dev_addr, ETH_ALEN);
  1254. queue_work(vfdi_workqueue, &efx->peer_work);
  1255. }
  1256. void efx_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
  1257. {
  1258. struct efx_vf *vf;
  1259. unsigned queue, qid;
  1260. queue = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
  1261. if (map_vi_index(efx, queue, &vf, &qid))
  1262. return;
  1263. /* Ignore flush completions triggered by an FLR */
  1264. if (!test_bit(qid, vf->txq_mask))
  1265. return;
  1266. __clear_bit(qid, vf->txq_mask);
  1267. --vf->txq_count;
  1268. if (efx_vfdi_flush_wake(vf))
  1269. wake_up(&vf->flush_waitq);
  1270. }
  1271. void efx_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event)
  1272. {
  1273. struct efx_vf *vf;
  1274. unsigned ev_failed, queue, qid;
  1275. queue = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
  1276. ev_failed = EFX_QWORD_FIELD(*event,
  1277. FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
  1278. if (map_vi_index(efx, queue, &vf, &qid))
  1279. return;
  1280. if (!test_bit(qid, vf->rxq_mask))
  1281. return;
  1282. if (ev_failed) {
  1283. set_bit(qid, vf->rxq_retry_mask);
  1284. atomic_inc(&vf->rxq_retry_count);
  1285. } else {
  1286. __clear_bit(qid, vf->rxq_mask);
  1287. --vf->rxq_count;
  1288. }
  1289. if (efx_vfdi_flush_wake(vf))
  1290. wake_up(&vf->flush_waitq);
  1291. }
  1292. /* Called from napi. Schedule the reset work item */
  1293. void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq)
  1294. {
  1295. struct efx_vf *vf;
  1296. unsigned int rel;
  1297. if (map_vi_index(efx, dmaq, &vf, &rel))
  1298. return;
  1299. if (net_ratelimit())
  1300. netif_err(efx, hw, efx->net_dev,
  1301. "VF %d DMA Q %d reports descriptor fetch error.\n",
  1302. vf->index, rel);
  1303. queue_work(vfdi_workqueue, &vf->reset_work);
  1304. }
  1305. /* Reset all VFs */
  1306. void efx_sriov_reset(struct efx_nic *efx)
  1307. {
  1308. unsigned int vf_i;
  1309. struct efx_buffer buf;
  1310. struct efx_vf *vf;
  1311. ASSERT_RTNL();
  1312. if (efx->vf_init_count == 0)
  1313. return;
  1314. efx_sriov_usrev(efx, true);
  1315. (void)efx_sriov_cmd(efx, true, NULL, NULL);
  1316. if (efx_nic_alloc_buffer(efx, &buf, EFX_PAGE_SIZE))
  1317. return;
  1318. for (vf_i = 0; vf_i < efx->vf_init_count; ++vf_i) {
  1319. vf = efx->vf + vf_i;
  1320. efx_sriov_reset_vf(vf, &buf);
  1321. }
  1322. efx_nic_free_buffer(efx, &buf);
  1323. }
  1324. int efx_init_sriov(void)
  1325. {
  1326. /* A single threaded workqueue is sufficient. efx_sriov_vfdi() and
  1327. * efx_sriov_peer_work() spend almost all their time sleeping for
  1328. * MCDI to complete anyway
  1329. */
  1330. vfdi_workqueue = create_singlethread_workqueue("sfc_vfdi");
  1331. if (!vfdi_workqueue)
  1332. return -ENOMEM;
  1333. return 0;
  1334. }
  1335. void efx_fini_sriov(void)
  1336. {
  1337. destroy_workqueue(vfdi_workqueue);
  1338. }
  1339. int efx_sriov_set_vf_mac(struct net_device *net_dev, int vf_i, u8 *mac)
  1340. {
  1341. struct efx_nic *efx = netdev_priv(net_dev);
  1342. struct efx_vf *vf;
  1343. if (vf_i >= efx->vf_init_count)
  1344. return -EINVAL;
  1345. vf = efx->vf + vf_i;
  1346. mutex_lock(&vf->status_lock);
  1347. memcpy(vf->addr.mac_addr, mac, ETH_ALEN);
  1348. __efx_sriov_update_vf_addr(vf);
  1349. mutex_unlock(&vf->status_lock);
  1350. return 0;
  1351. }
  1352. int efx_sriov_set_vf_vlan(struct net_device *net_dev, int vf_i,
  1353. u16 vlan, u8 qos)
  1354. {
  1355. struct efx_nic *efx = netdev_priv(net_dev);
  1356. struct efx_vf *vf;
  1357. u16 tci;
  1358. if (vf_i >= efx->vf_init_count)
  1359. return -EINVAL;
  1360. vf = efx->vf + vf_i;
  1361. mutex_lock(&vf->status_lock);
  1362. tci = (vlan & VLAN_VID_MASK) | ((qos & 0x7) << VLAN_PRIO_SHIFT);
  1363. vf->addr.tci = htons(tci);
  1364. __efx_sriov_update_vf_addr(vf);
  1365. mutex_unlock(&vf->status_lock);
  1366. return 0;
  1367. }
  1368. int efx_sriov_set_vf_spoofchk(struct net_device *net_dev, int vf_i,
  1369. bool spoofchk)
  1370. {
  1371. struct efx_nic *efx = netdev_priv(net_dev);
  1372. struct efx_vf *vf;
  1373. int rc;
  1374. if (vf_i >= efx->vf_init_count)
  1375. return -EINVAL;
  1376. vf = efx->vf + vf_i;
  1377. mutex_lock(&vf->txq_lock);
  1378. if (vf->txq_count == 0) {
  1379. vf->tx_filter_mode =
  1380. spoofchk ? VF_TX_FILTER_ON : VF_TX_FILTER_OFF;
  1381. rc = 0;
  1382. } else {
  1383. /* This cannot be changed while TX queues are running */
  1384. rc = -EBUSY;
  1385. }
  1386. mutex_unlock(&vf->txq_lock);
  1387. return rc;
  1388. }
  1389. int efx_sriov_get_vf_config(struct net_device *net_dev, int vf_i,
  1390. struct ifla_vf_info *ivi)
  1391. {
  1392. struct efx_nic *efx = netdev_priv(net_dev);
  1393. struct efx_vf *vf;
  1394. u16 tci;
  1395. if (vf_i >= efx->vf_init_count)
  1396. return -EINVAL;
  1397. vf = efx->vf + vf_i;
  1398. ivi->vf = vf_i;
  1399. memcpy(ivi->mac, vf->addr.mac_addr, ETH_ALEN);
  1400. ivi->tx_rate = 0;
  1401. tci = ntohs(vf->addr.tci);
  1402. ivi->vlan = tci & VLAN_VID_MASK;
  1403. ivi->qos = (tci >> VLAN_PRIO_SHIFT) & 0x7;
  1404. ivi->spoofchk = vf->tx_filter_mode == VF_TX_FILTER_ON;
  1405. return 0;
  1406. }