fw.c 44 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
  4. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. */
  34. #include <linux/etherdevice.h>
  35. #include <linux/mlx4/cmd.h>
  36. #include <linux/module.h>
  37. #include <linux/cache.h>
  38. #include "fw.h"
  39. #include "icm.h"
  40. enum {
  41. MLX4_COMMAND_INTERFACE_MIN_REV = 2,
  42. MLX4_COMMAND_INTERFACE_MAX_REV = 3,
  43. MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
  44. };
  45. extern void __buggy_use_of_MLX4_GET(void);
  46. extern void __buggy_use_of_MLX4_PUT(void);
  47. static bool enable_qos;
  48. module_param(enable_qos, bool, 0444);
  49. MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
  50. #define MLX4_GET(dest, source, offset) \
  51. do { \
  52. void *__p = (char *) (source) + (offset); \
  53. switch (sizeof (dest)) { \
  54. case 1: (dest) = *(u8 *) __p; break; \
  55. case 2: (dest) = be16_to_cpup(__p); break; \
  56. case 4: (dest) = be32_to_cpup(__p); break; \
  57. case 8: (dest) = be64_to_cpup(__p); break; \
  58. default: __buggy_use_of_MLX4_GET(); \
  59. } \
  60. } while (0)
  61. #define MLX4_PUT(dest, source, offset) \
  62. do { \
  63. void *__d = ((char *) (dest) + (offset)); \
  64. switch (sizeof(source)) { \
  65. case 1: *(u8 *) __d = (source); break; \
  66. case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
  67. case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
  68. case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
  69. default: __buggy_use_of_MLX4_PUT(); \
  70. } \
  71. } while (0)
  72. static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
  73. {
  74. static const char *fname[] = {
  75. [ 0] = "RC transport",
  76. [ 1] = "UC transport",
  77. [ 2] = "UD transport",
  78. [ 3] = "XRC transport",
  79. [ 4] = "reliable multicast",
  80. [ 5] = "FCoIB support",
  81. [ 6] = "SRQ support",
  82. [ 7] = "IPoIB checksum offload",
  83. [ 8] = "P_Key violation counter",
  84. [ 9] = "Q_Key violation counter",
  85. [10] = "VMM",
  86. [12] = "DPDP",
  87. [15] = "Big LSO headers",
  88. [16] = "MW support",
  89. [17] = "APM support",
  90. [18] = "Atomic ops support",
  91. [19] = "Raw multicast support",
  92. [20] = "Address vector port checking support",
  93. [21] = "UD multicast support",
  94. [24] = "Demand paging support",
  95. [25] = "Router support",
  96. [30] = "IBoE support",
  97. [32] = "Unicast loopback support",
  98. [34] = "FCS header control",
  99. [38] = "Wake On LAN support",
  100. [40] = "UDP RSS support",
  101. [41] = "Unicast VEP steering support",
  102. [42] = "Multicast VEP steering support",
  103. [48] = "Counters support",
  104. };
  105. int i;
  106. mlx4_dbg(dev, "DEV_CAP flags:\n");
  107. for (i = 0; i < ARRAY_SIZE(fname); ++i)
  108. if (fname[i] && (flags & (1LL << i)))
  109. mlx4_dbg(dev, " %s\n", fname[i]);
  110. }
  111. int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
  112. {
  113. struct mlx4_cmd_mailbox *mailbox;
  114. u32 *inbox;
  115. int err = 0;
  116. #define MOD_STAT_CFG_IN_SIZE 0x100
  117. #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
  118. #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
  119. mailbox = mlx4_alloc_cmd_mailbox(dev);
  120. if (IS_ERR(mailbox))
  121. return PTR_ERR(mailbox);
  122. inbox = mailbox->buf;
  123. memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
  124. MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
  125. MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
  126. err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
  127. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  128. mlx4_free_cmd_mailbox(dev, mailbox);
  129. return err;
  130. }
  131. int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
  132. struct mlx4_vhcr *vhcr,
  133. struct mlx4_cmd_mailbox *inbox,
  134. struct mlx4_cmd_mailbox *outbox,
  135. struct mlx4_cmd_info *cmd)
  136. {
  137. u8 field;
  138. u32 size;
  139. int err = 0;
  140. #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
  141. #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
  142. #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
  143. #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
  144. #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
  145. #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
  146. #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
  147. #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
  148. #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
  149. #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
  150. #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0X30
  151. #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
  152. #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
  153. if (vhcr->op_modifier == 1) {
  154. field = vhcr->in_modifier;
  155. MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
  156. field = 0; /* ensure fvl bit is not set */
  157. MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
  158. } else if (vhcr->op_modifier == 0) {
  159. field = 1 << 7; /* enable only ethernet interface */
  160. MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
  161. field = dev->caps.num_ports;
  162. MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
  163. size = 0; /* no PF behavious is set for now */
  164. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
  165. size = dev->caps.num_qps;
  166. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
  167. size = dev->caps.num_srqs;
  168. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
  169. size = dev->caps.num_cqs;
  170. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
  171. size = dev->caps.num_eqs;
  172. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
  173. size = dev->caps.reserved_eqs;
  174. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
  175. size = dev->caps.num_mpts;
  176. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
  177. size = dev->caps.num_mtts;
  178. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
  179. size = dev->caps.num_mgms + dev->caps.num_amgms;
  180. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
  181. } else
  182. err = -EINVAL;
  183. return err;
  184. }
  185. int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, struct mlx4_func_cap *func_cap)
  186. {
  187. struct mlx4_cmd_mailbox *mailbox;
  188. u32 *outbox;
  189. u8 field;
  190. u32 size;
  191. int i;
  192. int err = 0;
  193. mailbox = mlx4_alloc_cmd_mailbox(dev);
  194. if (IS_ERR(mailbox))
  195. return PTR_ERR(mailbox);
  196. err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FUNC_CAP,
  197. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  198. if (err)
  199. goto out;
  200. outbox = mailbox->buf;
  201. MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
  202. if (!(field & (1 << 7))) {
  203. mlx4_err(dev, "The host doesn't support eth interface\n");
  204. err = -EPROTONOSUPPORT;
  205. goto out;
  206. }
  207. MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
  208. func_cap->num_ports = field;
  209. MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
  210. func_cap->pf_context_behaviour = size;
  211. MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
  212. func_cap->qp_quota = size & 0xFFFFFF;
  213. MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
  214. func_cap->srq_quota = size & 0xFFFFFF;
  215. MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
  216. func_cap->cq_quota = size & 0xFFFFFF;
  217. MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
  218. func_cap->max_eq = size & 0xFFFFFF;
  219. MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
  220. func_cap->reserved_eq = size & 0xFFFFFF;
  221. MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
  222. func_cap->mpt_quota = size & 0xFFFFFF;
  223. MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
  224. func_cap->mtt_quota = size & 0xFFFFFF;
  225. MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
  226. func_cap->mcg_quota = size & 0xFFFFFF;
  227. for (i = 1; i <= func_cap->num_ports; ++i) {
  228. err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 1,
  229. MLX4_CMD_QUERY_FUNC_CAP,
  230. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  231. if (err)
  232. goto out;
  233. MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
  234. if (field & (1 << 7)) {
  235. mlx4_err(dev, "VLAN is enforced on this port\n");
  236. err = -EPROTONOSUPPORT;
  237. goto out;
  238. }
  239. if (field & (1 << 6)) {
  240. mlx4_err(dev, "Force mac is enabled on this port\n");
  241. err = -EPROTONOSUPPORT;
  242. goto out;
  243. }
  244. MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
  245. func_cap->physical_port[i] = field;
  246. }
  247. /* All other resources are allocated by the master, but we still report
  248. * 'num' and 'reserved' capabilities as follows:
  249. * - num remains the maximum resource index
  250. * - 'num - reserved' is the total available objects of a resource, but
  251. * resource indices may be less than 'reserved'
  252. * TODO: set per-resource quotas */
  253. out:
  254. mlx4_free_cmd_mailbox(dev, mailbox);
  255. return err;
  256. }
  257. int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
  258. {
  259. struct mlx4_cmd_mailbox *mailbox;
  260. u32 *outbox;
  261. u8 field;
  262. u32 field32, flags, ext_flags;
  263. u16 size;
  264. u16 stat_rate;
  265. int err;
  266. int i;
  267. #define QUERY_DEV_CAP_OUT_SIZE 0x100
  268. #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
  269. #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
  270. #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
  271. #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
  272. #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
  273. #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
  274. #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
  275. #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
  276. #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
  277. #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
  278. #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
  279. #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
  280. #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
  281. #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
  282. #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
  283. #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
  284. #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
  285. #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
  286. #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
  287. #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
  288. #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
  289. #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
  290. #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
  291. #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
  292. #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
  293. #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
  294. #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
  295. #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
  296. #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
  297. #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
  298. #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
  299. #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
  300. #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
  301. #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
  302. #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
  303. #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
  304. #define QUERY_DEV_CAP_BF_OFFSET 0x4c
  305. #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
  306. #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
  307. #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
  308. #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
  309. #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
  310. #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
  311. #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
  312. #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
  313. #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
  314. #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
  315. #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
  316. #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
  317. #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
  318. #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
  319. #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
  320. #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
  321. #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
  322. #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
  323. #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
  324. #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
  325. #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
  326. #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
  327. #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
  328. #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
  329. #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
  330. #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
  331. #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
  332. #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
  333. mailbox = mlx4_alloc_cmd_mailbox(dev);
  334. if (IS_ERR(mailbox))
  335. return PTR_ERR(mailbox);
  336. outbox = mailbox->buf;
  337. err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
  338. MLX4_CMD_TIME_CLASS_A, !mlx4_is_slave(dev));
  339. if (err)
  340. goto out;
  341. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
  342. dev_cap->reserved_qps = 1 << (field & 0xf);
  343. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
  344. dev_cap->max_qps = 1 << (field & 0x1f);
  345. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
  346. dev_cap->reserved_srqs = 1 << (field >> 4);
  347. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
  348. dev_cap->max_srqs = 1 << (field & 0x1f);
  349. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
  350. dev_cap->max_cq_sz = 1 << field;
  351. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
  352. dev_cap->reserved_cqs = 1 << (field & 0xf);
  353. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
  354. dev_cap->max_cqs = 1 << (field & 0x1f);
  355. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
  356. dev_cap->max_mpts = 1 << (field & 0x3f);
  357. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
  358. dev_cap->reserved_eqs = field & 0xf;
  359. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
  360. dev_cap->max_eqs = 1 << (field & 0xf);
  361. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
  362. dev_cap->reserved_mtts = 1 << (field >> 4);
  363. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
  364. dev_cap->max_mrw_sz = 1 << field;
  365. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
  366. dev_cap->reserved_mrws = 1 << (field & 0xf);
  367. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
  368. dev_cap->max_mtt_seg = 1 << (field & 0x3f);
  369. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
  370. dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
  371. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
  372. dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
  373. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
  374. field &= 0x1f;
  375. if (!field)
  376. dev_cap->max_gso_sz = 0;
  377. else
  378. dev_cap->max_gso_sz = 1 << field;
  379. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
  380. dev_cap->max_rdma_global = 1 << (field & 0x3f);
  381. MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
  382. dev_cap->local_ca_ack_delay = field & 0x1f;
  383. MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
  384. dev_cap->num_ports = field & 0xf;
  385. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
  386. dev_cap->max_msg_sz = 1 << (field & 0x1f);
  387. MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
  388. dev_cap->stat_rate_support = stat_rate;
  389. MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
  390. MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
  391. dev_cap->flags = flags | (u64)ext_flags << 32;
  392. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
  393. dev_cap->reserved_uars = field >> 4;
  394. MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
  395. dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
  396. MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
  397. dev_cap->min_page_sz = 1 << field;
  398. MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
  399. if (field & 0x80) {
  400. MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
  401. dev_cap->bf_reg_size = 1 << (field & 0x1f);
  402. MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
  403. if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
  404. field = 3;
  405. dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
  406. mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
  407. dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
  408. } else {
  409. dev_cap->bf_reg_size = 0;
  410. mlx4_dbg(dev, "BlueFlame not available\n");
  411. }
  412. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
  413. dev_cap->max_sq_sg = field;
  414. MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
  415. dev_cap->max_sq_desc_sz = size;
  416. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
  417. dev_cap->max_qp_per_mcg = 1 << field;
  418. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
  419. dev_cap->reserved_mgms = field & 0xf;
  420. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
  421. dev_cap->max_mcgs = 1 << field;
  422. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
  423. dev_cap->reserved_pds = field >> 4;
  424. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
  425. dev_cap->max_pds = 1 << (field & 0x3f);
  426. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
  427. dev_cap->reserved_xrcds = field >> 4;
  428. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
  429. dev_cap->max_xrcds = 1 << (field & 0x1f);
  430. MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
  431. dev_cap->rdmarc_entry_sz = size;
  432. MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
  433. dev_cap->qpc_entry_sz = size;
  434. MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
  435. dev_cap->aux_entry_sz = size;
  436. MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
  437. dev_cap->altc_entry_sz = size;
  438. MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
  439. dev_cap->eqc_entry_sz = size;
  440. MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
  441. dev_cap->cqc_entry_sz = size;
  442. MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
  443. dev_cap->srq_entry_sz = size;
  444. MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
  445. dev_cap->cmpt_entry_sz = size;
  446. MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
  447. dev_cap->mtt_entry_sz = size;
  448. MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
  449. dev_cap->dmpt_entry_sz = size;
  450. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
  451. dev_cap->max_srq_sz = 1 << field;
  452. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
  453. dev_cap->max_qp_sz = 1 << field;
  454. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
  455. dev_cap->resize_srq = field & 1;
  456. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
  457. dev_cap->max_rq_sg = field;
  458. MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
  459. dev_cap->max_rq_desc_sz = size;
  460. MLX4_GET(dev_cap->bmme_flags, outbox,
  461. QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
  462. MLX4_GET(dev_cap->reserved_lkey, outbox,
  463. QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
  464. MLX4_GET(dev_cap->max_icm_sz, outbox,
  465. QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
  466. if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
  467. MLX4_GET(dev_cap->max_counters, outbox,
  468. QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
  469. if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
  470. for (i = 1; i <= dev_cap->num_ports; ++i) {
  471. MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
  472. dev_cap->max_vl[i] = field >> 4;
  473. MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
  474. dev_cap->ib_mtu[i] = field >> 4;
  475. dev_cap->max_port_width[i] = field & 0xf;
  476. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
  477. dev_cap->max_gids[i] = 1 << (field & 0xf);
  478. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
  479. dev_cap->max_pkeys[i] = 1 << (field & 0xf);
  480. }
  481. } else {
  482. #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
  483. #define QUERY_PORT_MTU_OFFSET 0x01
  484. #define QUERY_PORT_ETH_MTU_OFFSET 0x02
  485. #define QUERY_PORT_WIDTH_OFFSET 0x06
  486. #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
  487. #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
  488. #define QUERY_PORT_MAX_VL_OFFSET 0x0b
  489. #define QUERY_PORT_MAC_OFFSET 0x10
  490. #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
  491. #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
  492. #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
  493. for (i = 1; i <= dev_cap->num_ports; ++i) {
  494. err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
  495. MLX4_CMD_TIME_CLASS_B,
  496. !mlx4_is_slave(dev));
  497. if (err)
  498. goto out;
  499. MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
  500. dev_cap->supported_port_types[i] = field & 3;
  501. dev_cap->suggested_type[i] = (field >> 3) & 1;
  502. dev_cap->default_sense[i] = (field >> 4) & 1;
  503. MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
  504. dev_cap->ib_mtu[i] = field & 0xf;
  505. MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
  506. dev_cap->max_port_width[i] = field & 0xf;
  507. MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
  508. dev_cap->max_gids[i] = 1 << (field >> 4);
  509. dev_cap->max_pkeys[i] = 1 << (field & 0xf);
  510. MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
  511. dev_cap->max_vl[i] = field & 0xf;
  512. MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
  513. dev_cap->log_max_macs[i] = field & 0xf;
  514. dev_cap->log_max_vlans[i] = field >> 4;
  515. MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
  516. MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
  517. MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
  518. dev_cap->trans_type[i] = field32 >> 24;
  519. dev_cap->vendor_oui[i] = field32 & 0xffffff;
  520. MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
  521. MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
  522. }
  523. }
  524. mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
  525. dev_cap->bmme_flags, dev_cap->reserved_lkey);
  526. /*
  527. * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
  528. * we can't use any EQs whose doorbell falls on that page,
  529. * even if the EQ itself isn't reserved.
  530. */
  531. dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
  532. dev_cap->reserved_eqs);
  533. mlx4_dbg(dev, "Max ICM size %lld MB\n",
  534. (unsigned long long) dev_cap->max_icm_sz >> 20);
  535. mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
  536. dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
  537. mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
  538. dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
  539. mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
  540. dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
  541. mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
  542. dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
  543. mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
  544. dev_cap->reserved_mrws, dev_cap->reserved_mtts);
  545. mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
  546. dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
  547. mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
  548. dev_cap->max_pds, dev_cap->reserved_mgms);
  549. mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
  550. dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
  551. mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
  552. dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
  553. dev_cap->max_port_width[1]);
  554. mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
  555. dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
  556. mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
  557. dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
  558. mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
  559. mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
  560. dump_dev_cap_flags(dev, dev_cap->flags);
  561. out:
  562. mlx4_free_cmd_mailbox(dev, mailbox);
  563. return err;
  564. }
  565. int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
  566. struct mlx4_vhcr *vhcr,
  567. struct mlx4_cmd_mailbox *inbox,
  568. struct mlx4_cmd_mailbox *outbox,
  569. struct mlx4_cmd_info *cmd)
  570. {
  571. u64 def_mac;
  572. u8 port_type;
  573. int err;
  574. #define MLX4_PORT_SUPPORT_IB (1 << 0)
  575. #define MLX4_PORT_SUGGEST_TYPE (1 << 3)
  576. #define MLX4_PORT_DEFAULT_SENSE (1 << 4)
  577. #define MLX4_VF_PORT_ETH_ONLY_MASK (0xff & ~MLX4_PORT_SUPPORT_IB & \
  578. ~MLX4_PORT_SUGGEST_TYPE & \
  579. ~MLX4_PORT_DEFAULT_SENSE)
  580. err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
  581. MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
  582. MLX4_CMD_NATIVE);
  583. if (!err && dev->caps.function != slave) {
  584. /* set slave default_mac address */
  585. MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
  586. def_mac += slave << 8;
  587. MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
  588. /* get port type - currently only eth is enabled */
  589. MLX4_GET(port_type, outbox->buf,
  590. QUERY_PORT_SUPPORTED_TYPE_OFFSET);
  591. /* Allow only Eth port, no link sensing allowed */
  592. port_type &= MLX4_VF_PORT_ETH_ONLY_MASK;
  593. /* check eth is enabled for this port */
  594. if (!(port_type & 2))
  595. mlx4_dbg(dev, "QUERY PORT: eth not supported by host");
  596. MLX4_PUT(outbox->buf, port_type,
  597. QUERY_PORT_SUPPORTED_TYPE_OFFSET);
  598. }
  599. return err;
  600. }
  601. int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
  602. {
  603. struct mlx4_cmd_mailbox *mailbox;
  604. struct mlx4_icm_iter iter;
  605. __be64 *pages;
  606. int lg;
  607. int nent = 0;
  608. int i;
  609. int err = 0;
  610. int ts = 0, tc = 0;
  611. mailbox = mlx4_alloc_cmd_mailbox(dev);
  612. if (IS_ERR(mailbox))
  613. return PTR_ERR(mailbox);
  614. memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
  615. pages = mailbox->buf;
  616. for (mlx4_icm_first(icm, &iter);
  617. !mlx4_icm_last(&iter);
  618. mlx4_icm_next(&iter)) {
  619. /*
  620. * We have to pass pages that are aligned to their
  621. * size, so find the least significant 1 in the
  622. * address or size and use that as our log2 size.
  623. */
  624. lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
  625. if (lg < MLX4_ICM_PAGE_SHIFT) {
  626. mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
  627. MLX4_ICM_PAGE_SIZE,
  628. (unsigned long long) mlx4_icm_addr(&iter),
  629. mlx4_icm_size(&iter));
  630. err = -EINVAL;
  631. goto out;
  632. }
  633. for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
  634. if (virt != -1) {
  635. pages[nent * 2] = cpu_to_be64(virt);
  636. virt += 1 << lg;
  637. }
  638. pages[nent * 2 + 1] =
  639. cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
  640. (lg - MLX4_ICM_PAGE_SHIFT));
  641. ts += 1 << (lg - 10);
  642. ++tc;
  643. if (++nent == MLX4_MAILBOX_SIZE / 16) {
  644. err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
  645. MLX4_CMD_TIME_CLASS_B,
  646. MLX4_CMD_NATIVE);
  647. if (err)
  648. goto out;
  649. nent = 0;
  650. }
  651. }
  652. }
  653. if (nent)
  654. err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
  655. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
  656. if (err)
  657. goto out;
  658. switch (op) {
  659. case MLX4_CMD_MAP_FA:
  660. mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
  661. break;
  662. case MLX4_CMD_MAP_ICM_AUX:
  663. mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
  664. break;
  665. case MLX4_CMD_MAP_ICM:
  666. mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
  667. tc, ts, (unsigned long long) virt - (ts << 10));
  668. break;
  669. }
  670. out:
  671. mlx4_free_cmd_mailbox(dev, mailbox);
  672. return err;
  673. }
  674. int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
  675. {
  676. return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
  677. }
  678. int mlx4_UNMAP_FA(struct mlx4_dev *dev)
  679. {
  680. return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
  681. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
  682. }
  683. int mlx4_RUN_FW(struct mlx4_dev *dev)
  684. {
  685. return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
  686. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  687. }
  688. int mlx4_QUERY_FW(struct mlx4_dev *dev)
  689. {
  690. struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
  691. struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
  692. struct mlx4_cmd_mailbox *mailbox;
  693. u32 *outbox;
  694. int err = 0;
  695. u64 fw_ver;
  696. u16 cmd_if_rev;
  697. u8 lg;
  698. #define QUERY_FW_OUT_SIZE 0x100
  699. #define QUERY_FW_VER_OFFSET 0x00
  700. #define QUERY_FW_PPF_ID 0x09
  701. #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
  702. #define QUERY_FW_MAX_CMD_OFFSET 0x0f
  703. #define QUERY_FW_ERR_START_OFFSET 0x30
  704. #define QUERY_FW_ERR_SIZE_OFFSET 0x38
  705. #define QUERY_FW_ERR_BAR_OFFSET 0x3c
  706. #define QUERY_FW_SIZE_OFFSET 0x00
  707. #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
  708. #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
  709. #define QUERY_FW_COMM_BASE_OFFSET 0x40
  710. #define QUERY_FW_COMM_BAR_OFFSET 0x48
  711. mailbox = mlx4_alloc_cmd_mailbox(dev);
  712. if (IS_ERR(mailbox))
  713. return PTR_ERR(mailbox);
  714. outbox = mailbox->buf;
  715. err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
  716. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  717. if (err)
  718. goto out;
  719. MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
  720. /*
  721. * FW subminor version is at more significant bits than minor
  722. * version, so swap here.
  723. */
  724. dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
  725. ((fw_ver & 0xffff0000ull) >> 16) |
  726. ((fw_ver & 0x0000ffffull) << 16);
  727. MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
  728. dev->caps.function = lg;
  729. MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
  730. if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
  731. cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
  732. mlx4_err(dev, "Installed FW has unsupported "
  733. "command interface revision %d.\n",
  734. cmd_if_rev);
  735. mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
  736. (int) (dev->caps.fw_ver >> 32),
  737. (int) (dev->caps.fw_ver >> 16) & 0xffff,
  738. (int) dev->caps.fw_ver & 0xffff);
  739. mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
  740. MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
  741. err = -ENODEV;
  742. goto out;
  743. }
  744. if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
  745. dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
  746. MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
  747. cmd->max_cmds = 1 << lg;
  748. mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
  749. (int) (dev->caps.fw_ver >> 32),
  750. (int) (dev->caps.fw_ver >> 16) & 0xffff,
  751. (int) dev->caps.fw_ver & 0xffff,
  752. cmd_if_rev, cmd->max_cmds);
  753. MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
  754. MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
  755. MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
  756. fw->catas_bar = (fw->catas_bar >> 6) * 2;
  757. mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
  758. (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
  759. MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
  760. MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
  761. MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
  762. fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
  763. MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
  764. MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
  765. fw->comm_bar = (fw->comm_bar >> 6) * 2;
  766. mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
  767. fw->comm_bar, fw->comm_base);
  768. mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
  769. /*
  770. * Round up number of system pages needed in case
  771. * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
  772. */
  773. fw->fw_pages =
  774. ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
  775. (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
  776. mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
  777. (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
  778. out:
  779. mlx4_free_cmd_mailbox(dev, mailbox);
  780. return err;
  781. }
  782. static void get_board_id(void *vsd, char *board_id)
  783. {
  784. int i;
  785. #define VSD_OFFSET_SIG1 0x00
  786. #define VSD_OFFSET_SIG2 0xde
  787. #define VSD_OFFSET_MLX_BOARD_ID 0xd0
  788. #define VSD_OFFSET_TS_BOARD_ID 0x20
  789. #define VSD_SIGNATURE_TOPSPIN 0x5ad
  790. memset(board_id, 0, MLX4_BOARD_ID_LEN);
  791. if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
  792. be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
  793. strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
  794. } else {
  795. /*
  796. * The board ID is a string but the firmware byte
  797. * swaps each 4-byte word before passing it back to
  798. * us. Therefore we need to swab it before printing.
  799. */
  800. for (i = 0; i < 4; ++i)
  801. ((u32 *) board_id)[i] =
  802. swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
  803. }
  804. }
  805. int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
  806. {
  807. struct mlx4_cmd_mailbox *mailbox;
  808. u32 *outbox;
  809. int err;
  810. #define QUERY_ADAPTER_OUT_SIZE 0x100
  811. #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
  812. #define QUERY_ADAPTER_VSD_OFFSET 0x20
  813. mailbox = mlx4_alloc_cmd_mailbox(dev);
  814. if (IS_ERR(mailbox))
  815. return PTR_ERR(mailbox);
  816. outbox = mailbox->buf;
  817. err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
  818. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  819. if (err)
  820. goto out;
  821. MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
  822. get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
  823. adapter->board_id);
  824. out:
  825. mlx4_free_cmd_mailbox(dev, mailbox);
  826. return err;
  827. }
  828. int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
  829. {
  830. struct mlx4_cmd_mailbox *mailbox;
  831. __be32 *inbox;
  832. int err;
  833. #define INIT_HCA_IN_SIZE 0x200
  834. #define INIT_HCA_VERSION_OFFSET 0x000
  835. #define INIT_HCA_VERSION 2
  836. #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
  837. #define INIT_HCA_FLAGS_OFFSET 0x014
  838. #define INIT_HCA_QPC_OFFSET 0x020
  839. #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
  840. #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
  841. #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
  842. #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
  843. #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
  844. #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
  845. #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
  846. #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
  847. #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
  848. #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
  849. #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
  850. #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
  851. #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
  852. #define INIT_HCA_MCAST_OFFSET 0x0c0
  853. #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
  854. #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
  855. #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
  856. #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
  857. #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
  858. #define INIT_HCA_TPT_OFFSET 0x0f0
  859. #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
  860. #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
  861. #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
  862. #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
  863. #define INIT_HCA_UAR_OFFSET 0x120
  864. #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
  865. #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
  866. mailbox = mlx4_alloc_cmd_mailbox(dev);
  867. if (IS_ERR(mailbox))
  868. return PTR_ERR(mailbox);
  869. inbox = mailbox->buf;
  870. memset(inbox, 0, INIT_HCA_IN_SIZE);
  871. *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
  872. *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
  873. (ilog2(cache_line_size()) - 4) << 5;
  874. #if defined(__LITTLE_ENDIAN)
  875. *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
  876. #elif defined(__BIG_ENDIAN)
  877. *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
  878. #else
  879. #error Host endianness not defined
  880. #endif
  881. /* Check port for UD address vector: */
  882. *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
  883. /* Enable IPoIB checksumming if we can: */
  884. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
  885. *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
  886. /* Enable QoS support if module parameter set */
  887. if (enable_qos)
  888. *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
  889. /* enable counters */
  890. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
  891. *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
  892. /* QPC/EEC/CQC/EQC/RDMARC attributes */
  893. MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
  894. MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
  895. MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
  896. MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
  897. MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
  898. MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
  899. MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
  900. MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
  901. MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
  902. MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
  903. MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
  904. MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
  905. /* multicast attributes */
  906. MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
  907. MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
  908. MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
  909. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
  910. MLX4_PUT(inbox, (u8) (1 << 3), INIT_HCA_UC_STEERING_OFFSET);
  911. MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
  912. /* TPT attributes */
  913. MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
  914. MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
  915. MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
  916. MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
  917. /* UAR attributes */
  918. MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
  919. MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
  920. err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
  921. MLX4_CMD_NATIVE);
  922. if (err)
  923. mlx4_err(dev, "INIT_HCA returns %d\n", err);
  924. mlx4_free_cmd_mailbox(dev, mailbox);
  925. return err;
  926. }
  927. int mlx4_QUERY_HCA(struct mlx4_dev *dev,
  928. struct mlx4_init_hca_param *param)
  929. {
  930. struct mlx4_cmd_mailbox *mailbox;
  931. __be32 *outbox;
  932. int err;
  933. #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
  934. mailbox = mlx4_alloc_cmd_mailbox(dev);
  935. if (IS_ERR(mailbox))
  936. return PTR_ERR(mailbox);
  937. outbox = mailbox->buf;
  938. err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
  939. MLX4_CMD_QUERY_HCA,
  940. MLX4_CMD_TIME_CLASS_B,
  941. !mlx4_is_slave(dev));
  942. if (err)
  943. goto out;
  944. MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
  945. /* QPC/EEC/CQC/EQC/RDMARC attributes */
  946. MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
  947. MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
  948. MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
  949. MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
  950. MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
  951. MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
  952. MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
  953. MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
  954. MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
  955. MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
  956. MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
  957. MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
  958. /* multicast attributes */
  959. MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
  960. MLX4_GET(param->log_mc_entry_sz, outbox,
  961. INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
  962. MLX4_GET(param->log_mc_hash_sz, outbox,
  963. INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
  964. MLX4_GET(param->log_mc_table_sz, outbox,
  965. INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
  966. /* TPT attributes */
  967. MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
  968. MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
  969. MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
  970. MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
  971. /* UAR attributes */
  972. MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
  973. MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
  974. out:
  975. mlx4_free_cmd_mailbox(dev, mailbox);
  976. return err;
  977. }
  978. int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
  979. struct mlx4_vhcr *vhcr,
  980. struct mlx4_cmd_mailbox *inbox,
  981. struct mlx4_cmd_mailbox *outbox,
  982. struct mlx4_cmd_info *cmd)
  983. {
  984. struct mlx4_priv *priv = mlx4_priv(dev);
  985. int port = vhcr->in_modifier;
  986. int err;
  987. if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
  988. return 0;
  989. if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
  990. return -ENODEV;
  991. /* Enable port only if it was previously disabled */
  992. if (!priv->mfunc.master.init_port_ref[port]) {
  993. err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
  994. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  995. if (err)
  996. return err;
  997. priv->mfunc.master.slave_state[slave].init_port_mask |=
  998. (1 << port);
  999. }
  1000. ++priv->mfunc.master.init_port_ref[port];
  1001. return 0;
  1002. }
  1003. int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
  1004. {
  1005. struct mlx4_cmd_mailbox *mailbox;
  1006. u32 *inbox;
  1007. int err;
  1008. u32 flags;
  1009. u16 field;
  1010. if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
  1011. #define INIT_PORT_IN_SIZE 256
  1012. #define INIT_PORT_FLAGS_OFFSET 0x00
  1013. #define INIT_PORT_FLAG_SIG (1 << 18)
  1014. #define INIT_PORT_FLAG_NG (1 << 17)
  1015. #define INIT_PORT_FLAG_G0 (1 << 16)
  1016. #define INIT_PORT_VL_SHIFT 4
  1017. #define INIT_PORT_PORT_WIDTH_SHIFT 8
  1018. #define INIT_PORT_MTU_OFFSET 0x04
  1019. #define INIT_PORT_MAX_GID_OFFSET 0x06
  1020. #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
  1021. #define INIT_PORT_GUID0_OFFSET 0x10
  1022. #define INIT_PORT_NODE_GUID_OFFSET 0x18
  1023. #define INIT_PORT_SI_GUID_OFFSET 0x20
  1024. mailbox = mlx4_alloc_cmd_mailbox(dev);
  1025. if (IS_ERR(mailbox))
  1026. return PTR_ERR(mailbox);
  1027. inbox = mailbox->buf;
  1028. memset(inbox, 0, INIT_PORT_IN_SIZE);
  1029. flags = 0;
  1030. flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
  1031. flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
  1032. MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
  1033. field = 128 << dev->caps.ib_mtu_cap[port];
  1034. MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
  1035. field = dev->caps.gid_table_len[port];
  1036. MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
  1037. field = dev->caps.pkey_table_len[port];
  1038. MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
  1039. err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
  1040. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  1041. mlx4_free_cmd_mailbox(dev, mailbox);
  1042. } else
  1043. err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
  1044. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  1045. return err;
  1046. }
  1047. EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
  1048. int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
  1049. struct mlx4_vhcr *vhcr,
  1050. struct mlx4_cmd_mailbox *inbox,
  1051. struct mlx4_cmd_mailbox *outbox,
  1052. struct mlx4_cmd_info *cmd)
  1053. {
  1054. struct mlx4_priv *priv = mlx4_priv(dev);
  1055. int port = vhcr->in_modifier;
  1056. int err;
  1057. if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
  1058. (1 << port)))
  1059. return 0;
  1060. if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
  1061. return -ENODEV;
  1062. if (priv->mfunc.master.init_port_ref[port] == 1) {
  1063. err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
  1064. MLX4_CMD_NATIVE);
  1065. if (err)
  1066. return err;
  1067. }
  1068. priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
  1069. --priv->mfunc.master.init_port_ref[port];
  1070. return 0;
  1071. }
  1072. int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
  1073. {
  1074. return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
  1075. MLX4_CMD_WRAPPED);
  1076. }
  1077. EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
  1078. int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
  1079. {
  1080. return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
  1081. MLX4_CMD_NATIVE);
  1082. }
  1083. int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
  1084. {
  1085. int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
  1086. MLX4_CMD_SET_ICM_SIZE,
  1087. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  1088. if (ret)
  1089. return ret;
  1090. /*
  1091. * Round up number of system pages needed in case
  1092. * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
  1093. */
  1094. *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
  1095. (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
  1096. return 0;
  1097. }
  1098. int mlx4_NOP(struct mlx4_dev *dev)
  1099. {
  1100. /* Input modifier of 0x1f means "finish as soon as possible." */
  1101. return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
  1102. }
  1103. #define MLX4_WOL_SETUP_MODE (5 << 28)
  1104. int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
  1105. {
  1106. u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
  1107. return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
  1108. MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
  1109. MLX4_CMD_NATIVE);
  1110. }
  1111. EXPORT_SYMBOL_GPL(mlx4_wol_read);
  1112. int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
  1113. {
  1114. u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
  1115. return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
  1116. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  1117. }
  1118. EXPORT_SYMBOL_GPL(mlx4_wol_write);