dma.c 5.4 KB

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  1. /*
  2. * DMA implementation for Hexagon
  3. *
  4. * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 and
  8. * only version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  18. * 02110-1301, USA.
  19. */
  20. #include <linux/dma-mapping.h>
  21. #include <linux/bootmem.h>
  22. #include <linux/genalloc.h>
  23. #include <asm/dma-mapping.h>
  24. struct dma_map_ops *dma_ops;
  25. EXPORT_SYMBOL(dma_ops);
  26. int bad_dma_address; /* globals are automatically initialized to zero */
  27. int dma_supported(struct device *dev, u64 mask)
  28. {
  29. if (mask == DMA_BIT_MASK(32))
  30. return 1;
  31. else
  32. return 0;
  33. }
  34. EXPORT_SYMBOL(dma_supported);
  35. int dma_set_mask(struct device *dev, u64 mask)
  36. {
  37. if (!dev->dma_mask || !dma_supported(dev, mask))
  38. return -EIO;
  39. *dev->dma_mask = mask;
  40. return 0;
  41. }
  42. EXPORT_SYMBOL(dma_set_mask);
  43. static struct gen_pool *coherent_pool;
  44. /* Allocates from a pool of uncached memory that was reserved at boot time */
  45. void *hexagon_dma_alloc_coherent(struct device *dev, size_t size,
  46. dma_addr_t *dma_addr, gfp_t flag)
  47. {
  48. void *ret;
  49. if (coherent_pool == NULL) {
  50. coherent_pool = gen_pool_create(PAGE_SHIFT, -1);
  51. if (coherent_pool == NULL)
  52. panic("Can't create %s() memory pool!", __func__);
  53. else
  54. gen_pool_add(coherent_pool,
  55. (PAGE_OFFSET + (max_low_pfn << PAGE_SHIFT)),
  56. hexagon_coherent_pool_size, -1);
  57. }
  58. ret = (void *) gen_pool_alloc(coherent_pool, size);
  59. if (ret) {
  60. memset(ret, 0, size);
  61. *dma_addr = (dma_addr_t) (ret - PAGE_OFFSET);
  62. } else
  63. *dma_addr = ~0;
  64. return ret;
  65. }
  66. static void hexagon_free_coherent(struct device *dev, size_t size, void *vaddr,
  67. dma_addr_t dma_addr)
  68. {
  69. gen_pool_free(coherent_pool, (unsigned long) vaddr, size);
  70. }
  71. static int check_addr(const char *name, struct device *hwdev,
  72. dma_addr_t bus, size_t size)
  73. {
  74. if (hwdev && hwdev->dma_mask && !dma_capable(hwdev, bus, size)) {
  75. if (*hwdev->dma_mask >= DMA_BIT_MASK(32))
  76. printk(KERN_ERR
  77. "%s: overflow %Lx+%zu of device mask %Lx\n",
  78. name, (long long)bus, size,
  79. (long long)*hwdev->dma_mask);
  80. return 0;
  81. }
  82. return 1;
  83. }
  84. static int hexagon_map_sg(struct device *hwdev, struct scatterlist *sg,
  85. int nents, enum dma_data_direction dir,
  86. struct dma_attrs *attrs)
  87. {
  88. struct scatterlist *s;
  89. int i;
  90. WARN_ON(nents == 0 || sg[0].length == 0);
  91. for_each_sg(sg, s, nents, i) {
  92. s->dma_address = sg_phys(s);
  93. if (!check_addr("map_sg", hwdev, s->dma_address, s->length))
  94. return 0;
  95. s->dma_length = s->length;
  96. flush_dcache_range(PAGE_OFFSET + s->dma_address,
  97. PAGE_OFFSET + s->dma_address + s->length);
  98. }
  99. return nents;
  100. }
  101. /*
  102. * address is virtual
  103. */
  104. static inline void dma_sync(void *addr, size_t size,
  105. enum dma_data_direction dir)
  106. {
  107. switch (dir) {
  108. case DMA_TO_DEVICE:
  109. hexagon_clean_dcache_range((unsigned long) addr,
  110. (unsigned long) addr + size);
  111. break;
  112. case DMA_FROM_DEVICE:
  113. hexagon_inv_dcache_range((unsigned long) addr,
  114. (unsigned long) addr + size);
  115. break;
  116. case DMA_BIDIRECTIONAL:
  117. flush_dcache_range((unsigned long) addr,
  118. (unsigned long) addr + size);
  119. break;
  120. default:
  121. BUG();
  122. }
  123. }
  124. static inline void *dma_addr_to_virt(dma_addr_t dma_addr)
  125. {
  126. return phys_to_virt((unsigned long) dma_addr);
  127. }
  128. /**
  129. * hexagon_map_page() - maps an address for device DMA
  130. * @dev: pointer to DMA device
  131. * @page: pointer to page struct of DMA memory
  132. * @offset: offset within page
  133. * @size: size of memory to map
  134. * @dir: transfer direction
  135. * @attrs: pointer to DMA attrs (not used)
  136. *
  137. * Called to map a memory address to a DMA address prior
  138. * to accesses to/from device.
  139. *
  140. * We don't particularly have many hoops to jump through
  141. * so far. Straight translation between phys and virtual.
  142. *
  143. * DMA is not cache coherent so sync is necessary; this
  144. * seems to be a convenient place to do it.
  145. *
  146. */
  147. static dma_addr_t hexagon_map_page(struct device *dev, struct page *page,
  148. unsigned long offset, size_t size,
  149. enum dma_data_direction dir,
  150. struct dma_attrs *attrs)
  151. {
  152. dma_addr_t bus = page_to_phys(page) + offset;
  153. WARN_ON(size == 0);
  154. if (!check_addr("map_single", dev, bus, size))
  155. return bad_dma_address;
  156. dma_sync(dma_addr_to_virt(bus), size, dir);
  157. return bus;
  158. }
  159. static void hexagon_sync_single_for_cpu(struct device *dev,
  160. dma_addr_t dma_handle, size_t size,
  161. enum dma_data_direction dir)
  162. {
  163. dma_sync(dma_addr_to_virt(dma_handle), size, dir);
  164. }
  165. static void hexagon_sync_single_for_device(struct device *dev,
  166. dma_addr_t dma_handle, size_t size,
  167. enum dma_data_direction dir)
  168. {
  169. dma_sync(dma_addr_to_virt(dma_handle), size, dir);
  170. }
  171. struct dma_map_ops hexagon_dma_ops = {
  172. .alloc_coherent = hexagon_dma_alloc_coherent,
  173. .free_coherent = hexagon_free_coherent,
  174. .map_sg = hexagon_map_sg,
  175. .map_page = hexagon_map_page,
  176. .sync_single_for_cpu = hexagon_sync_single_for_cpu,
  177. .sync_single_for_device = hexagon_sync_single_for_device,
  178. .is_phys = 1,
  179. };
  180. void __init hexagon_dma_init(void)
  181. {
  182. if (dma_ops)
  183. return;
  184. dma_ops = &hexagon_dma_ops;
  185. }