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irqs-db8500.h

irqs-db8500.h 6.5 KB
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  1. /*
    2. 

  2.  * Copyright (C) ST-Ericsson SA 2010
    3. 

  3.  *
    4. 

  4.  * Author: Rabin Vincent <rabin.vincent@stericsson.com>
    5. 

  5.  * License terms: GNU General Public License (GPL) version 2
    6. 

  6.  */
    7. 

  7. 

  8. #ifndef __MACH_IRQS_DB8500_H
    9. 

  9. #define __MACH_IRQS_DB8500_H
    10. 

  10. 

  11. #define IRQ_DB8500_MTU0			(IRQ_SHPI_START + 4)
    12. 

  12. #define IRQ_DB8500_SPI2			(IRQ_SHPI_START + 6)
    13. 

  13. #define IRQ_DB8500_PMU			(IRQ_SHPI_START + 7)
    14. 

  14. #define IRQ_DB8500_SPI0			(IRQ_SHPI_START + 8)
    15. 

  15. #define IRQ_DB8500_RTT			(IRQ_SHPI_START + 9)
    16. 

  16. #define IRQ_DB8500_PKA			(IRQ_SHPI_START + 10)
    17. 

  17. #define IRQ_DB8500_UART0		(IRQ_SHPI_START + 11)
    18. 

  18. #define IRQ_DB8500_I2C3			(IRQ_SHPI_START + 12)
    19. 

  19. #define IRQ_DB8500_L2CC			(IRQ_SHPI_START + 13)
    20. 

  20. #define IRQ_DB8500_SSP0			(IRQ_SHPI_START + 14)
    21. 

  21. #define IRQ_DB8500_CRYP1		(IRQ_SHPI_START + 15)
    22. 

  22. #define IRQ_DB8500_MSP1_RX		(IRQ_SHPI_START + 16)
    23. 

  23. #define IRQ_DB8500_MTU1			(IRQ_SHPI_START + 17)
    24. 

  24. #define IRQ_DB8500_RTC			(IRQ_SHPI_START + 18)
    25. 

  25. #define IRQ_DB8500_UART1		(IRQ_SHPI_START + 19)
    26. 

  26. #define IRQ_DB8500_USB_WAKEUP		(IRQ_SHPI_START + 20)
    27. 

  27. #define IRQ_DB8500_I2C0			(IRQ_SHPI_START + 21)
    28. 

  28. #define IRQ_DB8500_I2C1			(IRQ_SHPI_START + 22)
    29. 

  29. #define IRQ_DB8500_USBOTG		(IRQ_SHPI_START + 23)
    30. 

  30. #define IRQ_DB8500_DMA_SECURE		(IRQ_SHPI_START + 24)
    31. 

  31. #define IRQ_DB8500_DMA			(IRQ_SHPI_START + 25)
    32. 

  32. #define IRQ_DB8500_UART2		(IRQ_SHPI_START + 26)
    33. 

  33. #define IRQ_DB8500_ICN_PMU1		(IRQ_SHPI_START + 27)
    34. 

  34. #define IRQ_DB8500_ICN_PMU2		(IRQ_SHPI_START + 28)
    35. 

  35. #define IRQ_DB8500_HSIR_EXCEP		(IRQ_SHPI_START + 29)
    36. 

  36. #define IRQ_DB8500_MSP0			(IRQ_SHPI_START + 31)
    37. 

  37. #define IRQ_DB8500_HSIR_CH0_OVRRUN	(IRQ_SHPI_START + 32)
    38. 

  38. #define IRQ_DB8500_HSIR_CH1_OVRRUN	(IRQ_SHPI_START + 33)
    39. 

  39. #define IRQ_DB8500_HSIR_CH2_OVRRUN	(IRQ_SHPI_START + 34)
    40. 

  40. #define IRQ_DB8500_HSIR_CH3_OVRRUN	(IRQ_SHPI_START + 35)
    41. 

  41. #define IRQ_DB8500_HSIR_CH4_OVRRUN	(IRQ_SHPI_START + 36)
    42. 

  42. #define IRQ_DB8500_HSIR_CH5_OVRRUN	(IRQ_SHPI_START + 37)
    43. 

  43. #define IRQ_DB8500_HSIR_CH6_OVRRUN	(IRQ_SHPI_START + 38)
    44. 

  44. #define IRQ_DB8500_HSIR_CH7_OVRRUN	(IRQ_SHPI_START + 39)
    45. 

  45. #define IRQ_DB8500_AB8500		(IRQ_SHPI_START + 40)
    46. 

  46. #define IRQ_DB8500_SDMMC2		(IRQ_SHPI_START + 41)
    47. 

  47. #define IRQ_DB8500_SIA			(IRQ_SHPI_START + 42)
    48. 

  48. #define IRQ_DB8500_SIA2			(IRQ_SHPI_START + 43)
    49. 

  49. #define IRQ_DB8500_SVA			(IRQ_SHPI_START + 44)
    50. 

  50. #define IRQ_DB8500_SVA2			(IRQ_SHPI_START + 45)
    51. 

  51. #define IRQ_DB8500_PRCMU0		(IRQ_SHPI_START + 46)
    52. 

  52. #define IRQ_DB8500_PRCMU1		(IRQ_SHPI_START + 47)
    53. 

  53. #define IRQ_DB8500_DISP			(IRQ_SHPI_START + 48)
    54. 

  54. #define IRQ_DB8500_SPI3			(IRQ_SHPI_START + 49)
    55. 

  55. #define IRQ_DB8500_SDMMC1		(IRQ_SHPI_START + 50)
    56. 

  56. #define IRQ_DB8500_I2C4			(IRQ_SHPI_START + 51)
    57. 

  57. #define IRQ_DB8500_SSP1			(IRQ_SHPI_START + 52)
    58. 

  58. #define IRQ_DB8500_SKE			(IRQ_SHPI_START + 53)
    59. 

  59. #define IRQ_DB8500_KB			(IRQ_SHPI_START + 54)
    60. 

  60. #define IRQ_DB8500_I2C2			(IRQ_SHPI_START + 55)
    61. 

  61. #define IRQ_DB8500_B2R2			(IRQ_SHPI_START + 56)
    62. 

  62. #define IRQ_DB8500_CRYP0		(IRQ_SHPI_START + 57)
    63. 

  63. #define IRQ_DB8500_SDMMC3		(IRQ_SHPI_START + 59)
    64. 

  64. #define IRQ_DB8500_SDMMC0		(IRQ_SHPI_START + 60)
    65. 

  65. #define IRQ_DB8500_HSEM			(IRQ_SHPI_START + 61)
    66. 

  66. #define IRQ_DB8500_MSP1			(IRQ_SHPI_START + 62)
    67. 

  67. #define IRQ_DB8500_SBAG			(IRQ_SHPI_START + 63)
    68. 

  68. #define IRQ_DB8500_SPI1			(IRQ_SHPI_START + 96)
    69. 

  69. #define IRQ_DB8500_SRPTIMER		(IRQ_SHPI_START + 97)
    70. 

  70. #define IRQ_DB8500_MSP2			(IRQ_SHPI_START + 98)
    71. 

  71. #define IRQ_DB8500_SDMMC4		(IRQ_SHPI_START + 99)
    72. 

  72. #define IRQ_DB8500_SDMMC5		(IRQ_SHPI_START + 100)
    73. 

  73. #define IRQ_DB8500_HSIRD0		(IRQ_SHPI_START + 104)
    74. 

  74. #define IRQ_DB8500_HSIRD1		(IRQ_SHPI_START + 105)
    75. 

  75. #define IRQ_DB8500_HSITD0		(IRQ_SHPI_START + 106)
    76. 

  76. #define IRQ_DB8500_HSITD1		(IRQ_SHPI_START + 107)
    77. 

  77. #define IRQ_DB8500_CTI0			(IRQ_SHPI_START + 108)
    78. 

  78. #define IRQ_DB8500_CTI1			(IRQ_SHPI_START + 109)
    79. 

  79. #define IRQ_DB8500_ICN_ERR		(IRQ_SHPI_START + 110)
    80. 

  80. #define IRQ_DB8500_MALI_PPMMU		(IRQ_SHPI_START + 112)
    81. 

  81. #define IRQ_DB8500_MALI_PP		(IRQ_SHPI_START + 113)
    82. 

  82. #define IRQ_DB8500_MALI_GPMMU		(IRQ_SHPI_START + 114)
    83. 

  83. #define IRQ_DB8500_MALI_GP		(IRQ_SHPI_START + 115)
    84. 

  84. #define IRQ_DB8500_MALI			(IRQ_SHPI_START + 116)
    85. 

  85. #define IRQ_DB8500_PRCMU_SEM		(IRQ_SHPI_START + 118)
    86. 

  86. #define IRQ_DB8500_GPIO0		(IRQ_SHPI_START + 119)
    87. 

  87. #define IRQ_DB8500_GPIO1		(IRQ_SHPI_START + 120)
    88. 

  88. #define IRQ_DB8500_GPIO2		(IRQ_SHPI_START + 121)
    89. 

  89. #define IRQ_DB8500_GPIO3		(IRQ_SHPI_START + 122)
    90. 

  90. #define IRQ_DB8500_GPIO4		(IRQ_SHPI_START + 123)
    91. 

  91. #define IRQ_DB8500_GPIO5		(IRQ_SHPI_START + 124)
    92. 

  92. #define IRQ_DB8500_GPIO6		(IRQ_SHPI_START + 125)
    93. 

  93. #define IRQ_DB8500_GPIO7		(IRQ_SHPI_START + 126)
    94. 

  94. #define IRQ_DB8500_GPIO8		(IRQ_SHPI_START + 127)
    95. 

  95. 

  96. #define IRQ_CA_WAKE_REQ_ED			(IRQ_SHPI_START + 71)
    97. 

  97. #define IRQ_AC_READ_NOTIFICATION_0_ED		(IRQ_SHPI_START + 66)
    98. 

  98. #define IRQ_AC_READ_NOTIFICATION_1_ED		(IRQ_SHPI_START + 64)
    99. 

  99. #define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED	(IRQ_SHPI_START + 67)
    100. 

  100. #define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED	(IRQ_SHPI_START + 65)
    101. 

  101. 

  102. #define IRQ_CA_WAKE_REQ_V1			(IRQ_SHPI_START + 83)
    103. 

  103. #define IRQ_AC_READ_NOTIFICATION_0_V1		(IRQ_SHPI_START + 78)
    104. 

  104. #define IRQ_AC_READ_NOTIFICATION_1_V1		(IRQ_SHPI_START + 76)
    105. 

  105. #define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1	(IRQ_SHPI_START + 79)
    106. 

  106. #define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1	(IRQ_SHPI_START + 77)
    107. 

  107. 

  108. #ifdef CONFIG_UX500_SOC_DB8500
    109. 

  109. 

  110. /* Virtual interrupts corresponding to the PRCMU wakeups.  */
    111. 

  111. #define IRQ_PRCMU_BASE IRQ_SOC_START
    112. 

  112. #define NUM_PRCMU_WAKEUPS (IRQ_PRCMU_END - IRQ_PRCMU_BASE)
    113. 

  113. 

  114. #define IRQ_PRCMU_RTC (IRQ_PRCMU_BASE)
    115. 

  115. #define IRQ_PRCMU_RTT0 (IRQ_PRCMU_BASE + 1)
    116. 

  116. #define IRQ_PRCMU_RTT1 (IRQ_PRCMU_BASE + 2)
    117. 

  117. #define IRQ_PRCMU_HSI0 (IRQ_PRCMU_BASE + 3)
    118. 

  118. #define IRQ_PRCMU_HSI1 (IRQ_PRCMU_BASE + 4)
    119. 

  119. #define IRQ_PRCMU_CA_WAKE (IRQ_PRCMU_BASE + 5)
    120. 

  120. #define IRQ_PRCMU_USB (IRQ_PRCMU_BASE + 6)
    121. 

  121. #define IRQ_PRCMU_ABB (IRQ_PRCMU_BASE + 7)
    122. 

  122. #define IRQ_PRCMU_ABB_FIFO (IRQ_PRCMU_BASE + 8)
    123. 

  123. #define IRQ_PRCMU_ARM (IRQ_PRCMU_BASE + 9)
    124. 

  124. #define IRQ_PRCMU_MODEM_SW_RESET_REQ (IRQ_PRCMU_BASE + 10)
    125. 

  125. #define IRQ_PRCMU_GPIO0 (IRQ_PRCMU_BASE + 11)
    126. 

  126. #define IRQ_PRCMU_GPIO1 (IRQ_PRCMU_BASE + 12)
    127. 

  127. #define IRQ_PRCMU_GPIO2 (IRQ_PRCMU_BASE + 13)
    128. 

  128. #define IRQ_PRCMU_GPIO3 (IRQ_PRCMU_BASE + 14)
    129. 

  129. #define IRQ_PRCMU_GPIO4 (IRQ_PRCMU_BASE + 15)
    130. 

  130. #define IRQ_PRCMU_GPIO5 (IRQ_PRCMU_BASE + 16)
    131. 

  131. #define IRQ_PRCMU_GPIO6 (IRQ_PRCMU_BASE + 17)
    132. 

  132. #define IRQ_PRCMU_GPIO7 (IRQ_PRCMU_BASE + 18)
    133. 

  133. #define IRQ_PRCMU_GPIO8 (IRQ_PRCMU_BASE + 19)
    134. 

  134. #define IRQ_PRCMU_CA_SLEEP (IRQ_PRCMU_BASE + 20)
    135. 

  135. #define IRQ_PRCMU_HOTMON_LOW (IRQ_PRCMU_BASE + 21)
    136. 

  136. #define IRQ_PRCMU_HOTMON_HIGH (IRQ_PRCMU_BASE + 22)
    137. 

  137. #define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23)
    138. 

  138. 

  139. /*
    140. 

  140.  * We may have several SoCs, but only one will run at a
    141. 

  141.  * time, so the one with most IRQs will bump this ahead,
    142. 

  142.  * but the IRQ_SOC_START remains the same for either SoC.
    143. 

  143.  */
    144. 

  144. #if IRQ_SOC_END < IRQ_PRCMU_END
    145. 

  145. #undef IRQ_SOC_END
    146. 

  146. #define IRQ_SOC_END IRQ_PRCMU_END
    147. 

  147. #endif
    148. 

  148. 

  149. #endif /* CONFIG_UX500_SOC_DB8500 */
    150. 

  150. #endif
    151.