powergate.c 4.2 KB

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  1. /*
  2. * drivers/powergate/tegra-powergate.c
  3. *
  4. * Copyright (c) 2010 Google, Inc
  5. *
  6. * Author:
  7. * Colin Cross <ccross@google.com>
  8. *
  9. * This software is licensed under the terms of the GNU General Public
  10. * License version 2, as published by the Free Software Foundation, and
  11. * may be copied, distributed, and modified under those terms.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/clk.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/delay.h>
  23. #include <linux/err.h>
  24. #include <linux/init.h>
  25. #include <linux/io.h>
  26. #include <linux/seq_file.h>
  27. #include <linux/spinlock.h>
  28. #include <mach/clk.h>
  29. #include <mach/iomap.h>
  30. #include <mach/powergate.h>
  31. #define PWRGATE_TOGGLE 0x30
  32. #define PWRGATE_TOGGLE_START (1 << 8)
  33. #define REMOVE_CLAMPING 0x34
  34. #define PWRGATE_STATUS 0x38
  35. static DEFINE_SPINLOCK(tegra_powergate_lock);
  36. static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
  37. static u32 pmc_read(unsigned long reg)
  38. {
  39. return readl(pmc + reg);
  40. }
  41. static void pmc_write(u32 val, unsigned long reg)
  42. {
  43. writel(val, pmc + reg);
  44. }
  45. static int tegra_powergate_set(int id, bool new_state)
  46. {
  47. bool status;
  48. unsigned long flags;
  49. spin_lock_irqsave(&tegra_powergate_lock, flags);
  50. status = pmc_read(PWRGATE_STATUS) & (1 << id);
  51. if (status == new_state) {
  52. spin_unlock_irqrestore(&tegra_powergate_lock, flags);
  53. return -EINVAL;
  54. }
  55. pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
  56. spin_unlock_irqrestore(&tegra_powergate_lock, flags);
  57. return 0;
  58. }
  59. int tegra_powergate_power_on(int id)
  60. {
  61. if (id < 0 || id >= TEGRA_NUM_POWERGATE)
  62. return -EINVAL;
  63. return tegra_powergate_set(id, true);
  64. }
  65. int tegra_powergate_power_off(int id)
  66. {
  67. if (id < 0 || id >= TEGRA_NUM_POWERGATE)
  68. return -EINVAL;
  69. return tegra_powergate_set(id, false);
  70. }
  71. static bool tegra_powergate_is_powered(int id)
  72. {
  73. u32 status;
  74. WARN_ON(id < 0 || id >= TEGRA_NUM_POWERGATE);
  75. status = pmc_read(PWRGATE_STATUS) & (1 << id);
  76. return !!status;
  77. }
  78. int tegra_powergate_remove_clamping(int id)
  79. {
  80. u32 mask;
  81. if (id < 0 || id >= TEGRA_NUM_POWERGATE)
  82. return -EINVAL;
  83. /*
  84. * Tegra 2 has a bug where PCIE and VDE clamping masks are
  85. * swapped relatively to the partition ids
  86. */
  87. if (id == TEGRA_POWERGATE_VDEC)
  88. mask = (1 << TEGRA_POWERGATE_PCIE);
  89. else if (id == TEGRA_POWERGATE_PCIE)
  90. mask = (1 << TEGRA_POWERGATE_VDEC);
  91. else
  92. mask = (1 << id);
  93. pmc_write(mask, REMOVE_CLAMPING);
  94. return 0;
  95. }
  96. /* Must be called with clk disabled, and returns with clk enabled */
  97. int tegra_powergate_sequence_power_up(int id, struct clk *clk)
  98. {
  99. int ret;
  100. tegra_periph_reset_assert(clk);
  101. ret = tegra_powergate_power_on(id);
  102. if (ret)
  103. goto err_power;
  104. ret = clk_enable(clk);
  105. if (ret)
  106. goto err_clk;
  107. udelay(10);
  108. ret = tegra_powergate_remove_clamping(id);
  109. if (ret)
  110. goto err_clamp;
  111. udelay(10);
  112. tegra_periph_reset_deassert(clk);
  113. return 0;
  114. err_clamp:
  115. clk_disable(clk);
  116. err_clk:
  117. tegra_powergate_power_off(id);
  118. err_power:
  119. return ret;
  120. }
  121. #ifdef CONFIG_DEBUG_FS
  122. static const char * const powergate_name[] = {
  123. [TEGRA_POWERGATE_CPU] = "cpu",
  124. [TEGRA_POWERGATE_3D] = "3d",
  125. [TEGRA_POWERGATE_VENC] = "venc",
  126. [TEGRA_POWERGATE_VDEC] = "vdec",
  127. [TEGRA_POWERGATE_PCIE] = "pcie",
  128. [TEGRA_POWERGATE_L2] = "l2",
  129. [TEGRA_POWERGATE_MPE] = "mpe",
  130. };
  131. static int powergate_show(struct seq_file *s, void *data)
  132. {
  133. int i;
  134. seq_printf(s, " powergate powered\n");
  135. seq_printf(s, "------------------\n");
  136. for (i = 0; i < TEGRA_NUM_POWERGATE; i++)
  137. seq_printf(s, " %9s %7s\n", powergate_name[i],
  138. tegra_powergate_is_powered(i) ? "yes" : "no");
  139. return 0;
  140. }
  141. static int powergate_open(struct inode *inode, struct file *file)
  142. {
  143. return single_open(file, powergate_show, inode->i_private);
  144. }
  145. static const struct file_operations powergate_fops = {
  146. .open = powergate_open,
  147. .read = seq_read,
  148. .llseek = seq_lseek,
  149. .release = single_release,
  150. };
  151. static int __init powergate_debugfs_init(void)
  152. {
  153. struct dentry *d;
  154. int err = -ENOMEM;
  155. d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
  156. &powergate_fops);
  157. if (!d)
  158. return -ENOMEM;
  159. return err;
  160. }
  161. late_initcall(powergate_debugfs_init);
  162. #endif