pinmux.h 6.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302
  1. /*
  2. * linux/arch/arm/mach-tegra/include/mach/pinmux.h
  3. *
  4. * Copyright (C) 2010 Google, Inc.
  5. * Copyright (C) 2010,2011 Nvidia, Inc.
  6. *
  7. * This software is licensed under the terms of the GNU General Public
  8. * License version 2, as published by the Free Software Foundation, and
  9. * may be copied, distributed, and modified under those terms.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. */
  17. #ifndef __MACH_TEGRA_PINMUX_H
  18. #define __MACH_TEGRA_PINMUX_H
  19. enum tegra_mux_func {
  20. TEGRA_MUX_RSVD = 0x8000,
  21. TEGRA_MUX_RSVD1 = 0x8000,
  22. TEGRA_MUX_RSVD2 = 0x8001,
  23. TEGRA_MUX_RSVD3 = 0x8002,
  24. TEGRA_MUX_RSVD4 = 0x8003,
  25. TEGRA_MUX_INVALID = 0x4000,
  26. TEGRA_MUX_NONE = -1,
  27. TEGRA_MUX_AHB_CLK,
  28. TEGRA_MUX_APB_CLK,
  29. TEGRA_MUX_AUDIO_SYNC,
  30. TEGRA_MUX_CRT,
  31. TEGRA_MUX_DAP1,
  32. TEGRA_MUX_DAP2,
  33. TEGRA_MUX_DAP3,
  34. TEGRA_MUX_DAP4,
  35. TEGRA_MUX_DAP5,
  36. TEGRA_MUX_DISPLAYA,
  37. TEGRA_MUX_DISPLAYB,
  38. TEGRA_MUX_EMC_TEST0_DLL,
  39. TEGRA_MUX_EMC_TEST1_DLL,
  40. TEGRA_MUX_GMI,
  41. TEGRA_MUX_GMI_INT,
  42. TEGRA_MUX_HDMI,
  43. TEGRA_MUX_I2C,
  44. TEGRA_MUX_I2C2,
  45. TEGRA_MUX_I2C3,
  46. TEGRA_MUX_IDE,
  47. TEGRA_MUX_IRDA,
  48. TEGRA_MUX_KBC,
  49. TEGRA_MUX_MIO,
  50. TEGRA_MUX_MIPI_HS,
  51. TEGRA_MUX_NAND,
  52. TEGRA_MUX_OSC,
  53. TEGRA_MUX_OWR,
  54. TEGRA_MUX_PCIE,
  55. TEGRA_MUX_PLLA_OUT,
  56. TEGRA_MUX_PLLC_OUT1,
  57. TEGRA_MUX_PLLM_OUT1,
  58. TEGRA_MUX_PLLP_OUT2,
  59. TEGRA_MUX_PLLP_OUT3,
  60. TEGRA_MUX_PLLP_OUT4,
  61. TEGRA_MUX_PWM,
  62. TEGRA_MUX_PWR_INTR,
  63. TEGRA_MUX_PWR_ON,
  64. TEGRA_MUX_RTCK,
  65. TEGRA_MUX_SDIO1,
  66. TEGRA_MUX_SDIO2,
  67. TEGRA_MUX_SDIO3,
  68. TEGRA_MUX_SDIO4,
  69. TEGRA_MUX_SFLASH,
  70. TEGRA_MUX_SPDIF,
  71. TEGRA_MUX_SPI1,
  72. TEGRA_MUX_SPI2,
  73. TEGRA_MUX_SPI2_ALT,
  74. TEGRA_MUX_SPI3,
  75. TEGRA_MUX_SPI4,
  76. TEGRA_MUX_TRACE,
  77. TEGRA_MUX_TWC,
  78. TEGRA_MUX_UARTA,
  79. TEGRA_MUX_UARTB,
  80. TEGRA_MUX_UARTC,
  81. TEGRA_MUX_UARTD,
  82. TEGRA_MUX_UARTE,
  83. TEGRA_MUX_ULPI,
  84. TEGRA_MUX_VI,
  85. TEGRA_MUX_VI_SENSOR_CLK,
  86. TEGRA_MUX_XIO,
  87. TEGRA_MUX_BLINK,
  88. TEGRA_MUX_CEC,
  89. TEGRA_MUX_CLK12,
  90. TEGRA_MUX_DAP,
  91. TEGRA_MUX_DAPSDMMC2,
  92. TEGRA_MUX_DDR,
  93. TEGRA_MUX_DEV3,
  94. TEGRA_MUX_DTV,
  95. TEGRA_MUX_VI_ALT1,
  96. TEGRA_MUX_VI_ALT2,
  97. TEGRA_MUX_VI_ALT3,
  98. TEGRA_MUX_EMC_DLL,
  99. TEGRA_MUX_EXTPERIPH1,
  100. TEGRA_MUX_EXTPERIPH2,
  101. TEGRA_MUX_EXTPERIPH3,
  102. TEGRA_MUX_GMI_ALT,
  103. TEGRA_MUX_HDA,
  104. TEGRA_MUX_HSI,
  105. TEGRA_MUX_I2C4,
  106. TEGRA_MUX_I2C5,
  107. TEGRA_MUX_I2CPWR,
  108. TEGRA_MUX_I2S0,
  109. TEGRA_MUX_I2S1,
  110. TEGRA_MUX_I2S2,
  111. TEGRA_MUX_I2S3,
  112. TEGRA_MUX_I2S4,
  113. TEGRA_MUX_NAND_ALT,
  114. TEGRA_MUX_POPSDIO4,
  115. TEGRA_MUX_POPSDMMC4,
  116. TEGRA_MUX_PWM0,
  117. TEGRA_MUX_PWM1,
  118. TEGRA_MUX_PWM2,
  119. TEGRA_MUX_PWM3,
  120. TEGRA_MUX_SATA,
  121. TEGRA_MUX_SPI5,
  122. TEGRA_MUX_SPI6,
  123. TEGRA_MUX_SYSCLK,
  124. TEGRA_MUX_VGP1,
  125. TEGRA_MUX_VGP2,
  126. TEGRA_MUX_VGP3,
  127. TEGRA_MUX_VGP4,
  128. TEGRA_MUX_VGP5,
  129. TEGRA_MUX_VGP6,
  130. TEGRA_MUX_SAFE,
  131. TEGRA_MAX_MUX,
  132. };
  133. enum tegra_pullupdown {
  134. TEGRA_PUPD_NORMAL = 0,
  135. TEGRA_PUPD_PULL_DOWN,
  136. TEGRA_PUPD_PULL_UP,
  137. };
  138. enum tegra_tristate {
  139. TEGRA_TRI_NORMAL = 0,
  140. TEGRA_TRI_TRISTATE = 1,
  141. };
  142. enum tegra_pin_io {
  143. TEGRA_PIN_OUTPUT = 0,
  144. TEGRA_PIN_INPUT = 1,
  145. };
  146. enum tegra_vddio {
  147. TEGRA_VDDIO_BB = 0,
  148. TEGRA_VDDIO_LCD,
  149. TEGRA_VDDIO_VI,
  150. TEGRA_VDDIO_UART,
  151. TEGRA_VDDIO_DDR,
  152. TEGRA_VDDIO_NAND,
  153. TEGRA_VDDIO_SYS,
  154. TEGRA_VDDIO_AUDIO,
  155. TEGRA_VDDIO_SD,
  156. TEGRA_VDDIO_CAM,
  157. TEGRA_VDDIO_GMI,
  158. TEGRA_VDDIO_PEXCTL,
  159. TEGRA_VDDIO_SDMMC1,
  160. TEGRA_VDDIO_SDMMC3,
  161. TEGRA_VDDIO_SDMMC4,
  162. };
  163. struct tegra_pingroup_config {
  164. int pingroup;
  165. enum tegra_mux_func func;
  166. enum tegra_pullupdown pupd;
  167. enum tegra_tristate tristate;
  168. };
  169. enum tegra_slew {
  170. TEGRA_SLEW_FASTEST = 0,
  171. TEGRA_SLEW_FAST,
  172. TEGRA_SLEW_SLOW,
  173. TEGRA_SLEW_SLOWEST,
  174. TEGRA_MAX_SLEW,
  175. };
  176. enum tegra_pull_strength {
  177. TEGRA_PULL_0 = 0,
  178. TEGRA_PULL_1,
  179. TEGRA_PULL_2,
  180. TEGRA_PULL_3,
  181. TEGRA_PULL_4,
  182. TEGRA_PULL_5,
  183. TEGRA_PULL_6,
  184. TEGRA_PULL_7,
  185. TEGRA_PULL_8,
  186. TEGRA_PULL_9,
  187. TEGRA_PULL_10,
  188. TEGRA_PULL_11,
  189. TEGRA_PULL_12,
  190. TEGRA_PULL_13,
  191. TEGRA_PULL_14,
  192. TEGRA_PULL_15,
  193. TEGRA_PULL_16,
  194. TEGRA_PULL_17,
  195. TEGRA_PULL_18,
  196. TEGRA_PULL_19,
  197. TEGRA_PULL_20,
  198. TEGRA_PULL_21,
  199. TEGRA_PULL_22,
  200. TEGRA_PULL_23,
  201. TEGRA_PULL_24,
  202. TEGRA_PULL_25,
  203. TEGRA_PULL_26,
  204. TEGRA_PULL_27,
  205. TEGRA_PULL_28,
  206. TEGRA_PULL_29,
  207. TEGRA_PULL_30,
  208. TEGRA_PULL_31,
  209. TEGRA_MAX_PULL,
  210. };
  211. enum tegra_drive {
  212. TEGRA_DRIVE_DIV_8 = 0,
  213. TEGRA_DRIVE_DIV_4,
  214. TEGRA_DRIVE_DIV_2,
  215. TEGRA_DRIVE_DIV_1,
  216. TEGRA_MAX_DRIVE,
  217. };
  218. enum tegra_hsm {
  219. TEGRA_HSM_DISABLE = 0,
  220. TEGRA_HSM_ENABLE,
  221. };
  222. enum tegra_schmitt {
  223. TEGRA_SCHMITT_DISABLE = 0,
  224. TEGRA_SCHMITT_ENABLE,
  225. };
  226. struct tegra_drive_pingroup_config {
  227. int pingroup;
  228. enum tegra_hsm hsm;
  229. enum tegra_schmitt schmitt;
  230. enum tegra_drive drive;
  231. enum tegra_pull_strength pull_down;
  232. enum tegra_pull_strength pull_up;
  233. enum tegra_slew slew_rising;
  234. enum tegra_slew slew_falling;
  235. };
  236. struct tegra_drive_pingroup_desc {
  237. const char *name;
  238. s16 reg_bank;
  239. s16 reg;
  240. };
  241. struct tegra_pingroup_desc {
  242. const char *name;
  243. int funcs[4];
  244. int func_safe;
  245. int vddio;
  246. enum tegra_pin_io io_default;
  247. s16 tri_bank; /* Register bank the tri_reg exists within */
  248. s16 mux_bank; /* Register bank the mux_reg exists within */
  249. s16 pupd_bank; /* Register bank the pupd_reg exists within */
  250. s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */
  251. s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
  252. s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
  253. s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
  254. s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
  255. s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
  256. s8 lock_bit; /* offset of the LOCK bit into mux register bit */
  257. s8 od_bit; /* offset of the OD bit into mux register bit */
  258. s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
  259. };
  260. typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
  261. int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
  262. int *pgdrive_max);
  263. void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
  264. const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
  265. void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
  266. const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
  267. int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
  268. int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
  269. void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
  270. int len);
  271. void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
  272. int len);
  273. void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
  274. int len);
  275. void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
  276. int len);
  277. void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
  278. int len, enum tegra_tristate tristate);
  279. void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
  280. int len, enum tegra_pullupdown pupd);
  281. #endif