nanoengine.c 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121
  1. /*
  2. * linux/arch/arm/mach-sa1100/nanoengine.c
  3. *
  4. * Bright Star Engineering's nanoEngine board init code.
  5. *
  6. * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/init.h>
  14. #include <linux/kernel.h>
  15. #include <linux/mtd/mtd.h>
  16. #include <linux/mtd/partitions.h>
  17. #include <linux/root_dev.h>
  18. #include <asm/mach-types.h>
  19. #include <asm/setup.h>
  20. #include <asm/page.h>
  21. #include <asm/mach/arch.h>
  22. #include <asm/mach/flash.h>
  23. #include <asm/mach/map.h>
  24. #include <asm/mach/serial_sa1100.h>
  25. #include <mach/hardware.h>
  26. #include <mach/nanoengine.h>
  27. #include "generic.h"
  28. /* Flash bank 0 */
  29. static struct mtd_partition nanoengine_partitions[] = {
  30. {
  31. .name = "nanoEngine boot firmware and parameter table",
  32. .size = 0x00010000, /* 32K */
  33. .offset = 0,
  34. .mask_flags = MTD_WRITEABLE,
  35. }, {
  36. .name = "kernel/initrd reserved",
  37. .size = 0x002f0000,
  38. .offset = 0x00010000,
  39. .mask_flags = MTD_WRITEABLE,
  40. }, {
  41. .name = "experimental filesystem allocation",
  42. .size = 0x00100000,
  43. .offset = 0x00300000,
  44. .mask_flags = MTD_WRITEABLE,
  45. }
  46. };
  47. static struct flash_platform_data nanoengine_flash_data = {
  48. .map_name = "jedec_probe",
  49. .parts = nanoengine_partitions,
  50. .nr_parts = ARRAY_SIZE(nanoengine_partitions),
  51. };
  52. static struct resource nanoengine_flash_resources[] = {
  53. {
  54. .start = SA1100_CS0_PHYS,
  55. .end = SA1100_CS0_PHYS + SZ_32M - 1,
  56. .flags = IORESOURCE_MEM,
  57. }, {
  58. .start = SA1100_CS1_PHYS,
  59. .end = SA1100_CS1_PHYS + SZ_32M - 1,
  60. .flags = IORESOURCE_MEM,
  61. }
  62. };
  63. static struct map_desc nanoengine_io_desc[] __initdata = {
  64. {
  65. /* System Registers */
  66. .virtual = 0xf0000000,
  67. .pfn = __phys_to_pfn(0x10000000),
  68. .length = 0x00100000,
  69. .type = MT_DEVICE
  70. }, {
  71. /* Internal PCI Memory Read/Write */
  72. .virtual = NANO_PCI_MEM_RW_VIRT,
  73. .pfn = __phys_to_pfn(NANO_PCI_MEM_RW_PHYS),
  74. .length = NANO_PCI_MEM_RW_SIZE,
  75. .type = MT_DEVICE
  76. }, {
  77. /* Internal PCI Config Space */
  78. .virtual = NANO_PCI_CONFIG_SPACE_VIRT,
  79. .pfn = __phys_to_pfn(NANO_PCI_CONFIG_SPACE_PHYS),
  80. .length = NANO_PCI_CONFIG_SPACE_SIZE,
  81. .type = MT_DEVICE
  82. }
  83. };
  84. static void __init nanoengine_map_io(void)
  85. {
  86. sa1100_map_io();
  87. iotable_init(nanoengine_io_desc, ARRAY_SIZE(nanoengine_io_desc));
  88. sa1100_register_uart(0, 1);
  89. sa1100_register_uart(1, 2);
  90. sa1100_register_uart(2, 3);
  91. Ser1SDCR0 |= SDCR0_UART;
  92. /* disable IRDA -- UART2 is used as a normal serial port */
  93. Ser2UTCR4 = 0;
  94. Ser2HSCR0 = 0;
  95. }
  96. static void __init nanoengine_init(void)
  97. {
  98. sa11x0_register_mtd(&nanoengine_flash_data, nanoengine_flash_resources,
  99. ARRAY_SIZE(nanoengine_flash_resources));
  100. }
  101. MACHINE_START(NANOENGINE, "BSE nanoEngine")
  102. .atag_offset = 0x100,
  103. .map_io = nanoengine_map_io,
  104. .init_irq = sa1100_init_irq,
  105. .timer = &sa1100_timer,
  106. .init_machine = nanoengine_init,
  107. .restart = sa11x0_restart,
  108. MACHINE_END