common-pci.c 12 KB

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  1. /*
  2. * arch/arm/mach-ixp4xx/common-pci.c
  3. *
  4. * IXP4XX PCI routines for all platforms
  5. *
  6. * Maintainer: Deepak Saxena <dsaxena@plexity.net>
  7. *
  8. * Copyright (C) 2002 Intel Corporation.
  9. * Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com>
  10. * Copyright (C) 2003-2004 MontaVista Software, Inc.
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. *
  16. */
  17. #include <linux/sched.h>
  18. #include <linux/kernel.h>
  19. #include <linux/pci.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/mm.h>
  22. #include <linux/init.h>
  23. #include <linux/ioport.h>
  24. #include <linux/slab.h>
  25. #include <linux/delay.h>
  26. #include <linux/device.h>
  27. #include <linux/io.h>
  28. #include <linux/export.h>
  29. #include <asm/dma-mapping.h>
  30. #include <asm/cputype.h>
  31. #include <asm/irq.h>
  32. #include <asm/sizes.h>
  33. #include <asm/system.h>
  34. #include <asm/mach/pci.h>
  35. #include <mach/hardware.h>
  36. /*
  37. * IXP4xx PCI read function is dependent on whether we are
  38. * running A0 or B0 (AppleGate) silicon.
  39. */
  40. int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
  41. /*
  42. * Base address for PCI regsiter region
  43. */
  44. unsigned long ixp4xx_pci_reg_base = 0;
  45. /*
  46. * PCI cfg an I/O routines are done by programming a
  47. * command/byte enable register, and then read/writing
  48. * the data from a data regsiter. We need to ensure
  49. * these transactions are atomic or we will end up
  50. * with corrupt data on the bus or in a driver.
  51. */
  52. static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock);
  53. /*
  54. * Read from PCI config space
  55. */
  56. static void crp_read(u32 ad_cbe, u32 *data)
  57. {
  58. unsigned long flags;
  59. raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
  60. *PCI_CRP_AD_CBE = ad_cbe;
  61. *data = *PCI_CRP_RDATA;
  62. raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
  63. }
  64. /*
  65. * Write to PCI config space
  66. */
  67. static void crp_write(u32 ad_cbe, u32 data)
  68. {
  69. unsigned long flags;
  70. raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
  71. *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
  72. *PCI_CRP_WDATA = data;
  73. raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
  74. }
  75. static inline int check_master_abort(void)
  76. {
  77. /* check Master Abort bit after access */
  78. unsigned long isr = *PCI_ISR;
  79. if (isr & PCI_ISR_PFE) {
  80. /* make sure the Master Abort bit is reset */
  81. *PCI_ISR = PCI_ISR_PFE;
  82. pr_debug("%s failed\n", __func__);
  83. return 1;
  84. }
  85. return 0;
  86. }
  87. int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
  88. {
  89. unsigned long flags;
  90. int retval = 0;
  91. int i;
  92. raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
  93. *PCI_NP_AD = addr;
  94. /*
  95. * PCI workaround - only works if NP PCI space reads have
  96. * no side effects!!! Read 8 times. last one will be good.
  97. */
  98. for (i = 0; i < 8; i++) {
  99. *PCI_NP_CBE = cmd;
  100. *data = *PCI_NP_RDATA;
  101. *data = *PCI_NP_RDATA;
  102. }
  103. if(check_master_abort())
  104. retval = 1;
  105. raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
  106. return retval;
  107. }
  108. int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
  109. {
  110. unsigned long flags;
  111. int retval = 0;
  112. raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
  113. *PCI_NP_AD = addr;
  114. /* set up and execute the read */
  115. *PCI_NP_CBE = cmd;
  116. /* the result of the read is now in NP_RDATA */
  117. *data = *PCI_NP_RDATA;
  118. if(check_master_abort())
  119. retval = 1;
  120. raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
  121. return retval;
  122. }
  123. int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
  124. {
  125. unsigned long flags;
  126. int retval = 0;
  127. raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
  128. *PCI_NP_AD = addr;
  129. /* set up the write */
  130. *PCI_NP_CBE = cmd;
  131. /* execute the write by writing to NP_WDATA */
  132. *PCI_NP_WDATA = data;
  133. if(check_master_abort())
  134. retval = 1;
  135. raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
  136. return retval;
  137. }
  138. static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
  139. {
  140. u32 addr;
  141. if (!bus_num) {
  142. /* type 0 */
  143. addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) |
  144. (where & ~3);
  145. } else {
  146. /* type 1 */
  147. addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) |
  148. ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
  149. }
  150. return addr;
  151. }
  152. /*
  153. * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
  154. * 0 and 3 are not valid indexes...
  155. */
  156. static u32 bytemask[] = {
  157. /*0*/ 0,
  158. /*1*/ 0xff,
  159. /*2*/ 0xffff,
  160. /*3*/ 0,
  161. /*4*/ 0xffffffff,
  162. };
  163. static u32 local_byte_lane_enable_bits(u32 n, int size)
  164. {
  165. if (size == 1)
  166. return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
  167. if (size == 2)
  168. return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
  169. if (size == 4)
  170. return 0;
  171. return 0xffffffff;
  172. }
  173. static int local_read_config(int where, int size, u32 *value)
  174. {
  175. u32 n, data;
  176. pr_debug("local_read_config from %d size %d\n", where, size);
  177. n = where % 4;
  178. crp_read(where & ~3, &data);
  179. *value = (data >> (8*n)) & bytemask[size];
  180. pr_debug("local_read_config read %#x\n", *value);
  181. return PCIBIOS_SUCCESSFUL;
  182. }
  183. static int local_write_config(int where, int size, u32 value)
  184. {
  185. u32 n, byte_enables, data;
  186. pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
  187. n = where % 4;
  188. byte_enables = local_byte_lane_enable_bits(n, size);
  189. if (byte_enables == 0xffffffff)
  190. return PCIBIOS_BAD_REGISTER_NUMBER;
  191. data = value << (8*n);
  192. crp_write((where & ~3) | byte_enables, data);
  193. return PCIBIOS_SUCCESSFUL;
  194. }
  195. static u32 byte_lane_enable_bits(u32 n, int size)
  196. {
  197. if (size == 1)
  198. return (0xf & ~BIT(n)) << 4;
  199. if (size == 2)
  200. return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
  201. if (size == 4)
  202. return 0;
  203. return 0xffffffff;
  204. }
  205. static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
  206. {
  207. u32 n, byte_enables, addr, data;
  208. u8 bus_num = bus->number;
  209. pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
  210. bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
  211. *value = 0xffffffff;
  212. n = where % 4;
  213. byte_enables = byte_lane_enable_bits(n, size);
  214. if (byte_enables == 0xffffffff)
  215. return PCIBIOS_BAD_REGISTER_NUMBER;
  216. addr = ixp4xx_config_addr(bus_num, devfn, where);
  217. if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data))
  218. return PCIBIOS_DEVICE_NOT_FOUND;
  219. *value = (data >> (8*n)) & bytemask[size];
  220. pr_debug("read_config_byte read %#x\n", *value);
  221. return PCIBIOS_SUCCESSFUL;
  222. }
  223. static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
  224. {
  225. u32 n, byte_enables, addr, data;
  226. u8 bus_num = bus->number;
  227. pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
  228. size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
  229. n = where % 4;
  230. byte_enables = byte_lane_enable_bits(n, size);
  231. if (byte_enables == 0xffffffff)
  232. return PCIBIOS_BAD_REGISTER_NUMBER;
  233. addr = ixp4xx_config_addr(bus_num, devfn, where);
  234. data = value << (8*n);
  235. if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data))
  236. return PCIBIOS_DEVICE_NOT_FOUND;
  237. return PCIBIOS_SUCCESSFUL;
  238. }
  239. struct pci_ops ixp4xx_ops = {
  240. .read = ixp4xx_pci_read_config,
  241. .write = ixp4xx_pci_write_config,
  242. };
  243. /*
  244. * PCI abort handler
  245. */
  246. static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
  247. {
  248. u32 isr, status;
  249. isr = *PCI_ISR;
  250. local_read_config(PCI_STATUS, 2, &status);
  251. pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
  252. "status = %#x\n", addr, isr, status);
  253. /* make sure the Master Abort bit is reset */
  254. *PCI_ISR = PCI_ISR_PFE;
  255. status |= PCI_STATUS_REC_MASTER_ABORT;
  256. local_write_config(PCI_STATUS, 2, status);
  257. /*
  258. * If it was an imprecise abort, then we need to correct the
  259. * return address to be _after_ the instruction.
  260. */
  261. if (fsr & (1 << 10))
  262. regs->ARM_pc += 4;
  263. return 0;
  264. }
  265. static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
  266. {
  267. return (dma_addr + size) >= SZ_64M;
  268. }
  269. /*
  270. * Setup DMA mask to 64MB on PCI devices. Ignore all other devices.
  271. */
  272. static int ixp4xx_pci_platform_notify(struct device *dev)
  273. {
  274. if(dev->bus == &pci_bus_type) {
  275. *dev->dma_mask = SZ_64M - 1;
  276. dev->coherent_dma_mask = SZ_64M - 1;
  277. dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
  278. }
  279. return 0;
  280. }
  281. static int ixp4xx_pci_platform_notify_remove(struct device *dev)
  282. {
  283. if(dev->bus == &pci_bus_type) {
  284. dmabounce_unregister_dev(dev);
  285. }
  286. return 0;
  287. }
  288. void __init ixp4xx_pci_preinit(void)
  289. {
  290. unsigned long cpuid = read_cpuid_id();
  291. #ifdef CONFIG_IXP4XX_INDIRECT_PCI
  292. pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */
  293. #else
  294. pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */
  295. #endif
  296. /*
  297. * Determine which PCI read method to use.
  298. * Rev 0 IXP425 requires workaround.
  299. */
  300. if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
  301. printk("PCI: IXP42x A0 silicon detected - "
  302. "PCI Non-Prefetch Workaround Enabled\n");
  303. ixp4xx_pci_read = ixp4xx_pci_read_errata;
  304. } else
  305. ixp4xx_pci_read = ixp4xx_pci_read_no_errata;
  306. /* hook in our fault handler for PCI errors */
  307. hook_fault_code(16+6, abort_handler, SIGBUS, 0,
  308. "imprecise external abort");
  309. pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
  310. /*
  311. * We use identity AHB->PCI address translation
  312. * in the 0x48000000 to 0x4bffffff address space
  313. */
  314. *PCI_PCIMEMBASE = 0x48494A4B;
  315. /*
  316. * We also use identity PCI->AHB address translation
  317. * in 4 16MB BARs that begin at the physical memory start
  318. */
  319. *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
  320. ((PHYS_OFFSET & 0xFF000000) >> 8) +
  321. ((PHYS_OFFSET & 0xFF000000) >> 16) +
  322. ((PHYS_OFFSET & 0xFF000000) >> 24) +
  323. 0x00010203;
  324. if (*PCI_CSR & PCI_CSR_HOST) {
  325. printk("PCI: IXP4xx is host\n");
  326. pr_debug("setup BARs in controller\n");
  327. /*
  328. * We configure the PCI inbound memory windows to be
  329. * 1:1 mapped to SDRAM
  330. */
  331. local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
  332. local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
  333. local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
  334. local_write_config(PCI_BASE_ADDRESS_3, 4,
  335. PHYS_OFFSET + SZ_32M + SZ_16M);
  336. /*
  337. * Enable CSR window at 64 MiB to allow PCI masters
  338. * to continue prefetching past 64 MiB boundary.
  339. */
  340. local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);
  341. /*
  342. * Enable the IO window to be way up high, at 0xfffffc00
  343. */
  344. local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
  345. } else {
  346. printk("PCI: IXP4xx is target - No bus scan performed\n");
  347. }
  348. printk("PCI: IXP4xx Using %s access for memory space\n",
  349. #ifndef CONFIG_IXP4XX_INDIRECT_PCI
  350. "direct"
  351. #else
  352. "indirect"
  353. #endif
  354. );
  355. pr_debug("clear error bits in ISR\n");
  356. *PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
  357. /*
  358. * Set Initialize Complete in PCI Control Register: allow IXP4XX to
  359. * respond to PCI configuration cycles. Specify that the AHB bus is
  360. * operating in big endian mode. Set up byte lane swapping between
  361. * little-endian PCI and the big-endian AHB bus
  362. */
  363. #ifdef __ARMEB__
  364. *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
  365. #else
  366. *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE;
  367. #endif
  368. pr_debug("DONE\n");
  369. }
  370. int ixp4xx_setup(int nr, struct pci_sys_data *sys)
  371. {
  372. struct resource *res;
  373. if (nr >= 1)
  374. return 0;
  375. res = kzalloc(sizeof(*res) * 2, GFP_KERNEL);
  376. if (res == NULL) {
  377. /*
  378. * If we're out of memory this early, something is wrong,
  379. * so we might as well catch it here.
  380. */
  381. panic("PCI: unable to allocate resources?\n");
  382. }
  383. local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
  384. res[0].name = "PCI I/O Space";
  385. res[0].start = 0x00000000;
  386. res[0].end = 0x0000ffff;
  387. res[0].flags = IORESOURCE_IO;
  388. res[1].name = "PCI Memory Space";
  389. res[1].start = PCIBIOS_MIN_MEM;
  390. res[1].end = PCIBIOS_MAX_MEM;
  391. res[1].flags = IORESOURCE_MEM;
  392. request_resource(&ioport_resource, &res[0]);
  393. request_resource(&iomem_resource, &res[1]);
  394. pci_add_resource(&sys->resources, &res[0]);
  395. pci_add_resource(&sys->resources, &res[1]);
  396. platform_notify = ixp4xx_pci_platform_notify;
  397. platform_notify_remove = ixp4xx_pci_platform_notify_remove;
  398. return 1;
  399. }
  400. struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
  401. {
  402. return pci_scan_root_bus(NULL, sys->busnr, &ixp4xx_ops, sys,
  403. &sys->resources);
  404. }
  405. int dma_set_coherent_mask(struct device *dev, u64 mask)
  406. {
  407. if (mask >= SZ_64M - 1)
  408. return 0;
  409. return -EIO;
  410. }
  411. EXPORT_SYMBOL(ixp4xx_pci_read);
  412. EXPORT_SYMBOL(ixp4xx_pci_write);
  413. EXPORT_SYMBOL(dma_set_coherent_mask);