pci.c 6.2 KB

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  1. /*
  2. * arch/arm/mach-ixp23xx/pci.c
  3. *
  4. * PCI routines for IXP23XX based systems
  5. *
  6. * Copyright (c) 2005 MontaVista Software, Inc.
  7. *
  8. * based on original code:
  9. *
  10. * Author: Naeem Afzal <naeem.m.afzal@intel.com>
  11. * Copyright 2002-2005 Intel Corp.
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. */
  18. #include <linux/sched.h>
  19. #include <linux/kernel.h>
  20. #include <linux/pci.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/mm.h>
  23. #include <linux/init.h>
  24. #include <linux/ioport.h>
  25. #include <linux/delay.h>
  26. #include <linux/io.h>
  27. #include <asm/irq.h>
  28. #include <asm/sizes.h>
  29. #include <asm/system.h>
  30. #include <asm/mach/pci.h>
  31. #include <mach/hardware.h>
  32. extern int (*external_fault) (unsigned long, struct pt_regs *);
  33. static volatile int pci_master_aborts = 0;
  34. #ifdef DEBUG
  35. #define DBG(x...) printk(x)
  36. #else
  37. #define DBG(x...)
  38. #endif
  39. int clear_master_aborts(void);
  40. static u32
  41. *ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
  42. {
  43. u32 *paddress;
  44. /*
  45. * Must be dword aligned
  46. */
  47. where &= ~3;
  48. /*
  49. * For top bus, generate type 0, else type 1
  50. */
  51. if (!bus_nr) {
  52. if (PCI_SLOT(devfn) >= 8)
  53. return 0;
  54. paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT
  55. | (1 << (PCI_SLOT(devfn) + 16))
  56. | (PCI_FUNC(devfn) << 8) | where);
  57. } else {
  58. paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT
  59. | (bus_nr << 16)
  60. | (PCI_SLOT(devfn) << 11)
  61. | (PCI_FUNC(devfn) << 8) | where);
  62. }
  63. return paddress;
  64. }
  65. /*
  66. * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
  67. * 0 and 3 are not valid indexes...
  68. */
  69. static u32 bytemask[] = {
  70. /*0*/ 0,
  71. /*1*/ 0xff,
  72. /*2*/ 0xffff,
  73. /*3*/ 0,
  74. /*4*/ 0xffffffff,
  75. };
  76. static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  77. int where, int size, u32 *value)
  78. {
  79. u32 n;
  80. u32 *addr;
  81. n = where % 4;
  82. DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where,
  83. bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
  84. addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
  85. if (!addr)
  86. return PCIBIOS_DEVICE_NOT_FOUND;
  87. pci_master_aborts = 0;
  88. *value = (*addr >> (8*n)) & bytemask[size];
  89. if (pci_master_aborts) {
  90. pci_master_aborts = 0;
  91. *value = 0xffffffff;
  92. return PCIBIOS_DEVICE_NOT_FOUND;
  93. }
  94. return PCIBIOS_SUCCESSFUL;
  95. }
  96. /*
  97. * We don't do error checking on the address for writes.
  98. * It's assumed that the user checked for the device existing first
  99. * by doing a read first.
  100. */
  101. static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
  102. int where, int size, u32 value)
  103. {
  104. u32 mask;
  105. u32 *addr;
  106. u32 temp;
  107. mask = ~(bytemask[size] << ((where % 0x4) * 8));
  108. addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
  109. if (!addr)
  110. return PCIBIOS_DEVICE_NOT_FOUND;
  111. temp = (u32) (value) << ((where % 0x4) * 8);
  112. *addr = (*addr & mask) | temp;
  113. clear_master_aborts();
  114. return PCIBIOS_SUCCESSFUL;
  115. }
  116. struct pci_ops ixp23xx_pci_ops = {
  117. .read = ixp23xx_pci_read_config,
  118. .write = ixp23xx_pci_write_config,
  119. };
  120. struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
  121. {
  122. return pci_scan_root_bus(NULL, sysdata->busnr, &ixp23xx_pci_ops,
  123. sysdata, &sysdata->resources);
  124. }
  125. int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
  126. {
  127. volatile unsigned long temp;
  128. unsigned long flags;
  129. pci_master_aborts = 1;
  130. local_irq_save(flags);
  131. temp = *IXP23XX_PCI_CONTROL;
  132. /*
  133. * master abort and cmd tgt err
  134. */
  135. if (temp & ((1 << 8) | (1 << 5)))
  136. *IXP23XX_PCI_CONTROL = temp;
  137. temp = *IXP23XX_PCI_CMDSTAT;
  138. if (temp & (1 << 29))
  139. *IXP23XX_PCI_CMDSTAT = temp;
  140. local_irq_restore(flags);
  141. /*
  142. * If it was an imprecise abort, then we need to correct the
  143. * return address to be _after_ the instruction.
  144. */
  145. if (fsr & (1 << 10))
  146. regs->ARM_pc += 4;
  147. return 0;
  148. }
  149. int clear_master_aborts(void)
  150. {
  151. volatile u32 temp;
  152. temp = *IXP23XX_PCI_CONTROL;
  153. /*
  154. * master abort and cmd tgt err
  155. */
  156. if (temp & ((1 << 8) | (1 << 5)))
  157. *IXP23XX_PCI_CONTROL = temp;
  158. temp = *IXP23XX_PCI_CMDSTAT;
  159. if (temp & (1 << 29))
  160. *IXP23XX_PCI_CMDSTAT = temp;
  161. return 0;
  162. }
  163. static void __init ixp23xx_pci_common_init(void)
  164. {
  165. #ifdef __ARMEB__
  166. *IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */
  167. #endif
  168. /*
  169. * ADDR_31 needs to be clear for PCI memory access to CPP memory
  170. */
  171. *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31;
  172. *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF;
  173. /*
  174. * Select correct memory for PCI inbound transactions
  175. */
  176. if (ixp23xx_cpp_boot()) {
  177. *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1);
  178. } else {
  179. *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1);
  180. /*
  181. * Enable coherency on A2 silicon.
  182. */
  183. if (arch_is_coherent())
  184. *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF;
  185. }
  186. }
  187. void __init ixp23xx_pci_preinit(void)
  188. {
  189. pcibios_min_io = 0;
  190. pcibios_min_mem = 0xe0000000;
  191. pci_set_flags(0);
  192. ixp23xx_pci_common_init();
  193. hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0,
  194. "PCI config cycle to non-existent device");
  195. *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
  196. }
  197. /*
  198. * Prevent PCI layer from seeing the inbound host-bridge resources
  199. */
  200. static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev)
  201. {
  202. int i;
  203. dev->class &= 0xff;
  204. dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
  205. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  206. dev->resource[i].start = 0;
  207. dev->resource[i].end = 0;
  208. dev->resource[i].flags = 0;
  209. }
  210. }
  211. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx);
  212. /*
  213. * IXP2300 systems often have large resource requirements, so we just
  214. * use our own resource space.
  215. */
  216. static struct resource ixp23xx_pci_mem_space = {
  217. .start = IXP23XX_PCI_MEM_START,
  218. .end = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1,
  219. .flags = IORESOURCE_MEM,
  220. .name = "PCI Mem Space"
  221. };
  222. static struct resource ixp23xx_pci_io_space = {
  223. .start = 0x00000100,
  224. .end = 0x01ffffff,
  225. .flags = IORESOURCE_IO,
  226. .name = "PCI I/O Space"
  227. };
  228. int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
  229. {
  230. if (nr >= 1)
  231. return 0;
  232. pci_add_resource(&sys->resources, &ixp23xx_pci_io_space);
  233. pci_add_resource(&sys->resources, &ixp23xx_pci_mem_space);
  234. return 1;
  235. }
  236. void __init ixp23xx_pci_slave_init(void)
  237. {
  238. ixp23xx_pci_common_init();
  239. }