dma.c 3.6 KB

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  1. /* linux/arch/arm/mach-exynos4/dma.c
  2. *
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  7. * Jaswinder Singh <jassi.brar@samsung.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/dma-mapping.h>
  24. #include <linux/amba/bus.h>
  25. #include <linux/amba/pl330.h>
  26. #include <linux/of.h>
  27. #include <asm/irq.h>
  28. #include <plat/devs.h>
  29. #include <plat/irqs.h>
  30. #include <mach/map.h>
  31. #include <mach/irqs.h>
  32. #include <mach/dma.h>
  33. static u64 dma_dmamask = DMA_BIT_MASK(32);
  34. u8 pdma0_peri[] = {
  35. DMACH_PCM0_RX,
  36. DMACH_PCM0_TX,
  37. DMACH_PCM2_RX,
  38. DMACH_PCM2_TX,
  39. DMACH_MSM_REQ0,
  40. DMACH_MSM_REQ2,
  41. DMACH_SPI0_RX,
  42. DMACH_SPI0_TX,
  43. DMACH_SPI2_RX,
  44. DMACH_SPI2_TX,
  45. DMACH_I2S0S_TX,
  46. DMACH_I2S0_RX,
  47. DMACH_I2S0_TX,
  48. DMACH_I2S2_RX,
  49. DMACH_I2S2_TX,
  50. DMACH_UART0_RX,
  51. DMACH_UART0_TX,
  52. DMACH_UART2_RX,
  53. DMACH_UART2_TX,
  54. DMACH_UART4_RX,
  55. DMACH_UART4_TX,
  56. DMACH_SLIMBUS0_RX,
  57. DMACH_SLIMBUS0_TX,
  58. DMACH_SLIMBUS2_RX,
  59. DMACH_SLIMBUS2_TX,
  60. DMACH_SLIMBUS4_RX,
  61. DMACH_SLIMBUS4_TX,
  62. DMACH_AC97_MICIN,
  63. DMACH_AC97_PCMIN,
  64. DMACH_AC97_PCMOUT,
  65. };
  66. struct dma_pl330_platdata exynos4_pdma0_pdata = {
  67. .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
  68. .peri_id = pdma0_peri,
  69. };
  70. struct amba_device exynos4_device_pdma0 = {
  71. .dev = {
  72. .init_name = "dma-pl330.0",
  73. .dma_mask = &dma_dmamask,
  74. .coherent_dma_mask = DMA_BIT_MASK(32),
  75. .platform_data = &exynos4_pdma0_pdata,
  76. },
  77. .res = {
  78. .start = EXYNOS4_PA_PDMA0,
  79. .end = EXYNOS4_PA_PDMA0 + SZ_4K,
  80. .flags = IORESOURCE_MEM,
  81. },
  82. .irq = {IRQ_PDMA0, NO_IRQ},
  83. .periphid = 0x00041330,
  84. };
  85. u8 pdma1_peri[] = {
  86. DMACH_PCM0_RX,
  87. DMACH_PCM0_TX,
  88. DMACH_PCM1_RX,
  89. DMACH_PCM1_TX,
  90. DMACH_MSM_REQ1,
  91. DMACH_MSM_REQ3,
  92. DMACH_SPI1_RX,
  93. DMACH_SPI1_TX,
  94. DMACH_I2S0S_TX,
  95. DMACH_I2S0_RX,
  96. DMACH_I2S0_TX,
  97. DMACH_I2S1_RX,
  98. DMACH_I2S1_TX,
  99. DMACH_UART0_RX,
  100. DMACH_UART0_TX,
  101. DMACH_UART1_RX,
  102. DMACH_UART1_TX,
  103. DMACH_UART3_RX,
  104. DMACH_UART3_TX,
  105. DMACH_SLIMBUS1_RX,
  106. DMACH_SLIMBUS1_TX,
  107. DMACH_SLIMBUS3_RX,
  108. DMACH_SLIMBUS3_TX,
  109. DMACH_SLIMBUS5_RX,
  110. DMACH_SLIMBUS5_TX,
  111. };
  112. struct dma_pl330_platdata exynos4_pdma1_pdata = {
  113. .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
  114. .peri_id = pdma1_peri,
  115. };
  116. struct amba_device exynos4_device_pdma1 = {
  117. .dev = {
  118. .init_name = "dma-pl330.1",
  119. .dma_mask = &dma_dmamask,
  120. .coherent_dma_mask = DMA_BIT_MASK(32),
  121. .platform_data = &exynos4_pdma1_pdata,
  122. },
  123. .res = {
  124. .start = EXYNOS4_PA_PDMA1,
  125. .end = EXYNOS4_PA_PDMA1 + SZ_4K,
  126. .flags = IORESOURCE_MEM,
  127. },
  128. .irq = {IRQ_PDMA1, NO_IRQ},
  129. .periphid = 0x00041330,
  130. };
  131. static int __init exynos4_dma_init(void)
  132. {
  133. if (of_have_populated_dt())
  134. return 0;
  135. dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
  136. dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
  137. amba_device_register(&exynos4_device_pdma0, &iomem_resource);
  138. dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
  139. dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
  140. amba_device_register(&exynos4_device_pdma1, &iomem_resource);
  141. return 0;
  142. }
  143. arch_initcall(exynos4_dma_init);