cg3.c 12 KB

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  1. /* cg3.c: CGTHREE frame buffer driver
  2. *
  3. * Copyright (C) 2003 David S. Miller (davem@redhat.com)
  4. * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
  5. * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
  6. * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
  7. *
  8. * Driver layout based loosely on tgafb.c, see that file for credits.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/errno.h>
  13. #include <linux/string.h>
  14. #include <linux/slab.h>
  15. #include <linux/delay.h>
  16. #include <linux/init.h>
  17. #include <linux/fb.h>
  18. #include <linux/mm.h>
  19. #include <asm/io.h>
  20. #include <asm/sbus.h>
  21. #include <asm/oplib.h>
  22. #include <asm/fbio.h>
  23. #include "sbuslib.h"
  24. /*
  25. * Local functions.
  26. */
  27. static int cg3_setcolreg(unsigned, unsigned, unsigned, unsigned,
  28. unsigned, struct fb_info *);
  29. static int cg3_blank(int, struct fb_info *);
  30. static int cg3_mmap(struct fb_info *, struct file *, struct vm_area_struct *);
  31. static int cg3_ioctl(struct inode *, struct file *, unsigned int,
  32. unsigned long, struct fb_info *);
  33. /*
  34. * Frame buffer operations
  35. */
  36. static struct fb_ops cg3_ops = {
  37. .owner = THIS_MODULE,
  38. .fb_setcolreg = cg3_setcolreg,
  39. .fb_blank = cg3_blank,
  40. .fb_fillrect = cfb_fillrect,
  41. .fb_copyarea = cfb_copyarea,
  42. .fb_imageblit = cfb_imageblit,
  43. .fb_mmap = cg3_mmap,
  44. .fb_ioctl = cg3_ioctl,
  45. };
  46. /* Control Register Constants */
  47. #define CG3_CR_ENABLE_INTS 0x80
  48. #define CG3_CR_ENABLE_VIDEO 0x40
  49. #define CG3_CR_ENABLE_TIMING 0x20
  50. #define CG3_CR_ENABLE_CURCMP 0x10
  51. #define CG3_CR_XTAL_MASK 0x0c
  52. #define CG3_CR_DIVISOR_MASK 0x03
  53. /* Status Register Constants */
  54. #define CG3_SR_PENDING_INT 0x80
  55. #define CG3_SR_RES_MASK 0x70
  56. #define CG3_SR_1152_900_76_A 0x40
  57. #define CG3_SR_1152_900_76_B 0x60
  58. #define CG3_SR_ID_MASK 0x0f
  59. #define CG3_SR_ID_COLOR 0x01
  60. #define CG3_SR_ID_MONO 0x02
  61. #define CG3_SR_ID_MONO_ECL 0x03
  62. enum cg3_type {
  63. CG3_AT_66HZ = 0,
  64. CG3_AT_76HZ,
  65. CG3_RDI
  66. };
  67. struct bt_regs {
  68. volatile u32 addr;
  69. volatile u32 color_map;
  70. volatile u32 control;
  71. volatile u32 cursor;
  72. };
  73. struct cg3_regs {
  74. struct bt_regs cmap;
  75. volatile u8 control;
  76. volatile u8 status;
  77. volatile u8 cursor_start;
  78. volatile u8 cursor_end;
  79. volatile u8 h_blank_start;
  80. volatile u8 h_blank_end;
  81. volatile u8 h_sync_start;
  82. volatile u8 h_sync_end;
  83. volatile u8 comp_sync_end;
  84. volatile u8 v_blank_start_high;
  85. volatile u8 v_blank_start_low;
  86. volatile u8 v_blank_end;
  87. volatile u8 v_sync_start;
  88. volatile u8 v_sync_end;
  89. volatile u8 xfer_holdoff_start;
  90. volatile u8 xfer_holdoff_end;
  91. };
  92. /* Offset of interesting structures in the OBIO space */
  93. #define CG3_REGS_OFFSET 0x400000UL
  94. #define CG3_RAM_OFFSET 0x800000UL
  95. struct cg3_par {
  96. spinlock_t lock;
  97. struct cg3_regs __iomem *regs;
  98. u32 sw_cmap[((256 * 3) + 3) / 4];
  99. u32 flags;
  100. #define CG3_FLAG_BLANKED 0x00000001
  101. #define CG3_FLAG_RDI 0x00000002
  102. unsigned long physbase;
  103. unsigned long fbsize;
  104. struct sbus_dev *sdev;
  105. struct list_head list;
  106. };
  107. /**
  108. * cg3_setcolreg - Optional function. Sets a color register.
  109. * @regno: boolean, 0 copy local, 1 get_user() function
  110. * @red: frame buffer colormap structure
  111. * @green: The green value which can be up to 16 bits wide
  112. * @blue: The blue value which can be up to 16 bits wide.
  113. * @transp: If supported the alpha value which can be up to 16 bits wide.
  114. * @info: frame buffer info structure
  115. *
  116. * The cg3 palette is loaded with 4 color values at each time
  117. * so you end up with: (rgb)(r), (gb)(rg), (b)(rgb), and so on.
  118. * We keep a sw copy of the hw cmap to assist us in this esoteric
  119. * loading procedure.
  120. */
  121. static int cg3_setcolreg(unsigned regno,
  122. unsigned red, unsigned green, unsigned blue,
  123. unsigned transp, struct fb_info *info)
  124. {
  125. struct cg3_par *par = (struct cg3_par *) info->par;
  126. struct bt_regs __iomem *bt = &par->regs->cmap;
  127. unsigned long flags;
  128. u32 *p32;
  129. u8 *p8;
  130. int count;
  131. if (regno >= 256)
  132. return 1;
  133. red >>= 8;
  134. green >>= 8;
  135. blue >>= 8;
  136. spin_lock_irqsave(&par->lock, flags);
  137. p8 = (u8 *)par->sw_cmap + (regno * 3);
  138. p8[0] = red;
  139. p8[1] = green;
  140. p8[2] = blue;
  141. #define D4M3(x) ((((x)>>2)<<1) + ((x)>>2)) /* (x/4)*3 */
  142. #define D4M4(x) ((x)&~0x3) /* (x/4)*4 */
  143. count = 3;
  144. p32 = &par->sw_cmap[D4M3(regno)];
  145. sbus_writel(D4M4(regno), &bt->addr);
  146. while (count--)
  147. sbus_writel(*p32++, &bt->color_map);
  148. #undef D4M3
  149. #undef D4M4
  150. spin_unlock_irqrestore(&par->lock, flags);
  151. return 0;
  152. }
  153. /**
  154. * cg3_blank - Optional function. Blanks the display.
  155. * @blank_mode: the blank mode we want.
  156. * @info: frame buffer structure that represents a single frame buffer
  157. */
  158. static int
  159. cg3_blank(int blank, struct fb_info *info)
  160. {
  161. struct cg3_par *par = (struct cg3_par *) info->par;
  162. struct cg3_regs __iomem *regs = par->regs;
  163. unsigned long flags;
  164. u8 val;
  165. spin_lock_irqsave(&par->lock, flags);
  166. switch (blank) {
  167. case FB_BLANK_UNBLANK: /* Unblanking */
  168. val = sbus_readb(&regs->control);
  169. val |= CG3_CR_ENABLE_VIDEO;
  170. sbus_writeb(val, &regs->control);
  171. par->flags &= ~CG3_FLAG_BLANKED;
  172. break;
  173. case FB_BLANK_NORMAL: /* Normal blanking */
  174. case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
  175. case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
  176. case FB_BLANK_POWERDOWN: /* Poweroff */
  177. val = sbus_readb(&regs->control);
  178. val &= ~CG3_CR_ENABLE_VIDEO;
  179. sbus_writeb(val, &regs->control);
  180. par->flags |= CG3_FLAG_BLANKED;
  181. break;
  182. }
  183. spin_unlock_irqrestore(&par->lock, flags);
  184. return 0;
  185. }
  186. static struct sbus_mmap_map cg3_mmap_map[] = {
  187. {
  188. .voff = CG3_MMAP_OFFSET,
  189. .poff = CG3_RAM_OFFSET,
  190. .size = SBUS_MMAP_FBSIZE(1)
  191. },
  192. { .size = 0 }
  193. };
  194. static int cg3_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
  195. {
  196. struct cg3_par *par = (struct cg3_par *)info->par;
  197. return sbusfb_mmap_helper(cg3_mmap_map,
  198. par->physbase, par->fbsize,
  199. par->sdev->reg_addrs[0].which_io,
  200. vma);
  201. }
  202. static int cg3_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
  203. unsigned long arg, struct fb_info *info)
  204. {
  205. struct cg3_par *par = (struct cg3_par *) info->par;
  206. return sbusfb_ioctl_helper(cmd, arg, info,
  207. FBTYPE_SUN3COLOR, 8, par->fbsize);
  208. }
  209. /*
  210. * Initialisation
  211. */
  212. static void
  213. cg3_init_fix(struct fb_info *info, int linebytes)
  214. {
  215. struct cg3_par *par = (struct cg3_par *)info->par;
  216. strlcpy(info->fix.id, par->sdev->prom_name, sizeof(info->fix.id));
  217. info->fix.type = FB_TYPE_PACKED_PIXELS;
  218. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  219. info->fix.line_length = linebytes;
  220. info->fix.accel = FB_ACCEL_SUN_CGTHREE;
  221. }
  222. static void cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var,
  223. struct sbus_dev *sdev)
  224. {
  225. char buffer[40];
  226. char *p;
  227. int ww, hh;
  228. *buffer = 0;
  229. prom_getstring(sdev->prom_node, "params", buffer, sizeof(buffer));
  230. if (*buffer) {
  231. ww = simple_strtoul(buffer, &p, 10);
  232. if (ww && *p == 'x') {
  233. hh = simple_strtoul(p + 1, &p, 10);
  234. if (hh && *p == '-') {
  235. if (var->xres != ww ||
  236. var->yres != hh) {
  237. var->xres = var->xres_virtual = ww;
  238. var->yres = var->yres_virtual = hh;
  239. }
  240. }
  241. }
  242. }
  243. }
  244. static u8 cg3regvals_66hz[] __initdata = { /* 1152 x 900, 66 Hz */
  245. 0x14, 0xbb, 0x15, 0x2b, 0x16, 0x04, 0x17, 0x14,
  246. 0x18, 0xae, 0x19, 0x03, 0x1a, 0xa8, 0x1b, 0x24,
  247. 0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01,
  248. 0x10, 0x20, 0
  249. };
  250. static u8 cg3regvals_76hz[] __initdata = { /* 1152 x 900, 76 Hz */
  251. 0x14, 0xb7, 0x15, 0x27, 0x16, 0x03, 0x17, 0x0f,
  252. 0x18, 0xae, 0x19, 0x03, 0x1a, 0xae, 0x1b, 0x2a,
  253. 0x1c, 0x01, 0x1d, 0x09, 0x1e, 0xff, 0x1f, 0x01,
  254. 0x10, 0x24, 0
  255. };
  256. static u8 cg3regvals_rdi[] __initdata = { /* 640 x 480, cgRDI */
  257. 0x14, 0x70, 0x15, 0x20, 0x16, 0x08, 0x17, 0x10,
  258. 0x18, 0x06, 0x19, 0x02, 0x1a, 0x31, 0x1b, 0x51,
  259. 0x1c, 0x06, 0x1d, 0x0c, 0x1e, 0xff, 0x1f, 0x01,
  260. 0x10, 0x22, 0
  261. };
  262. static u8 *cg3_regvals[] __initdata = {
  263. cg3regvals_66hz, cg3regvals_76hz, cg3regvals_rdi
  264. };
  265. static u_char cg3_dacvals[] __initdata = {
  266. 4, 0xff, 5, 0x00, 6, 0x70, 7, 0x00, 0
  267. };
  268. static void cg3_do_default_mode(struct cg3_par *par)
  269. {
  270. enum cg3_type type;
  271. u8 *p;
  272. if (par->flags & CG3_FLAG_RDI)
  273. type = CG3_RDI;
  274. else {
  275. u8 status = sbus_readb(&par->regs->status), mon;
  276. if ((status & CG3_SR_ID_MASK) == CG3_SR_ID_COLOR) {
  277. mon = status & CG3_SR_RES_MASK;
  278. if (mon == CG3_SR_1152_900_76_A ||
  279. mon == CG3_SR_1152_900_76_B)
  280. type = CG3_AT_76HZ;
  281. else
  282. type = CG3_AT_66HZ;
  283. } else {
  284. prom_printf("cgthree: can't handle SR %02x\n",
  285. status);
  286. prom_halt();
  287. return;
  288. }
  289. }
  290. for (p = cg3_regvals[type]; *p; p += 2) {
  291. u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]];
  292. sbus_writeb(p[1], regp);
  293. }
  294. for (p = cg3_dacvals; *p; p += 2) {
  295. volatile u8 __iomem *regp;
  296. regp = (volatile u8 __iomem *)&par->regs->cmap.addr;
  297. sbus_writeb(p[0], regp);
  298. regp = (volatile u8 __iomem *)&par->regs->cmap.control;
  299. sbus_writeb(p[1], regp);
  300. }
  301. }
  302. struct all_info {
  303. struct fb_info info;
  304. struct cg3_par par;
  305. struct list_head list;
  306. };
  307. static LIST_HEAD(cg3_list);
  308. static void cg3_init_one(struct sbus_dev *sdev)
  309. {
  310. struct all_info *all;
  311. int linebytes;
  312. all = kmalloc(sizeof(*all), GFP_KERNEL);
  313. if (!all) {
  314. printk(KERN_ERR "cg3: Cannot allocate memory.\n");
  315. return;
  316. }
  317. memset(all, 0, sizeof(*all));
  318. INIT_LIST_HEAD(&all->list);
  319. spin_lock_init(&all->par.lock);
  320. all->par.sdev = sdev;
  321. all->par.physbase = sdev->reg_addrs[0].phys_addr;
  322. sbusfb_fill_var(&all->info.var, sdev->prom_node, 8);
  323. all->info.var.red.length = 8;
  324. all->info.var.green.length = 8;
  325. all->info.var.blue.length = 8;
  326. if (!strcmp(sdev->prom_name, "cgRDI"))
  327. all->par.flags |= CG3_FLAG_RDI;
  328. if (all->par.flags & CG3_FLAG_RDI)
  329. cg3_rdi_maybe_fixup_var(&all->info.var, sdev);
  330. linebytes = prom_getintdefault(sdev->prom_node, "linebytes",
  331. all->info.var.xres);
  332. all->par.fbsize = PAGE_ALIGN(linebytes * all->info.var.yres);
  333. all->par.regs = sbus_ioremap(&sdev->resource[0], CG3_REGS_OFFSET,
  334. sizeof(struct cg3_regs), "cg3 regs");
  335. all->info.flags = FBINFO_DEFAULT;
  336. all->info.fbops = &cg3_ops;
  337. #ifdef CONFIG_SPARC32
  338. all->info.screen_base = (char __iomem *)
  339. prom_getintdefault(sdev->prom_node, "address", 0);
  340. #endif
  341. if (!all->info.screen_base)
  342. all->info.screen_base =
  343. sbus_ioremap(&sdev->resource[0], CG3_RAM_OFFSET,
  344. all->par.fbsize, "cg3 ram");
  345. all->info.par = &all->par;
  346. cg3_blank(0, &all->info);
  347. if (!prom_getbool(sdev->prom_node, "width"))
  348. cg3_do_default_mode(&all->par);
  349. if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
  350. printk(KERN_ERR "cg3: Could not allocate color map.\n");
  351. kfree(all);
  352. return;
  353. }
  354. fb_set_cmap(&all->info.cmap, &all->info);
  355. cg3_init_fix(&all->info, linebytes);
  356. if (register_framebuffer(&all->info) < 0) {
  357. printk(KERN_ERR "cg3: Could not register framebuffer.\n");
  358. fb_dealloc_cmap(&all->info.cmap);
  359. kfree(all);
  360. return;
  361. }
  362. list_add(&all->list, &cg3_list);
  363. printk("cg3: %s at %lx:%lx\n",
  364. sdev->prom_name,
  365. (long) sdev->reg_addrs[0].which_io,
  366. (long) sdev->reg_addrs[0].phys_addr);
  367. }
  368. int __init cg3_init(void)
  369. {
  370. struct sbus_bus *sbus;
  371. struct sbus_dev *sdev;
  372. if (fb_get_options("cg3fb", NULL))
  373. return -ENODEV;
  374. for_all_sbusdev(sdev, sbus) {
  375. if (!strcmp(sdev->prom_name, "cgthree") ||
  376. !strcmp(sdev->prom_name, "cgRDI"))
  377. cg3_init_one(sdev);
  378. }
  379. return 0;
  380. }
  381. void __exit cg3_exit(void)
  382. {
  383. struct list_head *pos, *tmp;
  384. list_for_each_safe(pos, tmp, &cg3_list) {
  385. struct all_info *all = list_entry(pos, typeof(*all), list);
  386. unregister_framebuffer(&all->info);
  387. fb_dealloc_cmap(&all->info.cmap);
  388. kfree(all);
  389. }
  390. }
  391. int __init
  392. cg3_setup(char *arg)
  393. {
  394. /* No cmdline options yet... */
  395. return 0;
  396. }
  397. module_init(cg3_init);
  398. #ifdef MODULE
  399. module_exit(cg3_exit);
  400. #endif
  401. MODULE_DESCRIPTION("framebuffer driver for CGthree chipsets");
  402. MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
  403. MODULE_LICENSE("GPL");