mthca_main.c 31 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/config.h>
  37. #include <linux/module.h>
  38. #include <linux/init.h>
  39. #include <linux/errno.h>
  40. #include <linux/pci.h>
  41. #include <linux/interrupt.h>
  42. #include "mthca_dev.h"
  43. #include "mthca_config_reg.h"
  44. #include "mthca_cmd.h"
  45. #include "mthca_profile.h"
  46. #include "mthca_memfree.h"
  47. MODULE_AUTHOR("Roland Dreier");
  48. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  49. MODULE_LICENSE("Dual BSD/GPL");
  50. MODULE_VERSION(DRV_VERSION);
  51. #ifdef CONFIG_PCI_MSI
  52. static int msi_x = 0;
  53. module_param(msi_x, int, 0444);
  54. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  55. static int msi = 0;
  56. module_param(msi, int, 0444);
  57. MODULE_PARM_DESC(msi, "attempt to use MSI if nonzero");
  58. #else /* CONFIG_PCI_MSI */
  59. #define msi_x (0)
  60. #define msi (0)
  61. #endif /* CONFIG_PCI_MSI */
  62. static const char mthca_version[] __devinitdata =
  63. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  64. DRV_VERSION " (" DRV_RELDATE ")\n";
  65. static struct mthca_profile default_profile = {
  66. .num_qp = 1 << 16,
  67. .rdb_per_qp = 4,
  68. .num_cq = 1 << 16,
  69. .num_mcg = 1 << 13,
  70. .num_mpt = 1 << 17,
  71. .num_mtt = 1 << 20,
  72. .num_udav = 1 << 15, /* Tavor only */
  73. .fmr_reserved_mtts = 1 << 18, /* Tavor only */
  74. .uarc_size = 1 << 18, /* Arbel only */
  75. };
  76. static int __devinit mthca_tune_pci(struct mthca_dev *mdev)
  77. {
  78. int cap;
  79. u16 val;
  80. /* First try to max out Read Byte Count */
  81. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
  82. if (cap) {
  83. if (pci_read_config_word(mdev->pdev, cap + PCI_X_CMD, &val)) {
  84. mthca_err(mdev, "Couldn't read PCI-X command register, "
  85. "aborting.\n");
  86. return -ENODEV;
  87. }
  88. val = (val & ~PCI_X_CMD_MAX_READ) | (3 << 2);
  89. if (pci_write_config_word(mdev->pdev, cap + PCI_X_CMD, val)) {
  90. mthca_err(mdev, "Couldn't write PCI-X command register, "
  91. "aborting.\n");
  92. return -ENODEV;
  93. }
  94. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  95. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  96. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP);
  97. if (cap) {
  98. if (pci_read_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, &val)) {
  99. mthca_err(mdev, "Couldn't read PCI Express device control "
  100. "register, aborting.\n");
  101. return -ENODEV;
  102. }
  103. val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
  104. if (pci_write_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, val)) {
  105. mthca_err(mdev, "Couldn't write PCI Express device control "
  106. "register, aborting.\n");
  107. return -ENODEV;
  108. }
  109. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  110. mthca_info(mdev, "No PCI Express capability, "
  111. "not setting Max Read Request Size.\n");
  112. return 0;
  113. }
  114. static int __devinit mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  115. {
  116. int err;
  117. u8 status;
  118. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  119. if (err) {
  120. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  121. return err;
  122. }
  123. if (status) {
  124. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  125. "aborting.\n", status);
  126. return -EINVAL;
  127. }
  128. if (dev_lim->min_page_sz > PAGE_SIZE) {
  129. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  130. "kernel PAGE_SIZE of %ld, aborting.\n",
  131. dev_lim->min_page_sz, PAGE_SIZE);
  132. return -ENODEV;
  133. }
  134. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  135. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  136. "aborting.\n",
  137. dev_lim->num_ports, MTHCA_MAX_PORTS);
  138. return -ENODEV;
  139. }
  140. mdev->limits.num_ports = dev_lim->num_ports;
  141. mdev->limits.vl_cap = dev_lim->max_vl;
  142. mdev->limits.mtu_cap = dev_lim->max_mtu;
  143. mdev->limits.gid_table_len = dev_lim->max_gids;
  144. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  145. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  146. mdev->limits.max_sg = dev_lim->max_sg;
  147. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  148. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  149. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  150. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  151. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  152. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  153. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  154. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  155. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  156. mdev->limits.port_width_cap = dev_lim->max_port_width;
  157. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  158. May be doable since hardware supports it for SRQ.
  159. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  160. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  161. supported by driver. */
  162. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  163. IB_DEVICE_PORT_ACTIVE_EVENT |
  164. IB_DEVICE_SYS_IMAGE_GUID |
  165. IB_DEVICE_RC_RNR_NAK_GEN;
  166. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  167. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  168. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  169. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  170. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  171. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  172. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  173. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  174. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  175. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  176. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  177. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  178. return 0;
  179. }
  180. static int __devinit mthca_init_tavor(struct mthca_dev *mdev)
  181. {
  182. u8 status;
  183. int err;
  184. struct mthca_dev_lim dev_lim;
  185. struct mthca_profile profile;
  186. struct mthca_init_hca_param init_hca;
  187. err = mthca_SYS_EN(mdev, &status);
  188. if (err) {
  189. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  190. return err;
  191. }
  192. if (status) {
  193. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  194. "aborting.\n", status);
  195. return -EINVAL;
  196. }
  197. err = mthca_QUERY_FW(mdev, &status);
  198. if (err) {
  199. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  200. goto err_disable;
  201. }
  202. if (status) {
  203. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  204. "aborting.\n", status);
  205. err = -EINVAL;
  206. goto err_disable;
  207. }
  208. err = mthca_QUERY_DDR(mdev, &status);
  209. if (err) {
  210. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  211. goto err_disable;
  212. }
  213. if (status) {
  214. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  215. "aborting.\n", status);
  216. err = -EINVAL;
  217. goto err_disable;
  218. }
  219. err = mthca_dev_lim(mdev, &dev_lim);
  220. profile = default_profile;
  221. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  222. profile.uarc_size = 0;
  223. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  224. profile.num_srq = dev_lim.max_srqs;
  225. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  226. if (err < 0)
  227. goto err_disable;
  228. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  229. if (err) {
  230. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  231. goto err_disable;
  232. }
  233. if (status) {
  234. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  235. "aborting.\n", status);
  236. err = -EINVAL;
  237. goto err_disable;
  238. }
  239. return 0;
  240. err_disable:
  241. mthca_SYS_DIS(mdev, &status);
  242. return err;
  243. }
  244. static int __devinit mthca_load_fw(struct mthca_dev *mdev)
  245. {
  246. u8 status;
  247. int err;
  248. /* FIXME: use HCA-attached memory for FW if present */
  249. mdev->fw.arbel.fw_icm =
  250. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  251. GFP_HIGHUSER | __GFP_NOWARN);
  252. if (!mdev->fw.arbel.fw_icm) {
  253. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  254. return -ENOMEM;
  255. }
  256. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  257. if (err) {
  258. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  259. goto err_free;
  260. }
  261. if (status) {
  262. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  263. err = -EINVAL;
  264. goto err_free;
  265. }
  266. err = mthca_RUN_FW(mdev, &status);
  267. if (err) {
  268. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  269. goto err_unmap_fa;
  270. }
  271. if (status) {
  272. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  273. err = -EINVAL;
  274. goto err_unmap_fa;
  275. }
  276. return 0;
  277. err_unmap_fa:
  278. mthca_UNMAP_FA(mdev, &status);
  279. err_free:
  280. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  281. return err;
  282. }
  283. static int __devinit mthca_init_icm(struct mthca_dev *mdev,
  284. struct mthca_dev_lim *dev_lim,
  285. struct mthca_init_hca_param *init_hca,
  286. u64 icm_size)
  287. {
  288. u64 aux_pages;
  289. u8 status;
  290. int err;
  291. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  292. if (err) {
  293. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  294. return err;
  295. }
  296. if (status) {
  297. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  298. "aborting.\n", status);
  299. return -EINVAL;
  300. }
  301. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  302. (unsigned long long) icm_size >> 10,
  303. (unsigned long long) aux_pages << 2);
  304. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  305. GFP_HIGHUSER | __GFP_NOWARN);
  306. if (!mdev->fw.arbel.aux_icm) {
  307. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  308. return -ENOMEM;
  309. }
  310. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  311. if (err) {
  312. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  313. goto err_free_aux;
  314. }
  315. if (status) {
  316. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  317. err = -EINVAL;
  318. goto err_free_aux;
  319. }
  320. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  321. if (err) {
  322. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  323. goto err_unmap_aux;
  324. }
  325. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  326. MTHCA_MTT_SEG_SIZE,
  327. mdev->limits.num_mtt_segs,
  328. mdev->limits.reserved_mtts, 1);
  329. if (!mdev->mr_table.mtt_table) {
  330. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  331. err = -ENOMEM;
  332. goto err_unmap_eq;
  333. }
  334. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  335. dev_lim->mpt_entry_sz,
  336. mdev->limits.num_mpts,
  337. mdev->limits.reserved_mrws, 1);
  338. if (!mdev->mr_table.mpt_table) {
  339. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  340. err = -ENOMEM;
  341. goto err_unmap_mtt;
  342. }
  343. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  344. dev_lim->qpc_entry_sz,
  345. mdev->limits.num_qps,
  346. mdev->limits.reserved_qps, 0);
  347. if (!mdev->qp_table.qp_table) {
  348. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  349. err = -ENOMEM;
  350. goto err_unmap_mpt;
  351. }
  352. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  353. dev_lim->eqpc_entry_sz,
  354. mdev->limits.num_qps,
  355. mdev->limits.reserved_qps, 0);
  356. if (!mdev->qp_table.eqp_table) {
  357. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  358. err = -ENOMEM;
  359. goto err_unmap_qp;
  360. }
  361. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  362. MTHCA_RDB_ENTRY_SIZE,
  363. mdev->limits.num_qps <<
  364. mdev->qp_table.rdb_shift,
  365. 0, 0);
  366. if (!mdev->qp_table.rdb_table) {
  367. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  368. err = -ENOMEM;
  369. goto err_unmap_eqp;
  370. }
  371. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  372. dev_lim->cqc_entry_sz,
  373. mdev->limits.num_cqs,
  374. mdev->limits.reserved_cqs, 0);
  375. if (!mdev->cq_table.table) {
  376. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  377. err = -ENOMEM;
  378. goto err_unmap_rdb;
  379. }
  380. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  381. mdev->srq_table.table =
  382. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  383. dev_lim->srq_entry_sz,
  384. mdev->limits.num_srqs,
  385. mdev->limits.reserved_srqs, 0);
  386. if (!mdev->srq_table.table) {
  387. mthca_err(mdev, "Failed to map SRQ context memory, "
  388. "aborting.\n");
  389. err = -ENOMEM;
  390. goto err_unmap_cq;
  391. }
  392. }
  393. /*
  394. * It's not strictly required, but for simplicity just map the
  395. * whole multicast group table now. The table isn't very big
  396. * and it's a lot easier than trying to track ref counts.
  397. */
  398. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  399. MTHCA_MGM_ENTRY_SIZE,
  400. mdev->limits.num_mgms +
  401. mdev->limits.num_amgms,
  402. mdev->limits.num_mgms +
  403. mdev->limits.num_amgms,
  404. 0);
  405. if (!mdev->mcg_table.table) {
  406. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  407. err = -ENOMEM;
  408. goto err_unmap_srq;
  409. }
  410. return 0;
  411. err_unmap_srq:
  412. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  413. mthca_free_icm_table(mdev, mdev->srq_table.table);
  414. err_unmap_cq:
  415. mthca_free_icm_table(mdev, mdev->cq_table.table);
  416. err_unmap_rdb:
  417. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  418. err_unmap_eqp:
  419. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  420. err_unmap_qp:
  421. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  422. err_unmap_mpt:
  423. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  424. err_unmap_mtt:
  425. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  426. err_unmap_eq:
  427. mthca_unmap_eq_icm(mdev);
  428. err_unmap_aux:
  429. mthca_UNMAP_ICM_AUX(mdev, &status);
  430. err_free_aux:
  431. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  432. return err;
  433. }
  434. static void mthca_free_icms(struct mthca_dev *mdev)
  435. {
  436. u8 status;
  437. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  438. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  439. mthca_free_icm_table(mdev, mdev->srq_table.table);
  440. mthca_free_icm_table(mdev, mdev->cq_table.table);
  441. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  442. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  443. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  444. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  445. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  446. mthca_unmap_eq_icm(mdev);
  447. mthca_UNMAP_ICM_AUX(mdev, &status);
  448. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  449. }
  450. static int __devinit mthca_init_arbel(struct mthca_dev *mdev)
  451. {
  452. struct mthca_dev_lim dev_lim;
  453. struct mthca_profile profile;
  454. struct mthca_init_hca_param init_hca;
  455. u64 icm_size;
  456. u8 status;
  457. int err;
  458. err = mthca_QUERY_FW(mdev, &status);
  459. if (err) {
  460. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  461. return err;
  462. }
  463. if (status) {
  464. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  465. "aborting.\n", status);
  466. return -EINVAL;
  467. }
  468. err = mthca_ENABLE_LAM(mdev, &status);
  469. if (err) {
  470. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  471. return err;
  472. }
  473. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  474. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  475. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  476. } else if (status) {
  477. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  478. "aborting.\n", status);
  479. return -EINVAL;
  480. }
  481. err = mthca_load_fw(mdev);
  482. if (err) {
  483. mthca_err(mdev, "Failed to start FW, aborting.\n");
  484. goto err_disable;
  485. }
  486. err = mthca_dev_lim(mdev, &dev_lim);
  487. if (err) {
  488. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  489. goto err_stop_fw;
  490. }
  491. profile = default_profile;
  492. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  493. profile.num_udav = 0;
  494. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  495. profile.num_srq = dev_lim.max_srqs;
  496. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  497. if ((int) icm_size < 0) {
  498. err = icm_size;
  499. goto err_stop_fw;
  500. }
  501. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  502. if (err)
  503. goto err_stop_fw;
  504. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  505. if (err) {
  506. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  507. goto err_free_icm;
  508. }
  509. if (status) {
  510. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  511. "aborting.\n", status);
  512. err = -EINVAL;
  513. goto err_free_icm;
  514. }
  515. return 0;
  516. err_free_icm:
  517. mthca_free_icms(mdev);
  518. err_stop_fw:
  519. mthca_UNMAP_FA(mdev, &status);
  520. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  521. err_disable:
  522. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  523. mthca_DISABLE_LAM(mdev, &status);
  524. return err;
  525. }
  526. static void mthca_close_hca(struct mthca_dev *mdev)
  527. {
  528. u8 status;
  529. mthca_CLOSE_HCA(mdev, 0, &status);
  530. if (mthca_is_memfree(mdev)) {
  531. mthca_free_icms(mdev);
  532. mthca_UNMAP_FA(mdev, &status);
  533. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  534. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  535. mthca_DISABLE_LAM(mdev, &status);
  536. } else
  537. mthca_SYS_DIS(mdev, &status);
  538. }
  539. static int __devinit mthca_init_hca(struct mthca_dev *mdev)
  540. {
  541. u8 status;
  542. int err;
  543. struct mthca_adapter adapter;
  544. if (mthca_is_memfree(mdev))
  545. err = mthca_init_arbel(mdev);
  546. else
  547. err = mthca_init_tavor(mdev);
  548. if (err)
  549. return err;
  550. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  551. if (err) {
  552. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  553. goto err_close;
  554. }
  555. if (status) {
  556. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  557. "aborting.\n", status);
  558. err = -EINVAL;
  559. goto err_close;
  560. }
  561. mdev->eq_table.inta_pin = adapter.inta_pin;
  562. mdev->rev_id = adapter.revision_id;
  563. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  564. return 0;
  565. err_close:
  566. mthca_close_hca(mdev);
  567. return err;
  568. }
  569. static int __devinit mthca_setup_hca(struct mthca_dev *dev)
  570. {
  571. int err;
  572. u8 status;
  573. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  574. err = mthca_init_uar_table(dev);
  575. if (err) {
  576. mthca_err(dev, "Failed to initialize "
  577. "user access region table, aborting.\n");
  578. return err;
  579. }
  580. err = mthca_uar_alloc(dev, &dev->driver_uar);
  581. if (err) {
  582. mthca_err(dev, "Failed to allocate driver access region, "
  583. "aborting.\n");
  584. goto err_uar_table_free;
  585. }
  586. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  587. if (!dev->kar) {
  588. mthca_err(dev, "Couldn't map kernel access region, "
  589. "aborting.\n");
  590. err = -ENOMEM;
  591. goto err_uar_free;
  592. }
  593. err = mthca_init_pd_table(dev);
  594. if (err) {
  595. mthca_err(dev, "Failed to initialize "
  596. "protection domain table, aborting.\n");
  597. goto err_kar_unmap;
  598. }
  599. err = mthca_init_mr_table(dev);
  600. if (err) {
  601. mthca_err(dev, "Failed to initialize "
  602. "memory region table, aborting.\n");
  603. goto err_pd_table_free;
  604. }
  605. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  606. if (err) {
  607. mthca_err(dev, "Failed to create driver PD, "
  608. "aborting.\n");
  609. goto err_mr_table_free;
  610. }
  611. err = mthca_init_eq_table(dev);
  612. if (err) {
  613. mthca_err(dev, "Failed to initialize "
  614. "event queue table, aborting.\n");
  615. goto err_pd_free;
  616. }
  617. err = mthca_cmd_use_events(dev);
  618. if (err) {
  619. mthca_err(dev, "Failed to switch to event-driven "
  620. "firmware commands, aborting.\n");
  621. goto err_eq_table_free;
  622. }
  623. err = mthca_NOP(dev, &status);
  624. if (err || status) {
  625. mthca_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting.\n",
  626. dev->mthca_flags & MTHCA_FLAG_MSI_X ?
  627. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector :
  628. dev->pdev->irq);
  629. if (dev->mthca_flags & (MTHCA_FLAG_MSI | MTHCA_FLAG_MSI_X))
  630. mthca_err(dev, "Try again with MSI/MSI-X disabled.\n");
  631. else
  632. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  633. goto err_cmd_poll;
  634. }
  635. mthca_dbg(dev, "NOP command IRQ test passed\n");
  636. err = mthca_init_cq_table(dev);
  637. if (err) {
  638. mthca_err(dev, "Failed to initialize "
  639. "completion queue table, aborting.\n");
  640. goto err_cmd_poll;
  641. }
  642. err = mthca_init_srq_table(dev);
  643. if (err) {
  644. mthca_err(dev, "Failed to initialize "
  645. "shared receive queue table, aborting.\n");
  646. goto err_cq_table_free;
  647. }
  648. err = mthca_init_qp_table(dev);
  649. if (err) {
  650. mthca_err(dev, "Failed to initialize "
  651. "queue pair table, aborting.\n");
  652. goto err_srq_table_free;
  653. }
  654. err = mthca_init_av_table(dev);
  655. if (err) {
  656. mthca_err(dev, "Failed to initialize "
  657. "address vector table, aborting.\n");
  658. goto err_qp_table_free;
  659. }
  660. err = mthca_init_mcg_table(dev);
  661. if (err) {
  662. mthca_err(dev, "Failed to initialize "
  663. "multicast group table, aborting.\n");
  664. goto err_av_table_free;
  665. }
  666. return 0;
  667. err_av_table_free:
  668. mthca_cleanup_av_table(dev);
  669. err_qp_table_free:
  670. mthca_cleanup_qp_table(dev);
  671. err_srq_table_free:
  672. mthca_cleanup_srq_table(dev);
  673. err_cq_table_free:
  674. mthca_cleanup_cq_table(dev);
  675. err_cmd_poll:
  676. mthca_cmd_use_polling(dev);
  677. err_eq_table_free:
  678. mthca_cleanup_eq_table(dev);
  679. err_pd_free:
  680. mthca_pd_free(dev, &dev->driver_pd);
  681. err_mr_table_free:
  682. mthca_cleanup_mr_table(dev);
  683. err_pd_table_free:
  684. mthca_cleanup_pd_table(dev);
  685. err_kar_unmap:
  686. iounmap(dev->kar);
  687. err_uar_free:
  688. mthca_uar_free(dev, &dev->driver_uar);
  689. err_uar_table_free:
  690. mthca_cleanup_uar_table(dev);
  691. return err;
  692. }
  693. static int __devinit mthca_request_regions(struct pci_dev *pdev,
  694. int ddr_hidden)
  695. {
  696. int err;
  697. /*
  698. * We can't just use pci_request_regions() because the MSI-X
  699. * table is right in the middle of the first BAR. If we did
  700. * pci_request_region and grab all of the first BAR, then
  701. * setting up MSI-X would fail, since the PCI core wants to do
  702. * request_mem_region on the MSI-X vector table.
  703. *
  704. * So just request what we need right now, and request any
  705. * other regions we need when setting up EQs.
  706. */
  707. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  708. MTHCA_HCR_SIZE, DRV_NAME))
  709. return -EBUSY;
  710. err = pci_request_region(pdev, 2, DRV_NAME);
  711. if (err)
  712. goto err_bar2_failed;
  713. if (!ddr_hidden) {
  714. err = pci_request_region(pdev, 4, DRV_NAME);
  715. if (err)
  716. goto err_bar4_failed;
  717. }
  718. return 0;
  719. err_bar4_failed:
  720. pci_release_region(pdev, 2);
  721. err_bar2_failed:
  722. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  723. MTHCA_HCR_SIZE);
  724. return err;
  725. }
  726. static void mthca_release_regions(struct pci_dev *pdev,
  727. int ddr_hidden)
  728. {
  729. if (!ddr_hidden)
  730. pci_release_region(pdev, 4);
  731. pci_release_region(pdev, 2);
  732. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  733. MTHCA_HCR_SIZE);
  734. }
  735. static int __devinit mthca_enable_msi_x(struct mthca_dev *mdev)
  736. {
  737. struct msix_entry entries[3];
  738. int err;
  739. entries[0].entry = 0;
  740. entries[1].entry = 1;
  741. entries[2].entry = 2;
  742. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  743. if (err) {
  744. if (err > 0)
  745. mthca_info(mdev, "Only %d MSI-X vectors available, "
  746. "not using MSI-X\n", err);
  747. return err;
  748. }
  749. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  750. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  751. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  752. return 0;
  753. }
  754. /* Types of supported HCA */
  755. enum {
  756. TAVOR, /* MT23108 */
  757. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  758. ARBEL_NATIVE, /* MT25208 with extended features */
  759. SINAI /* MT25204 */
  760. };
  761. #define MTHCA_FW_VER(major, minor, subminor) \
  762. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  763. static struct {
  764. u64 latest_fw;
  765. int is_memfree;
  766. int is_pcie;
  767. } mthca_hca_table[] = {
  768. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 3, 3), .is_memfree = 0, .is_pcie = 0 },
  769. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 0), .is_memfree = 0, .is_pcie = 1 },
  770. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 0), .is_memfree = 1, .is_pcie = 1 },
  771. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 0, 1), .is_memfree = 1, .is_pcie = 1 }
  772. };
  773. static int __devinit mthca_init_one(struct pci_dev *pdev,
  774. const struct pci_device_id *id)
  775. {
  776. static int mthca_version_printed = 0;
  777. int ddr_hidden = 0;
  778. int err;
  779. struct mthca_dev *mdev;
  780. if (!mthca_version_printed) {
  781. printk(KERN_INFO "%s", mthca_version);
  782. ++mthca_version_printed;
  783. }
  784. printk(KERN_INFO PFX "Initializing %s\n",
  785. pci_name(pdev));
  786. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  787. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  788. pci_name(pdev), id->driver_data);
  789. return -ENODEV;
  790. }
  791. err = pci_enable_device(pdev);
  792. if (err) {
  793. dev_err(&pdev->dev, "Cannot enable PCI device, "
  794. "aborting.\n");
  795. return err;
  796. }
  797. /*
  798. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  799. * be present)
  800. */
  801. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  802. pci_resource_len(pdev, 0) != 1 << 20) {
  803. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  804. err = -ENODEV;
  805. goto err_disable_pdev;
  806. }
  807. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM) ||
  808. pci_resource_len(pdev, 2) != 1 << 23) {
  809. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  810. err = -ENODEV;
  811. goto err_disable_pdev;
  812. }
  813. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  814. ddr_hidden = 1;
  815. err = mthca_request_regions(pdev, ddr_hidden);
  816. if (err) {
  817. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  818. "aborting.\n");
  819. goto err_disable_pdev;
  820. }
  821. pci_set_master(pdev);
  822. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  823. if (err) {
  824. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  825. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  826. if (err) {
  827. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  828. goto err_free_res;
  829. }
  830. }
  831. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  832. if (err) {
  833. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  834. "consistent PCI DMA mask.\n");
  835. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  836. if (err) {
  837. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  838. "aborting.\n");
  839. goto err_free_res;
  840. }
  841. }
  842. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  843. if (!mdev) {
  844. dev_err(&pdev->dev, "Device struct alloc failed, "
  845. "aborting.\n");
  846. err = -ENOMEM;
  847. goto err_free_res;
  848. }
  849. mdev->pdev = pdev;
  850. if (ddr_hidden)
  851. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  852. if (mthca_hca_table[id->driver_data].is_memfree)
  853. mdev->mthca_flags |= MTHCA_FLAG_MEMFREE;
  854. if (mthca_hca_table[id->driver_data].is_pcie)
  855. mdev->mthca_flags |= MTHCA_FLAG_PCIE;
  856. /*
  857. * Now reset the HCA before we touch the PCI capabilities or
  858. * attempt a firmware command, since a boot ROM may have left
  859. * the HCA in an undefined state.
  860. */
  861. err = mthca_reset(mdev);
  862. if (err) {
  863. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  864. goto err_free_dev;
  865. }
  866. if (msi_x && !mthca_enable_msi_x(mdev))
  867. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  868. if (msi && !(mdev->mthca_flags & MTHCA_FLAG_MSI_X) &&
  869. !pci_enable_msi(pdev))
  870. mdev->mthca_flags |= MTHCA_FLAG_MSI;
  871. if (mthca_cmd_init(mdev)) {
  872. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  873. goto err_free_dev;
  874. }
  875. err = mthca_tune_pci(mdev);
  876. if (err)
  877. goto err_cmd;
  878. err = mthca_init_hca(mdev);
  879. if (err)
  880. goto err_cmd;
  881. if (mdev->fw_ver < mthca_hca_table[id->driver_data].latest_fw) {
  882. mthca_warn(mdev, "HCA FW version %x.%x.%x is old (%x.%x.%x is current).\n",
  883. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  884. (int) (mdev->fw_ver & 0xffff),
  885. (int) (mthca_hca_table[id->driver_data].latest_fw >> 32),
  886. (int) (mthca_hca_table[id->driver_data].latest_fw >> 16) & 0xffff,
  887. (int) (mthca_hca_table[id->driver_data].latest_fw & 0xffff));
  888. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  889. }
  890. err = mthca_setup_hca(mdev);
  891. if (err)
  892. goto err_close;
  893. err = mthca_register_device(mdev);
  894. if (err)
  895. goto err_cleanup;
  896. err = mthca_create_agents(mdev);
  897. if (err)
  898. goto err_unregister;
  899. pci_set_drvdata(pdev, mdev);
  900. return 0;
  901. err_unregister:
  902. mthca_unregister_device(mdev);
  903. err_cleanup:
  904. mthca_cleanup_mcg_table(mdev);
  905. mthca_cleanup_av_table(mdev);
  906. mthca_cleanup_qp_table(mdev);
  907. mthca_cleanup_srq_table(mdev);
  908. mthca_cleanup_cq_table(mdev);
  909. mthca_cmd_use_polling(mdev);
  910. mthca_cleanup_eq_table(mdev);
  911. mthca_pd_free(mdev, &mdev->driver_pd);
  912. mthca_cleanup_mr_table(mdev);
  913. mthca_cleanup_pd_table(mdev);
  914. mthca_cleanup_uar_table(mdev);
  915. err_close:
  916. mthca_close_hca(mdev);
  917. err_cmd:
  918. mthca_cmd_cleanup(mdev);
  919. err_free_dev:
  920. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  921. pci_disable_msix(pdev);
  922. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  923. pci_disable_msi(pdev);
  924. ib_dealloc_device(&mdev->ib_dev);
  925. err_free_res:
  926. mthca_release_regions(pdev, ddr_hidden);
  927. err_disable_pdev:
  928. pci_disable_device(pdev);
  929. pci_set_drvdata(pdev, NULL);
  930. return err;
  931. }
  932. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  933. {
  934. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  935. u8 status;
  936. int p;
  937. if (mdev) {
  938. mthca_free_agents(mdev);
  939. mthca_unregister_device(mdev);
  940. for (p = 1; p <= mdev->limits.num_ports; ++p)
  941. mthca_CLOSE_IB(mdev, p, &status);
  942. mthca_cleanup_mcg_table(mdev);
  943. mthca_cleanup_av_table(mdev);
  944. mthca_cleanup_qp_table(mdev);
  945. mthca_cleanup_srq_table(mdev);
  946. mthca_cleanup_cq_table(mdev);
  947. mthca_cmd_use_polling(mdev);
  948. mthca_cleanup_eq_table(mdev);
  949. mthca_pd_free(mdev, &mdev->driver_pd);
  950. mthca_cleanup_mr_table(mdev);
  951. mthca_cleanup_pd_table(mdev);
  952. iounmap(mdev->kar);
  953. mthca_uar_free(mdev, &mdev->driver_uar);
  954. mthca_cleanup_uar_table(mdev);
  955. mthca_close_hca(mdev);
  956. mthca_cmd_cleanup(mdev);
  957. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  958. pci_disable_msix(pdev);
  959. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  960. pci_disable_msi(pdev);
  961. ib_dealloc_device(&mdev->ib_dev);
  962. mthca_release_regions(pdev, mdev->mthca_flags &
  963. MTHCA_FLAG_DDR_HIDDEN);
  964. pci_disable_device(pdev);
  965. pci_set_drvdata(pdev, NULL);
  966. }
  967. }
  968. static struct pci_device_id mthca_pci_table[] = {
  969. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  970. .driver_data = TAVOR },
  971. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  972. .driver_data = TAVOR },
  973. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  974. .driver_data = ARBEL_COMPAT },
  975. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  976. .driver_data = ARBEL_COMPAT },
  977. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  978. .driver_data = ARBEL_NATIVE },
  979. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  980. .driver_data = ARBEL_NATIVE },
  981. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  982. .driver_data = SINAI },
  983. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  984. .driver_data = SINAI },
  985. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  986. .driver_data = SINAI },
  987. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  988. .driver_data = SINAI },
  989. { 0, }
  990. };
  991. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  992. static struct pci_driver mthca_driver = {
  993. .name = DRV_NAME,
  994. .id_table = mthca_pci_table,
  995. .probe = mthca_init_one,
  996. .remove = __devexit_p(mthca_remove_one)
  997. };
  998. static int __init mthca_init(void)
  999. {
  1000. int ret;
  1001. ret = pci_register_driver(&mthca_driver);
  1002. return ret < 0 ? ret : 0;
  1003. }
  1004. static void __exit mthca_cleanup(void)
  1005. {
  1006. pci_unregister_driver(&mthca_driver);
  1007. }
  1008. module_init(mthca_init);
  1009. module_exit(mthca_cleanup);