suspend.c 6.6 KB

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  1. /*
  2. * Suspend support specific for i386.
  3. *
  4. * Distribute under GPLv2
  5. *
  6. * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
  7. * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
  8. */
  9. #include <linux/config.h>
  10. #include <linux/smp.h>
  11. #include <linux/suspend.h>
  12. #include <asm/proto.h>
  13. #include <asm/page.h>
  14. #include <asm/pgtable.h>
  15. struct saved_context saved_context;
  16. unsigned long saved_context_eax, saved_context_ebx, saved_context_ecx, saved_context_edx;
  17. unsigned long saved_context_esp, saved_context_ebp, saved_context_esi, saved_context_edi;
  18. unsigned long saved_context_r08, saved_context_r09, saved_context_r10, saved_context_r11;
  19. unsigned long saved_context_r12, saved_context_r13, saved_context_r14, saved_context_r15;
  20. unsigned long saved_context_eflags;
  21. void __save_processor_state(struct saved_context *ctxt)
  22. {
  23. kernel_fpu_begin();
  24. /*
  25. * descriptor tables
  26. */
  27. asm volatile ("sgdt %0" : "=m" (ctxt->gdt_limit));
  28. asm volatile ("sidt %0" : "=m" (ctxt->idt_limit));
  29. asm volatile ("str %0" : "=m" (ctxt->tr));
  30. /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
  31. /* EFER should be constant for kernel version, no need to handle it. */
  32. /*
  33. * segment registers
  34. */
  35. asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
  36. asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
  37. asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
  38. asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
  39. asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
  40. rdmsrl(MSR_FS_BASE, ctxt->fs_base);
  41. rdmsrl(MSR_GS_BASE, ctxt->gs_base);
  42. rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
  43. /*
  44. * control registers
  45. */
  46. asm volatile ("movq %%cr0, %0" : "=r" (ctxt->cr0));
  47. asm volatile ("movq %%cr2, %0" : "=r" (ctxt->cr2));
  48. asm volatile ("movq %%cr3, %0" : "=r" (ctxt->cr3));
  49. asm volatile ("movq %%cr4, %0" : "=r" (ctxt->cr4));
  50. asm volatile ("movq %%cr8, %0" : "=r" (ctxt->cr8));
  51. }
  52. void save_processor_state(void)
  53. {
  54. __save_processor_state(&saved_context);
  55. }
  56. static void
  57. do_fpu_end(void)
  58. {
  59. /* restore FPU regs if necessary */
  60. /* Do it out of line so that gcc does not move cr0 load to some stupid place */
  61. kernel_fpu_end();
  62. mxcsr_feature_mask_init();
  63. }
  64. void __restore_processor_state(struct saved_context *ctxt)
  65. {
  66. /*
  67. * control registers
  68. */
  69. asm volatile ("movq %0, %%cr8" :: "r" (ctxt->cr8));
  70. asm volatile ("movq %0, %%cr4" :: "r" (ctxt->cr4));
  71. asm volatile ("movq %0, %%cr3" :: "r" (ctxt->cr3));
  72. asm volatile ("movq %0, %%cr2" :: "r" (ctxt->cr2));
  73. asm volatile ("movq %0, %%cr0" :: "r" (ctxt->cr0));
  74. /*
  75. * now restore the descriptor tables to their proper values
  76. * ltr is done i fix_processor_context().
  77. */
  78. asm volatile ("lgdt %0" :: "m" (ctxt->gdt_limit));
  79. asm volatile ("lidt %0" :: "m" (ctxt->idt_limit));
  80. /*
  81. * segment registers
  82. */
  83. asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
  84. asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
  85. asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
  86. load_gs_index(ctxt->gs);
  87. asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
  88. wrmsrl(MSR_FS_BASE, ctxt->fs_base);
  89. wrmsrl(MSR_GS_BASE, ctxt->gs_base);
  90. wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
  91. fix_processor_context();
  92. do_fpu_end();
  93. mtrr_ap_init();
  94. }
  95. void restore_processor_state(void)
  96. {
  97. __restore_processor_state(&saved_context);
  98. }
  99. void fix_processor_context(void)
  100. {
  101. int cpu = smp_processor_id();
  102. struct tss_struct *t = &per_cpu(init_tss, cpu);
  103. set_tss_desc(cpu,t); /* This just modifies memory; should not be neccessary. But... This is neccessary, because 386 hardware has concept of busy TSS or some similar stupidity. */
  104. cpu_gdt_table[cpu][GDT_ENTRY_TSS].type = 9;
  105. syscall_init(); /* This sets MSR_*STAR and related */
  106. load_TR_desc(); /* This does ltr */
  107. load_LDT(&current->active_mm->context); /* This does lldt */
  108. /*
  109. * Now maybe reload the debug registers
  110. */
  111. if (current->thread.debugreg7){
  112. loaddebug(&current->thread, 0);
  113. loaddebug(&current->thread, 1);
  114. loaddebug(&current->thread, 2);
  115. loaddebug(&current->thread, 3);
  116. /* no 4 and 5 */
  117. loaddebug(&current->thread, 6);
  118. loaddebug(&current->thread, 7);
  119. }
  120. }
  121. #ifdef CONFIG_SOFTWARE_SUSPEND
  122. /* Defined in arch/x86_64/kernel/suspend_asm.S */
  123. extern int restore_image(void);
  124. pgd_t *temp_level4_pgt;
  125. static void **pages;
  126. static inline void *__add_page(void)
  127. {
  128. void **c;
  129. c = (void **)get_usable_page(GFP_ATOMIC);
  130. if (c) {
  131. *c = pages;
  132. pages = c;
  133. }
  134. return c;
  135. }
  136. static inline void *__next_page(void)
  137. {
  138. void **c;
  139. c = pages;
  140. if (c) {
  141. pages = *c;
  142. *c = NULL;
  143. }
  144. return c;
  145. }
  146. /*
  147. * Try to allocate as many usable pages as needed and daisy chain them.
  148. * If one allocation fails, free the pages allocated so far
  149. */
  150. static int alloc_usable_pages(unsigned long n)
  151. {
  152. void *p;
  153. pages = NULL;
  154. do
  155. if (!__add_page())
  156. break;
  157. while (--n);
  158. if (n) {
  159. p = __next_page();
  160. while (p) {
  161. free_page((unsigned long)p);
  162. p = __next_page();
  163. }
  164. return -ENOMEM;
  165. }
  166. return 0;
  167. }
  168. static void res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
  169. {
  170. long i, j;
  171. i = pud_index(address);
  172. pud = pud + i;
  173. for (; i < PTRS_PER_PUD; pud++, i++) {
  174. unsigned long paddr;
  175. pmd_t *pmd;
  176. paddr = address + i*PUD_SIZE;
  177. if (paddr >= end)
  178. break;
  179. pmd = (pmd_t *)__next_page();
  180. set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
  181. for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) {
  182. unsigned long pe;
  183. if (paddr >= end)
  184. break;
  185. pe = _PAGE_NX | _PAGE_PSE | _KERNPG_TABLE | paddr;
  186. pe &= __supported_pte_mask;
  187. set_pmd(pmd, __pmd(pe));
  188. }
  189. }
  190. }
  191. static void set_up_temporary_mappings(void)
  192. {
  193. unsigned long start, end, next;
  194. temp_level4_pgt = (pgd_t *)__next_page();
  195. /* It is safe to reuse the original kernel mapping */
  196. set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map),
  197. init_level4_pgt[pgd_index(__START_KERNEL_map)]);
  198. /* Set up the direct mapping from scratch */
  199. start = (unsigned long)pfn_to_kaddr(0);
  200. end = (unsigned long)pfn_to_kaddr(end_pfn);
  201. for (; start < end; start = next) {
  202. pud_t *pud = (pud_t *)__next_page();
  203. next = start + PGDIR_SIZE;
  204. if (next > end)
  205. next = end;
  206. res_phys_pud_init(pud, __pa(start), __pa(next));
  207. set_pgd(temp_level4_pgt + pgd_index(start),
  208. mk_kernel_pgd(__pa(pud)));
  209. }
  210. }
  211. int swsusp_arch_resume(void)
  212. {
  213. unsigned long n;
  214. n = ((end_pfn << PAGE_SHIFT) + PUD_SIZE - 1) >> PUD_SHIFT;
  215. n += (n + PTRS_PER_PUD - 1) / PTRS_PER_PUD + 1;
  216. pr_debug("swsusp_arch_resume(): pages needed = %lu\n", n);
  217. if (alloc_usable_pages(n)) {
  218. free_eaten_memory();
  219. return -ENOMEM;
  220. }
  221. /* We have got enough memory and from now on we cannot recover */
  222. set_up_temporary_mappings();
  223. restore_image();
  224. return 0;
  225. }
  226. #endif /* CONFIG_SOFTWARE_SUSPEND */