sh_mobile_hdmi.c 39 KB

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  1. /*
  2. * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
  3. * for SLISHDMI13T and SLIPHDMIT IP cores
  4. *
  5. * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/console.h>
  13. #include <linux/delay.h>
  14. #include <linux/err.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/module.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/slab.h>
  22. #include <linux/types.h>
  23. #include <linux/workqueue.h>
  24. #include <video/sh_mobile_hdmi.h>
  25. #include <video/sh_mobile_lcdc.h>
  26. #include "sh_mobile_lcdcfb.h"
  27. #define HDMI_SYSTEM_CTRL 0x00 /* System control */
  28. #define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
  29. bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
  30. #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
  31. #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
  32. #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency,
  33. bits 19..16 of Internal CTS */
  34. #define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */
  35. #define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */
  36. #define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */
  37. #define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */
  38. #define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */
  39. #define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */
  40. #define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */
  41. #define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */
  42. #define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */
  43. #define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */
  44. #define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */
  45. #define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */
  46. #define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */
  47. #define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */
  48. #define HDMI_CATEGORY_CODE 0x13 /* Category code */
  49. #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */
  50. #define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */
  51. #define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */
  52. #define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */
  53. /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
  54. #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
  55. #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */
  56. #define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */
  57. #define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */
  58. #define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */
  59. #define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */
  60. #define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */
  61. #define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */
  62. #define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */
  63. #define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */
  64. #define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */
  65. #define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */
  66. #define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */
  67. #define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */
  68. #define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */
  69. #define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */
  70. #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */
  71. #define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */
  72. #define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */
  73. #define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */
  74. #define HDMI_OUTPUT_OPTION 0x46 /* Output option */
  75. #define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */
  76. #define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */
  77. #define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */
  78. #define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */
  79. #define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */
  80. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */
  81. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */
  82. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */
  83. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */
  84. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */
  85. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */
  86. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */
  87. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */
  88. #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */
  89. #define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */
  90. #define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */
  91. #define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */
  92. #define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */
  93. #define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */
  94. #define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */
  95. #define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */
  96. #define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */
  97. #define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */
  98. #define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */
  99. #define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */
  100. #define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */
  101. #define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */
  102. #define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */
  103. #define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */
  104. #define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */
  105. #define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */
  106. #define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */
  107. #define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */
  108. #define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */
  109. #define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */
  110. #define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */
  111. #define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */
  112. #define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */
  113. #define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */
  114. #define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */
  115. #define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */
  116. #define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */
  117. #define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */
  118. #define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */
  119. #define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */
  120. #define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */
  121. #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */
  122. #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */
  123. #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */
  124. #define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */
  125. #define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */
  126. #define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */
  127. #define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */
  128. #define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */
  129. #define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */
  130. #define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */
  131. #define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */
  132. #define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */
  133. #define HDMI_FRAME_COUNTER 0x9C /* Frame counter */
  134. #define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */
  135. #define HDMI_HDCP_CONTROL 0xAF /* HDCP control */
  136. #define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */
  137. #define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */
  138. #define HDMI_HDCP_STATUS 0xB8 /* HDCP status */
  139. #define HDMI_SHA0 0xB9 /* sha0 */
  140. #define HDMI_SHA1 0xBA /* sha1 */
  141. #define HDMI_SHA2 0xBB /* sha2 */
  142. #define HDMI_SHA3 0xBC /* sha3 */
  143. #define HDMI_SHA4 0xBD /* sha4 */
  144. #define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */
  145. #define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */
  146. #define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */
  147. #define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */
  148. #define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */
  149. #define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */
  150. #define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */
  151. #define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */
  152. #define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */
  153. #define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */
  154. #define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */
  155. #define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */
  156. #define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */
  157. #define HDMI_RI_READ_COUNT 0xCB /* Ri read count */
  158. #define HDMI_AN_SEED 0xCC /* An seed */
  159. #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */
  160. #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */
  161. #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */
  162. #define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */
  163. #define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */
  164. #define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */
  165. #define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */
  166. #define HDMI_RI_7_0 0xD5 /* Ri[7:0] */
  167. #define HDMI_RI_15_8 0xD6 /* Ri[15:8] */
  168. #define HDMI_PJ 0xD7 /* Pj */
  169. #define HDMI_SHA_RD 0xD8 /* sha_rd */
  170. #define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */
  171. #define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */
  172. #define HDMI_PJ_SAVED 0xDB /* Pj saved */
  173. #define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */
  174. #define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */
  175. #define HDMI_BCAPS_WRITE 0xE0 /* bcaps */
  176. #define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */
  177. #define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */
  178. #define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */
  179. #define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */
  180. #define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */
  181. #define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */
  182. #define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */
  183. #define HDMI_AN_7_0 0xE8 /* An[7:0] */
  184. #define HDMI_AN_15_8 0xE9 /* An [15:8] */
  185. #define HDMI_AN_23_16 0xEA /* An [23:16] */
  186. #define HDMI_AN_31_24 0xEB /* An [31:24] */
  187. #define HDMI_AN_39_32 0xEC /* An [39:32] */
  188. #define HDMI_AN_47_40 0xED /* An [47:40] */
  189. #define HDMI_AN_55_48 0xEE /* An [55:48] */
  190. #define HDMI_AN_63_56 0xEF /* An [63:56] */
  191. #define HDMI_PRODUCT_ID 0xF0 /* Product ID */
  192. #define HDMI_REVISION_ID 0xF1 /* Revision ID */
  193. #define HDMI_TEST_MODE 0xFE /* Test mode */
  194. enum hotplug_state {
  195. HDMI_HOTPLUG_DISCONNECTED,
  196. HDMI_HOTPLUG_CONNECTED,
  197. HDMI_HOTPLUG_EDID_DONE,
  198. };
  199. struct sh_hdmi {
  200. void __iomem *base;
  201. enum hotplug_state hp_state; /* hot-plug status */
  202. bool preprogrammed_mode; /* use a pre-programmed VIC or the external mode */
  203. struct clk *hdmi_clk;
  204. struct device *dev;
  205. struct fb_info *info;
  206. struct mutex mutex; /* Protect the info pointer */
  207. struct delayed_work edid_work;
  208. struct fb_var_screeninfo var;
  209. struct fb_monspecs monspec;
  210. };
  211. static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
  212. {
  213. iowrite8(data, hdmi->base + reg);
  214. }
  215. static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
  216. {
  217. return ioread8(hdmi->base + reg);
  218. }
  219. /* External video parameter settings */
  220. static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
  221. {
  222. struct fb_var_screeninfo *var = &hdmi->var;
  223. u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
  224. u8 sync = 0;
  225. htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
  226. hdelay = var->hsync_len + var->left_margin;
  227. hblank = var->right_margin + hdelay;
  228. /*
  229. * Vertical timing looks a bit different in Figure 18,
  230. * but let's try the same first by setting offset = 0
  231. */
  232. vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
  233. vdelay = var->vsync_len + var->upper_margin;
  234. vblank = var->lower_margin + vdelay;
  235. voffset = min(var->upper_margin / 2, 6U);
  236. /*
  237. * [3]: VSYNC polarity: Positive
  238. * [2]: HSYNC polarity: Positive
  239. * [1]: Interlace/Progressive: Progressive
  240. * [0]: External video settings enable: used.
  241. */
  242. if (var->sync & FB_SYNC_HOR_HIGH_ACT)
  243. sync |= 4;
  244. if (var->sync & FB_SYNC_VERT_HIGH_ACT)
  245. sync |= 8;
  246. dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
  247. htotal, hblank, hdelay, var->hsync_len,
  248. vtotal, vblank, vdelay, var->vsync_len, sync);
  249. hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
  250. hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
  251. hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
  252. hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
  253. hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
  254. hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
  255. hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
  256. hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
  257. hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
  258. hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
  259. hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
  260. hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
  261. hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
  262. hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
  263. /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
  264. if (!hdmi->preprogrammed_mode)
  265. hdmi_write(hdmi, sync | 1 | (voffset << 4),
  266. HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
  267. }
  268. /**
  269. * sh_hdmi_video_config()
  270. */
  271. static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
  272. {
  273. /*
  274. * [7:4]: Audio sampling frequency: 48kHz
  275. * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
  276. * [0]: Internal/External DE select: internal
  277. */
  278. hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
  279. /*
  280. * [7:6]: Video output format: RGB 4:4:4
  281. * [5:4]: Input video data width: 8 bit
  282. * [3:1]: EAV/SAV location: channel 1
  283. * [0]: Video input color space: RGB
  284. */
  285. hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
  286. /*
  287. * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
  288. * left at 0 by default, this configures 24bpp and sets the Color Depth
  289. * (CD) field in the General Control Packet
  290. */
  291. hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
  292. }
  293. /**
  294. * sh_hdmi_audio_config()
  295. */
  296. static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
  297. {
  298. /*
  299. * [7:4] L/R data swap control
  300. * [3:0] appropriate N[19:16]
  301. */
  302. hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
  303. /* appropriate N[15:8] */
  304. hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
  305. /* appropriate N[7:0] */
  306. hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
  307. /* [7:4] 48 kHz SPDIF not used */
  308. hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
  309. /*
  310. * [6:5] set required down sampling rate if required
  311. * [4:3] set required audio source
  312. */
  313. hdmi_write(hdmi, 0x00, HDMI_AUDIO_SETTING_1);
  314. /* [3:0] set sending channel number for channel status */
  315. hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
  316. /*
  317. * [5:2] set valid I2S source input pin
  318. * [1:0] set input I2S source mode
  319. */
  320. hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
  321. /* [7:4] set valid DSD source input pin */
  322. hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
  323. /* [7:0] set appropriate I2S input pin swap settings if required */
  324. hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
  325. /*
  326. * [7] set validity bit for channel status
  327. * [3:0] set original sample frequency for channel status
  328. */
  329. hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
  330. /*
  331. * [7] set value for channel status
  332. * [6] set value for channel status
  333. * [5] set copyright bit for channel status
  334. * [4:2] set additional information for channel status
  335. * [1:0] set clock accuracy for channel status
  336. */
  337. hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
  338. /* [7:0] set category code for channel status */
  339. hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
  340. /*
  341. * [7:4] set source number for channel status
  342. * [3:0] set word length for channel status
  343. */
  344. hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
  345. /* [7:4] set sample frequency for channel status */
  346. hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
  347. }
  348. /**
  349. * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
  350. */
  351. static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
  352. {
  353. if (hdmi->var.yres > 480) {
  354. /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
  355. /*
  356. * [1:0] Speed_A
  357. * [3:2] Speed_B
  358. * [4] PLLA_Bypass
  359. * [6] DRV_TEST_EN
  360. * [7] DRV_TEST_IN
  361. */
  362. hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
  363. /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
  364. hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
  365. /*
  366. * [2:0] BGR_I_OFFSET
  367. * [6:4] BGR_V_OFFSET
  368. */
  369. hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
  370. /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
  371. hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
  372. /*
  373. * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
  374. * LPF capacitance, LPF resistance[1]
  375. */
  376. hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
  377. /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
  378. hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
  379. /*
  380. * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
  381. * LPF capacitance, LPF resistance[1]
  382. */
  383. hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
  384. /* DRV_CONFIG, PE_CONFIG */
  385. hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
  386. /*
  387. * [2:0] AMON_SEL (4 == LPF voltage)
  388. * [4] PLLA_CONFIG[16]
  389. * [5] PLLB_CONFIG[16]
  390. */
  391. hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
  392. } else {
  393. /* for 480p8bit 27MHz */
  394. hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
  395. hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
  396. hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
  397. hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
  398. hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
  399. hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
  400. hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
  401. hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
  402. hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
  403. }
  404. }
  405. /**
  406. * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
  407. */
  408. static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
  409. {
  410. u8 vic;
  411. /* AVI InfoFrame */
  412. hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
  413. /* Packet Type = 0x82 */
  414. hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
  415. /* Version = 0x02 */
  416. hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
  417. /* Length = 13 (0x0D) */
  418. hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
  419. /* N. A. Checksum */
  420. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
  421. /*
  422. * Y = RGB
  423. * A0 = No Data
  424. * B = Bar Data not valid
  425. * S = No Data
  426. */
  427. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
  428. /*
  429. * [7:6] C = Colorimetry: no data
  430. * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
  431. * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
  432. */
  433. hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
  434. /*
  435. * ITC = No Data
  436. * EC = xvYCC601
  437. * Q = Default (depends on video format)
  438. * SC = No Known non_uniform Scaling
  439. */
  440. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
  441. /*
  442. * VIC = 1280 x 720p: ignored if external config is used
  443. * Send 2 for 720 x 480p, 16 for 1080p, ignored in external mode
  444. */
  445. if (hdmi->var.yres == 1080 && hdmi->var.xres == 1920)
  446. vic = 16;
  447. else if (hdmi->var.yres == 480 && hdmi->var.xres == 720)
  448. vic = 2;
  449. else
  450. vic = 4;
  451. hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
  452. /* PR = No Repetition */
  453. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
  454. /* Line Number of End of Top Bar (lower 8 bits) */
  455. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
  456. /* Line Number of End of Top Bar (upper 8 bits) */
  457. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
  458. /* Line Number of Start of Bottom Bar (lower 8 bits) */
  459. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
  460. /* Line Number of Start of Bottom Bar (upper 8 bits) */
  461. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
  462. /* Pixel Number of End of Left Bar (lower 8 bits) */
  463. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
  464. /* Pixel Number of End of Left Bar (upper 8 bits) */
  465. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
  466. /* Pixel Number of Start of Right Bar (lower 8 bits) */
  467. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
  468. /* Pixel Number of Start of Right Bar (upper 8 bits) */
  469. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
  470. }
  471. /**
  472. * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
  473. */
  474. static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
  475. {
  476. /* Audio InfoFrame */
  477. hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
  478. /* Packet Type = 0x84 */
  479. hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
  480. /* Version Number = 0x01 */
  481. hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
  482. /* 0 Length = 10 (0x0A) */
  483. hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
  484. /* n. a. Checksum */
  485. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
  486. /* Audio Channel Count = Refer to Stream Header */
  487. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
  488. /* Refer to Stream Header */
  489. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
  490. /* Format depends on coding type (i.e. CT0...CT3) */
  491. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
  492. /* Speaker Channel Allocation = Front Right + Front Left */
  493. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
  494. /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
  495. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
  496. /* Reserved (0) */
  497. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
  498. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
  499. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
  500. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
  501. hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
  502. }
  503. /**
  504. * sh_hdmi_configure() - Initialise HDMI for output
  505. */
  506. static void sh_hdmi_configure(struct sh_hdmi *hdmi)
  507. {
  508. /* Configure video format */
  509. sh_hdmi_video_config(hdmi);
  510. /* Configure audio format */
  511. sh_hdmi_audio_config(hdmi);
  512. /* Configure PHY */
  513. sh_hdmi_phy_config(hdmi);
  514. /* Auxiliary Video Information (AVI) InfoFrame */
  515. sh_hdmi_avi_infoframe_setup(hdmi);
  516. /* Audio InfoFrame */
  517. sh_hdmi_audio_infoframe_setup(hdmi);
  518. /*
  519. * Control packet auto send with VSYNC control: auto send
  520. * General control, Gamut metadata, ISRC, and ACP packets
  521. */
  522. hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
  523. /* FIXME */
  524. msleep(10);
  525. /* PS mode b->d, reset PLLA and PLLB */
  526. hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
  527. udelay(10);
  528. hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
  529. }
  530. static int sh_hdmi_read_edid(struct sh_hdmi *hdmi)
  531. {
  532. struct fb_var_screeninfo tmpvar;
  533. /* TODO: When we are ready to use EDID, use this to fill &hdmi->var */
  534. struct fb_var_screeninfo *var = &tmpvar;
  535. const struct fb_videomode *mode, *found = NULL;
  536. int i;
  537. u8 edid[128];
  538. /* Read EDID */
  539. dev_dbg(hdmi->dev, "Read back EDID code:");
  540. for (i = 0; i < 128; i++) {
  541. edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
  542. #ifdef DEBUG
  543. if ((i % 16) == 0) {
  544. printk(KERN_CONT "\n");
  545. printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
  546. } else {
  547. printk(KERN_CONT " %02X", edid[i]);
  548. }
  549. #endif
  550. }
  551. #ifdef DEBUG
  552. printk(KERN_CONT "\n");
  553. #endif
  554. fb_edid_to_monspecs(edid, &hdmi->monspec);
  555. /* First look for an exact match */
  556. for (i = 0, mode = hdmi->monspec.modedb; i < hdmi->monspec.modedb_len;
  557. i++, mode++) {
  558. dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u @ %lu kHz monitor detected\n",
  559. mode->left_margin, mode->xres,
  560. mode->right_margin, mode->hsync_len,
  561. mode->upper_margin, mode->yres,
  562. mode->lower_margin, mode->vsync_len,
  563. PICOS2KHZ(mode->pixclock));
  564. if (!found && hdmi->info) {
  565. fb_videomode_to_var(var, mode);
  566. found = fb_match_mode(var, &hdmi->info->modelist);
  567. /*
  568. * If an exact match found, we're good to bail out, but
  569. * continue to print out all modes
  570. */
  571. }
  572. }
  573. /*
  574. * The monitor might also work with a mode, that is smaller, than one of
  575. * its modes, use the first (default) one for this
  576. */
  577. if (!found && hdmi->info && hdmi->monspec.modedb_len) {
  578. struct fb_modelist *modelist;
  579. unsigned int min_err = UINT_MAX, err;
  580. const struct fb_videomode *mon_mode = hdmi->monspec.modedb;
  581. list_for_each_entry(modelist, &hdmi->info->modelist, list) {
  582. mode = &modelist->mode;
  583. dev_dbg(hdmi->dev, "matching %ux%u to %ux%u\n", mode->xres, mode->yres,
  584. mon_mode->xres, mon_mode->yres);
  585. if (mode->xres <= mon_mode->xres && mode->yres <= mon_mode->yres) {
  586. err = mon_mode->xres - mode->xres + mon_mode->yres - mode->yres;
  587. if (!err) {
  588. found = mode;
  589. break;
  590. }
  591. if (err < min_err) {
  592. found = mode;
  593. min_err = err;
  594. }
  595. }
  596. }
  597. }
  598. /* Nothing suitable specified by the platform: use monitor's first mode */
  599. if (!found && hdmi->monspec.modedb_len)
  600. found = hdmi->monspec.modedb;
  601. /* No valid timing info in EDID - last resort: use platform default mode */
  602. if (!found && hdmi->info) {
  603. struct fb_modelist *modelist = list_entry(hdmi->info->modelist.next,
  604. struct fb_modelist, list);
  605. found = &modelist->mode;
  606. }
  607. /* No cookie today */
  608. if (!found)
  609. return -ENXIO;
  610. dev_dbg(hdmi->dev, "best \"%s\" %ux%u@%ups\n", found->name,
  611. found->xres, found->yres, found->pixclock);
  612. if ((found->xres == 720 && found->yres == 480) ||
  613. (found->xres == 1280 && found->yres == 720) ||
  614. (found->xres == 1920 && found->yres == 1080))
  615. hdmi->preprogrammed_mode = true;
  616. else
  617. hdmi->preprogrammed_mode = false;
  618. fb_videomode_to_var(&hdmi->var, found);
  619. sh_hdmi_external_video_param(hdmi);
  620. return 0;
  621. }
  622. static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
  623. {
  624. struct sh_hdmi *hdmi = dev_id;
  625. u8 status1, status2, mask1, mask2;
  626. /* mode_b and PLLA and PLLB reset */
  627. hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
  628. /* How long shall reset be held? */
  629. udelay(10);
  630. /* mode_b and PLLA and PLLB reset release */
  631. hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
  632. status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
  633. status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
  634. mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
  635. mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
  636. /* Correct would be to ack only set bits, but the datasheet requires 0xff */
  637. hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
  638. hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
  639. if (printk_ratelimit())
  640. dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
  641. irq, status1, mask1, status2, mask2);
  642. if (!((status1 & mask1) | (status2 & mask2))) {
  643. return IRQ_NONE;
  644. } else if (status1 & 0xc0) {
  645. u8 msens;
  646. /* Datasheet specifies 10ms... */
  647. udelay(500);
  648. msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
  649. dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
  650. /* Check, if hot plug & MSENS pin status are both high */
  651. if ((msens & 0xC0) == 0xC0) {
  652. /* Display plug in */
  653. hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
  654. /* Set EDID word address */
  655. hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
  656. /* Set EDID segment pointer */
  657. hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
  658. /* Enable EDID interrupt */
  659. hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
  660. } else if (!(status1 & 0x80)) {
  661. /* Display unplug, beware multiple interrupts */
  662. if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
  663. schedule_delayed_work(&hdmi->edid_work, 0);
  664. hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
  665. /* display_off will switch back to mode_a */
  666. }
  667. } else if (status1 & 2) {
  668. /* EDID error interrupt: retry */
  669. /* Set EDID word address */
  670. hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
  671. /* Set EDID segment pointer */
  672. hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
  673. } else if (status1 & 4) {
  674. /* Disable EDID interrupt */
  675. hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
  676. hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
  677. schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
  678. }
  679. return IRQ_HANDLED;
  680. }
  681. /* locking: called with info->lock held, or before register_framebuffer() */
  682. static void sh_hdmi_display_on(void *arg, struct fb_info *info)
  683. {
  684. /*
  685. * info is guaranteed to be valid, when we are called, because our
  686. * FB_EVENT_FB_UNBIND notify is also called with info->lock held
  687. */
  688. struct sh_hdmi *hdmi = arg;
  689. struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
  690. struct sh_mobile_lcdc_chan *ch = info->par;
  691. dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
  692. pdata->lcd_dev, info->state);
  693. /* No need to lock */
  694. hdmi->info = info;
  695. /*
  696. * hp_state can be set to
  697. * HDMI_HOTPLUG_DISCONNECTED: on monitor unplug
  698. * HDMI_HOTPLUG_CONNECTED: on monitor plug-in
  699. * HDMI_HOTPLUG_EDID_DONE: on EDID read completion
  700. */
  701. switch (hdmi->hp_state) {
  702. case HDMI_HOTPLUG_EDID_DONE:
  703. /* PS mode d->e. All functions are active */
  704. hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
  705. dev_dbg(hdmi->dev, "HDMI running\n");
  706. break;
  707. case HDMI_HOTPLUG_DISCONNECTED:
  708. info->state = FBINFO_STATE_SUSPENDED;
  709. default:
  710. hdmi->var = ch->display_var;
  711. }
  712. }
  713. /* locking: called with info->lock held */
  714. static void sh_hdmi_display_off(void *arg)
  715. {
  716. struct sh_hdmi *hdmi = arg;
  717. struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
  718. dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
  719. /* PS mode e->a */
  720. hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
  721. }
  722. static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
  723. {
  724. struct fb_info *info = hdmi->info;
  725. struct sh_mobile_lcdc_chan *ch = info->par;
  726. struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
  727. struct fb_videomode mode1, mode2;
  728. fb_var_to_videomode(&mode1, old_var);
  729. fb_var_to_videomode(&mode2, new_var);
  730. dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
  731. mode1.xres, mode1.yres, mode2.xres, mode2.yres);
  732. if (fb_mode_is_equal(&mode1, &mode2))
  733. return false;
  734. dev_dbg(info->dev, "Switching %u -> %u lines\n",
  735. mode1.yres, mode2.yres);
  736. *old_var = *new_var;
  737. return true;
  738. }
  739. /**
  740. * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
  741. * @hdmi: driver context
  742. * @pixclock: pixel clock period in picoseconds
  743. * return: configured positive rate if successful
  744. * 0 if couldn't set the rate, but managed to enable the clock
  745. * negative error, if couldn't enable the clock
  746. */
  747. static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long pixclock)
  748. {
  749. long rate;
  750. int ret;
  751. rate = PICOS2KHZ(pixclock) * 1000;
  752. rate = clk_round_rate(hdmi->hdmi_clk, rate);
  753. if (rate > 0) {
  754. ret = clk_set_rate(hdmi->hdmi_clk, rate);
  755. if (ret < 0) {
  756. dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", rate, ret);
  757. rate = 0;
  758. } else {
  759. dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", rate);
  760. }
  761. } else {
  762. rate = 0;
  763. dev_warn(hdmi->dev, "Cannot get suitable rate: %ld\n", rate);
  764. }
  765. ret = clk_enable(hdmi->hdmi_clk);
  766. if (ret < 0) {
  767. dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
  768. return ret;
  769. }
  770. return rate;
  771. }
  772. /* Hotplug interrupt occurred, read EDID */
  773. static void sh_hdmi_edid_work_fn(struct work_struct *work)
  774. {
  775. struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
  776. struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
  777. struct sh_mobile_lcdc_chan *ch;
  778. int ret;
  779. dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
  780. pdata->lcd_dev, hdmi->hp_state);
  781. if (!pdata->lcd_dev)
  782. return;
  783. mutex_lock(&hdmi->mutex);
  784. if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
  785. /* A device has been plugged in */
  786. pm_runtime_get_sync(hdmi->dev);
  787. ret = sh_hdmi_read_edid(hdmi);
  788. if (ret < 0)
  789. goto out;
  790. /* Reconfigure the clock */
  791. clk_disable(hdmi->hdmi_clk);
  792. ret = sh_hdmi_clk_configure(hdmi, hdmi->var.pixclock);
  793. if (ret < 0)
  794. goto out;
  795. msleep(10);
  796. sh_hdmi_configure(hdmi);
  797. /* Switched to another (d) power-save mode */
  798. msleep(10);
  799. if (!hdmi->info)
  800. goto out;
  801. ch = hdmi->info->par;
  802. acquire_console_sem();
  803. /* HDMI plug in */
  804. if (!sh_hdmi_must_reconfigure(hdmi) &&
  805. hdmi->info->state == FBINFO_STATE_RUNNING) {
  806. /*
  807. * First activation with the default monitor - just turn
  808. * on, if we run a resume here, the logo disappears
  809. */
  810. if (lock_fb_info(hdmi->info)) {
  811. sh_hdmi_display_on(hdmi, hdmi->info);
  812. unlock_fb_info(hdmi->info);
  813. }
  814. } else {
  815. /* New monitor or have to wake up */
  816. fb_set_suspend(hdmi->info, 0);
  817. }
  818. release_console_sem();
  819. } else {
  820. ret = 0;
  821. if (!hdmi->info)
  822. goto out;
  823. acquire_console_sem();
  824. /* HDMI disconnect */
  825. fb_set_suspend(hdmi->info, 1);
  826. release_console_sem();
  827. pm_runtime_put(hdmi->dev);
  828. fb_destroy_modedb(hdmi->monspec.modedb);
  829. }
  830. out:
  831. if (ret < 0)
  832. hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
  833. mutex_unlock(&hdmi->mutex);
  834. dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
  835. }
  836. static int sh_hdmi_notify(struct notifier_block *nb,
  837. unsigned long action, void *data);
  838. static struct notifier_block sh_hdmi_notifier = {
  839. .notifier_call = sh_hdmi_notify,
  840. };
  841. static int sh_hdmi_notify(struct notifier_block *nb,
  842. unsigned long action, void *data)
  843. {
  844. struct fb_event *event = data;
  845. struct fb_info *info = event->info;
  846. struct sh_mobile_lcdc_chan *ch = info->par;
  847. struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
  848. struct sh_hdmi *hdmi = board_cfg->board_data;
  849. if (nb != &sh_hdmi_notifier || !hdmi || hdmi->info != info)
  850. return NOTIFY_DONE;
  851. switch(action) {
  852. case FB_EVENT_FB_REGISTERED:
  853. /* Unneeded, activation taken care by sh_hdmi_display_on() */
  854. break;
  855. case FB_EVENT_FB_UNREGISTERED:
  856. /*
  857. * We are called from unregister_framebuffer() with the
  858. * info->lock held. This is bad for us, because we can race with
  859. * the scheduled work, which has to call fb_set_suspend(), which
  860. * takes info->lock internally, so, sh_hdmi_edid_work_fn()
  861. * cannot take and hold info->lock for the whole function
  862. * duration. Using an additional lock creates a classical AB-BA
  863. * lock up. Therefore, we have to release the info->lock
  864. * temporarily, synchronise with the work queue and re-acquire
  865. * the info->lock.
  866. */
  867. unlock_fb_info(hdmi->info);
  868. mutex_lock(&hdmi->mutex);
  869. hdmi->info = NULL;
  870. mutex_unlock(&hdmi->mutex);
  871. lock_fb_info(hdmi->info);
  872. return NOTIFY_OK;
  873. }
  874. return NOTIFY_DONE;
  875. }
  876. static int __init sh_hdmi_probe(struct platform_device *pdev)
  877. {
  878. struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
  879. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  880. struct sh_mobile_lcdc_board_cfg *board_cfg;
  881. int irq = platform_get_irq(pdev, 0), ret;
  882. struct sh_hdmi *hdmi;
  883. long rate;
  884. if (!res || !pdata || irq < 0)
  885. return -ENODEV;
  886. hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
  887. if (!hdmi) {
  888. dev_err(&pdev->dev, "Cannot allocate device data\n");
  889. return -ENOMEM;
  890. }
  891. mutex_init(&hdmi->mutex);
  892. hdmi->dev = &pdev->dev;
  893. hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
  894. if (IS_ERR(hdmi->hdmi_clk)) {
  895. ret = PTR_ERR(hdmi->hdmi_clk);
  896. dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
  897. goto egetclk;
  898. }
  899. /* Some arbitrary relaxed pixclock just to get things started */
  900. rate = sh_hdmi_clk_configure(hdmi, 37037);
  901. if (rate < 0) {
  902. ret = rate;
  903. goto erate;
  904. }
  905. dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
  906. if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
  907. dev_err(&pdev->dev, "HDMI register region already claimed\n");
  908. ret = -EBUSY;
  909. goto ereqreg;
  910. }
  911. hdmi->base = ioremap(res->start, resource_size(res));
  912. if (!hdmi->base) {
  913. dev_err(&pdev->dev, "HDMI register region already claimed\n");
  914. ret = -ENOMEM;
  915. goto emap;
  916. }
  917. platform_set_drvdata(pdev, hdmi);
  918. /* Product and revision IDs are 0 in sh-mobile version */
  919. dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
  920. hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
  921. /* Set up LCDC callbacks */
  922. board_cfg = &pdata->lcd_chan->board_cfg;
  923. board_cfg->owner = THIS_MODULE;
  924. board_cfg->board_data = hdmi;
  925. board_cfg->display_on = sh_hdmi_display_on;
  926. board_cfg->display_off = sh_hdmi_display_off;
  927. INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
  928. pm_runtime_enable(&pdev->dev);
  929. pm_runtime_resume(&pdev->dev);
  930. ret = request_irq(irq, sh_hdmi_hotplug, 0,
  931. dev_name(&pdev->dev), hdmi);
  932. if (ret < 0) {
  933. dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
  934. goto ereqirq;
  935. }
  936. return 0;
  937. ereqirq:
  938. pm_runtime_disable(&pdev->dev);
  939. iounmap(hdmi->base);
  940. emap:
  941. release_mem_region(res->start, resource_size(res));
  942. ereqreg:
  943. clk_disable(hdmi->hdmi_clk);
  944. erate:
  945. clk_put(hdmi->hdmi_clk);
  946. egetclk:
  947. mutex_destroy(&hdmi->mutex);
  948. kfree(hdmi);
  949. return ret;
  950. }
  951. static int __exit sh_hdmi_remove(struct platform_device *pdev)
  952. {
  953. struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
  954. struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
  955. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  956. struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
  957. int irq = platform_get_irq(pdev, 0);
  958. board_cfg->display_on = NULL;
  959. board_cfg->display_off = NULL;
  960. board_cfg->board_data = NULL;
  961. board_cfg->owner = NULL;
  962. /* No new work will be scheduled, wait for running ISR */
  963. free_irq(irq, hdmi);
  964. /* Wait for already scheduled work */
  965. cancel_delayed_work_sync(&hdmi->edid_work);
  966. pm_runtime_disable(&pdev->dev);
  967. clk_disable(hdmi->hdmi_clk);
  968. clk_put(hdmi->hdmi_clk);
  969. iounmap(hdmi->base);
  970. release_mem_region(res->start, resource_size(res));
  971. mutex_destroy(&hdmi->mutex);
  972. kfree(hdmi);
  973. return 0;
  974. }
  975. static struct platform_driver sh_hdmi_driver = {
  976. .remove = __exit_p(sh_hdmi_remove),
  977. .driver = {
  978. .name = "sh-mobile-hdmi",
  979. },
  980. };
  981. static int __init sh_hdmi_init(void)
  982. {
  983. return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
  984. }
  985. module_init(sh_hdmi_init);
  986. static void __exit sh_hdmi_exit(void)
  987. {
  988. platform_driver_unregister(&sh_hdmi_driver);
  989. }
  990. module_exit(sh_hdmi_exit);
  991. MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
  992. MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
  993. MODULE_LICENSE("GPL v2");