main.c 41 KB

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  1. /*
  2. * Copyright (c) 2008 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. /* mac80211 and PCI callbacks */
  17. #include <linux/nl80211.h>
  18. #include "core.h"
  19. #include "reg.h"
  20. #define ATH_PCI_VERSION "0.1"
  21. static char *dev_info = "ath9k";
  22. MODULE_AUTHOR("Atheros Communications");
  23. MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  24. MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  25. MODULE_LICENSE("Dual BSD/GPL");
  26. static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  27. { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
  28. { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  29. { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
  30. { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
  31. { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  32. { 0 }
  33. };
  34. static void ath_detach(struct ath_softc *sc);
  35. static int ath_get_channel(struct ath_softc *sc,
  36. struct ieee80211_channel *chan)
  37. {
  38. int i;
  39. for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
  40. if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
  41. return i;
  42. }
  43. return -1;
  44. }
  45. static u32 ath_get_extchanmode(struct ath_softc *sc,
  46. struct ieee80211_channel *chan)
  47. {
  48. u32 chanmode = 0;
  49. u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
  50. enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
  51. switch (chan->band) {
  52. case IEEE80211_BAND_2GHZ:
  53. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
  54. (tx_chan_width == ATH9K_HT_MACMODE_20))
  55. chanmode = CHANNEL_G_HT20;
  56. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
  57. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  58. chanmode = CHANNEL_G_HT40PLUS;
  59. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
  60. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  61. chanmode = CHANNEL_G_HT40MINUS;
  62. break;
  63. case IEEE80211_BAND_5GHZ:
  64. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
  65. (tx_chan_width == ATH9K_HT_MACMODE_20))
  66. chanmode = CHANNEL_A_HT20;
  67. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
  68. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  69. chanmode = CHANNEL_A_HT40PLUS;
  70. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
  71. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  72. chanmode = CHANNEL_A_HT40MINUS;
  73. break;
  74. default:
  75. break;
  76. }
  77. return chanmode;
  78. }
  79. static int ath_setkey_tkip(struct ath_softc *sc,
  80. struct ieee80211_key_conf *key,
  81. struct ath9k_keyval *hk,
  82. const u8 *addr)
  83. {
  84. u8 *key_rxmic = NULL;
  85. u8 *key_txmic = NULL;
  86. key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
  87. key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
  88. if (addr == NULL) {
  89. /* Group key installation */
  90. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  91. return ath_keyset(sc, key->keyidx, hk, addr);
  92. }
  93. if (!sc->sc_splitmic) {
  94. /*
  95. * data key goes at first index,
  96. * the hal handles the MIC keys at index+64.
  97. */
  98. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  99. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
  100. return ath_keyset(sc, key->keyidx, hk, addr);
  101. }
  102. /*
  103. * TX key goes at first index, RX key at +32.
  104. * The hal handles the MIC keys at index+64.
  105. */
  106. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  107. if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
  108. /* Txmic entry failed. No need to proceed further */
  109. DPRINTF(sc, ATH_DBG_KEYCACHE,
  110. "%s Setting TX MIC Key Failed\n", __func__);
  111. return 0;
  112. }
  113. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  114. /* XXX delete tx key on failure? */
  115. return ath_keyset(sc, key->keyidx+32, hk, addr);
  116. }
  117. static int ath_key_config(struct ath_softc *sc,
  118. const u8 *addr,
  119. struct ieee80211_key_conf *key)
  120. {
  121. struct ieee80211_vif *vif;
  122. struct ath9k_keyval hk;
  123. const u8 *mac = NULL;
  124. int ret = 0;
  125. enum nl80211_iftype opmode;
  126. memset(&hk, 0, sizeof(hk));
  127. switch (key->alg) {
  128. case ALG_WEP:
  129. hk.kv_type = ATH9K_CIPHER_WEP;
  130. break;
  131. case ALG_TKIP:
  132. hk.kv_type = ATH9K_CIPHER_TKIP;
  133. break;
  134. case ALG_CCMP:
  135. hk.kv_type = ATH9K_CIPHER_AES_CCM;
  136. break;
  137. default:
  138. return -EINVAL;
  139. }
  140. hk.kv_len = key->keylen;
  141. memcpy(hk.kv_val, key->key, key->keylen);
  142. if (!sc->sc_vaps[0])
  143. return -EIO;
  144. vif = sc->sc_vaps[0];
  145. opmode = vif->type;
  146. /*
  147. * Strategy:
  148. * For _M_STA mc tx, we will not setup a key at all since we never
  149. * tx mc.
  150. * _M_STA mc rx, we will use the keyID.
  151. * for _M_IBSS mc tx, we will use the keyID, and no macaddr.
  152. * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
  153. * peer node. BUT we will plumb a cleartext key so that we can do
  154. * perSta default key table lookup in software.
  155. */
  156. if (is_broadcast_ether_addr(addr)) {
  157. switch (opmode) {
  158. case NL80211_IFTYPE_STATION:
  159. /* default key: could be group WPA key
  160. * or could be static WEP key */
  161. mac = NULL;
  162. break;
  163. case NL80211_IFTYPE_ADHOC:
  164. break;
  165. case NL80211_IFTYPE_AP:
  166. break;
  167. default:
  168. ASSERT(0);
  169. break;
  170. }
  171. } else {
  172. mac = addr;
  173. }
  174. if (key->alg == ALG_TKIP)
  175. ret = ath_setkey_tkip(sc, key, &hk, mac);
  176. else
  177. ret = ath_keyset(sc, key->keyidx, &hk, mac);
  178. if (!ret)
  179. return -EIO;
  180. return 0;
  181. }
  182. static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
  183. {
  184. int freeslot;
  185. freeslot = (key->keyidx >= 4) ? 1 : 0;
  186. ath_key_reset(sc, key->keyidx, freeslot);
  187. }
  188. static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
  189. {
  190. #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
  191. #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
  192. ht_info->ht_supported = true;
  193. ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  194. IEEE80211_HT_CAP_SM_PS |
  195. IEEE80211_HT_CAP_SGI_40 |
  196. IEEE80211_HT_CAP_DSSSCCK40;
  197. ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
  198. ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
  199. /* set up supported mcs set */
  200. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  201. ht_info->mcs.rx_mask[0] = 0xff;
  202. ht_info->mcs.rx_mask[1] = 0xff;
  203. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  204. }
  205. static void ath9k_ht_conf(struct ath_softc *sc,
  206. struct ieee80211_bss_conf *bss_conf)
  207. {
  208. struct ath_ht_info *ht_info = &sc->sc_ht_info;
  209. if (sc->hw->conf.ht.enabled) {
  210. ht_info->ext_chan_offset = bss_conf->ht.secondary_channel_offset;
  211. if (bss_conf->ht.width_40_ok)
  212. ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
  213. else
  214. ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
  215. ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
  216. }
  217. }
  218. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  219. struct ieee80211_vif *vif,
  220. struct ieee80211_bss_conf *bss_conf)
  221. {
  222. struct ieee80211_hw *hw = sc->hw;
  223. struct ieee80211_channel *curchan = hw->conf.channel;
  224. struct ath_vap *avp = (void *)vif->drv_priv;
  225. int pos;
  226. if (bss_conf->assoc) {
  227. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
  228. __func__,
  229. bss_conf->aid);
  230. /* New association, store aid */
  231. if (avp->av_opmode == ATH9K_M_STA) {
  232. sc->sc_curaid = bss_conf->aid;
  233. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  234. sc->sc_curaid);
  235. }
  236. /* Configure the beacon */
  237. ath_beacon_config(sc, 0);
  238. sc->sc_flags |= SC_OP_BEACONS;
  239. /* Reset rssi stats */
  240. sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
  241. sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
  242. sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
  243. sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
  244. /* Update chainmask */
  245. ath_update_chainmask(sc, hw->conf.ht.enabled);
  246. DPRINTF(sc, ATH_DBG_CONFIG,
  247. "%s: bssid %pM aid 0x%x\n",
  248. __func__,
  249. sc->sc_curbssid, sc->sc_curaid);
  250. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  251. __func__,
  252. curchan->center_freq);
  253. pos = ath_get_channel(sc, curchan);
  254. if (pos == -1) {
  255. DPRINTF(sc, ATH_DBG_FATAL,
  256. "%s: Invalid channel\n", __func__);
  257. return;
  258. }
  259. if (hw->conf.ht.enabled)
  260. sc->sc_ah->ah_channels[pos].chanmode =
  261. ath_get_extchanmode(sc, curchan);
  262. else
  263. sc->sc_ah->ah_channels[pos].chanmode =
  264. (curchan->band == IEEE80211_BAND_2GHZ) ?
  265. CHANNEL_G : CHANNEL_A;
  266. /* set h/w channel */
  267. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  268. DPRINTF(sc, ATH_DBG_FATAL,
  269. "%s: Unable to set channel\n",
  270. __func__);
  271. /* Start ANI */
  272. mod_timer(&sc->sc_ani.timer,
  273. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  274. } else {
  275. DPRINTF(sc, ATH_DBG_CONFIG,
  276. "%s: Bss Info DISSOC\n", __func__);
  277. sc->sc_curaid = 0;
  278. }
  279. }
  280. void ath_get_beaconconfig(struct ath_softc *sc,
  281. int if_id,
  282. struct ath_beacon_config *conf)
  283. {
  284. struct ieee80211_hw *hw = sc->hw;
  285. /* fill in beacon config data */
  286. conf->beacon_interval = hw->conf.beacon_int;
  287. conf->listen_interval = 100;
  288. conf->dtim_count = 1;
  289. conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
  290. }
  291. /********************************/
  292. /* LED functions */
  293. /********************************/
  294. static void ath_led_brightness(struct led_classdev *led_cdev,
  295. enum led_brightness brightness)
  296. {
  297. struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
  298. struct ath_softc *sc = led->sc;
  299. switch (brightness) {
  300. case LED_OFF:
  301. if (led->led_type == ATH_LED_ASSOC ||
  302. led->led_type == ATH_LED_RADIO)
  303. sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
  304. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
  305. (led->led_type == ATH_LED_RADIO) ? 1 :
  306. !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
  307. break;
  308. case LED_FULL:
  309. if (led->led_type == ATH_LED_ASSOC)
  310. sc->sc_flags |= SC_OP_LED_ASSOCIATED;
  311. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
  312. break;
  313. default:
  314. break;
  315. }
  316. }
  317. static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
  318. char *trigger)
  319. {
  320. int ret;
  321. led->sc = sc;
  322. led->led_cdev.name = led->name;
  323. led->led_cdev.default_trigger = trigger;
  324. led->led_cdev.brightness_set = ath_led_brightness;
  325. ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
  326. if (ret)
  327. DPRINTF(sc, ATH_DBG_FATAL,
  328. "Failed to register led:%s", led->name);
  329. else
  330. led->registered = 1;
  331. return ret;
  332. }
  333. static void ath_unregister_led(struct ath_led *led)
  334. {
  335. if (led->registered) {
  336. led_classdev_unregister(&led->led_cdev);
  337. led->registered = 0;
  338. }
  339. }
  340. static void ath_deinit_leds(struct ath_softc *sc)
  341. {
  342. ath_unregister_led(&sc->assoc_led);
  343. sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
  344. ath_unregister_led(&sc->tx_led);
  345. ath_unregister_led(&sc->rx_led);
  346. ath_unregister_led(&sc->radio_led);
  347. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  348. }
  349. static void ath_init_leds(struct ath_softc *sc)
  350. {
  351. char *trigger;
  352. int ret;
  353. /* Configure gpio 1 for output */
  354. ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
  355. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  356. /* LED off, active low */
  357. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  358. trigger = ieee80211_get_radio_led_name(sc->hw);
  359. snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
  360. "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
  361. ret = ath_register_led(sc, &sc->radio_led, trigger);
  362. sc->radio_led.led_type = ATH_LED_RADIO;
  363. if (ret)
  364. goto fail;
  365. trigger = ieee80211_get_assoc_led_name(sc->hw);
  366. snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
  367. "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
  368. ret = ath_register_led(sc, &sc->assoc_led, trigger);
  369. sc->assoc_led.led_type = ATH_LED_ASSOC;
  370. if (ret)
  371. goto fail;
  372. trigger = ieee80211_get_tx_led_name(sc->hw);
  373. snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
  374. "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
  375. ret = ath_register_led(sc, &sc->tx_led, trigger);
  376. sc->tx_led.led_type = ATH_LED_TX;
  377. if (ret)
  378. goto fail;
  379. trigger = ieee80211_get_rx_led_name(sc->hw);
  380. snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
  381. "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
  382. ret = ath_register_led(sc, &sc->rx_led, trigger);
  383. sc->rx_led.led_type = ATH_LED_RX;
  384. if (ret)
  385. goto fail;
  386. return;
  387. fail:
  388. ath_deinit_leds(sc);
  389. }
  390. #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
  391. /*******************/
  392. /* Rfkill */
  393. /*******************/
  394. static void ath_radio_enable(struct ath_softc *sc)
  395. {
  396. struct ath_hal *ah = sc->sc_ah;
  397. int status;
  398. spin_lock_bh(&sc->sc_resetlock);
  399. if (!ath9k_hw_reset(ah, ah->ah_curchan,
  400. sc->sc_ht_info.tx_chan_width,
  401. sc->sc_tx_chainmask,
  402. sc->sc_rx_chainmask,
  403. sc->sc_ht_extprotspacing,
  404. false, &status)) {
  405. DPRINTF(sc, ATH_DBG_FATAL,
  406. "%s: unable to reset channel %u (%uMhz) "
  407. "flags 0x%x hal status %u\n", __func__,
  408. ath9k_hw_mhz2ieee(ah,
  409. ah->ah_curchan->channel,
  410. ah->ah_curchan->channelFlags),
  411. ah->ah_curchan->channel,
  412. ah->ah_curchan->channelFlags, status);
  413. }
  414. spin_unlock_bh(&sc->sc_resetlock);
  415. ath_update_txpow(sc);
  416. if (ath_startrecv(sc) != 0) {
  417. DPRINTF(sc, ATH_DBG_FATAL,
  418. "%s: unable to restart recv logic\n", __func__);
  419. return;
  420. }
  421. if (sc->sc_flags & SC_OP_BEACONS)
  422. ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
  423. /* Re-Enable interrupts */
  424. ath9k_hw_set_interrupts(ah, sc->sc_imask);
  425. /* Enable LED */
  426. ath9k_hw_cfg_output(ah, ATH_LED_PIN,
  427. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  428. ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
  429. ieee80211_wake_queues(sc->hw);
  430. }
  431. static void ath_radio_disable(struct ath_softc *sc)
  432. {
  433. struct ath_hal *ah = sc->sc_ah;
  434. int status;
  435. ieee80211_stop_queues(sc->hw);
  436. /* Disable LED */
  437. ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
  438. ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
  439. /* Disable interrupts */
  440. ath9k_hw_set_interrupts(ah, 0);
  441. ath_draintxq(sc, false); /* clear pending tx frames */
  442. ath_stoprecv(sc); /* turn off frame recv */
  443. ath_flushrecv(sc); /* flush recv queue */
  444. spin_lock_bh(&sc->sc_resetlock);
  445. if (!ath9k_hw_reset(ah, ah->ah_curchan,
  446. sc->sc_ht_info.tx_chan_width,
  447. sc->sc_tx_chainmask,
  448. sc->sc_rx_chainmask,
  449. sc->sc_ht_extprotspacing,
  450. false, &status)) {
  451. DPRINTF(sc, ATH_DBG_FATAL,
  452. "%s: unable to reset channel %u (%uMhz) "
  453. "flags 0x%x hal status %u\n", __func__,
  454. ath9k_hw_mhz2ieee(ah,
  455. ah->ah_curchan->channel,
  456. ah->ah_curchan->channelFlags),
  457. ah->ah_curchan->channel,
  458. ah->ah_curchan->channelFlags, status);
  459. }
  460. spin_unlock_bh(&sc->sc_resetlock);
  461. ath9k_hw_phy_disable(ah);
  462. ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
  463. }
  464. static bool ath_is_rfkill_set(struct ath_softc *sc)
  465. {
  466. struct ath_hal *ah = sc->sc_ah;
  467. return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
  468. ah->ah_rfkill_polarity;
  469. }
  470. /* h/w rfkill poll function */
  471. static void ath_rfkill_poll(struct work_struct *work)
  472. {
  473. struct ath_softc *sc = container_of(work, struct ath_softc,
  474. rf_kill.rfkill_poll.work);
  475. bool radio_on;
  476. if (sc->sc_flags & SC_OP_INVALID)
  477. return;
  478. radio_on = !ath_is_rfkill_set(sc);
  479. /*
  480. * enable/disable radio only when there is a
  481. * state change in RF switch
  482. */
  483. if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
  484. enum rfkill_state state;
  485. if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
  486. state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
  487. : RFKILL_STATE_HARD_BLOCKED;
  488. } else if (radio_on) {
  489. ath_radio_enable(sc);
  490. state = RFKILL_STATE_UNBLOCKED;
  491. } else {
  492. ath_radio_disable(sc);
  493. state = RFKILL_STATE_HARD_BLOCKED;
  494. }
  495. if (state == RFKILL_STATE_HARD_BLOCKED)
  496. sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
  497. else
  498. sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
  499. rfkill_force_state(sc->rf_kill.rfkill, state);
  500. }
  501. queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
  502. msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
  503. }
  504. /* s/w rfkill handler */
  505. static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
  506. {
  507. struct ath_softc *sc = data;
  508. switch (state) {
  509. case RFKILL_STATE_SOFT_BLOCKED:
  510. if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
  511. SC_OP_RFKILL_SW_BLOCKED)))
  512. ath_radio_disable(sc);
  513. sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
  514. return 0;
  515. case RFKILL_STATE_UNBLOCKED:
  516. if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
  517. sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
  518. if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
  519. DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
  520. "radio as it is disabled by h/w \n");
  521. return -EPERM;
  522. }
  523. ath_radio_enable(sc);
  524. }
  525. return 0;
  526. default:
  527. return -EINVAL;
  528. }
  529. }
  530. /* Init s/w rfkill */
  531. static int ath_init_sw_rfkill(struct ath_softc *sc)
  532. {
  533. sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
  534. RFKILL_TYPE_WLAN);
  535. if (!sc->rf_kill.rfkill) {
  536. DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
  537. return -ENOMEM;
  538. }
  539. snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
  540. "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
  541. sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
  542. sc->rf_kill.rfkill->data = sc;
  543. sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
  544. sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
  545. sc->rf_kill.rfkill->user_claim_unsupported = 1;
  546. return 0;
  547. }
  548. /* Deinitialize rfkill */
  549. static void ath_deinit_rfkill(struct ath_softc *sc)
  550. {
  551. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  552. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  553. if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
  554. rfkill_unregister(sc->rf_kill.rfkill);
  555. sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
  556. sc->rf_kill.rfkill = NULL;
  557. }
  558. }
  559. static int ath_start_rfkill_poll(struct ath_softc *sc)
  560. {
  561. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  562. queue_delayed_work(sc->hw->workqueue,
  563. &sc->rf_kill.rfkill_poll, 0);
  564. if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
  565. if (rfkill_register(sc->rf_kill.rfkill)) {
  566. DPRINTF(sc, ATH_DBG_FATAL,
  567. "Unable to register rfkill\n");
  568. rfkill_free(sc->rf_kill.rfkill);
  569. /* Deinitialize the device */
  570. ath_detach(sc);
  571. if (sc->pdev->irq)
  572. free_irq(sc->pdev->irq, sc);
  573. pci_iounmap(sc->pdev, sc->mem);
  574. pci_release_region(sc->pdev, 0);
  575. pci_disable_device(sc->pdev);
  576. ieee80211_free_hw(sc->hw);
  577. return -EIO;
  578. } else {
  579. sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
  580. }
  581. }
  582. return 0;
  583. }
  584. #endif /* CONFIG_RFKILL */
  585. static void ath_detach(struct ath_softc *sc)
  586. {
  587. struct ieee80211_hw *hw = sc->hw;
  588. int i = 0;
  589. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
  590. #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
  591. ath_deinit_rfkill(sc);
  592. #endif
  593. ath_deinit_leds(sc);
  594. ieee80211_unregister_hw(hw);
  595. ath_rate_control_unregister();
  596. ath_rx_cleanup(sc);
  597. ath_tx_cleanup(sc);
  598. tasklet_kill(&sc->intr_tq);
  599. tasklet_kill(&sc->bcon_tasklet);
  600. if (!(sc->sc_flags & SC_OP_INVALID))
  601. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  602. /* cleanup tx queues */
  603. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
  604. if (ATH_TXQ_SETUP(sc, i))
  605. ath_tx_cleanupq(sc, &sc->sc_txq[i]);
  606. ath9k_hw_detach(sc->sc_ah);
  607. }
  608. static int ath_attach(u16 devid, struct ath_softc *sc)
  609. {
  610. struct ieee80211_hw *hw = sc->hw;
  611. int error = 0;
  612. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
  613. error = ath_init(devid, sc);
  614. if (error != 0)
  615. return error;
  616. /* get mac address from hardware and set in mac80211 */
  617. SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
  618. hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
  619. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  620. IEEE80211_HW_SIGNAL_DBM |
  621. IEEE80211_HW_AMPDU_AGGREGATION;
  622. hw->wiphy->interface_modes =
  623. BIT(NL80211_IFTYPE_AP) |
  624. BIT(NL80211_IFTYPE_STATION) |
  625. BIT(NL80211_IFTYPE_ADHOC);
  626. hw->queues = 4;
  627. hw->max_rates = 4;
  628. hw->max_rate_tries = ATH_11N_TXMAXTRY;
  629. hw->sta_data_size = sizeof(struct ath_node);
  630. hw->vif_data_size = sizeof(struct ath_vap);
  631. /* Register rate control */
  632. hw->rate_control_algorithm = "ath9k_rate_control";
  633. error = ath_rate_control_register();
  634. if (error != 0) {
  635. DPRINTF(sc, ATH_DBG_FATAL,
  636. "%s: Unable to register rate control "
  637. "algorithm:%d\n", __func__, error);
  638. ath_rate_control_unregister();
  639. goto bad;
  640. }
  641. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
  642. setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
  643. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
  644. setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
  645. }
  646. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
  647. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
  648. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  649. &sc->sbands[IEEE80211_BAND_5GHZ];
  650. /* initialize tx/rx engine */
  651. error = ath_tx_init(sc, ATH_TXBUF);
  652. if (error != 0)
  653. goto detach;
  654. error = ath_rx_init(sc, ATH_RXBUF);
  655. if (error != 0)
  656. goto detach;
  657. #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
  658. /* Initialze h/w Rfkill */
  659. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  660. INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
  661. /* Initialize s/w rfkill */
  662. if (ath_init_sw_rfkill(sc))
  663. goto detach;
  664. #endif
  665. error = ieee80211_register_hw(hw);
  666. if (error != 0) {
  667. ath_rate_control_unregister();
  668. goto bad;
  669. }
  670. /* Initialize LED control */
  671. ath_init_leds(sc);
  672. return 0;
  673. detach:
  674. ath_detach(sc);
  675. bad:
  676. return error;
  677. }
  678. static int ath9k_start(struct ieee80211_hw *hw)
  679. {
  680. struct ath_softc *sc = hw->priv;
  681. struct ieee80211_channel *curchan = hw->conf.channel;
  682. int error = 0, pos;
  683. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
  684. "initial channel: %d MHz\n", __func__, curchan->center_freq);
  685. memset(&sc->sc_ht_info, 0, sizeof(struct ath_ht_info));
  686. /* setup initial channel */
  687. pos = ath_get_channel(sc, curchan);
  688. if (pos == -1) {
  689. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  690. error = -EINVAL;
  691. goto exit;
  692. }
  693. sc->sc_ah->ah_channels[pos].chanmode =
  694. (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
  695. error = ath_open(sc, &sc->sc_ah->ah_channels[pos]);
  696. if (error) {
  697. DPRINTF(sc, ATH_DBG_FATAL,
  698. "%s: Unable to complete ath_open\n", __func__);
  699. goto exit;
  700. }
  701. #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
  702. error = ath_start_rfkill_poll(sc);
  703. #endif
  704. exit:
  705. return error;
  706. }
  707. static int ath9k_tx(struct ieee80211_hw *hw,
  708. struct sk_buff *skb)
  709. {
  710. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  711. struct ath_softc *sc = hw->priv;
  712. struct ath_tx_control txctl;
  713. int hdrlen, padsize;
  714. memset(&txctl, 0, sizeof(struct ath_tx_control));
  715. /*
  716. * As a temporary workaround, assign seq# here; this will likely need
  717. * to be cleaned up to work better with Beacon transmission and virtual
  718. * BSSes.
  719. */
  720. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  721. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  722. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  723. sc->seq_no += 0x10;
  724. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  725. hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
  726. }
  727. /* Add the padding after the header if this is not already done */
  728. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  729. if (hdrlen & 3) {
  730. padsize = hdrlen % 4;
  731. if (skb_headroom(skb) < padsize)
  732. return -1;
  733. skb_push(skb, padsize);
  734. memmove(skb->data, skb->data + padsize, hdrlen);
  735. }
  736. /* Check if a tx queue is available */
  737. txctl.txq = ath_test_get_txq(sc, skb);
  738. if (!txctl.txq)
  739. goto exit;
  740. DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
  741. __func__,
  742. skb);
  743. if (ath_tx_start(sc, skb, &txctl) != 0) {
  744. DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
  745. goto exit;
  746. }
  747. return 0;
  748. exit:
  749. dev_kfree_skb_any(skb);
  750. return 0;
  751. }
  752. static void ath9k_stop(struct ieee80211_hw *hw)
  753. {
  754. struct ath_softc *sc = hw->priv;
  755. if (sc->sc_flags & SC_OP_INVALID) {
  756. DPRINTF(sc, ATH_DBG_ANY, "%s: Device not present\n", __func__);
  757. return;
  758. }
  759. ath_stop(sc);
  760. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
  761. }
  762. static int ath9k_add_interface(struct ieee80211_hw *hw,
  763. struct ieee80211_if_init_conf *conf)
  764. {
  765. struct ath_softc *sc = hw->priv;
  766. struct ath_vap *avp = (void *)conf->vif->drv_priv;
  767. int ic_opmode = 0;
  768. /* Support only vap for now */
  769. if (sc->sc_nvaps)
  770. return -ENOBUFS;
  771. switch (conf->type) {
  772. case NL80211_IFTYPE_STATION:
  773. ic_opmode = ATH9K_M_STA;
  774. break;
  775. case NL80211_IFTYPE_ADHOC:
  776. ic_opmode = ATH9K_M_IBSS;
  777. break;
  778. case NL80211_IFTYPE_AP:
  779. ic_opmode = ATH9K_M_HOSTAP;
  780. break;
  781. default:
  782. DPRINTF(sc, ATH_DBG_FATAL,
  783. "%s: Interface type %d not yet supported\n",
  784. __func__, conf->type);
  785. return -EOPNOTSUPP;
  786. }
  787. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
  788. __func__,
  789. ic_opmode);
  790. /* Set the VAP opmode */
  791. avp->av_opmode = ic_opmode;
  792. avp->av_bslot = -1;
  793. if (ic_opmode == ATH9K_M_HOSTAP)
  794. ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
  795. sc->sc_vaps[0] = conf->vif;
  796. sc->sc_nvaps++;
  797. /* Set the device opmode */
  798. sc->sc_ah->ah_opmode = ic_opmode;
  799. if (conf->type == NL80211_IFTYPE_AP) {
  800. /* TODO: is this a suitable place to start ANI for AP mode? */
  801. /* Start ANI */
  802. mod_timer(&sc->sc_ani.timer,
  803. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  804. }
  805. return 0;
  806. }
  807. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  808. struct ieee80211_if_init_conf *conf)
  809. {
  810. struct ath_softc *sc = hw->priv;
  811. struct ath_vap *avp = (void *)conf->vif->drv_priv;
  812. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
  813. #ifdef CONFIG_SLOW_ANT_DIV
  814. ath_slow_ant_div_stop(&sc->sc_antdiv);
  815. #endif
  816. /* Stop ANI */
  817. del_timer_sync(&sc->sc_ani.timer);
  818. /* Reclaim beacon resources */
  819. if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
  820. sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
  821. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  822. ath_beacon_return(sc, avp);
  823. }
  824. sc->sc_flags &= ~SC_OP_BEACONS;
  825. sc->sc_vaps[0] = NULL;
  826. sc->sc_nvaps--;
  827. }
  828. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  829. {
  830. struct ath_softc *sc = hw->priv;
  831. struct ieee80211_channel *curchan = hw->conf.channel;
  832. struct ieee80211_conf *conf = &hw->conf;
  833. int pos;
  834. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  835. __func__,
  836. curchan->center_freq);
  837. /* Update chainmask */
  838. ath_update_chainmask(sc, conf->ht.enabled);
  839. pos = ath_get_channel(sc, curchan);
  840. if (pos == -1) {
  841. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  842. return -EINVAL;
  843. }
  844. sc->sc_ah->ah_channels[pos].chanmode =
  845. (curchan->band == IEEE80211_BAND_2GHZ) ?
  846. CHANNEL_G : CHANNEL_A;
  847. if (sc->sc_curaid && hw->conf.ht.enabled)
  848. sc->sc_ah->ah_channels[pos].chanmode =
  849. ath_get_extchanmode(sc, curchan);
  850. if (changed & IEEE80211_CONF_CHANGE_POWER)
  851. sc->sc_config.txpowlimit = 2 * conf->power_level;
  852. /* set h/w channel */
  853. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  854. DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
  855. __func__);
  856. return 0;
  857. }
  858. static int ath9k_config_interface(struct ieee80211_hw *hw,
  859. struct ieee80211_vif *vif,
  860. struct ieee80211_if_conf *conf)
  861. {
  862. struct ath_softc *sc = hw->priv;
  863. struct ath_hal *ah = sc->sc_ah;
  864. struct ath_vap *avp = (void *)vif->drv_priv;
  865. u32 rfilt = 0;
  866. int error, i;
  867. /* TODO: Need to decide which hw opmode to use for multi-interface
  868. * cases */
  869. if (vif->type == NL80211_IFTYPE_AP &&
  870. ah->ah_opmode != ATH9K_M_HOSTAP) {
  871. ah->ah_opmode = ATH9K_M_HOSTAP;
  872. ath9k_hw_setopmode(ah);
  873. ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
  874. /* Request full reset to get hw opmode changed properly */
  875. sc->sc_flags |= SC_OP_FULL_RESET;
  876. }
  877. if ((conf->changed & IEEE80211_IFCC_BSSID) &&
  878. !is_zero_ether_addr(conf->bssid)) {
  879. switch (vif->type) {
  880. case NL80211_IFTYPE_STATION:
  881. case NL80211_IFTYPE_ADHOC:
  882. /* Set BSSID */
  883. memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
  884. sc->sc_curaid = 0;
  885. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  886. sc->sc_curaid);
  887. /* Set aggregation protection mode parameters */
  888. sc->sc_config.ath_aggr_prot = 0;
  889. DPRINTF(sc, ATH_DBG_CONFIG,
  890. "%s: RX filter 0x%x bssid %pM aid 0x%x\n",
  891. __func__, rfilt,
  892. sc->sc_curbssid, sc->sc_curaid);
  893. /* need to reconfigure the beacon */
  894. sc->sc_flags &= ~SC_OP_BEACONS ;
  895. break;
  896. default:
  897. break;
  898. }
  899. }
  900. if ((conf->changed & IEEE80211_IFCC_BEACON) &&
  901. ((vif->type == NL80211_IFTYPE_ADHOC) ||
  902. (vif->type == NL80211_IFTYPE_AP))) {
  903. /*
  904. * Allocate and setup the beacon frame.
  905. *
  906. * Stop any previous beacon DMA. This may be
  907. * necessary, for example, when an ibss merge
  908. * causes reconfiguration; we may be called
  909. * with beacon transmission active.
  910. */
  911. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  912. error = ath_beacon_alloc(sc, 0);
  913. if (error != 0)
  914. return error;
  915. ath_beacon_sync(sc, 0);
  916. }
  917. /* Check for WLAN_CAPABILITY_PRIVACY ? */
  918. if ((avp->av_opmode != ATH9K_M_STA)) {
  919. for (i = 0; i < IEEE80211_WEP_NKID; i++)
  920. if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
  921. ath9k_hw_keysetmac(sc->sc_ah,
  922. (u16)i,
  923. sc->sc_curbssid);
  924. }
  925. /* Only legacy IBSS for now */
  926. if (vif->type == NL80211_IFTYPE_ADHOC)
  927. ath_update_chainmask(sc, 0);
  928. return 0;
  929. }
  930. #define SUPPORTED_FILTERS \
  931. (FIF_PROMISC_IN_BSS | \
  932. FIF_ALLMULTI | \
  933. FIF_CONTROL | \
  934. FIF_OTHER_BSS | \
  935. FIF_BCN_PRBRESP_PROMISC | \
  936. FIF_FCSFAIL)
  937. /* FIXME: sc->sc_full_reset ? */
  938. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  939. unsigned int changed_flags,
  940. unsigned int *total_flags,
  941. int mc_count,
  942. struct dev_mc_list *mclist)
  943. {
  944. struct ath_softc *sc = hw->priv;
  945. u32 rfilt;
  946. changed_flags &= SUPPORTED_FILTERS;
  947. *total_flags &= SUPPORTED_FILTERS;
  948. sc->rx_filter = *total_flags;
  949. rfilt = ath_calcrxfilter(sc);
  950. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  951. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  952. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  953. ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
  954. }
  955. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n",
  956. __func__, sc->rx_filter);
  957. }
  958. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  959. struct ieee80211_vif *vif,
  960. enum sta_notify_cmd cmd,
  961. struct ieee80211_sta *sta)
  962. {
  963. struct ath_softc *sc = hw->priv;
  964. switch (cmd) {
  965. case STA_NOTIFY_ADD:
  966. ath_node_attach(sc, sta);
  967. break;
  968. case STA_NOTIFY_REMOVE:
  969. ath_node_detach(sc, sta);
  970. break;
  971. default:
  972. break;
  973. }
  974. }
  975. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  976. u16 queue,
  977. const struct ieee80211_tx_queue_params *params)
  978. {
  979. struct ath_softc *sc = hw->priv;
  980. struct ath9k_tx_queue_info qi;
  981. int ret = 0, qnum;
  982. if (queue >= WME_NUM_AC)
  983. return 0;
  984. qi.tqi_aifs = params->aifs;
  985. qi.tqi_cwmin = params->cw_min;
  986. qi.tqi_cwmax = params->cw_max;
  987. qi.tqi_burstTime = params->txop;
  988. qnum = ath_get_hal_qnum(queue, sc);
  989. DPRINTF(sc, ATH_DBG_CONFIG,
  990. "%s: Configure tx [queue/halq] [%d/%d], "
  991. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  992. __func__,
  993. queue,
  994. qnum,
  995. params->aifs,
  996. params->cw_min,
  997. params->cw_max,
  998. params->txop);
  999. ret = ath_txq_update(sc, qnum, &qi);
  1000. if (ret)
  1001. DPRINTF(sc, ATH_DBG_FATAL,
  1002. "%s: TXQ Update failed\n", __func__);
  1003. return ret;
  1004. }
  1005. static int ath9k_set_key(struct ieee80211_hw *hw,
  1006. enum set_key_cmd cmd,
  1007. const u8 *local_addr,
  1008. const u8 *addr,
  1009. struct ieee80211_key_conf *key)
  1010. {
  1011. struct ath_softc *sc = hw->priv;
  1012. int ret = 0;
  1013. DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
  1014. switch (cmd) {
  1015. case SET_KEY:
  1016. ret = ath_key_config(sc, addr, key);
  1017. if (!ret) {
  1018. set_bit(key->keyidx, sc->sc_keymap);
  1019. key->hw_key_idx = key->keyidx;
  1020. /* push IV and Michael MIC generation to stack */
  1021. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1022. if (key->alg == ALG_TKIP)
  1023. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1024. }
  1025. break;
  1026. case DISABLE_KEY:
  1027. ath_key_delete(sc, key);
  1028. clear_bit(key->keyidx, sc->sc_keymap);
  1029. break;
  1030. default:
  1031. ret = -EINVAL;
  1032. }
  1033. return ret;
  1034. }
  1035. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1036. struct ieee80211_vif *vif,
  1037. struct ieee80211_bss_conf *bss_conf,
  1038. u32 changed)
  1039. {
  1040. struct ath_softc *sc = hw->priv;
  1041. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1042. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
  1043. __func__,
  1044. bss_conf->use_short_preamble);
  1045. if (bss_conf->use_short_preamble)
  1046. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1047. else
  1048. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1049. }
  1050. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1051. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
  1052. __func__,
  1053. bss_conf->use_cts_prot);
  1054. if (bss_conf->use_cts_prot &&
  1055. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1056. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1057. else
  1058. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1059. }
  1060. if (changed & BSS_CHANGED_HT) {
  1061. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT\n",
  1062. __func__);
  1063. ath9k_ht_conf(sc, bss_conf);
  1064. }
  1065. if (changed & BSS_CHANGED_ASSOC) {
  1066. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
  1067. __func__,
  1068. bss_conf->assoc);
  1069. ath9k_bss_assoc_info(sc, vif, bss_conf);
  1070. }
  1071. }
  1072. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1073. {
  1074. u64 tsf;
  1075. struct ath_softc *sc = hw->priv;
  1076. struct ath_hal *ah = sc->sc_ah;
  1077. tsf = ath9k_hw_gettsf64(ah);
  1078. return tsf;
  1079. }
  1080. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1081. {
  1082. struct ath_softc *sc = hw->priv;
  1083. struct ath_hal *ah = sc->sc_ah;
  1084. ath9k_hw_reset_tsf(ah);
  1085. }
  1086. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1087. enum ieee80211_ampdu_mlme_action action,
  1088. struct ieee80211_sta *sta,
  1089. u16 tid, u16 *ssn)
  1090. {
  1091. struct ath_softc *sc = hw->priv;
  1092. int ret = 0;
  1093. switch (action) {
  1094. case IEEE80211_AMPDU_RX_START:
  1095. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1096. ret = -ENOTSUPP;
  1097. break;
  1098. case IEEE80211_AMPDU_RX_STOP:
  1099. break;
  1100. case IEEE80211_AMPDU_TX_START:
  1101. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1102. if (ret < 0)
  1103. DPRINTF(sc, ATH_DBG_FATAL,
  1104. "%s: Unable to start TX aggregation\n",
  1105. __func__);
  1106. else
  1107. ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
  1108. break;
  1109. case IEEE80211_AMPDU_TX_STOP:
  1110. ret = ath_tx_aggr_stop(sc, sta, tid);
  1111. if (ret < 0)
  1112. DPRINTF(sc, ATH_DBG_FATAL,
  1113. "%s: Unable to stop TX aggregation\n",
  1114. __func__);
  1115. ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
  1116. break;
  1117. case IEEE80211_AMPDU_TX_RESUME:
  1118. ath_tx_aggr_resume(sc, sta, tid);
  1119. break;
  1120. default:
  1121. DPRINTF(sc, ATH_DBG_FATAL,
  1122. "%s: Unknown AMPDU action\n", __func__);
  1123. }
  1124. return ret;
  1125. }
  1126. static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
  1127. {
  1128. return -EOPNOTSUPP;
  1129. }
  1130. static struct ieee80211_ops ath9k_ops = {
  1131. .tx = ath9k_tx,
  1132. .start = ath9k_start,
  1133. .stop = ath9k_stop,
  1134. .add_interface = ath9k_add_interface,
  1135. .remove_interface = ath9k_remove_interface,
  1136. .config = ath9k_config,
  1137. .config_interface = ath9k_config_interface,
  1138. .configure_filter = ath9k_configure_filter,
  1139. .sta_notify = ath9k_sta_notify,
  1140. .conf_tx = ath9k_conf_tx,
  1141. .bss_info_changed = ath9k_bss_info_changed,
  1142. .set_key = ath9k_set_key,
  1143. .get_tsf = ath9k_get_tsf,
  1144. .reset_tsf = ath9k_reset_tsf,
  1145. .ampdu_action = ath9k_ampdu_action,
  1146. .set_frag_threshold = ath9k_no_fragmentation,
  1147. };
  1148. static struct {
  1149. u32 version;
  1150. const char * name;
  1151. } ath_mac_bb_names[] = {
  1152. { AR_SREV_VERSION_5416_PCI, "5416" },
  1153. { AR_SREV_VERSION_5416_PCIE, "5418" },
  1154. { AR_SREV_VERSION_9100, "9100" },
  1155. { AR_SREV_VERSION_9160, "9160" },
  1156. { AR_SREV_VERSION_9280, "9280" },
  1157. { AR_SREV_VERSION_9285, "9285" }
  1158. };
  1159. static struct {
  1160. u16 version;
  1161. const char * name;
  1162. } ath_rf_names[] = {
  1163. { 0, "5133" },
  1164. { AR_RAD5133_SREV_MAJOR, "5133" },
  1165. { AR_RAD5122_SREV_MAJOR, "5122" },
  1166. { AR_RAD2133_SREV_MAJOR, "2133" },
  1167. { AR_RAD2122_SREV_MAJOR, "2122" }
  1168. };
  1169. /*
  1170. * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
  1171. */
  1172. static const char *
  1173. ath_mac_bb_name(u32 mac_bb_version)
  1174. {
  1175. int i;
  1176. for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
  1177. if (ath_mac_bb_names[i].version == mac_bb_version) {
  1178. return ath_mac_bb_names[i].name;
  1179. }
  1180. }
  1181. return "????";
  1182. }
  1183. /*
  1184. * Return the RF name. "????" is returned if the RF is unknown.
  1185. */
  1186. static const char *
  1187. ath_rf_name(u16 rf_version)
  1188. {
  1189. int i;
  1190. for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
  1191. if (ath_rf_names[i].version == rf_version) {
  1192. return ath_rf_names[i].name;
  1193. }
  1194. }
  1195. return "????";
  1196. }
  1197. static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1198. {
  1199. void __iomem *mem;
  1200. struct ath_softc *sc;
  1201. struct ieee80211_hw *hw;
  1202. u8 csz;
  1203. u32 val;
  1204. int ret = 0;
  1205. struct ath_hal *ah;
  1206. if (pci_enable_device(pdev))
  1207. return -EIO;
  1208. ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  1209. if (ret) {
  1210. printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
  1211. goto bad;
  1212. }
  1213. ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  1214. if (ret) {
  1215. printk(KERN_ERR "ath9k: 32-bit DMA consistent "
  1216. "DMA enable faled\n");
  1217. goto bad;
  1218. }
  1219. /*
  1220. * Cache line size is used to size and align various
  1221. * structures used to communicate with the hardware.
  1222. */
  1223. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
  1224. if (csz == 0) {
  1225. /*
  1226. * Linux 2.4.18 (at least) writes the cache line size
  1227. * register as a 16-bit wide register which is wrong.
  1228. * We must have this setup properly for rx buffer
  1229. * DMA to work so force a reasonable value here if it
  1230. * comes up zero.
  1231. */
  1232. csz = L1_CACHE_BYTES / sizeof(u32);
  1233. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
  1234. }
  1235. /*
  1236. * The default setting of latency timer yields poor results,
  1237. * set it to the value used by other systems. It may be worth
  1238. * tweaking this setting more.
  1239. */
  1240. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
  1241. pci_set_master(pdev);
  1242. /*
  1243. * Disable the RETRY_TIMEOUT register (0x41) to keep
  1244. * PCI Tx retries from interfering with C3 CPU state.
  1245. */
  1246. pci_read_config_dword(pdev, 0x40, &val);
  1247. if ((val & 0x0000ff00) != 0)
  1248. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1249. ret = pci_request_region(pdev, 0, "ath9k");
  1250. if (ret) {
  1251. dev_err(&pdev->dev, "PCI memory region reserve error\n");
  1252. ret = -ENODEV;
  1253. goto bad;
  1254. }
  1255. mem = pci_iomap(pdev, 0, 0);
  1256. if (!mem) {
  1257. printk(KERN_ERR "PCI memory map error\n") ;
  1258. ret = -EIO;
  1259. goto bad1;
  1260. }
  1261. hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
  1262. if (hw == NULL) {
  1263. printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
  1264. goto bad2;
  1265. }
  1266. SET_IEEE80211_DEV(hw, &pdev->dev);
  1267. pci_set_drvdata(pdev, hw);
  1268. sc = hw->priv;
  1269. sc->hw = hw;
  1270. sc->pdev = pdev;
  1271. sc->mem = mem;
  1272. if (ath_attach(id->device, sc) != 0) {
  1273. ret = -ENODEV;
  1274. goto bad3;
  1275. }
  1276. /* setup interrupt service routine */
  1277. if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
  1278. printk(KERN_ERR "%s: request_irq failed\n",
  1279. wiphy_name(hw->wiphy));
  1280. ret = -EIO;
  1281. goto bad4;
  1282. }
  1283. ah = sc->sc_ah;
  1284. printk(KERN_INFO
  1285. "%s: Atheros AR%s MAC/BB Rev:%x "
  1286. "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
  1287. wiphy_name(hw->wiphy),
  1288. ath_mac_bb_name(ah->ah_macVersion),
  1289. ah->ah_macRev,
  1290. ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
  1291. ah->ah_phyRev,
  1292. (unsigned long)mem, pdev->irq);
  1293. return 0;
  1294. bad4:
  1295. ath_detach(sc);
  1296. bad3:
  1297. ieee80211_free_hw(hw);
  1298. bad2:
  1299. pci_iounmap(pdev, mem);
  1300. bad1:
  1301. pci_release_region(pdev, 0);
  1302. bad:
  1303. pci_disable_device(pdev);
  1304. return ret;
  1305. }
  1306. static void ath_pci_remove(struct pci_dev *pdev)
  1307. {
  1308. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1309. struct ath_softc *sc = hw->priv;
  1310. ath_detach(sc);
  1311. if (pdev->irq)
  1312. free_irq(pdev->irq, sc);
  1313. pci_iounmap(pdev, sc->mem);
  1314. pci_release_region(pdev, 0);
  1315. pci_disable_device(pdev);
  1316. ieee80211_free_hw(hw);
  1317. }
  1318. #ifdef CONFIG_PM
  1319. static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  1320. {
  1321. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1322. struct ath_softc *sc = hw->priv;
  1323. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  1324. #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
  1325. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1326. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  1327. #endif
  1328. pci_save_state(pdev);
  1329. pci_disable_device(pdev);
  1330. pci_set_power_state(pdev, 3);
  1331. return 0;
  1332. }
  1333. static int ath_pci_resume(struct pci_dev *pdev)
  1334. {
  1335. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1336. struct ath_softc *sc = hw->priv;
  1337. u32 val;
  1338. int err;
  1339. err = pci_enable_device(pdev);
  1340. if (err)
  1341. return err;
  1342. pci_restore_state(pdev);
  1343. /*
  1344. * Suspend/Resume resets the PCI configuration space, so we have to
  1345. * re-disable the RETRY_TIMEOUT register (0x41) to keep
  1346. * PCI Tx retries from interfering with C3 CPU state
  1347. */
  1348. pci_read_config_dword(pdev, 0x40, &val);
  1349. if ((val & 0x0000ff00) != 0)
  1350. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1351. /* Enable LED */
  1352. ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
  1353. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  1354. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  1355. #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
  1356. /*
  1357. * check the h/w rfkill state on resume
  1358. * and start the rfkill poll timer
  1359. */
  1360. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1361. queue_delayed_work(sc->hw->workqueue,
  1362. &sc->rf_kill.rfkill_poll, 0);
  1363. #endif
  1364. return 0;
  1365. }
  1366. #endif /* CONFIG_PM */
  1367. MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
  1368. static struct pci_driver ath_pci_driver = {
  1369. .name = "ath9k",
  1370. .id_table = ath_pci_id_table,
  1371. .probe = ath_pci_probe,
  1372. .remove = ath_pci_remove,
  1373. #ifdef CONFIG_PM
  1374. .suspend = ath_pci_suspend,
  1375. .resume = ath_pci_resume,
  1376. #endif /* CONFIG_PM */
  1377. };
  1378. static int __init init_ath_pci(void)
  1379. {
  1380. printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
  1381. if (pci_register_driver(&ath_pci_driver) < 0) {
  1382. printk(KERN_ERR
  1383. "ath_pci: No devices found, driver not installed.\n");
  1384. pci_unregister_driver(&ath_pci_driver);
  1385. return -ENODEV;
  1386. }
  1387. return 0;
  1388. }
  1389. module_init(init_ath_pci);
  1390. static void __exit exit_ath_pci(void)
  1391. {
  1392. pci_unregister_driver(&ath_pci_driver);
  1393. printk(KERN_INFO "%s: driver unloaded\n", dev_info);
  1394. }
  1395. module_exit(exit_ath_pci);