r8a66597-udc.h 6.1 KB

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  1. /*
  2. * R8A66597 UDC
  3. *
  4. * Copyright (C) 2007-2009 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #ifndef __R8A66597_H__
  23. #define __R8A66597_H__
  24. #include <linux/usb/r8a66597.h>
  25. #define R8A66597_MAX_SAMPLING 10
  26. #define R8A66597_MAX_NUM_PIPE 8
  27. #define R8A66597_MAX_NUM_BULK 3
  28. #define R8A66597_MAX_NUM_ISOC 2
  29. #define R8A66597_MAX_NUM_INT 2
  30. #define R8A66597_BASE_PIPENUM_BULK 3
  31. #define R8A66597_BASE_PIPENUM_ISOC 1
  32. #define R8A66597_BASE_PIPENUM_INT 6
  33. #define R8A66597_BASE_BUFNUM 6
  34. #define R8A66597_MAX_BUFNUM 0x4F
  35. #define is_bulk_pipe(pipenum) \
  36. ((pipenum >= R8A66597_BASE_PIPENUM_BULK) && \
  37. (pipenum < (R8A66597_BASE_PIPENUM_BULK + R8A66597_MAX_NUM_BULK)))
  38. #define is_interrupt_pipe(pipenum) \
  39. ((pipenum >= R8A66597_BASE_PIPENUM_INT) && \
  40. (pipenum < (R8A66597_BASE_PIPENUM_INT + R8A66597_MAX_NUM_INT)))
  41. #define is_isoc_pipe(pipenum) \
  42. ((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \
  43. (pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC)))
  44. struct r8a66597_pipe_info {
  45. u16 pipe;
  46. u16 epnum;
  47. u16 maxpacket;
  48. u16 type;
  49. u16 interval;
  50. u16 dir_in;
  51. };
  52. struct r8a66597_request {
  53. struct usb_request req;
  54. struct list_head queue;
  55. };
  56. struct r8a66597_ep {
  57. struct usb_ep ep;
  58. struct r8a66597 *r8a66597;
  59. struct list_head queue;
  60. unsigned busy:1;
  61. unsigned internal_ccpl:1; /* use only control */
  62. /* this member can able to after r8a66597_enable */
  63. unsigned use_dma:1;
  64. u16 pipenum;
  65. u16 type;
  66. const struct usb_endpoint_descriptor *desc;
  67. /* register address */
  68. unsigned char fifoaddr;
  69. unsigned char fifosel;
  70. unsigned char fifoctr;
  71. unsigned char fifotrn;
  72. unsigned char pipectr;
  73. };
  74. struct r8a66597 {
  75. spinlock_t lock;
  76. unsigned long reg;
  77. struct r8a66597_platdata *pdata;
  78. struct usb_gadget gadget;
  79. struct usb_gadget_driver *driver;
  80. struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE];
  81. struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE];
  82. struct r8a66597_ep *epaddr2ep[16];
  83. struct timer_list timer;
  84. struct usb_request *ep0_req; /* for internal request */
  85. u16 ep0_data; /* for internal request */
  86. u16 old_vbus;
  87. u16 scount;
  88. u16 old_dvsq;
  89. /* pipe config */
  90. unsigned short bi_bufnum; /* bulk and isochronous's bufnum */
  91. unsigned char bulk;
  92. unsigned char interrupt;
  93. unsigned char isochronous;
  94. unsigned char num_dma;
  95. unsigned irq_sense_low:1;
  96. };
  97. #define gadget_to_r8a66597(_gadget) \
  98. container_of(_gadget, struct r8a66597, gadget)
  99. #define r8a66597_to_gadget(r8a66597) (&r8a66597->gadget)
  100. static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
  101. {
  102. return inw(r8a66597->reg + offset);
  103. }
  104. static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
  105. unsigned long offset, u16 *buf,
  106. int len)
  107. {
  108. if (r8a66597->pdata->on_chip) {
  109. unsigned long fifoaddr = r8a66597->reg + offset;
  110. unsigned long count;
  111. union {
  112. unsigned long dword;
  113. unsigned char byte[4];
  114. } data;
  115. unsigned char *pb;
  116. int i;
  117. count = len / 4;
  118. insl(fifoaddr, buf, count);
  119. if (len & 0x00000003) {
  120. data.dword = inl(fifoaddr);
  121. pb = (unsigned char *)buf + count * 4;
  122. for (i = 0; i < (len & 0x00000003); i++)
  123. pb[i] = data.byte[i];
  124. }
  125. } else {
  126. len = (len + 1) / 2;
  127. insw(r8a66597->reg + offset, buf, len);
  128. }
  129. }
  130. static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
  131. unsigned long offset)
  132. {
  133. outw(val, r8a66597->reg + offset);
  134. }
  135. static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
  136. unsigned long offset, u16 *buf,
  137. int len)
  138. {
  139. unsigned long fifoaddr = r8a66597->reg + offset;
  140. if (r8a66597->pdata->on_chip) {
  141. unsigned long count;
  142. unsigned char *pb;
  143. int i;
  144. count = len / 4;
  145. outsl(fifoaddr, buf, count);
  146. if (len & 0x00000003) {
  147. pb = (unsigned char *)buf + count * 4;
  148. for (i = 0; i < (len & 0x00000003); i++) {
  149. if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
  150. outb(pb[i], fifoaddr + i);
  151. else
  152. outb(pb[i], fifoaddr + 3 - i);
  153. }
  154. }
  155. } else {
  156. int odd = len & 0x0001;
  157. len = len / 2;
  158. outsw(fifoaddr, buf, len);
  159. if (unlikely(odd)) {
  160. buf = &buf[len];
  161. outb((unsigned char)*buf, fifoaddr);
  162. }
  163. }
  164. }
  165. static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
  166. u16 val, u16 pat, unsigned long offset)
  167. {
  168. u16 tmp;
  169. tmp = r8a66597_read(r8a66597, offset);
  170. tmp = tmp & (~pat);
  171. tmp = tmp | val;
  172. r8a66597_write(r8a66597, tmp, offset);
  173. }
  174. static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
  175. {
  176. u16 clock = 0;
  177. switch (pdata->xtal) {
  178. case R8A66597_PLATDATA_XTAL_12MHZ:
  179. clock = XTAL12;
  180. break;
  181. case R8A66597_PLATDATA_XTAL_24MHZ:
  182. clock = XTAL24;
  183. break;
  184. case R8A66597_PLATDATA_XTAL_48MHZ:
  185. clock = XTAL48;
  186. break;
  187. default:
  188. printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
  189. break;
  190. }
  191. return clock;
  192. }
  193. #define r8a66597_bclr(r8a66597, val, offset) \
  194. r8a66597_mdfy(r8a66597, 0, val, offset)
  195. #define r8a66597_bset(r8a66597, val, offset) \
  196. r8a66597_mdfy(r8a66597, val, 0, offset)
  197. #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
  198. #define enable_irq_ready(r8a66597, pipenum) \
  199. enable_pipe_irq(r8a66597, pipenum, BRDYENB)
  200. #define disable_irq_ready(r8a66597, pipenum) \
  201. disable_pipe_irq(r8a66597, pipenum, BRDYENB)
  202. #define enable_irq_empty(r8a66597, pipenum) \
  203. enable_pipe_irq(r8a66597, pipenum, BEMPENB)
  204. #define disable_irq_empty(r8a66597, pipenum) \
  205. disable_pipe_irq(r8a66597, pipenum, BEMPENB)
  206. #define enable_irq_nrdy(r8a66597, pipenum) \
  207. enable_pipe_irq(r8a66597, pipenum, NRDYENB)
  208. #define disable_irq_nrdy(r8a66597, pipenum) \
  209. disable_pipe_irq(r8a66597, pipenum, NRDYENB)
  210. #endif /* __R8A66597_H__ */