r8a66597-udc.c 40 KB

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  1. /*
  2. * R8A66597 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2009 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/usb/ch9.h>
  28. #include <linux/usb/gadget.h>
  29. #include "r8a66597-udc.h"
  30. #define DRIVER_VERSION "2009-08-18"
  31. static const char udc_name[] = "r8a66597_udc";
  32. static const char *r8a66597_ep_name[] = {
  33. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7",
  34. "ep8", "ep9",
  35. };
  36. static void disable_controller(struct r8a66597 *r8a66597);
  37. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req);
  38. static void irq_packet_write(struct r8a66597_ep *ep,
  39. struct r8a66597_request *req);
  40. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  41. gfp_t gfp_flags);
  42. static void transfer_complete(struct r8a66597_ep *ep,
  43. struct r8a66597_request *req, int status);
  44. /*-------------------------------------------------------------------------*/
  45. static inline u16 get_usb_speed(struct r8a66597 *r8a66597)
  46. {
  47. return r8a66597_read(r8a66597, DVSTCTR0) & RHST;
  48. }
  49. static void enable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  50. unsigned long reg)
  51. {
  52. u16 tmp;
  53. tmp = r8a66597_read(r8a66597, INTENB0);
  54. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  55. INTENB0);
  56. r8a66597_bset(r8a66597, (1 << pipenum), reg);
  57. r8a66597_write(r8a66597, tmp, INTENB0);
  58. }
  59. static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  60. unsigned long reg)
  61. {
  62. u16 tmp;
  63. tmp = r8a66597_read(r8a66597, INTENB0);
  64. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  65. INTENB0);
  66. r8a66597_bclr(r8a66597, (1 << pipenum), reg);
  67. r8a66597_write(r8a66597, tmp, INTENB0);
  68. }
  69. static void r8a66597_usb_connect(struct r8a66597 *r8a66597)
  70. {
  71. r8a66597_bset(r8a66597, CTRE, INTENB0);
  72. r8a66597_bset(r8a66597, BEMPE | BRDYE, INTENB0);
  73. r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
  74. }
  75. static void r8a66597_usb_disconnect(struct r8a66597 *r8a66597)
  76. __releases(r8a66597->lock)
  77. __acquires(r8a66597->lock)
  78. {
  79. r8a66597_bclr(r8a66597, CTRE, INTENB0);
  80. r8a66597_bclr(r8a66597, BEMPE | BRDYE, INTENB0);
  81. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  82. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  83. spin_unlock(&r8a66597->lock);
  84. r8a66597->driver->disconnect(&r8a66597->gadget);
  85. spin_lock(&r8a66597->lock);
  86. disable_controller(r8a66597);
  87. INIT_LIST_HEAD(&r8a66597->ep[0].queue);
  88. }
  89. static inline u16 control_reg_get_pid(struct r8a66597 *r8a66597, u16 pipenum)
  90. {
  91. u16 pid = 0;
  92. unsigned long offset;
  93. if (pipenum == 0)
  94. pid = r8a66597_read(r8a66597, DCPCTR) & PID;
  95. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  96. offset = get_pipectr_addr(pipenum);
  97. pid = r8a66597_read(r8a66597, offset) & PID;
  98. } else
  99. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  100. return pid;
  101. }
  102. static inline void control_reg_set_pid(struct r8a66597 *r8a66597, u16 pipenum,
  103. u16 pid)
  104. {
  105. unsigned long offset;
  106. if (pipenum == 0)
  107. r8a66597_mdfy(r8a66597, pid, PID, DCPCTR);
  108. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  109. offset = get_pipectr_addr(pipenum);
  110. r8a66597_mdfy(r8a66597, pid, PID, offset);
  111. } else
  112. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  113. }
  114. static inline void pipe_start(struct r8a66597 *r8a66597, u16 pipenum)
  115. {
  116. control_reg_set_pid(r8a66597, pipenum, PID_BUF);
  117. }
  118. static inline void pipe_stop(struct r8a66597 *r8a66597, u16 pipenum)
  119. {
  120. control_reg_set_pid(r8a66597, pipenum, PID_NAK);
  121. }
  122. static inline void pipe_stall(struct r8a66597 *r8a66597, u16 pipenum)
  123. {
  124. control_reg_set_pid(r8a66597, pipenum, PID_STALL);
  125. }
  126. static inline u16 control_reg_get(struct r8a66597 *r8a66597, u16 pipenum)
  127. {
  128. u16 ret = 0;
  129. unsigned long offset;
  130. if (pipenum == 0)
  131. ret = r8a66597_read(r8a66597, DCPCTR);
  132. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  133. offset = get_pipectr_addr(pipenum);
  134. ret = r8a66597_read(r8a66597, offset);
  135. } else
  136. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  137. return ret;
  138. }
  139. static inline void control_reg_sqclr(struct r8a66597 *r8a66597, u16 pipenum)
  140. {
  141. unsigned long offset;
  142. pipe_stop(r8a66597, pipenum);
  143. if (pipenum == 0)
  144. r8a66597_bset(r8a66597, SQCLR, DCPCTR);
  145. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  146. offset = get_pipectr_addr(pipenum);
  147. r8a66597_bset(r8a66597, SQCLR, offset);
  148. } else
  149. printk(KERN_ERR "unexpect pipe num(%d)\n", pipenum);
  150. }
  151. static inline int get_buffer_size(struct r8a66597 *r8a66597, u16 pipenum)
  152. {
  153. u16 tmp;
  154. int size;
  155. if (pipenum == 0) {
  156. tmp = r8a66597_read(r8a66597, DCPCFG);
  157. if ((tmp & R8A66597_CNTMD) != 0)
  158. size = 256;
  159. else {
  160. tmp = r8a66597_read(r8a66597, DCPMAXP);
  161. size = tmp & MAXP;
  162. }
  163. } else {
  164. r8a66597_write(r8a66597, pipenum, PIPESEL);
  165. tmp = r8a66597_read(r8a66597, PIPECFG);
  166. if ((tmp & R8A66597_CNTMD) != 0) {
  167. tmp = r8a66597_read(r8a66597, PIPEBUF);
  168. size = ((tmp >> 10) + 1) * 64;
  169. } else {
  170. tmp = r8a66597_read(r8a66597, PIPEMAXP);
  171. size = tmp & MXPS;
  172. }
  173. }
  174. return size;
  175. }
  176. static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
  177. {
  178. if (r8a66597->pdata->on_chip)
  179. return MBW_32;
  180. else
  181. return MBW_16;
  182. }
  183. static inline void pipe_change(struct r8a66597 *r8a66597, u16 pipenum)
  184. {
  185. struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
  186. if (ep->use_dma)
  187. return;
  188. r8a66597_mdfy(r8a66597, pipenum, CURPIPE, ep->fifosel);
  189. ndelay(450);
  190. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  191. }
  192. static int pipe_buffer_setting(struct r8a66597 *r8a66597,
  193. struct r8a66597_pipe_info *info)
  194. {
  195. u16 bufnum = 0, buf_bsize = 0;
  196. u16 pipecfg = 0;
  197. if (info->pipe == 0)
  198. return -EINVAL;
  199. r8a66597_write(r8a66597, info->pipe, PIPESEL);
  200. if (info->dir_in)
  201. pipecfg |= R8A66597_DIR;
  202. pipecfg |= info->type;
  203. pipecfg |= info->epnum;
  204. switch (info->type) {
  205. case R8A66597_INT:
  206. bufnum = 4 + (info->pipe - R8A66597_BASE_PIPENUM_INT);
  207. buf_bsize = 0;
  208. break;
  209. case R8A66597_BULK:
  210. bufnum = r8a66597->bi_bufnum +
  211. (info->pipe - R8A66597_BASE_PIPENUM_BULK) * 16;
  212. r8a66597->bi_bufnum += 16;
  213. buf_bsize = 7;
  214. pipecfg |= R8A66597_DBLB;
  215. if (!info->dir_in)
  216. pipecfg |= R8A66597_SHTNAK;
  217. break;
  218. case R8A66597_ISO:
  219. bufnum = r8a66597->bi_bufnum +
  220. (info->pipe - R8A66597_BASE_PIPENUM_ISOC) * 16;
  221. r8a66597->bi_bufnum += 16;
  222. buf_bsize = 7;
  223. break;
  224. }
  225. if (r8a66597->bi_bufnum > R8A66597_MAX_BUFNUM) {
  226. printk(KERN_ERR "r8a66597 pipe memory is insufficient(%d)\n",
  227. r8a66597->bi_bufnum);
  228. return -ENOMEM;
  229. }
  230. r8a66597_write(r8a66597, pipecfg, PIPECFG);
  231. r8a66597_write(r8a66597, (buf_bsize << 10) | (bufnum), PIPEBUF);
  232. r8a66597_write(r8a66597, info->maxpacket, PIPEMAXP);
  233. if (info->interval)
  234. info->interval--;
  235. r8a66597_write(r8a66597, info->interval, PIPEPERI);
  236. return 0;
  237. }
  238. static void pipe_buffer_release(struct r8a66597 *r8a66597,
  239. struct r8a66597_pipe_info *info)
  240. {
  241. if (info->pipe == 0)
  242. return;
  243. switch (info->type) {
  244. case R8A66597_BULK:
  245. if (is_bulk_pipe(info->pipe))
  246. r8a66597->bi_bufnum -= 16;
  247. break;
  248. case R8A66597_ISO:
  249. if (is_isoc_pipe(info->pipe))
  250. r8a66597->bi_bufnum -= 16;
  251. break;
  252. }
  253. if (is_bulk_pipe(info->pipe))
  254. r8a66597->bulk--;
  255. else if (is_interrupt_pipe(info->pipe))
  256. r8a66597->interrupt--;
  257. else if (is_isoc_pipe(info->pipe)) {
  258. r8a66597->isochronous--;
  259. if (info->type == R8A66597_BULK)
  260. r8a66597->bulk--;
  261. } else
  262. printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
  263. info->pipe);
  264. }
  265. static void pipe_initialize(struct r8a66597_ep *ep)
  266. {
  267. struct r8a66597 *r8a66597 = ep->r8a66597;
  268. r8a66597_mdfy(r8a66597, 0, CURPIPE, ep->fifosel);
  269. r8a66597_write(r8a66597, ACLRM, ep->pipectr);
  270. r8a66597_write(r8a66597, 0, ep->pipectr);
  271. r8a66597_write(r8a66597, SQCLR, ep->pipectr);
  272. if (ep->use_dma) {
  273. r8a66597_mdfy(r8a66597, ep->pipenum, CURPIPE, ep->fifosel);
  274. ndelay(450);
  275. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  276. }
  277. }
  278. static void r8a66597_ep_setting(struct r8a66597 *r8a66597,
  279. struct r8a66597_ep *ep,
  280. const struct usb_endpoint_descriptor *desc,
  281. u16 pipenum, int dma)
  282. {
  283. ep->use_dma = 0;
  284. ep->fifoaddr = CFIFO;
  285. ep->fifosel = CFIFOSEL;
  286. ep->fifoctr = CFIFOCTR;
  287. ep->fifotrn = 0;
  288. ep->pipectr = get_pipectr_addr(pipenum);
  289. ep->pipenum = pipenum;
  290. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  291. r8a66597->pipenum2ep[pipenum] = ep;
  292. r8a66597->epaddr2ep[desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK]
  293. = ep;
  294. INIT_LIST_HEAD(&ep->queue);
  295. }
  296. static void r8a66597_ep_release(struct r8a66597_ep *ep)
  297. {
  298. struct r8a66597 *r8a66597 = ep->r8a66597;
  299. u16 pipenum = ep->pipenum;
  300. if (pipenum == 0)
  301. return;
  302. if (ep->use_dma)
  303. r8a66597->num_dma--;
  304. ep->pipenum = 0;
  305. ep->busy = 0;
  306. ep->use_dma = 0;
  307. }
  308. static int alloc_pipe_config(struct r8a66597_ep *ep,
  309. const struct usb_endpoint_descriptor *desc)
  310. {
  311. struct r8a66597 *r8a66597 = ep->r8a66597;
  312. struct r8a66597_pipe_info info;
  313. int dma = 0;
  314. unsigned char *counter;
  315. int ret;
  316. ep->desc = desc;
  317. if (ep->pipenum) /* already allocated pipe */
  318. return 0;
  319. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  320. case USB_ENDPOINT_XFER_BULK:
  321. if (r8a66597->bulk >= R8A66597_MAX_NUM_BULK) {
  322. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  323. printk(KERN_ERR "bulk pipe is insufficient\n");
  324. return -ENODEV;
  325. } else {
  326. info.pipe = R8A66597_BASE_PIPENUM_ISOC
  327. + r8a66597->isochronous;
  328. counter = &r8a66597->isochronous;
  329. }
  330. } else {
  331. info.pipe = R8A66597_BASE_PIPENUM_BULK + r8a66597->bulk;
  332. counter = &r8a66597->bulk;
  333. }
  334. info.type = R8A66597_BULK;
  335. dma = 1;
  336. break;
  337. case USB_ENDPOINT_XFER_INT:
  338. if (r8a66597->interrupt >= R8A66597_MAX_NUM_INT) {
  339. printk(KERN_ERR "interrupt pipe is insufficient\n");
  340. return -ENODEV;
  341. }
  342. info.pipe = R8A66597_BASE_PIPENUM_INT + r8a66597->interrupt;
  343. info.type = R8A66597_INT;
  344. counter = &r8a66597->interrupt;
  345. break;
  346. case USB_ENDPOINT_XFER_ISOC:
  347. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  348. printk(KERN_ERR "isochronous pipe is insufficient\n");
  349. return -ENODEV;
  350. }
  351. info.pipe = R8A66597_BASE_PIPENUM_ISOC + r8a66597->isochronous;
  352. info.type = R8A66597_ISO;
  353. counter = &r8a66597->isochronous;
  354. break;
  355. default:
  356. printk(KERN_ERR "unexpect xfer type\n");
  357. return -EINVAL;
  358. }
  359. ep->type = info.type;
  360. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  361. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  362. info.interval = desc->bInterval;
  363. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  364. info.dir_in = 1;
  365. else
  366. info.dir_in = 0;
  367. ret = pipe_buffer_setting(r8a66597, &info);
  368. if (ret < 0) {
  369. printk(KERN_ERR "pipe_buffer_setting fail\n");
  370. return ret;
  371. }
  372. (*counter)++;
  373. if ((counter == &r8a66597->isochronous) && info.type == R8A66597_BULK)
  374. r8a66597->bulk++;
  375. r8a66597_ep_setting(r8a66597, ep, desc, info.pipe, dma);
  376. pipe_initialize(ep);
  377. return 0;
  378. }
  379. static int free_pipe_config(struct r8a66597_ep *ep)
  380. {
  381. struct r8a66597 *r8a66597 = ep->r8a66597;
  382. struct r8a66597_pipe_info info;
  383. info.pipe = ep->pipenum;
  384. info.type = ep->type;
  385. pipe_buffer_release(r8a66597, &info);
  386. r8a66597_ep_release(ep);
  387. return 0;
  388. }
  389. /*-------------------------------------------------------------------------*/
  390. static void pipe_irq_enable(struct r8a66597 *r8a66597, u16 pipenum)
  391. {
  392. enable_irq_ready(r8a66597, pipenum);
  393. enable_irq_nrdy(r8a66597, pipenum);
  394. }
  395. static void pipe_irq_disable(struct r8a66597 *r8a66597, u16 pipenum)
  396. {
  397. disable_irq_ready(r8a66597, pipenum);
  398. disable_irq_nrdy(r8a66597, pipenum);
  399. }
  400. /* if complete is true, gadget driver complete function is not call */
  401. static void control_end(struct r8a66597 *r8a66597, unsigned ccpl)
  402. {
  403. r8a66597->ep[0].internal_ccpl = ccpl;
  404. pipe_start(r8a66597, 0);
  405. r8a66597_bset(r8a66597, CCPL, DCPCTR);
  406. }
  407. static void start_ep0_write(struct r8a66597_ep *ep,
  408. struct r8a66597_request *req)
  409. {
  410. struct r8a66597 *r8a66597 = ep->r8a66597;
  411. pipe_change(r8a66597, ep->pipenum);
  412. r8a66597_mdfy(r8a66597, ISEL, (ISEL | CURPIPE), CFIFOSEL);
  413. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  414. if (req->req.length == 0) {
  415. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  416. pipe_start(r8a66597, 0);
  417. transfer_complete(ep, req, 0);
  418. } else {
  419. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  420. irq_ep0_write(ep, req);
  421. }
  422. }
  423. static void start_packet_write(struct r8a66597_ep *ep,
  424. struct r8a66597_request *req)
  425. {
  426. struct r8a66597 *r8a66597 = ep->r8a66597;
  427. u16 tmp;
  428. pipe_change(r8a66597, ep->pipenum);
  429. disable_irq_empty(r8a66597, ep->pipenum);
  430. pipe_start(r8a66597, ep->pipenum);
  431. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  432. if (unlikely((tmp & FRDY) == 0))
  433. pipe_irq_enable(r8a66597, ep->pipenum);
  434. else
  435. irq_packet_write(ep, req);
  436. }
  437. static void start_packet_read(struct r8a66597_ep *ep,
  438. struct r8a66597_request *req)
  439. {
  440. struct r8a66597 *r8a66597 = ep->r8a66597;
  441. u16 pipenum = ep->pipenum;
  442. if (ep->pipenum == 0) {
  443. r8a66597_mdfy(r8a66597, 0, (ISEL | CURPIPE), CFIFOSEL);
  444. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  445. pipe_start(r8a66597, pipenum);
  446. pipe_irq_enable(r8a66597, pipenum);
  447. } else {
  448. if (ep->use_dma) {
  449. r8a66597_bset(r8a66597, TRCLR, ep->fifosel);
  450. pipe_change(r8a66597, pipenum);
  451. r8a66597_bset(r8a66597, TRENB, ep->fifosel);
  452. r8a66597_write(r8a66597,
  453. (req->req.length + ep->ep.maxpacket - 1)
  454. / ep->ep.maxpacket,
  455. ep->fifotrn);
  456. }
  457. pipe_start(r8a66597, pipenum); /* trigger once */
  458. pipe_irq_enable(r8a66597, pipenum);
  459. }
  460. }
  461. static void start_packet(struct r8a66597_ep *ep, struct r8a66597_request *req)
  462. {
  463. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  464. start_packet_write(ep, req);
  465. else
  466. start_packet_read(ep, req);
  467. }
  468. static void start_ep0(struct r8a66597_ep *ep, struct r8a66597_request *req)
  469. {
  470. u16 ctsq;
  471. ctsq = r8a66597_read(ep->r8a66597, INTSTS0) & CTSQ;
  472. switch (ctsq) {
  473. case CS_RDDS:
  474. start_ep0_write(ep, req);
  475. break;
  476. case CS_WRDS:
  477. start_packet_read(ep, req);
  478. break;
  479. case CS_WRND:
  480. control_end(ep->r8a66597, 0);
  481. break;
  482. default:
  483. printk(KERN_ERR "start_ep0: unexpect ctsq(%x)\n", ctsq);
  484. break;
  485. }
  486. }
  487. static void init_controller(struct r8a66597 *r8a66597)
  488. {
  489. u16 vif = r8a66597->pdata->vif ? LDRV : 0;
  490. u16 irq_sense = r8a66597->irq_sense_low ? INTL : 0;
  491. u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
  492. if (r8a66597->pdata->on_chip) {
  493. r8a66597_bset(r8a66597, 0x04, SYSCFG1);
  494. r8a66597_bset(r8a66597, HSE, SYSCFG0);
  495. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  496. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  497. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  498. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  499. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  500. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  501. DMA0CFG);
  502. } else {
  503. r8a66597_bset(r8a66597, vif | endian, PINCFG);
  504. r8a66597_bset(r8a66597, HSE, SYSCFG0); /* High spd */
  505. r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
  506. XTAL, SYSCFG0);
  507. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  508. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  509. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  510. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  511. msleep(3);
  512. r8a66597_bset(r8a66597, PLLC, SYSCFG0);
  513. msleep(1);
  514. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  515. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  516. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  517. DMA0CFG);
  518. }
  519. }
  520. static void disable_controller(struct r8a66597 *r8a66597)
  521. {
  522. if (r8a66597->pdata->on_chip) {
  523. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  524. r8a66597_write(r8a66597, 0, INTENB0);
  525. r8a66597_write(r8a66597, 0, INTENB1);
  526. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  527. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  528. } else {
  529. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  530. udelay(1);
  531. r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
  532. udelay(1);
  533. udelay(1);
  534. r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
  535. }
  536. }
  537. static void r8a66597_start_xclock(struct r8a66597 *r8a66597)
  538. {
  539. u16 tmp;
  540. if (!r8a66597->pdata->on_chip) {
  541. tmp = r8a66597_read(r8a66597, SYSCFG0);
  542. if (!(tmp & XCKE))
  543. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  544. }
  545. }
  546. static struct r8a66597_request *get_request_from_ep(struct r8a66597_ep *ep)
  547. {
  548. return list_entry(ep->queue.next, struct r8a66597_request, queue);
  549. }
  550. /*-------------------------------------------------------------------------*/
  551. static void transfer_complete(struct r8a66597_ep *ep,
  552. struct r8a66597_request *req, int status)
  553. __releases(r8a66597->lock)
  554. __acquires(r8a66597->lock)
  555. {
  556. int restart = 0;
  557. if (unlikely(ep->pipenum == 0)) {
  558. if (ep->internal_ccpl) {
  559. ep->internal_ccpl = 0;
  560. return;
  561. }
  562. }
  563. list_del_init(&req->queue);
  564. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  565. req->req.status = -ESHUTDOWN;
  566. else
  567. req->req.status = status;
  568. if (!list_empty(&ep->queue))
  569. restart = 1;
  570. spin_unlock(&ep->r8a66597->lock);
  571. req->req.complete(&ep->ep, &req->req);
  572. spin_lock(&ep->r8a66597->lock);
  573. if (restart) {
  574. req = get_request_from_ep(ep);
  575. if (ep->desc)
  576. start_packet(ep, req);
  577. }
  578. }
  579. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req)
  580. {
  581. int i;
  582. u16 tmp;
  583. unsigned bufsize;
  584. size_t size;
  585. void *buf;
  586. u16 pipenum = ep->pipenum;
  587. struct r8a66597 *r8a66597 = ep->r8a66597;
  588. pipe_change(r8a66597, pipenum);
  589. r8a66597_bset(r8a66597, ISEL, ep->fifosel);
  590. i = 0;
  591. do {
  592. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  593. if (i++ > 100000) {
  594. printk(KERN_ERR "pipe0 is busy. maybe cpu i/o bus"
  595. "conflict. please power off this controller.");
  596. return;
  597. }
  598. ndelay(1);
  599. } while ((tmp & FRDY) == 0);
  600. /* prepare parameters */
  601. bufsize = get_buffer_size(r8a66597, pipenum);
  602. buf = req->req.buf + req->req.actual;
  603. size = min(bufsize, req->req.length - req->req.actual);
  604. /* write fifo */
  605. if (req->req.buf) {
  606. if (size > 0)
  607. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  608. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  609. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  610. }
  611. /* update parameters */
  612. req->req.actual += size;
  613. /* check transfer finish */
  614. if ((!req->req.zero && (req->req.actual == req->req.length))
  615. || (size % ep->ep.maxpacket)
  616. || (size == 0)) {
  617. disable_irq_ready(r8a66597, pipenum);
  618. disable_irq_empty(r8a66597, pipenum);
  619. } else {
  620. disable_irq_ready(r8a66597, pipenum);
  621. enable_irq_empty(r8a66597, pipenum);
  622. }
  623. pipe_start(r8a66597, pipenum);
  624. }
  625. static void irq_packet_write(struct r8a66597_ep *ep,
  626. struct r8a66597_request *req)
  627. {
  628. u16 tmp;
  629. unsigned bufsize;
  630. size_t size;
  631. void *buf;
  632. u16 pipenum = ep->pipenum;
  633. struct r8a66597 *r8a66597 = ep->r8a66597;
  634. pipe_change(r8a66597, pipenum);
  635. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  636. if (unlikely((tmp & FRDY) == 0)) {
  637. pipe_stop(r8a66597, pipenum);
  638. pipe_irq_disable(r8a66597, pipenum);
  639. printk(KERN_ERR "write fifo not ready. pipnum=%d\n", pipenum);
  640. return;
  641. }
  642. /* prepare parameters */
  643. bufsize = get_buffer_size(r8a66597, pipenum);
  644. buf = req->req.buf + req->req.actual;
  645. size = min(bufsize, req->req.length - req->req.actual);
  646. /* write fifo */
  647. if (req->req.buf) {
  648. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  649. if ((size == 0)
  650. || ((size % ep->ep.maxpacket) != 0)
  651. || ((bufsize != ep->ep.maxpacket)
  652. && (bufsize > size)))
  653. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  654. }
  655. /* update parameters */
  656. req->req.actual += size;
  657. /* check transfer finish */
  658. if ((!req->req.zero && (req->req.actual == req->req.length))
  659. || (size % ep->ep.maxpacket)
  660. || (size == 0)) {
  661. disable_irq_ready(r8a66597, pipenum);
  662. enable_irq_empty(r8a66597, pipenum);
  663. } else {
  664. disable_irq_empty(r8a66597, pipenum);
  665. pipe_irq_enable(r8a66597, pipenum);
  666. }
  667. }
  668. static void irq_packet_read(struct r8a66597_ep *ep,
  669. struct r8a66597_request *req)
  670. {
  671. u16 tmp;
  672. int rcv_len, bufsize, req_len;
  673. int size;
  674. void *buf;
  675. u16 pipenum = ep->pipenum;
  676. struct r8a66597 *r8a66597 = ep->r8a66597;
  677. int finish = 0;
  678. pipe_change(r8a66597, pipenum);
  679. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  680. if (unlikely((tmp & FRDY) == 0)) {
  681. req->req.status = -EPIPE;
  682. pipe_stop(r8a66597, pipenum);
  683. pipe_irq_disable(r8a66597, pipenum);
  684. printk(KERN_ERR "read fifo not ready");
  685. return;
  686. }
  687. /* prepare parameters */
  688. rcv_len = tmp & DTLN;
  689. bufsize = get_buffer_size(r8a66597, pipenum);
  690. buf = req->req.buf + req->req.actual;
  691. req_len = req->req.length - req->req.actual;
  692. if (rcv_len < bufsize)
  693. size = min(rcv_len, req_len);
  694. else
  695. size = min(bufsize, req_len);
  696. /* update parameters */
  697. req->req.actual += size;
  698. /* check transfer finish */
  699. if ((!req->req.zero && (req->req.actual == req->req.length))
  700. || (size % ep->ep.maxpacket)
  701. || (size == 0)) {
  702. pipe_stop(r8a66597, pipenum);
  703. pipe_irq_disable(r8a66597, pipenum);
  704. finish = 1;
  705. }
  706. /* read fifo */
  707. if (req->req.buf) {
  708. if (size == 0)
  709. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  710. else
  711. r8a66597_read_fifo(r8a66597, ep->fifoaddr, buf, size);
  712. }
  713. if ((ep->pipenum != 0) && finish)
  714. transfer_complete(ep, req, 0);
  715. }
  716. static void irq_pipe_ready(struct r8a66597 *r8a66597, u16 status, u16 enb)
  717. {
  718. u16 check;
  719. u16 pipenum;
  720. struct r8a66597_ep *ep;
  721. struct r8a66597_request *req;
  722. if ((status & BRDY0) && (enb & BRDY0)) {
  723. r8a66597_write(r8a66597, ~BRDY0, BRDYSTS);
  724. r8a66597_mdfy(r8a66597, 0, CURPIPE, CFIFOSEL);
  725. ep = &r8a66597->ep[0];
  726. req = get_request_from_ep(ep);
  727. irq_packet_read(ep, req);
  728. } else {
  729. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  730. check = 1 << pipenum;
  731. if ((status & check) && (enb & check)) {
  732. r8a66597_write(r8a66597, ~check, BRDYSTS);
  733. ep = r8a66597->pipenum2ep[pipenum];
  734. req = get_request_from_ep(ep);
  735. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  736. irq_packet_write(ep, req);
  737. else
  738. irq_packet_read(ep, req);
  739. }
  740. }
  741. }
  742. }
  743. static void irq_pipe_empty(struct r8a66597 *r8a66597, u16 status, u16 enb)
  744. {
  745. u16 tmp;
  746. u16 check;
  747. u16 pipenum;
  748. struct r8a66597_ep *ep;
  749. struct r8a66597_request *req;
  750. if ((status & BEMP0) && (enb & BEMP0)) {
  751. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  752. ep = &r8a66597->ep[0];
  753. req = get_request_from_ep(ep);
  754. irq_ep0_write(ep, req);
  755. } else {
  756. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  757. check = 1 << pipenum;
  758. if ((status & check) && (enb & check)) {
  759. r8a66597_write(r8a66597, ~check, BEMPSTS);
  760. tmp = control_reg_get(r8a66597, pipenum);
  761. if ((tmp & INBUFM) == 0) {
  762. disable_irq_empty(r8a66597, pipenum);
  763. pipe_irq_disable(r8a66597, pipenum);
  764. pipe_stop(r8a66597, pipenum);
  765. ep = r8a66597->pipenum2ep[pipenum];
  766. req = get_request_from_ep(ep);
  767. if (!list_empty(&ep->queue))
  768. transfer_complete(ep, req, 0);
  769. }
  770. }
  771. }
  772. }
  773. }
  774. static void get_status(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  775. __releases(r8a66597->lock)
  776. __acquires(r8a66597->lock)
  777. {
  778. struct r8a66597_ep *ep;
  779. u16 pid;
  780. u16 status = 0;
  781. u16 w_index = le16_to_cpu(ctrl->wIndex);
  782. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  783. case USB_RECIP_DEVICE:
  784. status = 1 << USB_DEVICE_SELF_POWERED;
  785. break;
  786. case USB_RECIP_INTERFACE:
  787. status = 0;
  788. break;
  789. case USB_RECIP_ENDPOINT:
  790. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  791. pid = control_reg_get_pid(r8a66597, ep->pipenum);
  792. if (pid == PID_STALL)
  793. status = 1 << USB_ENDPOINT_HALT;
  794. else
  795. status = 0;
  796. break;
  797. default:
  798. pipe_stall(r8a66597, 0);
  799. return; /* exit */
  800. }
  801. r8a66597->ep0_data = cpu_to_le16(status);
  802. r8a66597->ep0_req->buf = &r8a66597->ep0_data;
  803. r8a66597->ep0_req->length = 2;
  804. /* AV: what happens if we get called again before that gets through? */
  805. spin_unlock(&r8a66597->lock);
  806. r8a66597_queue(r8a66597->gadget.ep0, r8a66597->ep0_req, GFP_KERNEL);
  807. spin_lock(&r8a66597->lock);
  808. }
  809. static void clear_feature(struct r8a66597 *r8a66597,
  810. struct usb_ctrlrequest *ctrl)
  811. {
  812. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  813. case USB_RECIP_DEVICE:
  814. control_end(r8a66597, 1);
  815. break;
  816. case USB_RECIP_INTERFACE:
  817. control_end(r8a66597, 1);
  818. break;
  819. case USB_RECIP_ENDPOINT: {
  820. struct r8a66597_ep *ep;
  821. struct r8a66597_request *req;
  822. u16 w_index = le16_to_cpu(ctrl->wIndex);
  823. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  824. pipe_stop(r8a66597, ep->pipenum);
  825. control_reg_sqclr(r8a66597, ep->pipenum);
  826. control_end(r8a66597, 1);
  827. req = get_request_from_ep(ep);
  828. if (ep->busy) {
  829. ep->busy = 0;
  830. if (list_empty(&ep->queue))
  831. break;
  832. start_packet(ep, req);
  833. } else if (!list_empty(&ep->queue))
  834. pipe_start(r8a66597, ep->pipenum);
  835. }
  836. break;
  837. default:
  838. pipe_stall(r8a66597, 0);
  839. break;
  840. }
  841. }
  842. static void set_feature(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  843. {
  844. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  845. case USB_RECIP_DEVICE:
  846. control_end(r8a66597, 1);
  847. break;
  848. case USB_RECIP_INTERFACE:
  849. control_end(r8a66597, 1);
  850. break;
  851. case USB_RECIP_ENDPOINT: {
  852. struct r8a66597_ep *ep;
  853. u16 w_index = le16_to_cpu(ctrl->wIndex);
  854. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  855. pipe_stall(r8a66597, ep->pipenum);
  856. control_end(r8a66597, 1);
  857. }
  858. break;
  859. default:
  860. pipe_stall(r8a66597, 0);
  861. break;
  862. }
  863. }
  864. /* if return value is true, call class driver's setup() */
  865. static int setup_packet(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  866. {
  867. u16 *p = (u16 *)ctrl;
  868. unsigned long offset = USBREQ;
  869. int i, ret = 0;
  870. /* read fifo */
  871. r8a66597_write(r8a66597, ~VALID, INTSTS0);
  872. for (i = 0; i < 4; i++)
  873. p[i] = r8a66597_read(r8a66597, offset + i*2);
  874. /* check request */
  875. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  876. switch (ctrl->bRequest) {
  877. case USB_REQ_GET_STATUS:
  878. get_status(r8a66597, ctrl);
  879. break;
  880. case USB_REQ_CLEAR_FEATURE:
  881. clear_feature(r8a66597, ctrl);
  882. break;
  883. case USB_REQ_SET_FEATURE:
  884. set_feature(r8a66597, ctrl);
  885. break;
  886. default:
  887. ret = 1;
  888. break;
  889. }
  890. } else
  891. ret = 1;
  892. return ret;
  893. }
  894. static void r8a66597_update_usb_speed(struct r8a66597 *r8a66597)
  895. {
  896. u16 speed = get_usb_speed(r8a66597);
  897. switch (speed) {
  898. case HSMODE:
  899. r8a66597->gadget.speed = USB_SPEED_HIGH;
  900. break;
  901. case FSMODE:
  902. r8a66597->gadget.speed = USB_SPEED_FULL;
  903. break;
  904. default:
  905. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  906. printk(KERN_ERR "USB speed unknown\n");
  907. }
  908. }
  909. static void irq_device_state(struct r8a66597 *r8a66597)
  910. {
  911. u16 dvsq;
  912. dvsq = r8a66597_read(r8a66597, INTSTS0) & DVSQ;
  913. r8a66597_write(r8a66597, ~DVST, INTSTS0);
  914. if (dvsq == DS_DFLT) {
  915. /* bus reset */
  916. r8a66597->driver->disconnect(&r8a66597->gadget);
  917. r8a66597_update_usb_speed(r8a66597);
  918. }
  919. if (r8a66597->old_dvsq == DS_CNFG && dvsq != DS_CNFG)
  920. r8a66597_update_usb_speed(r8a66597);
  921. if ((dvsq == DS_CNFG || dvsq == DS_ADDS)
  922. && r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  923. r8a66597_update_usb_speed(r8a66597);
  924. r8a66597->old_dvsq = dvsq;
  925. }
  926. static void irq_control_stage(struct r8a66597 *r8a66597)
  927. __releases(r8a66597->lock)
  928. __acquires(r8a66597->lock)
  929. {
  930. struct usb_ctrlrequest ctrl;
  931. u16 ctsq;
  932. ctsq = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
  933. r8a66597_write(r8a66597, ~CTRT, INTSTS0);
  934. switch (ctsq) {
  935. case CS_IDST: {
  936. struct r8a66597_ep *ep;
  937. struct r8a66597_request *req;
  938. ep = &r8a66597->ep[0];
  939. req = get_request_from_ep(ep);
  940. transfer_complete(ep, req, 0);
  941. }
  942. break;
  943. case CS_RDDS:
  944. case CS_WRDS:
  945. case CS_WRND:
  946. if (setup_packet(r8a66597, &ctrl)) {
  947. spin_unlock(&r8a66597->lock);
  948. if (r8a66597->driver->setup(&r8a66597->gadget, &ctrl)
  949. < 0)
  950. pipe_stall(r8a66597, 0);
  951. spin_lock(&r8a66597->lock);
  952. }
  953. break;
  954. case CS_RDSS:
  955. case CS_WRSS:
  956. control_end(r8a66597, 0);
  957. break;
  958. default:
  959. printk(KERN_ERR "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  960. break;
  961. }
  962. }
  963. static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
  964. {
  965. struct r8a66597 *r8a66597 = _r8a66597;
  966. u16 intsts0;
  967. u16 intenb0;
  968. u16 brdysts, nrdysts, bempsts;
  969. u16 brdyenb, nrdyenb, bempenb;
  970. u16 savepipe;
  971. u16 mask0;
  972. spin_lock(&r8a66597->lock);
  973. intsts0 = r8a66597_read(r8a66597, INTSTS0);
  974. intenb0 = r8a66597_read(r8a66597, INTENB0);
  975. savepipe = r8a66597_read(r8a66597, CFIFOSEL);
  976. mask0 = intsts0 & intenb0;
  977. if (mask0) {
  978. brdysts = r8a66597_read(r8a66597, BRDYSTS);
  979. nrdysts = r8a66597_read(r8a66597, NRDYSTS);
  980. bempsts = r8a66597_read(r8a66597, BEMPSTS);
  981. brdyenb = r8a66597_read(r8a66597, BRDYENB);
  982. nrdyenb = r8a66597_read(r8a66597, NRDYENB);
  983. bempenb = r8a66597_read(r8a66597, BEMPENB);
  984. if (mask0 & VBINT) {
  985. r8a66597_write(r8a66597, 0xffff & ~VBINT,
  986. INTSTS0);
  987. r8a66597_start_xclock(r8a66597);
  988. /* start vbus sampling */
  989. r8a66597->old_vbus = r8a66597_read(r8a66597, INTSTS0)
  990. & VBSTS;
  991. r8a66597->scount = R8A66597_MAX_SAMPLING;
  992. mod_timer(&r8a66597->timer,
  993. jiffies + msecs_to_jiffies(50));
  994. }
  995. if (intsts0 & DVSQ)
  996. irq_device_state(r8a66597);
  997. if ((intsts0 & BRDY) && (intenb0 & BRDYE)
  998. && (brdysts & brdyenb))
  999. irq_pipe_ready(r8a66597, brdysts, brdyenb);
  1000. if ((intsts0 & BEMP) && (intenb0 & BEMPE)
  1001. && (bempsts & bempenb))
  1002. irq_pipe_empty(r8a66597, bempsts, bempenb);
  1003. if (intsts0 & CTRT)
  1004. irq_control_stage(r8a66597);
  1005. }
  1006. r8a66597_write(r8a66597, savepipe, CFIFOSEL);
  1007. spin_unlock(&r8a66597->lock);
  1008. return IRQ_HANDLED;
  1009. }
  1010. static void r8a66597_timer(unsigned long _r8a66597)
  1011. {
  1012. struct r8a66597 *r8a66597 = (struct r8a66597 *)_r8a66597;
  1013. unsigned long flags;
  1014. u16 tmp;
  1015. spin_lock_irqsave(&r8a66597->lock, flags);
  1016. tmp = r8a66597_read(r8a66597, SYSCFG0);
  1017. if (r8a66597->scount > 0) {
  1018. tmp = r8a66597_read(r8a66597, INTSTS0) & VBSTS;
  1019. if (tmp == r8a66597->old_vbus) {
  1020. r8a66597->scount--;
  1021. if (r8a66597->scount == 0) {
  1022. if (tmp == VBSTS)
  1023. r8a66597_usb_connect(r8a66597);
  1024. else
  1025. r8a66597_usb_disconnect(r8a66597);
  1026. } else {
  1027. mod_timer(&r8a66597->timer,
  1028. jiffies + msecs_to_jiffies(50));
  1029. }
  1030. } else {
  1031. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1032. r8a66597->old_vbus = tmp;
  1033. mod_timer(&r8a66597->timer,
  1034. jiffies + msecs_to_jiffies(50));
  1035. }
  1036. }
  1037. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1038. }
  1039. /*-------------------------------------------------------------------------*/
  1040. static int r8a66597_enable(struct usb_ep *_ep,
  1041. const struct usb_endpoint_descriptor *desc)
  1042. {
  1043. struct r8a66597_ep *ep;
  1044. ep = container_of(_ep, struct r8a66597_ep, ep);
  1045. return alloc_pipe_config(ep, desc);
  1046. }
  1047. static int r8a66597_disable(struct usb_ep *_ep)
  1048. {
  1049. struct r8a66597_ep *ep;
  1050. struct r8a66597_request *req;
  1051. unsigned long flags;
  1052. ep = container_of(_ep, struct r8a66597_ep, ep);
  1053. BUG_ON(!ep);
  1054. while (!list_empty(&ep->queue)) {
  1055. req = get_request_from_ep(ep);
  1056. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1057. transfer_complete(ep, req, -ECONNRESET);
  1058. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1059. }
  1060. pipe_irq_disable(ep->r8a66597, ep->pipenum);
  1061. return free_pipe_config(ep);
  1062. }
  1063. static struct usb_request *r8a66597_alloc_request(struct usb_ep *_ep,
  1064. gfp_t gfp_flags)
  1065. {
  1066. struct r8a66597_request *req;
  1067. req = kzalloc(sizeof(struct r8a66597_request), gfp_flags);
  1068. if (!req)
  1069. return NULL;
  1070. INIT_LIST_HEAD(&req->queue);
  1071. return &req->req;
  1072. }
  1073. static void r8a66597_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1074. {
  1075. struct r8a66597_request *req;
  1076. req = container_of(_req, struct r8a66597_request, req);
  1077. kfree(req);
  1078. }
  1079. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  1080. gfp_t gfp_flags)
  1081. {
  1082. struct r8a66597_ep *ep;
  1083. struct r8a66597_request *req;
  1084. unsigned long flags;
  1085. int request = 0;
  1086. ep = container_of(_ep, struct r8a66597_ep, ep);
  1087. req = container_of(_req, struct r8a66597_request, req);
  1088. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  1089. return -ESHUTDOWN;
  1090. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1091. if (list_empty(&ep->queue))
  1092. request = 1;
  1093. list_add_tail(&req->queue, &ep->queue);
  1094. req->req.actual = 0;
  1095. req->req.status = -EINPROGRESS;
  1096. if (ep->desc == NULL) /* control */
  1097. start_ep0(ep, req);
  1098. else {
  1099. if (request && !ep->busy)
  1100. start_packet(ep, req);
  1101. }
  1102. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1103. return 0;
  1104. }
  1105. static int r8a66597_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1106. {
  1107. struct r8a66597_ep *ep;
  1108. struct r8a66597_request *req;
  1109. unsigned long flags;
  1110. ep = container_of(_ep, struct r8a66597_ep, ep);
  1111. req = container_of(_req, struct r8a66597_request, req);
  1112. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1113. if (!list_empty(&ep->queue))
  1114. transfer_complete(ep, req, -ECONNRESET);
  1115. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1116. return 0;
  1117. }
  1118. static int r8a66597_set_halt(struct usb_ep *_ep, int value)
  1119. {
  1120. struct r8a66597_ep *ep;
  1121. struct r8a66597_request *req;
  1122. unsigned long flags;
  1123. int ret = 0;
  1124. ep = container_of(_ep, struct r8a66597_ep, ep);
  1125. req = get_request_from_ep(ep);
  1126. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1127. if (!list_empty(&ep->queue)) {
  1128. ret = -EAGAIN;
  1129. goto out;
  1130. }
  1131. if (value) {
  1132. ep->busy = 1;
  1133. pipe_stall(ep->r8a66597, ep->pipenum);
  1134. } else {
  1135. ep->busy = 0;
  1136. pipe_stop(ep->r8a66597, ep->pipenum);
  1137. }
  1138. out:
  1139. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1140. return ret;
  1141. }
  1142. static void r8a66597_fifo_flush(struct usb_ep *_ep)
  1143. {
  1144. struct r8a66597_ep *ep;
  1145. unsigned long flags;
  1146. ep = container_of(_ep, struct r8a66597_ep, ep);
  1147. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1148. if (list_empty(&ep->queue) && !ep->busy) {
  1149. pipe_stop(ep->r8a66597, ep->pipenum);
  1150. r8a66597_bclr(ep->r8a66597, BCLR, ep->fifoctr);
  1151. }
  1152. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1153. }
  1154. static struct usb_ep_ops r8a66597_ep_ops = {
  1155. .enable = r8a66597_enable,
  1156. .disable = r8a66597_disable,
  1157. .alloc_request = r8a66597_alloc_request,
  1158. .free_request = r8a66597_free_request,
  1159. .queue = r8a66597_queue,
  1160. .dequeue = r8a66597_dequeue,
  1161. .set_halt = r8a66597_set_halt,
  1162. .fifo_flush = r8a66597_fifo_flush,
  1163. };
  1164. /*-------------------------------------------------------------------------*/
  1165. static struct r8a66597 *the_controller;
  1166. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1167. {
  1168. struct r8a66597 *r8a66597 = the_controller;
  1169. int retval;
  1170. if (!driver
  1171. || driver->speed != USB_SPEED_HIGH
  1172. || !driver->bind
  1173. || !driver->setup)
  1174. return -EINVAL;
  1175. if (!r8a66597)
  1176. return -ENODEV;
  1177. if (r8a66597->driver)
  1178. return -EBUSY;
  1179. /* hook up the driver */
  1180. driver->driver.bus = NULL;
  1181. r8a66597->driver = driver;
  1182. r8a66597->gadget.dev.driver = &driver->driver;
  1183. retval = device_add(&r8a66597->gadget.dev);
  1184. if (retval) {
  1185. printk(KERN_ERR "device_add error (%d)\n", retval);
  1186. goto error;
  1187. }
  1188. retval = driver->bind(&r8a66597->gadget);
  1189. if (retval) {
  1190. printk(KERN_ERR "bind to driver error (%d)\n", retval);
  1191. device_del(&r8a66597->gadget.dev);
  1192. goto error;
  1193. }
  1194. r8a66597_bset(r8a66597, VBSE, INTENB0);
  1195. if (r8a66597_read(r8a66597, INTSTS0) & VBSTS) {
  1196. r8a66597_start_xclock(r8a66597);
  1197. /* start vbus sampling */
  1198. r8a66597->old_vbus = r8a66597_read(r8a66597,
  1199. INTSTS0) & VBSTS;
  1200. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1201. mod_timer(&r8a66597->timer, jiffies + msecs_to_jiffies(50));
  1202. }
  1203. return 0;
  1204. error:
  1205. r8a66597->driver = NULL;
  1206. r8a66597->gadget.dev.driver = NULL;
  1207. return retval;
  1208. }
  1209. EXPORT_SYMBOL(usb_gadget_register_driver);
  1210. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1211. {
  1212. struct r8a66597 *r8a66597 = the_controller;
  1213. unsigned long flags;
  1214. if (driver != r8a66597->driver || !driver->unbind)
  1215. return -EINVAL;
  1216. spin_lock_irqsave(&r8a66597->lock, flags);
  1217. if (r8a66597->gadget.speed != USB_SPEED_UNKNOWN)
  1218. r8a66597_usb_disconnect(r8a66597);
  1219. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1220. r8a66597_bclr(r8a66597, VBSE, INTENB0);
  1221. driver->unbind(&r8a66597->gadget);
  1222. init_controller(r8a66597);
  1223. disable_controller(r8a66597);
  1224. device_del(&r8a66597->gadget.dev);
  1225. r8a66597->driver = NULL;
  1226. return 0;
  1227. }
  1228. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1229. /*-------------------------------------------------------------------------*/
  1230. static int r8a66597_get_frame(struct usb_gadget *_gadget)
  1231. {
  1232. struct r8a66597 *r8a66597 = gadget_to_r8a66597(_gadget);
  1233. return r8a66597_read(r8a66597, FRMNUM) & 0x03FF;
  1234. }
  1235. static struct usb_gadget_ops r8a66597_gadget_ops = {
  1236. .get_frame = r8a66597_get_frame,
  1237. };
  1238. static int __exit r8a66597_remove(struct platform_device *pdev)
  1239. {
  1240. struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
  1241. del_timer_sync(&r8a66597->timer);
  1242. iounmap((void *)r8a66597->reg);
  1243. free_irq(platform_get_irq(pdev, 0), r8a66597);
  1244. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1245. kfree(r8a66597);
  1246. return 0;
  1247. }
  1248. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1249. {
  1250. }
  1251. static int __init r8a66597_probe(struct platform_device *pdev)
  1252. {
  1253. struct resource *res, *ires;
  1254. int irq;
  1255. void __iomem *reg = NULL;
  1256. struct r8a66597 *r8a66597 = NULL;
  1257. int ret = 0;
  1258. int i;
  1259. unsigned long irq_trigger;
  1260. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1261. if (!res) {
  1262. ret = -ENODEV;
  1263. printk(KERN_ERR "platform_get_resource error.\n");
  1264. goto clean_up;
  1265. }
  1266. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1267. irq = ires->start;
  1268. irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1269. if (irq < 0) {
  1270. ret = -ENODEV;
  1271. printk(KERN_ERR "platform_get_irq error.\n");
  1272. goto clean_up;
  1273. }
  1274. reg = ioremap(res->start, resource_size(res));
  1275. if (reg == NULL) {
  1276. ret = -ENOMEM;
  1277. printk(KERN_ERR "ioremap error.\n");
  1278. goto clean_up;
  1279. }
  1280. /* initialize ucd */
  1281. r8a66597 = kzalloc(sizeof(struct r8a66597), GFP_KERNEL);
  1282. if (r8a66597 == NULL) {
  1283. printk(KERN_ERR "kzalloc error\n");
  1284. goto clean_up;
  1285. }
  1286. spin_lock_init(&r8a66597->lock);
  1287. dev_set_drvdata(&pdev->dev, r8a66597);
  1288. r8a66597->pdata = pdev->dev.platform_data;
  1289. r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
  1290. r8a66597->gadget.ops = &r8a66597_gadget_ops;
  1291. device_initialize(&r8a66597->gadget.dev);
  1292. dev_set_name(&r8a66597->gadget.dev, "gadget");
  1293. r8a66597->gadget.is_dualspeed = 1;
  1294. r8a66597->gadget.dev.parent = &pdev->dev;
  1295. r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1296. r8a66597->gadget.dev.release = pdev->dev.release;
  1297. r8a66597->gadget.name = udc_name;
  1298. init_timer(&r8a66597->timer);
  1299. r8a66597->timer.function = r8a66597_timer;
  1300. r8a66597->timer.data = (unsigned long)r8a66597;
  1301. r8a66597->reg = (unsigned long)reg;
  1302. r8a66597->bi_bufnum = R8A66597_BASE_BUFNUM;
  1303. disable_controller(r8a66597); /* make sure controller is disabled */
  1304. ret = request_irq(irq, r8a66597_irq, IRQF_DISABLED | IRQF_SHARED,
  1305. udc_name, r8a66597);
  1306. if (ret < 0) {
  1307. printk(KERN_ERR "request_irq error (%d)\n", ret);
  1308. goto clean_up;
  1309. }
  1310. INIT_LIST_HEAD(&r8a66597->gadget.ep_list);
  1311. r8a66597->gadget.ep0 = &r8a66597->ep[0].ep;
  1312. INIT_LIST_HEAD(&r8a66597->gadget.ep0->ep_list);
  1313. for (i = 0; i < R8A66597_MAX_NUM_PIPE; i++) {
  1314. struct r8a66597_ep *ep = &r8a66597->ep[i];
  1315. if (i != 0) {
  1316. INIT_LIST_HEAD(&r8a66597->ep[i].ep.ep_list);
  1317. list_add_tail(&r8a66597->ep[i].ep.ep_list,
  1318. &r8a66597->gadget.ep_list);
  1319. }
  1320. ep->r8a66597 = r8a66597;
  1321. INIT_LIST_HEAD(&ep->queue);
  1322. ep->ep.name = r8a66597_ep_name[i];
  1323. ep->ep.ops = &r8a66597_ep_ops;
  1324. ep->ep.maxpacket = 512;
  1325. }
  1326. r8a66597->ep[0].ep.maxpacket = 64;
  1327. r8a66597->ep[0].pipenum = 0;
  1328. r8a66597->ep[0].fifoaddr = CFIFO;
  1329. r8a66597->ep[0].fifosel = CFIFOSEL;
  1330. r8a66597->ep[0].fifoctr = CFIFOCTR;
  1331. r8a66597->ep[0].fifotrn = 0;
  1332. r8a66597->ep[0].pipectr = get_pipectr_addr(0);
  1333. r8a66597->pipenum2ep[0] = &r8a66597->ep[0];
  1334. r8a66597->epaddr2ep[0] = &r8a66597->ep[0];
  1335. the_controller = r8a66597;
  1336. r8a66597->ep0_req = r8a66597_alloc_request(&r8a66597->ep[0].ep,
  1337. GFP_KERNEL);
  1338. if (r8a66597->ep0_req == NULL)
  1339. goto clean_up2;
  1340. r8a66597->ep0_req->complete = nop_completion;
  1341. init_controller(r8a66597);
  1342. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1343. return 0;
  1344. clean_up2:
  1345. free_irq(irq, r8a66597);
  1346. clean_up:
  1347. if (r8a66597) {
  1348. if (r8a66597->ep0_req)
  1349. r8a66597_free_request(&r8a66597->ep[0].ep,
  1350. r8a66597->ep0_req);
  1351. kfree(r8a66597);
  1352. }
  1353. if (reg)
  1354. iounmap(reg);
  1355. return ret;
  1356. }
  1357. /*-------------------------------------------------------------------------*/
  1358. static struct platform_driver r8a66597_driver = {
  1359. .remove = __exit_p(r8a66597_remove),
  1360. .driver = {
  1361. .name = (char *) udc_name,
  1362. },
  1363. };
  1364. static int __init r8a66597_udc_init(void)
  1365. {
  1366. return platform_driver_probe(&r8a66597_driver, r8a66597_probe);
  1367. }
  1368. module_init(r8a66597_udc_init);
  1369. static void __exit r8a66597_udc_cleanup(void)
  1370. {
  1371. platform_driver_unregister(&r8a66597_driver);
  1372. }
  1373. module_exit(r8a66597_udc_cleanup);
  1374. MODULE_DESCRIPTION("R8A66597 USB gadget driver");
  1375. MODULE_LICENSE("GPL");
  1376. MODULE_AUTHOR("Yoshihiro Shimoda");