process.c 37 KB

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  1. /*
  2. * Derived from "arch/i386/kernel/process.c"
  3. * Copyright (C) 1995 Linus Torvalds
  4. *
  5. * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
  6. * Paul Mackerras (paulus@cs.anu.edu.au)
  7. *
  8. * PowerPC version
  9. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * as published by the Free Software Foundation; either version
  14. * 2 of the License, or (at your option) any later version.
  15. */
  16. #include <linux/errno.h>
  17. #include <linux/sched.h>
  18. #include <linux/kernel.h>
  19. #include <linux/mm.h>
  20. #include <linux/smp.h>
  21. #include <linux/stddef.h>
  22. #include <linux/unistd.h>
  23. #include <linux/ptrace.h>
  24. #include <linux/slab.h>
  25. #include <linux/user.h>
  26. #include <linux/elf.h>
  27. #include <linux/init.h>
  28. #include <linux/prctl.h>
  29. #include <linux/init_task.h>
  30. #include <linux/export.h>
  31. #include <linux/kallsyms.h>
  32. #include <linux/mqueue.h>
  33. #include <linux/hardirq.h>
  34. #include <linux/utsname.h>
  35. #include <linux/ftrace.h>
  36. #include <linux/kernel_stat.h>
  37. #include <linux/personality.h>
  38. #include <linux/random.h>
  39. #include <linux/hw_breakpoint.h>
  40. #include <asm/pgtable.h>
  41. #include <asm/uaccess.h>
  42. #include <asm/io.h>
  43. #include <asm/processor.h>
  44. #include <asm/mmu.h>
  45. #include <asm/prom.h>
  46. #include <asm/machdep.h>
  47. #include <asm/time.h>
  48. #include <asm/runlatch.h>
  49. #include <asm/syscalls.h>
  50. #include <asm/switch_to.h>
  51. #include <asm/tm.h>
  52. #include <asm/debug.h>
  53. #ifdef CONFIG_PPC64
  54. #include <asm/firmware.h>
  55. #endif
  56. #include <linux/kprobes.h>
  57. #include <linux/kdebug.h>
  58. /* Transactional Memory debug */
  59. #ifdef TM_DEBUG_SW
  60. #define TM_DEBUG(x...) printk(KERN_INFO x)
  61. #else
  62. #define TM_DEBUG(x...) do { } while(0)
  63. #endif
  64. extern unsigned long _get_SP(void);
  65. #ifndef CONFIG_SMP
  66. struct task_struct *last_task_used_math = NULL;
  67. struct task_struct *last_task_used_altivec = NULL;
  68. struct task_struct *last_task_used_vsx = NULL;
  69. struct task_struct *last_task_used_spe = NULL;
  70. #endif
  71. #ifdef CONFIG_PPC_FPU
  72. /*
  73. * Make sure the floating-point register state in the
  74. * the thread_struct is up to date for task tsk.
  75. */
  76. void flush_fp_to_thread(struct task_struct *tsk)
  77. {
  78. if (tsk->thread.regs) {
  79. /*
  80. * We need to disable preemption here because if we didn't,
  81. * another process could get scheduled after the regs->msr
  82. * test but before we have finished saving the FP registers
  83. * to the thread_struct. That process could take over the
  84. * FPU, and then when we get scheduled again we would store
  85. * bogus values for the remaining FP registers.
  86. */
  87. preempt_disable();
  88. if (tsk->thread.regs->msr & MSR_FP) {
  89. #ifdef CONFIG_SMP
  90. /*
  91. * This should only ever be called for current or
  92. * for a stopped child process. Since we save away
  93. * the FP register state on context switch on SMP,
  94. * there is something wrong if a stopped child appears
  95. * to still have its FP state in the CPU registers.
  96. */
  97. BUG_ON(tsk != current);
  98. #endif
  99. giveup_fpu(tsk);
  100. }
  101. preempt_enable();
  102. }
  103. }
  104. EXPORT_SYMBOL_GPL(flush_fp_to_thread);
  105. #endif
  106. void enable_kernel_fp(void)
  107. {
  108. WARN_ON(preemptible());
  109. #ifdef CONFIG_SMP
  110. if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
  111. giveup_fpu(current);
  112. else
  113. giveup_fpu(NULL); /* just enables FP for kernel */
  114. #else
  115. giveup_fpu(last_task_used_math);
  116. #endif /* CONFIG_SMP */
  117. }
  118. EXPORT_SYMBOL(enable_kernel_fp);
  119. #ifdef CONFIG_ALTIVEC
  120. void enable_kernel_altivec(void)
  121. {
  122. WARN_ON(preemptible());
  123. #ifdef CONFIG_SMP
  124. if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
  125. giveup_altivec(current);
  126. else
  127. giveup_altivec_notask();
  128. #else
  129. giveup_altivec(last_task_used_altivec);
  130. #endif /* CONFIG_SMP */
  131. }
  132. EXPORT_SYMBOL(enable_kernel_altivec);
  133. /*
  134. * Make sure the VMX/Altivec register state in the
  135. * the thread_struct is up to date for task tsk.
  136. */
  137. void flush_altivec_to_thread(struct task_struct *tsk)
  138. {
  139. if (tsk->thread.regs) {
  140. preempt_disable();
  141. if (tsk->thread.regs->msr & MSR_VEC) {
  142. #ifdef CONFIG_SMP
  143. BUG_ON(tsk != current);
  144. #endif
  145. giveup_altivec(tsk);
  146. }
  147. preempt_enable();
  148. }
  149. }
  150. EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
  151. #endif /* CONFIG_ALTIVEC */
  152. #ifdef CONFIG_VSX
  153. #if 0
  154. /* not currently used, but some crazy RAID module might want to later */
  155. void enable_kernel_vsx(void)
  156. {
  157. WARN_ON(preemptible());
  158. #ifdef CONFIG_SMP
  159. if (current->thread.regs && (current->thread.regs->msr & MSR_VSX))
  160. giveup_vsx(current);
  161. else
  162. giveup_vsx(NULL); /* just enable vsx for kernel - force */
  163. #else
  164. giveup_vsx(last_task_used_vsx);
  165. #endif /* CONFIG_SMP */
  166. }
  167. EXPORT_SYMBOL(enable_kernel_vsx);
  168. #endif
  169. void giveup_vsx(struct task_struct *tsk)
  170. {
  171. giveup_fpu(tsk);
  172. giveup_altivec(tsk);
  173. __giveup_vsx(tsk);
  174. }
  175. void flush_vsx_to_thread(struct task_struct *tsk)
  176. {
  177. if (tsk->thread.regs) {
  178. preempt_disable();
  179. if (tsk->thread.regs->msr & MSR_VSX) {
  180. #ifdef CONFIG_SMP
  181. BUG_ON(tsk != current);
  182. #endif
  183. giveup_vsx(tsk);
  184. }
  185. preempt_enable();
  186. }
  187. }
  188. EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
  189. #endif /* CONFIG_VSX */
  190. #ifdef CONFIG_SPE
  191. void enable_kernel_spe(void)
  192. {
  193. WARN_ON(preemptible());
  194. #ifdef CONFIG_SMP
  195. if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
  196. giveup_spe(current);
  197. else
  198. giveup_spe(NULL); /* just enable SPE for kernel - force */
  199. #else
  200. giveup_spe(last_task_used_spe);
  201. #endif /* __SMP __ */
  202. }
  203. EXPORT_SYMBOL(enable_kernel_spe);
  204. void flush_spe_to_thread(struct task_struct *tsk)
  205. {
  206. if (tsk->thread.regs) {
  207. preempt_disable();
  208. if (tsk->thread.regs->msr & MSR_SPE) {
  209. #ifdef CONFIG_SMP
  210. BUG_ON(tsk != current);
  211. #endif
  212. tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
  213. giveup_spe(tsk);
  214. }
  215. preempt_enable();
  216. }
  217. }
  218. #endif /* CONFIG_SPE */
  219. #ifndef CONFIG_SMP
  220. /*
  221. * If we are doing lazy switching of CPU state (FP, altivec or SPE),
  222. * and the current task has some state, discard it.
  223. */
  224. void discard_lazy_cpu_state(void)
  225. {
  226. preempt_disable();
  227. if (last_task_used_math == current)
  228. last_task_used_math = NULL;
  229. #ifdef CONFIG_ALTIVEC
  230. if (last_task_used_altivec == current)
  231. last_task_used_altivec = NULL;
  232. #endif /* CONFIG_ALTIVEC */
  233. #ifdef CONFIG_VSX
  234. if (last_task_used_vsx == current)
  235. last_task_used_vsx = NULL;
  236. #endif /* CONFIG_VSX */
  237. #ifdef CONFIG_SPE
  238. if (last_task_used_spe == current)
  239. last_task_used_spe = NULL;
  240. #endif
  241. preempt_enable();
  242. }
  243. #endif /* CONFIG_SMP */
  244. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  245. void do_send_trap(struct pt_regs *regs, unsigned long address,
  246. unsigned long error_code, int signal_code, int breakpt)
  247. {
  248. siginfo_t info;
  249. current->thread.trap_nr = signal_code;
  250. if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
  251. 11, SIGSEGV) == NOTIFY_STOP)
  252. return;
  253. /* Deliver the signal to userspace */
  254. info.si_signo = SIGTRAP;
  255. info.si_errno = breakpt; /* breakpoint or watchpoint id */
  256. info.si_code = signal_code;
  257. info.si_addr = (void __user *)address;
  258. force_sig_info(SIGTRAP, &info, current);
  259. }
  260. #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
  261. void do_break (struct pt_regs *regs, unsigned long address,
  262. unsigned long error_code)
  263. {
  264. siginfo_t info;
  265. current->thread.trap_nr = TRAP_HWBKPT;
  266. if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
  267. 11, SIGSEGV) == NOTIFY_STOP)
  268. return;
  269. if (debugger_break_match(regs))
  270. return;
  271. /* Clear the breakpoint */
  272. hw_breakpoint_disable();
  273. /* Deliver the signal to userspace */
  274. info.si_signo = SIGTRAP;
  275. info.si_errno = 0;
  276. info.si_code = TRAP_HWBKPT;
  277. info.si_addr = (void __user *)address;
  278. force_sig_info(SIGTRAP, &info, current);
  279. }
  280. #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
  281. static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
  282. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  283. /*
  284. * Set the debug registers back to their default "safe" values.
  285. */
  286. static void set_debug_reg_defaults(struct thread_struct *thread)
  287. {
  288. thread->iac1 = thread->iac2 = 0;
  289. #if CONFIG_PPC_ADV_DEBUG_IACS > 2
  290. thread->iac3 = thread->iac4 = 0;
  291. #endif
  292. thread->dac1 = thread->dac2 = 0;
  293. #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
  294. thread->dvc1 = thread->dvc2 = 0;
  295. #endif
  296. thread->dbcr0 = 0;
  297. #ifdef CONFIG_BOOKE
  298. /*
  299. * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
  300. */
  301. thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \
  302. DBCR1_IAC3US | DBCR1_IAC4US;
  303. /*
  304. * Force Data Address Compare User/Supervisor bits to be User-only
  305. * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
  306. */
  307. thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
  308. #else
  309. thread->dbcr1 = 0;
  310. #endif
  311. }
  312. static void prime_debug_regs(struct thread_struct *thread)
  313. {
  314. /*
  315. * We could have inherited MSR_DE from userspace, since
  316. * it doesn't get cleared on exception entry. Make sure
  317. * MSR_DE is clear before we enable any debug events.
  318. */
  319. mtmsr(mfmsr() & ~MSR_DE);
  320. mtspr(SPRN_IAC1, thread->iac1);
  321. mtspr(SPRN_IAC2, thread->iac2);
  322. #if CONFIG_PPC_ADV_DEBUG_IACS > 2
  323. mtspr(SPRN_IAC3, thread->iac3);
  324. mtspr(SPRN_IAC4, thread->iac4);
  325. #endif
  326. mtspr(SPRN_DAC1, thread->dac1);
  327. mtspr(SPRN_DAC2, thread->dac2);
  328. #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
  329. mtspr(SPRN_DVC1, thread->dvc1);
  330. mtspr(SPRN_DVC2, thread->dvc2);
  331. #endif
  332. mtspr(SPRN_DBCR0, thread->dbcr0);
  333. mtspr(SPRN_DBCR1, thread->dbcr1);
  334. #ifdef CONFIG_BOOKE
  335. mtspr(SPRN_DBCR2, thread->dbcr2);
  336. #endif
  337. }
  338. /*
  339. * Unless neither the old or new thread are making use of the
  340. * debug registers, set the debug registers from the values
  341. * stored in the new thread.
  342. */
  343. static void switch_booke_debug_regs(struct thread_struct *new_thread)
  344. {
  345. if ((current->thread.dbcr0 & DBCR0_IDM)
  346. || (new_thread->dbcr0 & DBCR0_IDM))
  347. prime_debug_regs(new_thread);
  348. }
  349. #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
  350. #ifndef CONFIG_HAVE_HW_BREAKPOINT
  351. static void set_debug_reg_defaults(struct thread_struct *thread)
  352. {
  353. thread->hw_brk.address = 0;
  354. thread->hw_brk.type = 0;
  355. set_breakpoint(&thread->hw_brk);
  356. }
  357. #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
  358. #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
  359. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  360. static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
  361. {
  362. mtspr(SPRN_DAC1, dabr);
  363. #ifdef CONFIG_PPC_47x
  364. isync();
  365. #endif
  366. return 0;
  367. }
  368. #elif defined(CONFIG_PPC_BOOK3S)
  369. static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
  370. {
  371. mtspr(SPRN_DABR, dabr);
  372. if (cpu_has_feature(CPU_FTR_DABRX))
  373. mtspr(SPRN_DABRX, dabrx);
  374. return 0;
  375. }
  376. #else
  377. static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
  378. {
  379. return -EINVAL;
  380. }
  381. #endif
  382. static inline int set_dabr(struct arch_hw_breakpoint *brk)
  383. {
  384. unsigned long dabr, dabrx;
  385. dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
  386. dabrx = ((brk->type >> 3) & 0x7);
  387. if (ppc_md.set_dabr)
  388. return ppc_md.set_dabr(dabr, dabrx);
  389. return __set_dabr(dabr, dabrx);
  390. }
  391. static inline int set_dawr(struct arch_hw_breakpoint *brk)
  392. {
  393. unsigned long dawr, dawrx, mrd;
  394. dawr = brk->address;
  395. dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
  396. << (63 - 58); //* read/write bits */
  397. dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
  398. << (63 - 59); //* translate */
  399. dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
  400. >> 3; //* PRIM bits */
  401. /* dawr length is stored in field MDR bits 48:53. Matches range in
  402. doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
  403. 0b111111=64DW.
  404. brk->len is in bytes.
  405. This aligns up to double word size, shifts and does the bias.
  406. */
  407. mrd = ((brk->len + 7) >> 3) - 1;
  408. dawrx |= (mrd & 0x3f) << (63 - 53);
  409. if (ppc_md.set_dawr)
  410. return ppc_md.set_dawr(dawr, dawrx);
  411. mtspr(SPRN_DAWR, dawr);
  412. mtspr(SPRN_DAWRX, dawrx);
  413. return 0;
  414. }
  415. int set_breakpoint(struct arch_hw_breakpoint *brk)
  416. {
  417. __get_cpu_var(current_brk) = *brk;
  418. if (cpu_has_feature(CPU_FTR_DAWR))
  419. return set_dawr(brk);
  420. return set_dabr(brk);
  421. }
  422. #ifdef CONFIG_PPC64
  423. DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
  424. #endif
  425. static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
  426. struct arch_hw_breakpoint *b)
  427. {
  428. if (a->address != b->address)
  429. return false;
  430. if (a->type != b->type)
  431. return false;
  432. if (a->len != b->len)
  433. return false;
  434. return true;
  435. }
  436. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  437. static inline void tm_reclaim_task(struct task_struct *tsk)
  438. {
  439. /* We have to work out if we're switching from/to a task that's in the
  440. * middle of a transaction.
  441. *
  442. * In switching we need to maintain a 2nd register state as
  443. * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
  444. * checkpointed (tbegin) state in ckpt_regs and saves the transactional
  445. * (current) FPRs into oldtask->thread.transact_fpr[].
  446. *
  447. * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
  448. */
  449. struct thread_struct *thr = &tsk->thread;
  450. if (!thr->regs)
  451. return;
  452. if (!MSR_TM_ACTIVE(thr->regs->msr))
  453. goto out_and_saveregs;
  454. /* Stash the original thread MSR, as giveup_fpu et al will
  455. * modify it. We hold onto it to see whether the task used
  456. * FP & vector regs.
  457. */
  458. thr->tm_orig_msr = thr->regs->msr;
  459. TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
  460. "ccr=%lx, msr=%lx, trap=%lx)\n",
  461. tsk->pid, thr->regs->nip,
  462. thr->regs->ccr, thr->regs->msr,
  463. thr->regs->trap);
  464. tm_reclaim(thr, thr->regs->msr, TM_CAUSE_RESCHED);
  465. TM_DEBUG("--- tm_reclaim on pid %d complete\n",
  466. tsk->pid);
  467. out_and_saveregs:
  468. /* Always save the regs here, even if a transaction's not active.
  469. * This context-switches a thread's TM info SPRs. We do it here to
  470. * be consistent with the restore path (in recheckpoint) which
  471. * cannot happen later in _switch().
  472. */
  473. tm_save_sprs(thr);
  474. }
  475. static inline void tm_recheckpoint_new_task(struct task_struct *new)
  476. {
  477. unsigned long msr;
  478. if (!cpu_has_feature(CPU_FTR_TM))
  479. return;
  480. /* Recheckpoint the registers of the thread we're about to switch to.
  481. *
  482. * If the task was using FP, we non-lazily reload both the original and
  483. * the speculative FP register states. This is because the kernel
  484. * doesn't see if/when a TM rollback occurs, so if we take an FP
  485. * unavoidable later, we are unable to determine which set of FP regs
  486. * need to be restored.
  487. */
  488. if (!new->thread.regs)
  489. return;
  490. /* The TM SPRs are restored here, so that TEXASR.FS can be set
  491. * before the trecheckpoint and no explosion occurs.
  492. */
  493. tm_restore_sprs(&new->thread);
  494. if (!MSR_TM_ACTIVE(new->thread.regs->msr))
  495. return;
  496. msr = new->thread.tm_orig_msr;
  497. /* Recheckpoint to restore original checkpointed register state. */
  498. TM_DEBUG("*** tm_recheckpoint of pid %d "
  499. "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
  500. new->pid, new->thread.regs->msr, msr);
  501. /* This loads the checkpointed FP/VEC state, if used */
  502. tm_recheckpoint(&new->thread, msr);
  503. /* This loads the speculative FP/VEC state, if used */
  504. if (msr & MSR_FP) {
  505. do_load_up_transact_fpu(&new->thread);
  506. new->thread.regs->msr |=
  507. (MSR_FP | new->thread.fpexc_mode);
  508. }
  509. #ifdef CONFIG_ALTIVEC
  510. if (msr & MSR_VEC) {
  511. do_load_up_transact_altivec(&new->thread);
  512. new->thread.regs->msr |= MSR_VEC;
  513. }
  514. #endif
  515. /* We may as well turn on VSX too since all the state is restored now */
  516. if (msr & MSR_VSX)
  517. new->thread.regs->msr |= MSR_VSX;
  518. TM_DEBUG("*** tm_recheckpoint of pid %d complete "
  519. "(kernel msr 0x%lx)\n",
  520. new->pid, mfmsr());
  521. }
  522. static inline void __switch_to_tm(struct task_struct *prev)
  523. {
  524. if (cpu_has_feature(CPU_FTR_TM)) {
  525. tm_enable();
  526. tm_reclaim_task(prev);
  527. }
  528. }
  529. #else
  530. #define tm_recheckpoint_new_task(new)
  531. #define __switch_to_tm(prev)
  532. #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  533. struct task_struct *__switch_to(struct task_struct *prev,
  534. struct task_struct *new)
  535. {
  536. struct thread_struct *new_thread, *old_thread;
  537. unsigned long flags;
  538. struct task_struct *last;
  539. #ifdef CONFIG_PPC_BOOK3S_64
  540. struct ppc64_tlb_batch *batch;
  541. #endif
  542. /* Back up the TAR across context switches.
  543. * Note that the TAR is not available for use in the kernel. (To
  544. * provide this, the TAR should be backed up/restored on exception
  545. * entry/exit instead, and be in pt_regs. FIXME, this should be in
  546. * pt_regs anyway (for debug).)
  547. * Save the TAR here before we do treclaim/trecheckpoint as these
  548. * will change the TAR.
  549. */
  550. save_tar(&prev->thread);
  551. __switch_to_tm(prev);
  552. #ifdef CONFIG_SMP
  553. /* avoid complexity of lazy save/restore of fpu
  554. * by just saving it every time we switch out if
  555. * this task used the fpu during the last quantum.
  556. *
  557. * If it tries to use the fpu again, it'll trap and
  558. * reload its fp regs. So we don't have to do a restore
  559. * every switch, just a save.
  560. * -- Cort
  561. */
  562. if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
  563. giveup_fpu(prev);
  564. #ifdef CONFIG_ALTIVEC
  565. /*
  566. * If the previous thread used altivec in the last quantum
  567. * (thus changing altivec regs) then save them.
  568. * We used to check the VRSAVE register but not all apps
  569. * set it, so we don't rely on it now (and in fact we need
  570. * to save & restore VSCR even if VRSAVE == 0). -- paulus
  571. *
  572. * On SMP we always save/restore altivec regs just to avoid the
  573. * complexity of changing processors.
  574. * -- Cort
  575. */
  576. if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
  577. giveup_altivec(prev);
  578. #endif /* CONFIG_ALTIVEC */
  579. #ifdef CONFIG_VSX
  580. if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
  581. /* VMX and FPU registers are already save here */
  582. __giveup_vsx(prev);
  583. #endif /* CONFIG_VSX */
  584. #ifdef CONFIG_SPE
  585. /*
  586. * If the previous thread used spe in the last quantum
  587. * (thus changing spe regs) then save them.
  588. *
  589. * On SMP we always save/restore spe regs just to avoid the
  590. * complexity of changing processors.
  591. */
  592. if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
  593. giveup_spe(prev);
  594. #endif /* CONFIG_SPE */
  595. #else /* CONFIG_SMP */
  596. #ifdef CONFIG_ALTIVEC
  597. /* Avoid the trap. On smp this this never happens since
  598. * we don't set last_task_used_altivec -- Cort
  599. */
  600. if (new->thread.regs && last_task_used_altivec == new)
  601. new->thread.regs->msr |= MSR_VEC;
  602. #endif /* CONFIG_ALTIVEC */
  603. #ifdef CONFIG_VSX
  604. if (new->thread.regs && last_task_used_vsx == new)
  605. new->thread.regs->msr |= MSR_VSX;
  606. #endif /* CONFIG_VSX */
  607. #ifdef CONFIG_SPE
  608. /* Avoid the trap. On smp this this never happens since
  609. * we don't set last_task_used_spe
  610. */
  611. if (new->thread.regs && last_task_used_spe == new)
  612. new->thread.regs->msr |= MSR_SPE;
  613. #endif /* CONFIG_SPE */
  614. #endif /* CONFIG_SMP */
  615. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  616. switch_booke_debug_regs(&new->thread);
  617. #else
  618. /*
  619. * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
  620. * schedule DABR
  621. */
  622. #ifndef CONFIG_HAVE_HW_BREAKPOINT
  623. if (unlikely(hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk)))
  624. set_breakpoint(&new->thread.hw_brk);
  625. #endif /* CONFIG_HAVE_HW_BREAKPOINT */
  626. #endif
  627. new_thread = &new->thread;
  628. old_thread = &current->thread;
  629. #ifdef CONFIG_PPC64
  630. /*
  631. * Collect processor utilization data per process
  632. */
  633. if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
  634. struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array);
  635. long unsigned start_tb, current_tb;
  636. start_tb = old_thread->start_tb;
  637. cu->current_tb = current_tb = mfspr(SPRN_PURR);
  638. old_thread->accum_tb += (current_tb - start_tb);
  639. new_thread->start_tb = current_tb;
  640. }
  641. #endif /* CONFIG_PPC64 */
  642. #ifdef CONFIG_PPC_BOOK3S_64
  643. batch = &__get_cpu_var(ppc64_tlb_batch);
  644. if (batch->active) {
  645. current_thread_info()->local_flags |= _TLF_LAZY_MMU;
  646. if (batch->index)
  647. __flush_tlb_pending(batch);
  648. batch->active = 0;
  649. }
  650. #endif /* CONFIG_PPC_BOOK3S_64 */
  651. local_irq_save(flags);
  652. /*
  653. * We can't take a PMU exception inside _switch() since there is a
  654. * window where the kernel stack SLB and the kernel stack are out
  655. * of sync. Hard disable here.
  656. */
  657. hard_irq_disable();
  658. tm_recheckpoint_new_task(new);
  659. last = _switch(old_thread, new_thread);
  660. #ifdef CONFIG_PPC_BOOK3S_64
  661. if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
  662. current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
  663. batch = &__get_cpu_var(ppc64_tlb_batch);
  664. batch->active = 1;
  665. }
  666. #endif /* CONFIG_PPC_BOOK3S_64 */
  667. local_irq_restore(flags);
  668. return last;
  669. }
  670. static int instructions_to_print = 16;
  671. static void show_instructions(struct pt_regs *regs)
  672. {
  673. int i;
  674. unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
  675. sizeof(int));
  676. printk("Instruction dump:");
  677. for (i = 0; i < instructions_to_print; i++) {
  678. int instr;
  679. if (!(i % 8))
  680. printk("\n");
  681. #if !defined(CONFIG_BOOKE)
  682. /* If executing with the IMMU off, adjust pc rather
  683. * than print XXXXXXXX.
  684. */
  685. if (!(regs->msr & MSR_IR))
  686. pc = (unsigned long)phys_to_virt(pc);
  687. #endif
  688. /* We use __get_user here *only* to avoid an OOPS on a
  689. * bad address because the pc *should* only be a
  690. * kernel address.
  691. */
  692. if (!__kernel_text_address(pc) ||
  693. __get_user(instr, (unsigned int __user *)pc)) {
  694. printk(KERN_CONT "XXXXXXXX ");
  695. } else {
  696. if (regs->nip == pc)
  697. printk(KERN_CONT "<%08x> ", instr);
  698. else
  699. printk(KERN_CONT "%08x ", instr);
  700. }
  701. pc += sizeof(int);
  702. }
  703. printk("\n");
  704. }
  705. static struct regbit {
  706. unsigned long bit;
  707. const char *name;
  708. } msr_bits[] = {
  709. #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
  710. {MSR_SF, "SF"},
  711. {MSR_HV, "HV"},
  712. #endif
  713. {MSR_VEC, "VEC"},
  714. {MSR_VSX, "VSX"},
  715. #ifdef CONFIG_BOOKE
  716. {MSR_CE, "CE"},
  717. #endif
  718. {MSR_EE, "EE"},
  719. {MSR_PR, "PR"},
  720. {MSR_FP, "FP"},
  721. {MSR_ME, "ME"},
  722. #ifdef CONFIG_BOOKE
  723. {MSR_DE, "DE"},
  724. #else
  725. {MSR_SE, "SE"},
  726. {MSR_BE, "BE"},
  727. #endif
  728. {MSR_IR, "IR"},
  729. {MSR_DR, "DR"},
  730. {MSR_PMM, "PMM"},
  731. #ifndef CONFIG_BOOKE
  732. {MSR_RI, "RI"},
  733. {MSR_LE, "LE"},
  734. #endif
  735. {0, NULL}
  736. };
  737. static void printbits(unsigned long val, struct regbit *bits)
  738. {
  739. const char *sep = "";
  740. printk("<");
  741. for (; bits->bit; ++bits)
  742. if (val & bits->bit) {
  743. printk("%s%s", sep, bits->name);
  744. sep = ",";
  745. }
  746. printk(">");
  747. }
  748. #ifdef CONFIG_PPC64
  749. #define REG "%016lx"
  750. #define REGS_PER_LINE 4
  751. #define LAST_VOLATILE 13
  752. #else
  753. #define REG "%08lx"
  754. #define REGS_PER_LINE 8
  755. #define LAST_VOLATILE 12
  756. #endif
  757. void show_regs(struct pt_regs * regs)
  758. {
  759. int i, trap;
  760. show_regs_print_info(KERN_DEFAULT);
  761. printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
  762. regs->nip, regs->link, regs->ctr);
  763. printk("REGS: %p TRAP: %04lx %s (%s)\n",
  764. regs, regs->trap, print_tainted(), init_utsname()->release);
  765. printk("MSR: "REG" ", regs->msr);
  766. printbits(regs->msr, msr_bits);
  767. printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
  768. #ifdef CONFIG_PPC64
  769. printk("SOFTE: %ld\n", regs->softe);
  770. #endif
  771. trap = TRAP(regs);
  772. if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
  773. printk("CFAR: "REG"\n", regs->orig_gpr3);
  774. if (trap == 0x300 || trap == 0x600)
  775. #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
  776. printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr);
  777. #else
  778. printk("DAR: "REG", DSISR: %08lx\n", regs->dar, regs->dsisr);
  779. #endif
  780. for (i = 0; i < 32; i++) {
  781. if ((i % REGS_PER_LINE) == 0)
  782. printk("\nGPR%02d: ", i);
  783. printk(REG " ", regs->gpr[i]);
  784. if (i == LAST_VOLATILE && !FULL_REGS(regs))
  785. break;
  786. }
  787. printk("\n");
  788. #ifdef CONFIG_KALLSYMS
  789. /*
  790. * Lookup NIP late so we have the best change of getting the
  791. * above info out without failing
  792. */
  793. printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
  794. printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
  795. #endif
  796. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  797. printk("PACATMSCRATCH [%llx]\n", get_paca()->tm_scratch);
  798. #endif
  799. show_stack(current, (unsigned long *) regs->gpr[1]);
  800. if (!user_mode(regs))
  801. show_instructions(regs);
  802. }
  803. void exit_thread(void)
  804. {
  805. discard_lazy_cpu_state();
  806. }
  807. void flush_thread(void)
  808. {
  809. discard_lazy_cpu_state();
  810. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  811. flush_ptrace_hw_breakpoint(current);
  812. #else /* CONFIG_HAVE_HW_BREAKPOINT */
  813. set_debug_reg_defaults(&current->thread);
  814. #endif /* CONFIG_HAVE_HW_BREAKPOINT */
  815. }
  816. void
  817. release_thread(struct task_struct *t)
  818. {
  819. }
  820. /*
  821. * this gets called so that we can store coprocessor state into memory and
  822. * copy the current task into the new thread.
  823. */
  824. int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  825. {
  826. flush_fp_to_thread(src);
  827. flush_altivec_to_thread(src);
  828. flush_vsx_to_thread(src);
  829. flush_spe_to_thread(src);
  830. *dst = *src;
  831. clear_task_ebb(dst);
  832. return 0;
  833. }
  834. /*
  835. * Copy a thread..
  836. */
  837. extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */
  838. int copy_thread(unsigned long clone_flags, unsigned long usp,
  839. unsigned long arg, struct task_struct *p)
  840. {
  841. struct pt_regs *childregs, *kregs;
  842. extern void ret_from_fork(void);
  843. extern void ret_from_kernel_thread(void);
  844. void (*f)(void);
  845. unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
  846. /* Copy registers */
  847. sp -= sizeof(struct pt_regs);
  848. childregs = (struct pt_regs *) sp;
  849. if (unlikely(p->flags & PF_KTHREAD)) {
  850. struct thread_info *ti = (void *)task_stack_page(p);
  851. memset(childregs, 0, sizeof(struct pt_regs));
  852. childregs->gpr[1] = sp + sizeof(struct pt_regs);
  853. childregs->gpr[14] = usp; /* function */
  854. #ifdef CONFIG_PPC64
  855. clear_tsk_thread_flag(p, TIF_32BIT);
  856. childregs->softe = 1;
  857. #endif
  858. childregs->gpr[15] = arg;
  859. p->thread.regs = NULL; /* no user register state */
  860. ti->flags |= _TIF_RESTOREALL;
  861. f = ret_from_kernel_thread;
  862. } else {
  863. struct pt_regs *regs = current_pt_regs();
  864. CHECK_FULL_REGS(regs);
  865. *childregs = *regs;
  866. if (usp)
  867. childregs->gpr[1] = usp;
  868. p->thread.regs = childregs;
  869. childregs->gpr[3] = 0; /* Result from fork() */
  870. if (clone_flags & CLONE_SETTLS) {
  871. #ifdef CONFIG_PPC64
  872. if (!is_32bit_task())
  873. childregs->gpr[13] = childregs->gpr[6];
  874. else
  875. #endif
  876. childregs->gpr[2] = childregs->gpr[6];
  877. }
  878. f = ret_from_fork;
  879. }
  880. sp -= STACK_FRAME_OVERHEAD;
  881. /*
  882. * The way this works is that at some point in the future
  883. * some task will call _switch to switch to the new task.
  884. * That will pop off the stack frame created below and start
  885. * the new task running at ret_from_fork. The new task will
  886. * do some house keeping and then return from the fork or clone
  887. * system call, using the stack frame created above.
  888. */
  889. ((unsigned long *)sp)[0] = 0;
  890. sp -= sizeof(struct pt_regs);
  891. kregs = (struct pt_regs *) sp;
  892. sp -= STACK_FRAME_OVERHEAD;
  893. p->thread.ksp = sp;
  894. #ifdef CONFIG_PPC32
  895. p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
  896. _ALIGN_UP(sizeof(struct thread_info), 16);
  897. #endif
  898. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  899. p->thread.ptrace_bps[0] = NULL;
  900. #endif
  901. #ifdef CONFIG_PPC_STD_MMU_64
  902. if (mmu_has_feature(MMU_FTR_SLB)) {
  903. unsigned long sp_vsid;
  904. unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
  905. if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
  906. sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
  907. << SLB_VSID_SHIFT_1T;
  908. else
  909. sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
  910. << SLB_VSID_SHIFT;
  911. sp_vsid |= SLB_VSID_KERNEL | llp;
  912. p->thread.ksp_vsid = sp_vsid;
  913. }
  914. #endif /* CONFIG_PPC_STD_MMU_64 */
  915. #ifdef CONFIG_PPC64
  916. if (cpu_has_feature(CPU_FTR_DSCR)) {
  917. p->thread.dscr_inherit = current->thread.dscr_inherit;
  918. p->thread.dscr = current->thread.dscr;
  919. }
  920. if (cpu_has_feature(CPU_FTR_HAS_PPR))
  921. p->thread.ppr = INIT_PPR;
  922. #endif
  923. /*
  924. * The PPC64 ABI makes use of a TOC to contain function
  925. * pointers. The function (ret_from_except) is actually a pointer
  926. * to the TOC entry. The first entry is a pointer to the actual
  927. * function.
  928. */
  929. #ifdef CONFIG_PPC64
  930. kregs->nip = *((unsigned long *)f);
  931. #else
  932. kregs->nip = (unsigned long)f;
  933. #endif
  934. return 0;
  935. }
  936. /*
  937. * Set up a thread for executing a new program
  938. */
  939. void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
  940. {
  941. #ifdef CONFIG_PPC64
  942. unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
  943. #endif
  944. /*
  945. * If we exec out of a kernel thread then thread.regs will not be
  946. * set. Do it now.
  947. */
  948. if (!current->thread.regs) {
  949. struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
  950. current->thread.regs = regs - 1;
  951. }
  952. memset(regs->gpr, 0, sizeof(regs->gpr));
  953. regs->ctr = 0;
  954. regs->link = 0;
  955. regs->xer = 0;
  956. regs->ccr = 0;
  957. regs->gpr[1] = sp;
  958. /*
  959. * We have just cleared all the nonvolatile GPRs, so make
  960. * FULL_REGS(regs) return true. This is necessary to allow
  961. * ptrace to examine the thread immediately after exec.
  962. */
  963. regs->trap &= ~1UL;
  964. #ifdef CONFIG_PPC32
  965. regs->mq = 0;
  966. regs->nip = start;
  967. regs->msr = MSR_USER;
  968. #else
  969. if (!is_32bit_task()) {
  970. unsigned long entry, toc;
  971. /* start is a relocated pointer to the function descriptor for
  972. * the elf _start routine. The first entry in the function
  973. * descriptor is the entry address of _start and the second
  974. * entry is the TOC value we need to use.
  975. */
  976. __get_user(entry, (unsigned long __user *)start);
  977. __get_user(toc, (unsigned long __user *)start+1);
  978. /* Check whether the e_entry function descriptor entries
  979. * need to be relocated before we can use them.
  980. */
  981. if (load_addr != 0) {
  982. entry += load_addr;
  983. toc += load_addr;
  984. }
  985. regs->nip = entry;
  986. regs->gpr[2] = toc;
  987. regs->msr = MSR_USER64;
  988. } else {
  989. regs->nip = start;
  990. regs->gpr[2] = 0;
  991. regs->msr = MSR_USER32;
  992. }
  993. #endif
  994. discard_lazy_cpu_state();
  995. #ifdef CONFIG_VSX
  996. current->thread.used_vsr = 0;
  997. #endif
  998. memset(current->thread.fpr, 0, sizeof(current->thread.fpr));
  999. current->thread.fpscr.val = 0;
  1000. #ifdef CONFIG_ALTIVEC
  1001. memset(current->thread.vr, 0, sizeof(current->thread.vr));
  1002. memset(&current->thread.vscr, 0, sizeof(current->thread.vscr));
  1003. current->thread.vscr.u[3] = 0x00010000; /* Java mode disabled */
  1004. current->thread.vrsave = 0;
  1005. current->thread.used_vr = 0;
  1006. #endif /* CONFIG_ALTIVEC */
  1007. #ifdef CONFIG_SPE
  1008. memset(current->thread.evr, 0, sizeof(current->thread.evr));
  1009. current->thread.acc = 0;
  1010. current->thread.spefscr = 0;
  1011. current->thread.used_spe = 0;
  1012. #endif /* CONFIG_SPE */
  1013. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1014. if (cpu_has_feature(CPU_FTR_TM))
  1015. regs->msr |= MSR_TM;
  1016. current->thread.tm_tfhar = 0;
  1017. current->thread.tm_texasr = 0;
  1018. current->thread.tm_tfiar = 0;
  1019. #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  1020. }
  1021. #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
  1022. | PR_FP_EXC_RES | PR_FP_EXC_INV)
  1023. int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
  1024. {
  1025. struct pt_regs *regs = tsk->thread.regs;
  1026. /* This is a bit hairy. If we are an SPE enabled processor
  1027. * (have embedded fp) we store the IEEE exception enable flags in
  1028. * fpexc_mode. fpexc_mode is also used for setting FP exception
  1029. * mode (asyn, precise, disabled) for 'Classic' FP. */
  1030. if (val & PR_FP_EXC_SW_ENABLE) {
  1031. #ifdef CONFIG_SPE
  1032. if (cpu_has_feature(CPU_FTR_SPE)) {
  1033. tsk->thread.fpexc_mode = val &
  1034. (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
  1035. return 0;
  1036. } else {
  1037. return -EINVAL;
  1038. }
  1039. #else
  1040. return -EINVAL;
  1041. #endif
  1042. }
  1043. /* on a CONFIG_SPE this does not hurt us. The bits that
  1044. * __pack_fe01 use do not overlap with bits used for
  1045. * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
  1046. * on CONFIG_SPE implementations are reserved so writing to
  1047. * them does not change anything */
  1048. if (val > PR_FP_EXC_PRECISE)
  1049. return -EINVAL;
  1050. tsk->thread.fpexc_mode = __pack_fe01(val);
  1051. if (regs != NULL && (regs->msr & MSR_FP) != 0)
  1052. regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
  1053. | tsk->thread.fpexc_mode;
  1054. return 0;
  1055. }
  1056. int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
  1057. {
  1058. unsigned int val;
  1059. if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
  1060. #ifdef CONFIG_SPE
  1061. if (cpu_has_feature(CPU_FTR_SPE))
  1062. val = tsk->thread.fpexc_mode;
  1063. else
  1064. return -EINVAL;
  1065. #else
  1066. return -EINVAL;
  1067. #endif
  1068. else
  1069. val = __unpack_fe01(tsk->thread.fpexc_mode);
  1070. return put_user(val, (unsigned int __user *) adr);
  1071. }
  1072. int set_endian(struct task_struct *tsk, unsigned int val)
  1073. {
  1074. struct pt_regs *regs = tsk->thread.regs;
  1075. if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
  1076. (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
  1077. return -EINVAL;
  1078. if (regs == NULL)
  1079. return -EINVAL;
  1080. if (val == PR_ENDIAN_BIG)
  1081. regs->msr &= ~MSR_LE;
  1082. else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
  1083. regs->msr |= MSR_LE;
  1084. else
  1085. return -EINVAL;
  1086. return 0;
  1087. }
  1088. int get_endian(struct task_struct *tsk, unsigned long adr)
  1089. {
  1090. struct pt_regs *regs = tsk->thread.regs;
  1091. unsigned int val;
  1092. if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
  1093. !cpu_has_feature(CPU_FTR_REAL_LE))
  1094. return -EINVAL;
  1095. if (regs == NULL)
  1096. return -EINVAL;
  1097. if (regs->msr & MSR_LE) {
  1098. if (cpu_has_feature(CPU_FTR_REAL_LE))
  1099. val = PR_ENDIAN_LITTLE;
  1100. else
  1101. val = PR_ENDIAN_PPC_LITTLE;
  1102. } else
  1103. val = PR_ENDIAN_BIG;
  1104. return put_user(val, (unsigned int __user *)adr);
  1105. }
  1106. int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
  1107. {
  1108. tsk->thread.align_ctl = val;
  1109. return 0;
  1110. }
  1111. int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
  1112. {
  1113. return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
  1114. }
  1115. static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
  1116. unsigned long nbytes)
  1117. {
  1118. unsigned long stack_page;
  1119. unsigned long cpu = task_cpu(p);
  1120. /*
  1121. * Avoid crashing if the stack has overflowed and corrupted
  1122. * task_cpu(p), which is in the thread_info struct.
  1123. */
  1124. if (cpu < NR_CPUS && cpu_possible(cpu)) {
  1125. stack_page = (unsigned long) hardirq_ctx[cpu];
  1126. if (sp >= stack_page + sizeof(struct thread_struct)
  1127. && sp <= stack_page + THREAD_SIZE - nbytes)
  1128. return 1;
  1129. stack_page = (unsigned long) softirq_ctx[cpu];
  1130. if (sp >= stack_page + sizeof(struct thread_struct)
  1131. && sp <= stack_page + THREAD_SIZE - nbytes)
  1132. return 1;
  1133. }
  1134. return 0;
  1135. }
  1136. int validate_sp(unsigned long sp, struct task_struct *p,
  1137. unsigned long nbytes)
  1138. {
  1139. unsigned long stack_page = (unsigned long)task_stack_page(p);
  1140. if (sp >= stack_page + sizeof(struct thread_struct)
  1141. && sp <= stack_page + THREAD_SIZE - nbytes)
  1142. return 1;
  1143. return valid_irq_stack(sp, p, nbytes);
  1144. }
  1145. EXPORT_SYMBOL(validate_sp);
  1146. unsigned long get_wchan(struct task_struct *p)
  1147. {
  1148. unsigned long ip, sp;
  1149. int count = 0;
  1150. if (!p || p == current || p->state == TASK_RUNNING)
  1151. return 0;
  1152. sp = p->thread.ksp;
  1153. if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
  1154. return 0;
  1155. do {
  1156. sp = *(unsigned long *)sp;
  1157. if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
  1158. return 0;
  1159. if (count > 0) {
  1160. ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
  1161. if (!in_sched_functions(ip))
  1162. return ip;
  1163. }
  1164. } while (count++ < 16);
  1165. return 0;
  1166. }
  1167. static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
  1168. void show_stack(struct task_struct *tsk, unsigned long *stack)
  1169. {
  1170. unsigned long sp, ip, lr, newsp;
  1171. int count = 0;
  1172. int firstframe = 1;
  1173. #ifdef CONFIG_FUNCTION_GRAPH_TRACER
  1174. int curr_frame = current->curr_ret_stack;
  1175. extern void return_to_handler(void);
  1176. unsigned long rth = (unsigned long)return_to_handler;
  1177. unsigned long mrth = -1;
  1178. #ifdef CONFIG_PPC64
  1179. extern void mod_return_to_handler(void);
  1180. rth = *(unsigned long *)rth;
  1181. mrth = (unsigned long)mod_return_to_handler;
  1182. mrth = *(unsigned long *)mrth;
  1183. #endif
  1184. #endif
  1185. sp = (unsigned long) stack;
  1186. if (tsk == NULL)
  1187. tsk = current;
  1188. if (sp == 0) {
  1189. if (tsk == current)
  1190. asm("mr %0,1" : "=r" (sp));
  1191. else
  1192. sp = tsk->thread.ksp;
  1193. }
  1194. lr = 0;
  1195. printk("Call Trace:\n");
  1196. do {
  1197. if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
  1198. return;
  1199. stack = (unsigned long *) sp;
  1200. newsp = stack[0];
  1201. ip = stack[STACK_FRAME_LR_SAVE];
  1202. if (!firstframe || ip != lr) {
  1203. printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
  1204. #ifdef CONFIG_FUNCTION_GRAPH_TRACER
  1205. if ((ip == rth || ip == mrth) && curr_frame >= 0) {
  1206. printk(" (%pS)",
  1207. (void *)current->ret_stack[curr_frame].ret);
  1208. curr_frame--;
  1209. }
  1210. #endif
  1211. if (firstframe)
  1212. printk(" (unreliable)");
  1213. printk("\n");
  1214. }
  1215. firstframe = 0;
  1216. /*
  1217. * See if this is an exception frame.
  1218. * We look for the "regshere" marker in the current frame.
  1219. */
  1220. if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
  1221. && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
  1222. struct pt_regs *regs = (struct pt_regs *)
  1223. (sp + STACK_FRAME_OVERHEAD);
  1224. lr = regs->link;
  1225. printk("--- Exception: %lx at %pS\n LR = %pS\n",
  1226. regs->trap, (void *)regs->nip, (void *)lr);
  1227. firstframe = 1;
  1228. }
  1229. sp = newsp;
  1230. } while (count++ < kstack_depth_to_print);
  1231. }
  1232. #ifdef CONFIG_PPC64
  1233. /* Called with hard IRQs off */
  1234. void notrace __ppc64_runlatch_on(void)
  1235. {
  1236. struct thread_info *ti = current_thread_info();
  1237. unsigned long ctrl;
  1238. ctrl = mfspr(SPRN_CTRLF);
  1239. ctrl |= CTRL_RUNLATCH;
  1240. mtspr(SPRN_CTRLT, ctrl);
  1241. ti->local_flags |= _TLF_RUNLATCH;
  1242. }
  1243. /* Called with hard IRQs off */
  1244. void notrace __ppc64_runlatch_off(void)
  1245. {
  1246. struct thread_info *ti = current_thread_info();
  1247. unsigned long ctrl;
  1248. ti->local_flags &= ~_TLF_RUNLATCH;
  1249. ctrl = mfspr(SPRN_CTRLF);
  1250. ctrl &= ~CTRL_RUNLATCH;
  1251. mtspr(SPRN_CTRLT, ctrl);
  1252. }
  1253. #endif /* CONFIG_PPC64 */
  1254. unsigned long arch_align_stack(unsigned long sp)
  1255. {
  1256. if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
  1257. sp -= get_random_int() & ~PAGE_MASK;
  1258. return sp & ~0xf;
  1259. }
  1260. static inline unsigned long brk_rnd(void)
  1261. {
  1262. unsigned long rnd = 0;
  1263. /* 8MB for 32bit, 1GB for 64bit */
  1264. if (is_32bit_task())
  1265. rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
  1266. else
  1267. rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
  1268. return rnd << PAGE_SHIFT;
  1269. }
  1270. unsigned long arch_randomize_brk(struct mm_struct *mm)
  1271. {
  1272. unsigned long base = mm->brk;
  1273. unsigned long ret;
  1274. #ifdef CONFIG_PPC_STD_MMU_64
  1275. /*
  1276. * If we are using 1TB segments and we are allowed to randomise
  1277. * the heap, we can put it above 1TB so it is backed by a 1TB
  1278. * segment. Otherwise the heap will be in the bottom 1TB
  1279. * which always uses 256MB segments and this may result in a
  1280. * performance penalty.
  1281. */
  1282. if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
  1283. base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
  1284. #endif
  1285. ret = PAGE_ALIGN(base + brk_rnd());
  1286. if (ret < mm->brk)
  1287. return mm->brk;
  1288. return ret;
  1289. }
  1290. unsigned long randomize_et_dyn(unsigned long base)
  1291. {
  1292. unsigned long ret = PAGE_ALIGN(base + brk_rnd());
  1293. if (ret < base)
  1294. return base;
  1295. return ret;
  1296. }