accel.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541
  1. /*
  2. * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
  3. * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public
  6. * License as published by the Free Software Foundation;
  7. * either version 2, or (at your option) any later version.
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  10. * the implied warranty of MERCHANTABILITY or FITNESS FOR
  11. * A PARTICULAR PURPOSE.See the GNU General Public License
  12. * for more details.
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc.,
  16. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. */
  18. #include "global.h"
  19. static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height,
  20. u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
  21. u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
  22. u32 fg_color, u32 bg_color, u8 fill_rop)
  23. {
  24. u32 ge_cmd = 0, tmp, i;
  25. if (!op || op > 3) {
  26. printk(KERN_WARNING "hw_bitblt_1: Invalid operation: %d\n", op);
  27. return -EINVAL;
  28. }
  29. if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
  30. if (src_x < dst_x) {
  31. ge_cmd |= 0x00008000;
  32. src_x += width - 1;
  33. dst_x += width - 1;
  34. }
  35. if (src_y < dst_y) {
  36. ge_cmd |= 0x00004000;
  37. src_y += height - 1;
  38. dst_y += height - 1;
  39. }
  40. }
  41. if (op == VIA_BITBLT_FILL) {
  42. switch (fill_rop) {
  43. case 0x00: /* blackness */
  44. case 0x5A: /* pattern inversion */
  45. case 0xF0: /* pattern copy */
  46. case 0xFF: /* whiteness */
  47. break;
  48. default:
  49. printk(KERN_WARNING "hw_bitblt_1: Invalid fill rop: "
  50. "%u\n", fill_rop);
  51. return -EINVAL;
  52. }
  53. }
  54. switch (dst_bpp) {
  55. case 8:
  56. tmp = 0x00000000;
  57. break;
  58. case 16:
  59. tmp = 0x00000100;
  60. break;
  61. case 32:
  62. tmp = 0x00000300;
  63. break;
  64. default:
  65. printk(KERN_WARNING "hw_bitblt_1: Unsupported bpp %d\n",
  66. dst_bpp);
  67. return -EINVAL;
  68. }
  69. writel(tmp, engine + 0x04);
  70. if (op != VIA_BITBLT_FILL) {
  71. if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
  72. || src_y & 0xFFFFF000) {
  73. printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
  74. "x/y %d %d\n", src_x, src_y);
  75. return -EINVAL;
  76. }
  77. tmp = src_x | (src_y << 16);
  78. writel(tmp, engine + 0x08);
  79. }
  80. if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
  81. printk(KERN_WARNING "hw_bitblt_1: Unsupported destination x/y "
  82. "%d %d\n", dst_x, dst_y);
  83. return -EINVAL;
  84. }
  85. tmp = dst_x | (dst_y << 16);
  86. writel(tmp, engine + 0x0C);
  87. if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
  88. printk(KERN_WARNING "hw_bitblt_1: Unsupported width/height "
  89. "%d %d\n", width, height);
  90. return -EINVAL;
  91. }
  92. tmp = (width - 1) | ((height - 1) << 16);
  93. writel(tmp, engine + 0x10);
  94. if (op != VIA_BITBLT_COLOR)
  95. writel(fg_color, engine + 0x18);
  96. if (op == VIA_BITBLT_MONO)
  97. writel(bg_color, engine + 0x1C);
  98. if (op != VIA_BITBLT_FILL) {
  99. tmp = src_mem ? 0 : src_addr;
  100. if (dst_addr & 0xE0000007) {
  101. printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
  102. "address %X\n", tmp);
  103. return -EINVAL;
  104. }
  105. tmp >>= 3;
  106. writel(tmp, engine + 0x30);
  107. }
  108. if (dst_addr & 0xE0000007) {
  109. printk(KERN_WARNING "hw_bitblt_1: Unsupported destination "
  110. "address %X\n", dst_addr);
  111. return -EINVAL;
  112. }
  113. tmp = dst_addr >> 3;
  114. writel(tmp, engine + 0x34);
  115. if (op == VIA_BITBLT_FILL)
  116. tmp = 0;
  117. else
  118. tmp = src_pitch;
  119. if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
  120. printk(KERN_WARNING "hw_bitblt_1: Unsupported pitch %X %X\n",
  121. tmp, dst_pitch);
  122. return -EINVAL;
  123. }
  124. tmp = (tmp >> 3) | (dst_pitch << (16 - 3));
  125. writel(tmp, engine + 0x38);
  126. if (op == VIA_BITBLT_FILL)
  127. ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
  128. else {
  129. ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
  130. if (src_mem)
  131. ge_cmd |= 0x00000040;
  132. if (op == VIA_BITBLT_MONO)
  133. ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
  134. else
  135. ge_cmd |= 0x00000001;
  136. }
  137. writel(ge_cmd, engine);
  138. if (op == VIA_BITBLT_FILL || !src_mem)
  139. return 0;
  140. tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
  141. 3) >> 2;
  142. for (i = 0; i < tmp; i++)
  143. writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
  144. return 0;
  145. }
  146. static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
  147. u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
  148. u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
  149. u32 fg_color, u32 bg_color, u8 fill_rop)
  150. {
  151. u32 ge_cmd = 0, tmp, i;
  152. if (!op || op > 3) {
  153. printk(KERN_WARNING "hw_bitblt_2: Invalid operation: %d\n", op);
  154. return -EINVAL;
  155. }
  156. if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
  157. if (src_x < dst_x) {
  158. ge_cmd |= 0x00008000;
  159. src_x += width - 1;
  160. dst_x += width - 1;
  161. }
  162. if (src_y < dst_y) {
  163. ge_cmd |= 0x00004000;
  164. src_y += height - 1;
  165. dst_y += height - 1;
  166. }
  167. }
  168. if (op == VIA_BITBLT_FILL) {
  169. switch (fill_rop) {
  170. case 0x00: /* blackness */
  171. case 0x5A: /* pattern inversion */
  172. case 0xF0: /* pattern copy */
  173. case 0xFF: /* whiteness */
  174. break;
  175. default:
  176. printk(KERN_WARNING "hw_bitblt_2: Invalid fill rop: "
  177. "%u\n", fill_rop);
  178. return -EINVAL;
  179. }
  180. }
  181. switch (dst_bpp) {
  182. case 8:
  183. tmp = 0x00000000;
  184. break;
  185. case 16:
  186. tmp = 0x00000100;
  187. break;
  188. case 32:
  189. tmp = 0x00000300;
  190. break;
  191. default:
  192. printk(KERN_WARNING "hw_bitblt_2: Unsupported bpp %d\n",
  193. dst_bpp);
  194. return -EINVAL;
  195. }
  196. writel(tmp, engine + 0x04);
  197. if (op == VIA_BITBLT_FILL)
  198. tmp = 0;
  199. else
  200. tmp = src_pitch;
  201. if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
  202. printk(KERN_WARNING "hw_bitblt_2: Unsupported pitch %X %X\n",
  203. tmp, dst_pitch);
  204. return -EINVAL;
  205. }
  206. tmp = (tmp >> 3) | (dst_pitch << (16 - 3));
  207. writel(tmp, engine + 0x08);
  208. if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
  209. printk(KERN_WARNING "hw_bitblt_2: Unsupported width/height "
  210. "%d %d\n", width, height);
  211. return -EINVAL;
  212. }
  213. tmp = (width - 1) | ((height - 1) << 16);
  214. writel(tmp, engine + 0x0C);
  215. if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
  216. printk(KERN_WARNING "hw_bitblt_2: Unsupported destination x/y "
  217. "%d %d\n", dst_x, dst_y);
  218. return -EINVAL;
  219. }
  220. tmp = dst_x | (dst_y << 16);
  221. writel(tmp, engine + 0x10);
  222. if (dst_addr & 0xE0000007) {
  223. printk(KERN_WARNING "hw_bitblt_2: Unsupported destination "
  224. "address %X\n", dst_addr);
  225. return -EINVAL;
  226. }
  227. tmp = dst_addr >> 3;
  228. writel(tmp, engine + 0x14);
  229. if (op != VIA_BITBLT_FILL) {
  230. if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
  231. || src_y & 0xFFFFF000) {
  232. printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
  233. "x/y %d %d\n", src_x, src_y);
  234. return -EINVAL;
  235. }
  236. tmp = src_x | (src_y << 16);
  237. writel(tmp, engine + 0x18);
  238. tmp = src_mem ? 0 : src_addr;
  239. if (dst_addr & 0xE0000007) {
  240. printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
  241. "address %X\n", tmp);
  242. return -EINVAL;
  243. }
  244. tmp >>= 3;
  245. writel(tmp, engine + 0x1C);
  246. }
  247. if (op != VIA_BITBLT_COLOR)
  248. writel(fg_color, engine + 0x4C);
  249. if (op == VIA_BITBLT_MONO)
  250. writel(bg_color, engine + 0x50);
  251. if (op == VIA_BITBLT_FILL)
  252. ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
  253. else {
  254. ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
  255. if (src_mem)
  256. ge_cmd |= 0x00000040;
  257. if (op == VIA_BITBLT_MONO)
  258. ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
  259. else
  260. ge_cmd |= 0x00000001;
  261. }
  262. writel(ge_cmd, engine);
  263. if (op == VIA_BITBLT_FILL || !src_mem)
  264. return 0;
  265. tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
  266. 3) >> 2;
  267. for (i = 0; i < tmp; i++)
  268. writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
  269. return 0;
  270. }
  271. void viafb_init_accel(struct viafb_shared *shared)
  272. {
  273. switch (shared->chip_info.gfx_chip_name) {
  274. case UNICHROME_CLE266:
  275. case UNICHROME_K400:
  276. case UNICHROME_K800:
  277. case UNICHROME_PM800:
  278. case UNICHROME_CN700:
  279. case UNICHROME_CX700:
  280. case UNICHROME_CN750:
  281. case UNICHROME_K8M890:
  282. case UNICHROME_P4M890:
  283. case UNICHROME_P4M900:
  284. shared->hw_bitblt = hw_bitblt_1;
  285. break;
  286. case UNICHROME_VX800:
  287. shared->hw_bitblt = hw_bitblt_2;
  288. break;
  289. default:
  290. shared->hw_bitblt = NULL;
  291. }
  292. viaparinfo->fbmem_free -= CURSOR_SIZE;
  293. viaparinfo->cursor_start = viaparinfo->fbmem_free;
  294. viaparinfo->fbmem_used += CURSOR_SIZE;
  295. /* Reverse 8*1024 memory space for cursor image */
  296. viaparinfo->fbmem_free -= (CURSOR_SIZE + VQ_SIZE);
  297. viaparinfo->VQ_start = viaparinfo->fbmem_free;
  298. viaparinfo->VQ_end = viaparinfo->VQ_start + VQ_SIZE - 1;
  299. viaparinfo->fbmem_used += (CURSOR_SIZE + VQ_SIZE);
  300. }
  301. void viafb_init_2d_engine(void)
  302. {
  303. u32 dwVQStartAddr, dwVQEndAddr;
  304. u32 dwVQLen, dwVQStartL, dwVQEndL, dwVQStartEndH;
  305. /* Init AGP and VQ regs */
  306. switch (viaparinfo->chip_info->gfx_chip_name) {
  307. case UNICHROME_K8M890:
  308. case UNICHROME_P4M900:
  309. writel(0x00100000, viaparinfo->io_virt + VIA_REG_CR_TRANSET);
  310. writel(0x680A0000, viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
  311. writel(0x02000000, viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
  312. break;
  313. default:
  314. writel(0x00100000, viaparinfo->io_virt + VIA_REG_TRANSET);
  315. writel(0x00000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
  316. writel(0x00333004, viaparinfo->io_virt + VIA_REG_TRANSPACE);
  317. writel(0x60000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
  318. writel(0x61000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
  319. writel(0x62000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
  320. writel(0x63000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
  321. writel(0x64000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
  322. writel(0x7D000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
  323. writel(0xFE020000, viaparinfo->io_virt + VIA_REG_TRANSET);
  324. writel(0x00000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
  325. break;
  326. }
  327. if (viaparinfo->VQ_start != 0) {
  328. /* Enable VQ */
  329. dwVQStartAddr = viaparinfo->VQ_start;
  330. dwVQEndAddr = viaparinfo->VQ_end;
  331. dwVQStartL = 0x50000000 | (dwVQStartAddr & 0xFFFFFF);
  332. dwVQEndL = 0x51000000 | (dwVQEndAddr & 0xFFFFFF);
  333. dwVQStartEndH = 0x52000000 |
  334. ((dwVQStartAddr & 0xFF000000) >> 24) |
  335. ((dwVQEndAddr & 0xFF000000) >> 16);
  336. dwVQLen = 0x53000000 | (VQ_SIZE >> 3);
  337. switch (viaparinfo->chip_info->gfx_chip_name) {
  338. case UNICHROME_K8M890:
  339. case UNICHROME_P4M900:
  340. dwVQStartL |= 0x20000000;
  341. dwVQEndL |= 0x20000000;
  342. dwVQStartEndH |= 0x20000000;
  343. dwVQLen |= 0x20000000;
  344. break;
  345. default:
  346. break;
  347. }
  348. switch (viaparinfo->chip_info->gfx_chip_name) {
  349. case UNICHROME_K8M890:
  350. case UNICHROME_P4M900:
  351. writel(0x00100000,
  352. viaparinfo->io_virt + VIA_REG_CR_TRANSET);
  353. writel(dwVQStartEndH,
  354. viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
  355. writel(dwVQStartL,
  356. viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
  357. writel(dwVQEndL,
  358. viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
  359. writel(dwVQLen,
  360. viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
  361. writel(0x74301001,
  362. viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
  363. writel(0x00000000,
  364. viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
  365. break;
  366. default:
  367. writel(0x00FE0000,
  368. viaparinfo->io_virt + VIA_REG_TRANSET);
  369. writel(0x080003FE,
  370. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  371. writel(0x0A00027C,
  372. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  373. writel(0x0B000260,
  374. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  375. writel(0x0C000274,
  376. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  377. writel(0x0D000264,
  378. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  379. writel(0x0E000000,
  380. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  381. writel(0x0F000020,
  382. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  383. writel(0x1000027E,
  384. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  385. writel(0x110002FE,
  386. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  387. writel(0x200F0060,
  388. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  389. writel(0x00000006,
  390. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  391. writel(0x40008C0F,
  392. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  393. writel(0x44000000,
  394. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  395. writel(0x45080C04,
  396. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  397. writel(0x46800408,
  398. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  399. writel(dwVQStartEndH,
  400. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  401. writel(dwVQStartL,
  402. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  403. writel(dwVQEndL,
  404. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  405. writel(dwVQLen,
  406. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  407. break;
  408. }
  409. } else {
  410. /* Disable VQ */
  411. switch (viaparinfo->chip_info->gfx_chip_name) {
  412. case UNICHROME_K8M890:
  413. case UNICHROME_P4M900:
  414. writel(0x00100000,
  415. viaparinfo->io_virt + VIA_REG_CR_TRANSET);
  416. writel(0x74301000,
  417. viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
  418. break;
  419. default:
  420. writel(0x00FE0000,
  421. viaparinfo->io_virt + VIA_REG_TRANSET);
  422. writel(0x00000004,
  423. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  424. writel(0x40008C0F,
  425. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  426. writel(0x44000000,
  427. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  428. writel(0x45080C04,
  429. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  430. writel(0x46800408,
  431. viaparinfo->io_virt + VIA_REG_TRANSPACE);
  432. break;
  433. }
  434. }
  435. }
  436. void viafb_hw_cursor_init(void)
  437. {
  438. /* Set Cursor Image Base Address */
  439. writel(viaparinfo->cursor_start,
  440. viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
  441. writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_POS);
  442. writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_ORG);
  443. writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_BG);
  444. writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_FG);
  445. }
  446. void viafb_show_hw_cursor(struct fb_info *info, int Status)
  447. {
  448. u32 temp;
  449. u32 iga_path = ((struct viafb_par *)(info->par))->iga_path;
  450. temp = readl(viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
  451. switch (Status) {
  452. case HW_Cursor_ON:
  453. temp |= 0x1;
  454. break;
  455. case HW_Cursor_OFF:
  456. temp &= 0xFFFFFFFE;
  457. break;
  458. }
  459. switch (iga_path) {
  460. case IGA2:
  461. temp |= 0x80000000;
  462. break;
  463. case IGA1:
  464. default:
  465. temp &= 0x7FFFFFFF;
  466. }
  467. writel(temp, viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
  468. }
  469. int viafb_wait_engine_idle(void)
  470. {
  471. int loop = 0;
  472. while (!(readl(viaparinfo->io_virt + VIA_REG_STATUS) &
  473. VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
  474. loop++;
  475. cpu_relax();
  476. }
  477. while ((readl(viaparinfo->io_virt + VIA_REG_STATUS) &
  478. (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) &&
  479. (loop < MAXLOOP)) {
  480. loop++;
  481. cpu_relax();
  482. }
  483. return loop >= MAXLOOP;
  484. }