mpic_pasemi_msi.c 4.3 KB

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  1. /*
  2. * Copyright 2007, Olof Johansson, PA Semi
  3. *
  4. * Based on arch/powerpc/sysdev/mpic_u3msi.c:
  5. *
  6. * Copyright 2006, Segher Boessenkool, IBM Corporation.
  7. * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; version 2 of the
  12. * License.
  13. *
  14. */
  15. #undef DEBUG
  16. #include <linux/irq.h>
  17. #include <linux/bootmem.h>
  18. #include <linux/msi.h>
  19. #include <asm/mpic.h>
  20. #include <asm/prom.h>
  21. #include <asm/hw_irq.h>
  22. #include <asm/ppc-pci.h>
  23. #include "mpic.h"
  24. /* Allocate 16 interrupts per device, to give an alignment of 16,
  25. * since that's the size of the grouping w.r.t. affinity. If someone
  26. * needs more than 32 MSI's down the road we'll have to rethink this,
  27. * but it should be OK for now.
  28. */
  29. #define ALLOC_CHUNK 16
  30. #define PASEMI_MSI_ADDR 0xfc080000
  31. /* A bit ugly, can we get this from the pci_dev somehow? */
  32. static struct mpic *msi_mpic;
  33. static void mpic_pasemi_msi_mask_irq(unsigned int irq)
  34. {
  35. pr_debug("mpic_pasemi_msi_mask_irq %d\n", irq);
  36. mask_msi_irq(irq);
  37. mpic_mask_irq(irq);
  38. }
  39. static void mpic_pasemi_msi_unmask_irq(unsigned int irq)
  40. {
  41. pr_debug("mpic_pasemi_msi_unmask_irq %d\n", irq);
  42. mpic_unmask_irq(irq);
  43. unmask_msi_irq(irq);
  44. }
  45. static struct irq_chip mpic_pasemi_msi_chip = {
  46. .shutdown = mpic_pasemi_msi_mask_irq,
  47. .mask = mpic_pasemi_msi_mask_irq,
  48. .unmask = mpic_pasemi_msi_unmask_irq,
  49. .eoi = mpic_end_irq,
  50. .set_type = mpic_set_irq_type,
  51. .set_affinity = mpic_set_affinity,
  52. .typename = "PASEMI-MSI ",
  53. };
  54. static int pasemi_msi_check_device(struct pci_dev *pdev, int nvec, int type)
  55. {
  56. if (type == PCI_CAP_ID_MSIX)
  57. pr_debug("pasemi_msi: MSI-X untested, trying anyway\n");
  58. return 0;
  59. }
  60. static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev)
  61. {
  62. struct msi_desc *entry;
  63. pr_debug("pasemi_msi_teardown_msi_irqs, pdev %p\n", pdev);
  64. list_for_each_entry(entry, &pdev->msi_list, list) {
  65. if (entry->irq == NO_IRQ)
  66. continue;
  67. set_irq_msi(entry->irq, NULL);
  68. mpic_msi_free_hwirqs(msi_mpic, virq_to_hw(entry->irq),
  69. ALLOC_CHUNK);
  70. irq_dispose_mapping(entry->irq);
  71. }
  72. return;
  73. }
  74. static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
  75. {
  76. irq_hw_number_t hwirq;
  77. unsigned int virq;
  78. struct msi_desc *entry;
  79. struct msi_msg msg;
  80. pr_debug("pasemi_msi_setup_msi_irqs, pdev %p nvec %d type %d\n",
  81. pdev, nvec, type);
  82. msg.address_hi = 0;
  83. msg.address_lo = PASEMI_MSI_ADDR;
  84. list_for_each_entry(entry, &pdev->msi_list, list) {
  85. /* Allocate 16 interrupts for now, since that's the grouping for
  86. * affinity. This can be changed later if it turns out 32 is too
  87. * few MSIs for someone, but restrictions will apply to how the
  88. * sources can be changed independently.
  89. */
  90. hwirq = mpic_msi_alloc_hwirqs(msi_mpic, ALLOC_CHUNK);
  91. if (hwirq < 0) {
  92. pr_debug("pasemi_msi: failed allocating hwirq\n");
  93. return hwirq;
  94. }
  95. virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
  96. if (virq == NO_IRQ) {
  97. pr_debug("pasemi_msi: failed mapping hwirq 0x%lx\n", hwirq);
  98. mpic_msi_free_hwirqs(msi_mpic, hwirq, ALLOC_CHUNK);
  99. return -ENOSPC;
  100. }
  101. /* Vector on MSI is really an offset, the hardware adds
  102. * it to the value written at the magic address. So set
  103. * it to 0 to remain sane.
  104. */
  105. mpic_set_vector(virq, 0);
  106. set_irq_msi(virq, entry);
  107. set_irq_chip(virq, &mpic_pasemi_msi_chip);
  108. set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
  109. pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%lx) addr 0x%x\n",
  110. virq, hwirq, msg.address_lo);
  111. /* Likewise, the device writes [0...511] into the target
  112. * register to generate MSI [512...1023]
  113. */
  114. msg.data = hwirq-0x200;
  115. write_msi_msg(virq, &msg);
  116. }
  117. return 0;
  118. }
  119. int mpic_pasemi_msi_init(struct mpic *mpic)
  120. {
  121. int rc;
  122. if (!mpic->irqhost->of_node ||
  123. !of_device_is_compatible(mpic->irqhost->of_node,
  124. "pasemi,pwrficient-openpic"))
  125. return -ENODEV;
  126. rc = mpic_msi_init_allocator(mpic);
  127. if (rc) {
  128. pr_debug("pasemi_msi: Error allocating bitmap!\n");
  129. return rc;
  130. }
  131. pr_debug("pasemi_msi: Registering PA Semi MPIC MSI callbacks\n");
  132. msi_mpic = mpic;
  133. WARN_ON(ppc_md.setup_msi_irqs);
  134. ppc_md.setup_msi_irqs = pasemi_msi_setup_msi_irqs;
  135. ppc_md.teardown_msi_irqs = pasemi_msi_teardown_msi_irqs;
  136. ppc_md.msi_check_device = pasemi_msi_check_device;
  137. return 0;
  138. }