quirks.c 44 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353
  1. /*
  2. * This file contains work-arounds for many known PCI hardware
  3. * bugs. Devices present only on certain architectures (host
  4. * bridges et cetera) should be handled in arch-specific code.
  5. *
  6. * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
  7. *
  8. * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
  9. *
  10. * The bridge optimization stuff has been removed. If you really
  11. * have a silly BIOS which is unable to set your host bridge right,
  12. * use the PowerTweak utility (see http://powertweak.sourceforge.net).
  13. */
  14. #include <linux/config.h>
  15. #include <linux/types.h>
  16. #include <linux/kernel.h>
  17. #include <linux/pci.h>
  18. #include <linux/init.h>
  19. #include <linux/delay.h>
  20. /* Deal with broken BIOS'es that neglect to enable passive release,
  21. which can cause problems in combination with the 82441FX/PPro MTRRs */
  22. static void __devinit quirk_passive_release(struct pci_dev *dev)
  23. {
  24. struct pci_dev *d = NULL;
  25. unsigned char dlc;
  26. /* We have to make sure a particular bit is set in the PIIX3
  27. ISA bridge, so we have to go out and find it. */
  28. while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
  29. pci_read_config_byte(d, 0x82, &dlc);
  30. if (!(dlc & 1<<1)) {
  31. printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
  32. dlc |= 1<<1;
  33. pci_write_config_byte(d, 0x82, dlc);
  34. }
  35. }
  36. }
  37. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
  38. /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
  39. but VIA don't answer queries. If you happen to have good contacts at VIA
  40. ask them for me please -- Alan
  41. This appears to be BIOS not version dependent. So presumably there is a
  42. chipset level fix */
  43. int isa_dma_bridge_buggy; /* Exported */
  44. static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
  45. {
  46. if (!isa_dma_bridge_buggy) {
  47. isa_dma_bridge_buggy=1;
  48. printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
  49. }
  50. }
  51. /*
  52. * Its not totally clear which chipsets are the problematic ones
  53. * We know 82C586 and 82C596 variants are affected.
  54. */
  55. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
  56. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
  57. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
  58. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
  59. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
  60. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
  61. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
  62. int pci_pci_problems;
  63. /*
  64. * Chipsets where PCI->PCI transfers vanish or hang
  65. */
  66. static void __devinit quirk_nopcipci(struct pci_dev *dev)
  67. {
  68. if ((pci_pci_problems & PCIPCI_FAIL)==0) {
  69. printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
  70. pci_pci_problems |= PCIPCI_FAIL;
  71. }
  72. }
  73. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
  74. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
  75. /*
  76. * Triton requires workarounds to be used by the drivers
  77. */
  78. static void __devinit quirk_triton(struct pci_dev *dev)
  79. {
  80. if ((pci_pci_problems&PCIPCI_TRITON)==0) {
  81. printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
  82. pci_pci_problems |= PCIPCI_TRITON;
  83. }
  84. }
  85. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
  86. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
  87. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
  88. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
  89. /*
  90. * VIA Apollo KT133 needs PCI latency patch
  91. * Made according to a windows driver based patch by George E. Breese
  92. * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
  93. * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
  94. * the info on which Mr Breese based his work.
  95. *
  96. * Updated based on further information from the site and also on
  97. * information provided by VIA
  98. */
  99. static void __devinit quirk_vialatency(struct pci_dev *dev)
  100. {
  101. struct pci_dev *p;
  102. u8 rev;
  103. u8 busarb;
  104. /* Ok we have a potential problem chipset here. Now see if we have
  105. a buggy southbridge */
  106. p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
  107. if (p!=NULL) {
  108. pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
  109. /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
  110. /* Check for buggy part revisions */
  111. if (rev < 0x40 || rev > 0x42)
  112. goto exit;
  113. } else {
  114. p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
  115. if (p==NULL) /* No problem parts */
  116. goto exit;
  117. pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
  118. /* Check for buggy part revisions */
  119. if (rev < 0x10 || rev > 0x12)
  120. goto exit;
  121. }
  122. /*
  123. * Ok we have the problem. Now set the PCI master grant to
  124. * occur every master grant. The apparent bug is that under high
  125. * PCI load (quite common in Linux of course) you can get data
  126. * loss when the CPU is held off the bus for 3 bus master requests
  127. * This happens to include the IDE controllers....
  128. *
  129. * VIA only apply this fix when an SB Live! is present but under
  130. * both Linux and Windows this isnt enough, and we have seen
  131. * corruption without SB Live! but with things like 3 UDMA IDE
  132. * controllers. So we ignore that bit of the VIA recommendation..
  133. */
  134. pci_read_config_byte(dev, 0x76, &busarb);
  135. /* Set bit 4 and bi 5 of byte 76 to 0x01
  136. "Master priority rotation on every PCI master grant */
  137. busarb &= ~(1<<5);
  138. busarb |= (1<<4);
  139. pci_write_config_byte(dev, 0x76, busarb);
  140. printk(KERN_INFO "Applying VIA southbridge workaround.\n");
  141. exit:
  142. pci_dev_put(p);
  143. }
  144. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
  145. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
  146. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
  147. /*
  148. * VIA Apollo VP3 needs ETBF on BT848/878
  149. */
  150. static void __devinit quirk_viaetbf(struct pci_dev *dev)
  151. {
  152. if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
  153. printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
  154. pci_pci_problems |= PCIPCI_VIAETBF;
  155. }
  156. }
  157. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
  158. static void __devinit quirk_vsfx(struct pci_dev *dev)
  159. {
  160. if ((pci_pci_problems&PCIPCI_VSFX)==0) {
  161. printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
  162. pci_pci_problems |= PCIPCI_VSFX;
  163. }
  164. }
  165. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
  166. /*
  167. * Ali Magik requires workarounds to be used by the drivers
  168. * that DMA to AGP space. Latency must be set to 0xA and triton
  169. * workaround applied too
  170. * [Info kindly provided by ALi]
  171. */
  172. static void __init quirk_alimagik(struct pci_dev *dev)
  173. {
  174. if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
  175. printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
  176. pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
  177. }
  178. }
  179. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
  180. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
  181. /*
  182. * Natoma has some interesting boundary conditions with Zoran stuff
  183. * at least
  184. */
  185. static void __devinit quirk_natoma(struct pci_dev *dev)
  186. {
  187. if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
  188. printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
  189. pci_pci_problems |= PCIPCI_NATOMA;
  190. }
  191. }
  192. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
  193. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
  194. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
  195. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
  196. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
  197. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
  198. /*
  199. * This chip can cause PCI parity errors if config register 0xA0 is read
  200. * while DMAs are occurring.
  201. */
  202. static void __devinit quirk_citrine(struct pci_dev *dev)
  203. {
  204. dev->cfg_size = 0xA0;
  205. }
  206. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
  207. /*
  208. * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
  209. * If it's needed, re-allocate the region.
  210. */
  211. static void __devinit quirk_s3_64M(struct pci_dev *dev)
  212. {
  213. struct resource *r = &dev->resource[0];
  214. if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
  215. r->start = 0;
  216. r->end = 0x3ffffff;
  217. }
  218. }
  219. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
  220. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
  221. static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
  222. {
  223. region &= ~(size-1);
  224. if (region) {
  225. struct resource *res = dev->resource + nr;
  226. res->name = pci_name(dev);
  227. res->start = region;
  228. res->end = region + size - 1;
  229. res->flags = IORESOURCE_IO;
  230. pci_claim_resource(dev, nr);
  231. }
  232. }
  233. /*
  234. * ATI Northbridge setups MCE the processor if you even
  235. * read somewhere between 0x3b0->0x3bb or read 0x3d3
  236. */
  237. static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
  238. {
  239. printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
  240. /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
  241. request_region(0x3b0, 0x0C, "RadeonIGP");
  242. request_region(0x3d3, 0x01, "RadeonIGP");
  243. }
  244. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
  245. /*
  246. * Let's make the southbridge information explicit instead
  247. * of having to worry about people probing the ACPI areas,
  248. * for example.. (Yes, it happens, and if you read the wrong
  249. * ACPI register it will put the machine to sleep with no
  250. * way of waking it up again. Bummer).
  251. *
  252. * ALI M7101: Two IO regions pointed to by words at
  253. * 0xE0 (64 bytes of ACPI registers)
  254. * 0xE2 (32 bytes of SMB registers)
  255. */
  256. static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
  257. {
  258. u16 region;
  259. pci_read_config_word(dev, 0xE0, &region);
  260. quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
  261. pci_read_config_word(dev, 0xE2, &region);
  262. quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
  263. }
  264. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
  265. /*
  266. * PIIX4 ACPI: Two IO regions pointed to by longwords at
  267. * 0x40 (64 bytes of ACPI registers)
  268. * 0x90 (32 bytes of SMB registers)
  269. */
  270. static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
  271. {
  272. u32 region;
  273. pci_read_config_dword(dev, 0x40, &region);
  274. quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
  275. pci_read_config_dword(dev, 0x90, &region);
  276. quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
  277. }
  278. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
  279. /*
  280. * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
  281. * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
  282. * 0x58 (64 bytes of GPIO I/O space)
  283. */
  284. static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
  285. {
  286. u32 region;
  287. pci_read_config_dword(dev, 0x40, &region);
  288. quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES);
  289. pci_read_config_dword(dev, 0x58, &region);
  290. quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1);
  291. }
  292. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
  293. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
  294. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
  295. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
  296. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
  297. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
  298. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
  299. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
  300. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
  301. /*
  302. * VIA ACPI: One IO region pointed to by longword at
  303. * 0x48 or 0x20 (256 bytes of ACPI registers)
  304. */
  305. static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
  306. {
  307. u8 rev;
  308. u32 region;
  309. pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
  310. if (rev & 0x10) {
  311. pci_read_config_dword(dev, 0x48, &region);
  312. region &= PCI_BASE_ADDRESS_IO_MASK;
  313. quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
  314. }
  315. }
  316. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
  317. /*
  318. * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
  319. * 0x48 (256 bytes of ACPI registers)
  320. * 0x70 (128 bytes of hardware monitoring register)
  321. * 0x90 (16 bytes of SMB registers)
  322. */
  323. static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
  324. {
  325. u16 hm;
  326. u32 smb;
  327. quirk_vt82c586_acpi(dev);
  328. pci_read_config_word(dev, 0x70, &hm);
  329. hm &= PCI_BASE_ADDRESS_IO_MASK;
  330. quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
  331. pci_read_config_dword(dev, 0x90, &smb);
  332. smb &= PCI_BASE_ADDRESS_IO_MASK;
  333. quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
  334. }
  335. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
  336. #ifdef CONFIG_X86_IO_APIC
  337. #include <asm/io_apic.h>
  338. /*
  339. * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
  340. * devices to the external APIC.
  341. *
  342. * TODO: When we have device-specific interrupt routers,
  343. * this code will go away from quirks.
  344. */
  345. static void __devinit quirk_via_ioapic(struct pci_dev *dev)
  346. {
  347. u8 tmp;
  348. if (nr_ioapics < 1)
  349. tmp = 0; /* nothing routed to external APIC */
  350. else
  351. tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
  352. printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
  353. tmp == 0 ? "Disa" : "Ena");
  354. /* Offset 0x58: External APIC IRQ output control */
  355. pci_write_config_byte (dev, 0x58, tmp);
  356. }
  357. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
  358. /*
  359. * The AMD io apic can hang the box when an apic irq is masked.
  360. * We check all revs >= B0 (yet not in the pre production!) as the bug
  361. * is currently marked NoFix
  362. *
  363. * We have multiple reports of hangs with this chipset that went away with
  364. * noapic specified. For the moment we assume its the errata. We may be wrong
  365. * of course. However the advice is demonstrably good even if so..
  366. */
  367. static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
  368. {
  369. u8 rev;
  370. pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
  371. if (rev >= 0x02) {
  372. printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
  373. printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
  374. }
  375. }
  376. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
  377. static void __init quirk_ioapic_rmw(struct pci_dev *dev)
  378. {
  379. if (dev->devfn == 0 && dev->bus->number == 0)
  380. sis_apic_bug = 1;
  381. }
  382. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
  383. int pci_msi_quirk;
  384. #define AMD8131_revA0 0x01
  385. #define AMD8131_revB0 0x11
  386. #define AMD8131_MISC 0x40
  387. #define AMD8131_NIOAMODE_BIT 0
  388. static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
  389. {
  390. unsigned char revid, tmp;
  391. pci_msi_quirk = 1;
  392. printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
  393. if (nr_ioapics == 0)
  394. return;
  395. pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
  396. if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
  397. printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
  398. pci_read_config_byte( dev, AMD8131_MISC, &tmp);
  399. tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
  400. pci_write_config_byte( dev, AMD8131_MISC, tmp);
  401. }
  402. }
  403. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic );
  404. #endif /* CONFIG_X86_IO_APIC */
  405. /*
  406. * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
  407. * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
  408. * when written, it makes an internal connection to the PIC.
  409. * For these devices, this register is defined to be 4 bits wide.
  410. * Normally this is fine. However for IO-APIC motherboards, or
  411. * non-x86 architectures (yes Via exists on PPC among other places),
  412. * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
  413. * interrupts delivered properly.
  414. *
  415. * TODO: When we have device-specific interrupt routers,
  416. * quirk_via_irqpic will go away from quirks.
  417. */
  418. /*
  419. * FIXME: it is questionable that quirk_via_acpi
  420. * is needed. It shows up as an ISA bridge, and does not
  421. * support the PCI_INTERRUPT_LINE register at all. Therefore
  422. * it seems like setting the pci_dev's 'irq' to the
  423. * value of the ACPI SCI interrupt is only done for convenience.
  424. * -jgarzik
  425. */
  426. static void __devinit quirk_via_acpi(struct pci_dev *d)
  427. {
  428. /*
  429. * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
  430. */
  431. u8 irq;
  432. pci_read_config_byte(d, 0x42, &irq);
  433. irq &= 0xf;
  434. if (irq && (irq != 2))
  435. d->irq = irq;
  436. }
  437. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
  438. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
  439. /*
  440. * PIIX3 USB: We have to disable USB interrupts that are
  441. * hardwired to PIRQD# and may be shared with an
  442. * external device.
  443. *
  444. * Legacy Support Register (LEGSUP):
  445. * bit13: USB PIRQ Enable (USBPIRQDEN),
  446. * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
  447. *
  448. * We mask out all r/wc bits, too.
  449. */
  450. static void __devinit quirk_piix3_usb(struct pci_dev *dev)
  451. {
  452. u16 legsup;
  453. pci_read_config_word(dev, 0xc0, &legsup);
  454. legsup &= 0x50ef;
  455. pci_write_config_word(dev, 0xc0, legsup);
  456. }
  457. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb );
  458. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb );
  459. /*
  460. * VIA VT82C598 has its device ID settable and many BIOSes
  461. * set it to the ID of VT82C597 for backward compatibility.
  462. * We need to switch it off to be able to recognize the real
  463. * type of the chip.
  464. */
  465. static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
  466. {
  467. pci_write_config_byte(dev, 0xfc, 0);
  468. pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
  469. }
  470. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
  471. /*
  472. * CardBus controllers have a legacy base address that enables them
  473. * to respond as i82365 pcmcia controllers. We don't want them to
  474. * do this even if the Linux CardBus driver is not loaded, because
  475. * the Linux i82365 driver does not (and should not) handle CardBus.
  476. */
  477. static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
  478. {
  479. if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
  480. return;
  481. pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
  482. }
  483. DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
  484. /*
  485. * Following the PCI ordering rules is optional on the AMD762. I'm not
  486. * sure what the designers were smoking but let's not inhale...
  487. *
  488. * To be fair to AMD, it follows the spec by default, its BIOS people
  489. * who turn it off!
  490. */
  491. static void __devinit quirk_amd_ordering(struct pci_dev *dev)
  492. {
  493. u32 pcic;
  494. pci_read_config_dword(dev, 0x4C, &pcic);
  495. if ((pcic&6)!=6) {
  496. pcic |= 6;
  497. printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
  498. pci_write_config_dword(dev, 0x4C, pcic);
  499. pci_read_config_dword(dev, 0x84, &pcic);
  500. pcic |= (1<<23); /* Required in this mode */
  501. pci_write_config_dword(dev, 0x84, pcic);
  502. }
  503. }
  504. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
  505. /*
  506. * DreamWorks provided workaround for Dunord I-3000 problem
  507. *
  508. * This card decodes and responds to addresses not apparently
  509. * assigned to it. We force a larger allocation to ensure that
  510. * nothing gets put too close to it.
  511. */
  512. static void __devinit quirk_dunord ( struct pci_dev * dev )
  513. {
  514. struct resource *r = &dev->resource [1];
  515. r->start = 0;
  516. r->end = 0xffffff;
  517. }
  518. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
  519. /*
  520. * i82380FB mobile docking controller: its PCI-to-PCI bridge
  521. * is subtractive decoding (transparent), and does indicate this
  522. * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
  523. * instead of 0x01.
  524. */
  525. static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
  526. {
  527. dev->transparent = 1;
  528. }
  529. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
  530. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
  531. /*
  532. * Common misconfiguration of the MediaGX/Geode PCI master that will
  533. * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
  534. * datasheets found at http://www.national.com/ds/GX for info on what
  535. * these bits do. <christer@weinigel.se>
  536. */
  537. static void __init quirk_mediagx_master(struct pci_dev *dev)
  538. {
  539. u8 reg;
  540. pci_read_config_byte(dev, 0x41, &reg);
  541. if (reg & 2) {
  542. reg &= ~2;
  543. printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
  544. pci_write_config_byte(dev, 0x41, reg);
  545. }
  546. }
  547. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
  548. /*
  549. * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
  550. * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
  551. * secondary channels respectively). If the device reports Compatible mode
  552. * but does use BAR0-3 for address decoding, we assume that firmware has
  553. * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
  554. * Exceptions (if they exist) must be handled in chip/architecture specific
  555. * fixups.
  556. *
  557. * Note: for non x86 people. You may need an arch specific quirk to handle
  558. * moving IDE devices to native mode as well. Some plug in card devices power
  559. * up in compatible mode and assume the BIOS will adjust them.
  560. *
  561. * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
  562. * we do now ? We don't want is pci_enable_device to come along
  563. * and assign new resources. Both approaches work for that.
  564. */
  565. static void __devinit quirk_ide_bases(struct pci_dev *dev)
  566. {
  567. struct resource *res;
  568. int first_bar = 2, last_bar = 0;
  569. if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
  570. return;
  571. res = &dev->resource[0];
  572. /* primary channel: ProgIf bit 0, BAR0, BAR1 */
  573. if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
  574. res[0].start = res[0].end = res[0].flags = 0;
  575. res[1].start = res[1].end = res[1].flags = 0;
  576. first_bar = 0;
  577. last_bar = 1;
  578. }
  579. /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
  580. if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
  581. res[2].start = res[2].end = res[2].flags = 0;
  582. res[3].start = res[3].end = res[3].flags = 0;
  583. last_bar = 3;
  584. }
  585. if (!last_bar)
  586. return;
  587. printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
  588. first_bar, last_bar, pci_name(dev));
  589. }
  590. DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
  591. /*
  592. * Ensure C0 rev restreaming is off. This is normally done by
  593. * the BIOS but in the odd case it is not the results are corruption
  594. * hence the presence of a Linux check
  595. */
  596. static void __init quirk_disable_pxb(struct pci_dev *pdev)
  597. {
  598. u16 config;
  599. u8 rev;
  600. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  601. if (rev != 0x04) /* Only C0 requires this */
  602. return;
  603. pci_read_config_word(pdev, 0x40, &config);
  604. if (config & (1<<6)) {
  605. config &= ~(1<<6);
  606. pci_write_config_word(pdev, 0x40, config);
  607. printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
  608. }
  609. }
  610. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
  611. /*
  612. * VIA northbridges care about PCI_INTERRUPT_LINE
  613. */
  614. int via_interrupt_line_quirk;
  615. static void __devinit quirk_via_bridge(struct pci_dev *pdev)
  616. {
  617. if(pdev->devfn == 0) {
  618. printk(KERN_INFO "PCI: Via IRQ fixup\n");
  619. via_interrupt_line_quirk = 1;
  620. }
  621. }
  622. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_bridge );
  623. /*
  624. * Serverworks CSB5 IDE does not fully support native mode
  625. */
  626. static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
  627. {
  628. u8 prog;
  629. pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
  630. if (prog & 5) {
  631. prog &= ~5;
  632. pdev->class &= ~5;
  633. pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
  634. /* need to re-assign BARs for compat mode */
  635. quirk_ide_bases(pdev);
  636. }
  637. }
  638. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
  639. /*
  640. * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
  641. */
  642. static void __init quirk_ide_samemode(struct pci_dev *pdev)
  643. {
  644. u8 prog;
  645. pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
  646. if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
  647. printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
  648. prog &= ~5;
  649. pdev->class &= ~5;
  650. pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
  651. /* need to re-assign BARs for compat mode */
  652. quirk_ide_bases(pdev);
  653. }
  654. }
  655. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
  656. /* This was originally an Alpha specific thing, but it really fits here.
  657. * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
  658. */
  659. static void __init quirk_eisa_bridge(struct pci_dev *dev)
  660. {
  661. dev->class = PCI_CLASS_BRIDGE_EISA << 8;
  662. }
  663. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
  664. /*
  665. * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
  666. * is not activated. The myth is that Asus said that they do not want the
  667. * users to be irritated by just another PCI Device in the Win98 device
  668. * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
  669. * package 2.7.0 for details)
  670. *
  671. * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
  672. * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
  673. * becomes necessary to do this tweak in two steps -- I've chosen the Host
  674. * bridge as trigger.
  675. */
  676. static int __initdata asus_hides_smbus = 0;
  677. static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
  678. {
  679. if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
  680. if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
  681. switch(dev->subsystem_device) {
  682. case 0x8070: /* P4B */
  683. case 0x8088: /* P4B533 */
  684. case 0x1626: /* L3C notebook */
  685. asus_hides_smbus = 1;
  686. }
  687. if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
  688. switch(dev->subsystem_device) {
  689. case 0x80b1: /* P4GE-V */
  690. case 0x80b2: /* P4PE */
  691. case 0x8093: /* P4B533-V */
  692. asus_hides_smbus = 1;
  693. }
  694. if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
  695. switch(dev->subsystem_device) {
  696. case 0x8030: /* P4T533 */
  697. asus_hides_smbus = 1;
  698. }
  699. if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
  700. switch (dev->subsystem_device) {
  701. case 0x8070: /* P4G8X Deluxe */
  702. asus_hides_smbus = 1;
  703. }
  704. if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
  705. switch (dev->subsystem_device) {
  706. case 0x1751: /* M2N notebook */
  707. case 0x1821: /* M5N notebook */
  708. asus_hides_smbus = 1;
  709. }
  710. if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
  711. switch (dev->subsystem_device) {
  712. case 0x184b: /* W1N notebook */
  713. case 0x186a: /* M6Ne notebook */
  714. asus_hides_smbus = 1;
  715. }
  716. } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
  717. if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
  718. switch(dev->subsystem_device) {
  719. case 0x088C: /* HP Compaq nc8000 */
  720. case 0x0890: /* HP Compaq nc6000 */
  721. asus_hides_smbus = 1;
  722. }
  723. if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
  724. switch (dev->subsystem_device) {
  725. case 0x12bc: /* HP D330L */
  726. asus_hides_smbus = 1;
  727. }
  728. } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
  729. if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
  730. switch(dev->subsystem_device) {
  731. case 0x0001: /* Toshiba Satellite A40 */
  732. asus_hides_smbus = 1;
  733. }
  734. } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
  735. if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
  736. switch(dev->subsystem_device) {
  737. case 0xC00C: /* Samsung P35 notebook */
  738. asus_hides_smbus = 1;
  739. }
  740. }
  741. }
  742. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
  743. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
  744. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
  745. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
  746. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
  747. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
  748. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
  749. static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
  750. {
  751. u16 val;
  752. if (likely(!asus_hides_smbus))
  753. return;
  754. pci_read_config_word(dev, 0xF2, &val);
  755. if (val & 0x8) {
  756. pci_write_config_word(dev, 0xF2, val & (~0x8));
  757. pci_read_config_word(dev, 0xF2, &val);
  758. if (val & 0x8)
  759. printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
  760. else
  761. printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
  762. }
  763. }
  764. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
  765. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
  766. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
  767. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
  768. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
  769. /*
  770. * SiS 96x south bridge: BIOS typically hides SMBus device...
  771. */
  772. static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
  773. {
  774. u8 val = 0;
  775. printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
  776. pci_read_config_byte(dev, 0x77, &val);
  777. pci_write_config_byte(dev, 0x77, val & ~0x10);
  778. pci_read_config_byte(dev, 0x77, &val);
  779. }
  780. #define UHCI_USBLEGSUP 0xc0 /* legacy support */
  781. #define UHCI_USBCMD 0 /* command register */
  782. #define UHCI_USBSTS 2 /* status register */
  783. #define UHCI_USBINTR 4 /* interrupt register */
  784. #define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
  785. #define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
  786. #define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */
  787. #define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */
  788. #define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */
  789. #define OHCI_CONTROL 0x04
  790. #define OHCI_CMDSTATUS 0x08
  791. #define OHCI_INTRSTATUS 0x0c
  792. #define OHCI_INTRENABLE 0x10
  793. #define OHCI_INTRDISABLE 0x14
  794. #define OHCI_OCR (1 << 3) /* ownership change request */
  795. #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
  796. #define OHCI_INTR_OC (1 << 30) /* ownership change */
  797. #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
  798. #define EHCI_USBCMD 0 /* command register */
  799. #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
  800. #define EHCI_USBSTS 4 /* status register */
  801. #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
  802. #define EHCI_USBINTR 8 /* interrupt register */
  803. #define EHCI_USBLEGSUP 0 /* legacy support register */
  804. #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
  805. #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
  806. #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
  807. #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
  808. int usb_early_handoff __devinitdata = 0;
  809. static int __init usb_handoff_early(char *str)
  810. {
  811. usb_early_handoff = 1;
  812. return 0;
  813. }
  814. __setup("usb-handoff", usb_handoff_early);
  815. static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
  816. {
  817. unsigned long base = 0;
  818. int wait_time, delta;
  819. u16 val, sts;
  820. int i;
  821. for (i = 0; i < PCI_ROM_RESOURCE; i++)
  822. if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
  823. base = pci_resource_start(pdev, i);
  824. break;
  825. }
  826. if (!base)
  827. return;
  828. /*
  829. * stop controller
  830. */
  831. sts = inw(base + UHCI_USBSTS);
  832. val = inw(base + UHCI_USBCMD);
  833. val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE);
  834. outw(val, base + UHCI_USBCMD);
  835. /*
  836. * wait while it stops if it was running
  837. */
  838. if ((sts & UHCI_USBSTS_HALTED) == 0)
  839. {
  840. wait_time = 1000;
  841. delta = 100;
  842. do {
  843. outw(0x1f, base + UHCI_USBSTS);
  844. udelay(delta);
  845. wait_time -= delta;
  846. val = inw(base + UHCI_USBSTS);
  847. if (val & UHCI_USBSTS_HALTED)
  848. break;
  849. } while (wait_time > 0);
  850. }
  851. /*
  852. * disable interrupts & legacy support
  853. */
  854. outw(0, base + UHCI_USBINTR);
  855. outw(0x1f, base + UHCI_USBSTS);
  856. pci_read_config_word(pdev, UHCI_USBLEGSUP, &val);
  857. if (val & 0xbf)
  858. pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT);
  859. }
  860. static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
  861. {
  862. void __iomem *base;
  863. int wait_time;
  864. base = ioremap_nocache(pci_resource_start(pdev, 0),
  865. pci_resource_len(pdev, 0));
  866. if (base == NULL) return;
  867. if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
  868. wait_time = 500; /* 0.5 seconds */
  869. writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
  870. writel(OHCI_OCR, base + OHCI_CMDSTATUS);
  871. while (wait_time > 0 &&
  872. readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
  873. wait_time -= 10;
  874. msleep(10);
  875. }
  876. }
  877. /*
  878. * disable interrupts
  879. */
  880. writel(~(u32)0, base + OHCI_INTRDISABLE);
  881. writel(~(u32)0, base + OHCI_INTRSTATUS);
  882. iounmap(base);
  883. }
  884. static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
  885. {
  886. int wait_time, delta;
  887. void __iomem *base, *op_reg_base;
  888. u32 hcc_params, val, temp;
  889. u8 cap_length;
  890. base = ioremap_nocache(pci_resource_start(pdev, 0),
  891. pci_resource_len(pdev, 0));
  892. if (base == NULL) return;
  893. cap_length = readb(base);
  894. op_reg_base = base + cap_length;
  895. hcc_params = readl(base + EHCI_HCC_PARAMS);
  896. hcc_params = (hcc_params >> 8) & 0xff;
  897. if (hcc_params) {
  898. pci_read_config_dword(pdev,
  899. hcc_params + EHCI_USBLEGSUP,
  900. &val);
  901. if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) {
  902. /*
  903. * Ok, BIOS is in smm mode, try to hand off...
  904. */
  905. pci_read_config_dword(pdev,
  906. hcc_params + EHCI_USBLEGCTLSTS,
  907. &temp);
  908. pci_write_config_dword(pdev,
  909. hcc_params + EHCI_USBLEGCTLSTS,
  910. temp | EHCI_USBLEGCTLSTS_SOOE);
  911. val |= EHCI_USBLEGSUP_OS;
  912. pci_write_config_dword(pdev,
  913. hcc_params + EHCI_USBLEGSUP,
  914. val);
  915. wait_time = 500;
  916. do {
  917. msleep(10);
  918. wait_time -= 10;
  919. pci_read_config_dword(pdev,
  920. hcc_params + EHCI_USBLEGSUP,
  921. &val);
  922. } while (wait_time && (val & EHCI_USBLEGSUP_BIOS));
  923. if (!wait_time) {
  924. /*
  925. * well, possibly buggy BIOS...
  926. */
  927. printk(KERN_WARNING "EHCI early BIOS handoff "
  928. "failed (BIOS bug ?)\n");
  929. pci_write_config_dword(pdev,
  930. hcc_params + EHCI_USBLEGSUP,
  931. EHCI_USBLEGSUP_OS);
  932. pci_write_config_dword(pdev,
  933. hcc_params + EHCI_USBLEGCTLSTS,
  934. 0);
  935. }
  936. }
  937. }
  938. /*
  939. * halt EHCI & disable its interrupts in any case
  940. */
  941. val = readl(op_reg_base + EHCI_USBSTS);
  942. if ((val & EHCI_USBSTS_HALTED) == 0) {
  943. val = readl(op_reg_base + EHCI_USBCMD);
  944. val &= ~EHCI_USBCMD_RUN;
  945. writel(val, op_reg_base + EHCI_USBCMD);
  946. wait_time = 2000;
  947. delta = 100;
  948. do {
  949. writel(0x3f, op_reg_base + EHCI_USBSTS);
  950. udelay(delta);
  951. wait_time -= delta;
  952. val = readl(op_reg_base + EHCI_USBSTS);
  953. if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
  954. break;
  955. }
  956. } while (wait_time > 0);
  957. }
  958. writel(0, op_reg_base + EHCI_USBINTR);
  959. writel(0x3f, op_reg_base + EHCI_USBSTS);
  960. iounmap(base);
  961. return;
  962. }
  963. static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
  964. {
  965. if (!usb_early_handoff)
  966. return;
  967. if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */
  968. quirk_usb_handoff_uhci(pdev);
  969. } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */
  970. quirk_usb_handoff_ohci(pdev);
  971. } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */
  972. quirk_usb_disable_ehci(pdev);
  973. }
  974. return;
  975. }
  976. DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
  977. /*
  978. * ... This is further complicated by the fact that some SiS96x south
  979. * bridges pretend to be 85C503/5513 instead. In that case see if we
  980. * spotted a compatible north bridge to make sure.
  981. * (pci_find_device doesn't work yet)
  982. *
  983. * We can also enable the sis96x bit in the discovery register..
  984. */
  985. static int __devinitdata sis_96x_compatible = 0;
  986. #define SIS_DETECT_REGISTER 0x40
  987. static void __init quirk_sis_503(struct pci_dev *dev)
  988. {
  989. u8 reg;
  990. u16 devid;
  991. pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
  992. pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
  993. pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
  994. if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
  995. pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
  996. return;
  997. }
  998. /* Make people aware that we changed the config.. */
  999. printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
  1000. /*
  1001. * Ok, it now shows up as a 96x.. The 96x quirks are after
  1002. * the 503 quirk in the quirk table, so they'll automatically
  1003. * run and enable things like the SMBus device
  1004. */
  1005. dev->device = devid;
  1006. }
  1007. static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
  1008. {
  1009. sis_96x_compatible = 1;
  1010. }
  1011. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
  1012. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
  1013. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
  1014. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
  1015. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
  1016. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
  1017. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
  1018. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
  1019. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
  1020. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
  1021. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
  1022. #ifdef CONFIG_X86_IO_APIC
  1023. static void __init quirk_alder_ioapic(struct pci_dev *pdev)
  1024. {
  1025. int i;
  1026. if ((pdev->class >> 8) != 0xff00)
  1027. return;
  1028. /* the first BAR is the location of the IO APIC...we must
  1029. * not touch this (and it's already covered by the fixmap), so
  1030. * forcibly insert it into the resource tree */
  1031. if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
  1032. insert_resource(&iomem_resource, &pdev->resource[0]);
  1033. /* The next five BARs all seem to be rubbish, so just clean
  1034. * them out */
  1035. for (i=1; i < 6; i++) {
  1036. memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
  1037. }
  1038. }
  1039. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
  1040. #endif
  1041. #ifdef CONFIG_SCSI_SATA
  1042. static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
  1043. {
  1044. u8 prog, comb, tmp;
  1045. int ich = 0;
  1046. /*
  1047. * Narrow down to Intel SATA PCI devices.
  1048. */
  1049. switch (pdev->device) {
  1050. /* PCI ids taken from drivers/scsi/ata_piix.c */
  1051. case 0x24d1:
  1052. case 0x24df:
  1053. case 0x25a3:
  1054. case 0x25b0:
  1055. ich = 5;
  1056. break;
  1057. case 0x2651:
  1058. case 0x2652:
  1059. case 0x2653:
  1060. case 0x2680: /* ESB2 */
  1061. ich = 6;
  1062. break;
  1063. case 0x27c0:
  1064. case 0x27c4:
  1065. ich = 7;
  1066. break;
  1067. default:
  1068. /* we do not handle this PCI device */
  1069. return;
  1070. }
  1071. /*
  1072. * Read combined mode register.
  1073. */
  1074. pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
  1075. if (ich == 5) {
  1076. tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
  1077. if (tmp == 0x4) /* bits 10x */
  1078. comb = (1 << 0); /* SATA port 0, PATA port 1 */
  1079. else if (tmp == 0x6) /* bits 11x */
  1080. comb = (1 << 2); /* PATA port 0, SATA port 1 */
  1081. else
  1082. return; /* not in combined mode */
  1083. } else {
  1084. WARN_ON((ich != 6) && (ich != 7));
  1085. tmp &= 0x3; /* interesting bits 1:0 */
  1086. if (tmp & (1 << 0))
  1087. comb = (1 << 2); /* PATA port 0, SATA port 1 */
  1088. else if (tmp & (1 << 1))
  1089. comb = (1 << 0); /* SATA port 0, PATA port 1 */
  1090. else
  1091. return; /* not in combined mode */
  1092. }
  1093. /*
  1094. * Read programming interface register.
  1095. * (Tells us if it's legacy or native mode)
  1096. */
  1097. pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
  1098. /* if SATA port is in native mode, we're ok. */
  1099. if (prog & comb)
  1100. return;
  1101. /* SATA port is in legacy mode. Reserve port so that
  1102. * IDE driver does not attempt to use it. If request_region
  1103. * fails, it will be obvious at boot time, so we don't bother
  1104. * checking return values.
  1105. */
  1106. if (comb == (1 << 0))
  1107. request_region(0x1f0, 8, "libata"); /* port 0 */
  1108. else
  1109. request_region(0x170, 8, "libata"); /* port 1 */
  1110. }
  1111. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
  1112. #endif /* CONFIG_SCSI_SATA */
  1113. int pcie_mch_quirk;
  1114. static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
  1115. {
  1116. pcie_mch_quirk = 1;
  1117. }
  1118. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
  1119. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
  1120. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
  1121. static void __devinit quirk_netmos(struct pci_dev *dev)
  1122. {
  1123. unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
  1124. unsigned int num_serial = dev->subsystem_device & 0xf;
  1125. /*
  1126. * These Netmos parts are multiport serial devices with optional
  1127. * parallel ports. Even when parallel ports are present, they
  1128. * are identified as class SERIAL, which means the serial driver
  1129. * will claim them. To prevent this, mark them as class OTHER.
  1130. * These combo devices should be claimed by parport_serial.
  1131. *
  1132. * The subdevice ID is of the form 0x00PS, where <P> is the number
  1133. * of parallel ports and <S> is the number of serial ports.
  1134. */
  1135. switch (dev->device) {
  1136. case PCI_DEVICE_ID_NETMOS_9735:
  1137. case PCI_DEVICE_ID_NETMOS_9745:
  1138. case PCI_DEVICE_ID_NETMOS_9835:
  1139. case PCI_DEVICE_ID_NETMOS_9845:
  1140. case PCI_DEVICE_ID_NETMOS_9855:
  1141. if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
  1142. num_parallel) {
  1143. printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
  1144. "%u serial); changing class SERIAL to OTHER "
  1145. "(use parport_serial)\n",
  1146. dev->device, num_parallel, num_serial);
  1147. dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
  1148. (dev->class & 0xff);
  1149. }
  1150. }
  1151. }
  1152. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
  1153. static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
  1154. {
  1155. while (f < end) {
  1156. if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
  1157. (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
  1158. pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
  1159. f->hook(dev);
  1160. }
  1161. f++;
  1162. }
  1163. }
  1164. extern struct pci_fixup __start_pci_fixups_early[];
  1165. extern struct pci_fixup __end_pci_fixups_early[];
  1166. extern struct pci_fixup __start_pci_fixups_header[];
  1167. extern struct pci_fixup __end_pci_fixups_header[];
  1168. extern struct pci_fixup __start_pci_fixups_final[];
  1169. extern struct pci_fixup __end_pci_fixups_final[];
  1170. extern struct pci_fixup __start_pci_fixups_enable[];
  1171. extern struct pci_fixup __end_pci_fixups_enable[];
  1172. void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
  1173. {
  1174. struct pci_fixup *start, *end;
  1175. switch(pass) {
  1176. case pci_fixup_early:
  1177. start = __start_pci_fixups_early;
  1178. end = __end_pci_fixups_early;
  1179. break;
  1180. case pci_fixup_header:
  1181. start = __start_pci_fixups_header;
  1182. end = __end_pci_fixups_header;
  1183. break;
  1184. case pci_fixup_final:
  1185. start = __start_pci_fixups_final;
  1186. end = __end_pci_fixups_final;
  1187. break;
  1188. case pci_fixup_enable:
  1189. start = __start_pci_fixups_enable;
  1190. end = __end_pci_fixups_enable;
  1191. break;
  1192. default:
  1193. /* stupid compiler warning, you would think with an enum... */
  1194. return;
  1195. }
  1196. pci_do_fixups(dev, start, end);
  1197. }
  1198. EXPORT_SYMBOL(pcie_mch_quirk);
  1199. #ifdef CONFIG_HOTPLUG
  1200. EXPORT_SYMBOL(pci_fixup_device);
  1201. #endif