traps.c 47 KB

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  1. /*
  2. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  3. * Copyright 2007-2010 Freescale Semiconductor, Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version
  8. * 2 of the License, or (at your option) any later version.
  9. *
  10. * Modified by Cort Dougan (cort@cs.nmt.edu)
  11. * and Paul Mackerras (paulus@samba.org)
  12. */
  13. /*
  14. * This file handles the architecture-dependent parts of hardware exceptions
  15. */
  16. #include <linux/errno.h>
  17. #include <linux/sched.h>
  18. #include <linux/kernel.h>
  19. #include <linux/mm.h>
  20. #include <linux/stddef.h>
  21. #include <linux/unistd.h>
  22. #include <linux/ptrace.h>
  23. #include <linux/user.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/init.h>
  26. #include <linux/module.h>
  27. #include <linux/prctl.h>
  28. #include <linux/delay.h>
  29. #include <linux/kprobes.h>
  30. #include <linux/kexec.h>
  31. #include <linux/backlight.h>
  32. #include <linux/bug.h>
  33. #include <linux/kdebug.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/ratelimit.h>
  36. #include <linux/context_tracking.h>
  37. #include <asm/emulated_ops.h>
  38. #include <asm/pgtable.h>
  39. #include <asm/uaccess.h>
  40. #include <asm/io.h>
  41. #include <asm/machdep.h>
  42. #include <asm/rtas.h>
  43. #include <asm/pmc.h>
  44. #ifdef CONFIG_PPC32
  45. #include <asm/reg.h>
  46. #endif
  47. #ifdef CONFIG_PMAC_BACKLIGHT
  48. #include <asm/backlight.h>
  49. #endif
  50. #ifdef CONFIG_PPC64
  51. #include <asm/firmware.h>
  52. #include <asm/processor.h>
  53. #include <asm/tm.h>
  54. #endif
  55. #include <asm/kexec.h>
  56. #include <asm/ppc-opcode.h>
  57. #include <asm/rio.h>
  58. #include <asm/fadump.h>
  59. #include <asm/switch_to.h>
  60. #include <asm/tm.h>
  61. #include <asm/debug.h>
  62. #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
  63. int (*__debugger)(struct pt_regs *regs) __read_mostly;
  64. int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
  65. int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
  66. int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
  67. int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
  68. int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
  69. int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
  70. EXPORT_SYMBOL(__debugger);
  71. EXPORT_SYMBOL(__debugger_ipi);
  72. EXPORT_SYMBOL(__debugger_bpt);
  73. EXPORT_SYMBOL(__debugger_sstep);
  74. EXPORT_SYMBOL(__debugger_iabr_match);
  75. EXPORT_SYMBOL(__debugger_break_match);
  76. EXPORT_SYMBOL(__debugger_fault_handler);
  77. #endif
  78. /* Transactional Memory trap debug */
  79. #ifdef TM_DEBUG_SW
  80. #define TM_DEBUG(x...) printk(KERN_INFO x)
  81. #else
  82. #define TM_DEBUG(x...) do { } while(0)
  83. #endif
  84. /*
  85. * Trap & Exception support
  86. */
  87. #ifdef CONFIG_PMAC_BACKLIGHT
  88. static void pmac_backlight_unblank(void)
  89. {
  90. mutex_lock(&pmac_backlight_mutex);
  91. if (pmac_backlight) {
  92. struct backlight_properties *props;
  93. props = &pmac_backlight->props;
  94. props->brightness = props->max_brightness;
  95. props->power = FB_BLANK_UNBLANK;
  96. backlight_update_status(pmac_backlight);
  97. }
  98. mutex_unlock(&pmac_backlight_mutex);
  99. }
  100. #else
  101. static inline void pmac_backlight_unblank(void) { }
  102. #endif
  103. static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
  104. static int die_owner = -1;
  105. static unsigned int die_nest_count;
  106. static int die_counter;
  107. static unsigned __kprobes long oops_begin(struct pt_regs *regs)
  108. {
  109. int cpu;
  110. unsigned long flags;
  111. if (debugger(regs))
  112. return 1;
  113. oops_enter();
  114. /* racy, but better than risking deadlock. */
  115. raw_local_irq_save(flags);
  116. cpu = smp_processor_id();
  117. if (!arch_spin_trylock(&die_lock)) {
  118. if (cpu == die_owner)
  119. /* nested oops. should stop eventually */;
  120. else
  121. arch_spin_lock(&die_lock);
  122. }
  123. die_nest_count++;
  124. die_owner = cpu;
  125. console_verbose();
  126. bust_spinlocks(1);
  127. if (machine_is(powermac))
  128. pmac_backlight_unblank();
  129. return flags;
  130. }
  131. static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
  132. int signr)
  133. {
  134. bust_spinlocks(0);
  135. die_owner = -1;
  136. add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
  137. die_nest_count--;
  138. oops_exit();
  139. printk("\n");
  140. if (!die_nest_count)
  141. /* Nest count reaches zero, release the lock. */
  142. arch_spin_unlock(&die_lock);
  143. raw_local_irq_restore(flags);
  144. crash_fadump(regs, "die oops");
  145. /*
  146. * A system reset (0x100) is a request to dump, so we always send
  147. * it through the crashdump code.
  148. */
  149. if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
  150. crash_kexec(regs);
  151. /*
  152. * We aren't the primary crash CPU. We need to send it
  153. * to a holding pattern to avoid it ending up in the panic
  154. * code.
  155. */
  156. crash_kexec_secondary(regs);
  157. }
  158. if (!signr)
  159. return;
  160. /*
  161. * While our oops output is serialised by a spinlock, output
  162. * from panic() called below can race and corrupt it. If we
  163. * know we are going to panic, delay for 1 second so we have a
  164. * chance to get clean backtraces from all CPUs that are oopsing.
  165. */
  166. if (in_interrupt() || panic_on_oops || !current->pid ||
  167. is_global_init(current)) {
  168. mdelay(MSEC_PER_SEC);
  169. }
  170. if (in_interrupt())
  171. panic("Fatal exception in interrupt");
  172. if (panic_on_oops)
  173. panic("Fatal exception");
  174. do_exit(signr);
  175. }
  176. static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
  177. {
  178. printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
  179. #ifdef CONFIG_PREEMPT
  180. printk("PREEMPT ");
  181. #endif
  182. #ifdef CONFIG_SMP
  183. printk("SMP NR_CPUS=%d ", NR_CPUS);
  184. #endif
  185. #ifdef CONFIG_DEBUG_PAGEALLOC
  186. printk("DEBUG_PAGEALLOC ");
  187. #endif
  188. #ifdef CONFIG_NUMA
  189. printk("NUMA ");
  190. #endif
  191. printk("%s\n", ppc_md.name ? ppc_md.name : "");
  192. if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
  193. return 1;
  194. print_modules();
  195. show_regs(regs);
  196. return 0;
  197. }
  198. void die(const char *str, struct pt_regs *regs, long err)
  199. {
  200. unsigned long flags = oops_begin(regs);
  201. if (__die(str, regs, err))
  202. err = 0;
  203. oops_end(flags, regs, err);
  204. }
  205. void user_single_step_siginfo(struct task_struct *tsk,
  206. struct pt_regs *regs, siginfo_t *info)
  207. {
  208. memset(info, 0, sizeof(*info));
  209. info->si_signo = SIGTRAP;
  210. info->si_code = TRAP_TRACE;
  211. info->si_addr = (void __user *)regs->nip;
  212. }
  213. void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
  214. {
  215. siginfo_t info;
  216. const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
  217. "at %08lx nip %08lx lr %08lx code %x\n";
  218. const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
  219. "at %016lx nip %016lx lr %016lx code %x\n";
  220. if (!user_mode(regs)) {
  221. die("Exception in kernel mode", regs, signr);
  222. return;
  223. }
  224. if (show_unhandled_signals && unhandled_signal(current, signr)) {
  225. printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
  226. current->comm, current->pid, signr,
  227. addr, regs->nip, regs->link, code);
  228. }
  229. if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
  230. local_irq_enable();
  231. current->thread.trap_nr = code;
  232. memset(&info, 0, sizeof(info));
  233. info.si_signo = signr;
  234. info.si_code = code;
  235. info.si_addr = (void __user *) addr;
  236. force_sig_info(signr, &info, current);
  237. }
  238. #ifdef CONFIG_PPC64
  239. void system_reset_exception(struct pt_regs *regs)
  240. {
  241. /* See if any machine dependent calls */
  242. if (ppc_md.system_reset_exception) {
  243. if (ppc_md.system_reset_exception(regs))
  244. return;
  245. }
  246. die("System Reset", regs, SIGABRT);
  247. /* Must die if the interrupt is not recoverable */
  248. if (!(regs->msr & MSR_RI))
  249. panic("Unrecoverable System Reset");
  250. /* What should we do here? We could issue a shutdown or hard reset. */
  251. }
  252. #endif
  253. /*
  254. * I/O accesses can cause machine checks on powermacs.
  255. * Check if the NIP corresponds to the address of a sync
  256. * instruction for which there is an entry in the exception
  257. * table.
  258. * Note that the 601 only takes a machine check on TEA
  259. * (transfer error ack) signal assertion, and does not
  260. * set any of the top 16 bits of SRR1.
  261. * -- paulus.
  262. */
  263. static inline int check_io_access(struct pt_regs *regs)
  264. {
  265. #ifdef CONFIG_PPC32
  266. unsigned long msr = regs->msr;
  267. const struct exception_table_entry *entry;
  268. unsigned int *nip = (unsigned int *)regs->nip;
  269. if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
  270. && (entry = search_exception_tables(regs->nip)) != NULL) {
  271. /*
  272. * Check that it's a sync instruction, or somewhere
  273. * in the twi; isync; nop sequence that inb/inw/inl uses.
  274. * As the address is in the exception table
  275. * we should be able to read the instr there.
  276. * For the debug message, we look at the preceding
  277. * load or store.
  278. */
  279. if (*nip == 0x60000000) /* nop */
  280. nip -= 2;
  281. else if (*nip == 0x4c00012c) /* isync */
  282. --nip;
  283. if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
  284. /* sync or twi */
  285. unsigned int rb;
  286. --nip;
  287. rb = (*nip >> 11) & 0x1f;
  288. printk(KERN_DEBUG "%s bad port %lx at %p\n",
  289. (*nip & 0x100)? "OUT to": "IN from",
  290. regs->gpr[rb] - _IO_BASE, nip);
  291. regs->msr |= MSR_RI;
  292. regs->nip = entry->fixup;
  293. return 1;
  294. }
  295. }
  296. #endif /* CONFIG_PPC32 */
  297. return 0;
  298. }
  299. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  300. /* On 4xx, the reason for the machine check or program exception
  301. is in the ESR. */
  302. #define get_reason(regs) ((regs)->dsisr)
  303. #ifndef CONFIG_FSL_BOOKE
  304. #define get_mc_reason(regs) ((regs)->dsisr)
  305. #else
  306. #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
  307. #endif
  308. #define REASON_FP ESR_FP
  309. #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
  310. #define REASON_PRIVILEGED ESR_PPR
  311. #define REASON_TRAP ESR_PTR
  312. /* single-step stuff */
  313. #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
  314. #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
  315. #else
  316. /* On non-4xx, the reason for the machine check or program
  317. exception is in the MSR. */
  318. #define get_reason(regs) ((regs)->msr)
  319. #define get_mc_reason(regs) ((regs)->msr)
  320. #define REASON_TM 0x200000
  321. #define REASON_FP 0x100000
  322. #define REASON_ILLEGAL 0x80000
  323. #define REASON_PRIVILEGED 0x40000
  324. #define REASON_TRAP 0x20000
  325. #define single_stepping(regs) ((regs)->msr & MSR_SE)
  326. #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
  327. #endif
  328. #if defined(CONFIG_4xx)
  329. int machine_check_4xx(struct pt_regs *regs)
  330. {
  331. unsigned long reason = get_mc_reason(regs);
  332. if (reason & ESR_IMCP) {
  333. printk("Instruction");
  334. mtspr(SPRN_ESR, reason & ~ESR_IMCP);
  335. } else
  336. printk("Data");
  337. printk(" machine check in kernel mode.\n");
  338. return 0;
  339. }
  340. int machine_check_440A(struct pt_regs *regs)
  341. {
  342. unsigned long reason = get_mc_reason(regs);
  343. printk("Machine check in kernel mode.\n");
  344. if (reason & ESR_IMCP){
  345. printk("Instruction Synchronous Machine Check exception\n");
  346. mtspr(SPRN_ESR, reason & ~ESR_IMCP);
  347. }
  348. else {
  349. u32 mcsr = mfspr(SPRN_MCSR);
  350. if (mcsr & MCSR_IB)
  351. printk("Instruction Read PLB Error\n");
  352. if (mcsr & MCSR_DRB)
  353. printk("Data Read PLB Error\n");
  354. if (mcsr & MCSR_DWB)
  355. printk("Data Write PLB Error\n");
  356. if (mcsr & MCSR_TLBP)
  357. printk("TLB Parity Error\n");
  358. if (mcsr & MCSR_ICP){
  359. flush_instruction_cache();
  360. printk("I-Cache Parity Error\n");
  361. }
  362. if (mcsr & MCSR_DCSP)
  363. printk("D-Cache Search Parity Error\n");
  364. if (mcsr & MCSR_DCFP)
  365. printk("D-Cache Flush Parity Error\n");
  366. if (mcsr & MCSR_IMPE)
  367. printk("Machine Check exception is imprecise\n");
  368. /* Clear MCSR */
  369. mtspr(SPRN_MCSR, mcsr);
  370. }
  371. return 0;
  372. }
  373. int machine_check_47x(struct pt_regs *regs)
  374. {
  375. unsigned long reason = get_mc_reason(regs);
  376. u32 mcsr;
  377. printk(KERN_ERR "Machine check in kernel mode.\n");
  378. if (reason & ESR_IMCP) {
  379. printk(KERN_ERR
  380. "Instruction Synchronous Machine Check exception\n");
  381. mtspr(SPRN_ESR, reason & ~ESR_IMCP);
  382. return 0;
  383. }
  384. mcsr = mfspr(SPRN_MCSR);
  385. if (mcsr & MCSR_IB)
  386. printk(KERN_ERR "Instruction Read PLB Error\n");
  387. if (mcsr & MCSR_DRB)
  388. printk(KERN_ERR "Data Read PLB Error\n");
  389. if (mcsr & MCSR_DWB)
  390. printk(KERN_ERR "Data Write PLB Error\n");
  391. if (mcsr & MCSR_TLBP)
  392. printk(KERN_ERR "TLB Parity Error\n");
  393. if (mcsr & MCSR_ICP) {
  394. flush_instruction_cache();
  395. printk(KERN_ERR "I-Cache Parity Error\n");
  396. }
  397. if (mcsr & MCSR_DCSP)
  398. printk(KERN_ERR "D-Cache Search Parity Error\n");
  399. if (mcsr & PPC47x_MCSR_GPR)
  400. printk(KERN_ERR "GPR Parity Error\n");
  401. if (mcsr & PPC47x_MCSR_FPR)
  402. printk(KERN_ERR "FPR Parity Error\n");
  403. if (mcsr & PPC47x_MCSR_IPR)
  404. printk(KERN_ERR "Machine Check exception is imprecise\n");
  405. /* Clear MCSR */
  406. mtspr(SPRN_MCSR, mcsr);
  407. return 0;
  408. }
  409. #elif defined(CONFIG_E500)
  410. int machine_check_e500mc(struct pt_regs *regs)
  411. {
  412. unsigned long mcsr = mfspr(SPRN_MCSR);
  413. unsigned long reason = mcsr;
  414. int recoverable = 1;
  415. if (reason & MCSR_LD) {
  416. recoverable = fsl_rio_mcheck_exception(regs);
  417. if (recoverable == 1)
  418. goto silent_out;
  419. }
  420. printk("Machine check in kernel mode.\n");
  421. printk("Caused by (from MCSR=%lx): ", reason);
  422. if (reason & MCSR_MCP)
  423. printk("Machine Check Signal\n");
  424. if (reason & MCSR_ICPERR) {
  425. printk("Instruction Cache Parity Error\n");
  426. /*
  427. * This is recoverable by invalidating the i-cache.
  428. */
  429. mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
  430. while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
  431. ;
  432. /*
  433. * This will generally be accompanied by an instruction
  434. * fetch error report -- only treat MCSR_IF as fatal
  435. * if it wasn't due to an L1 parity error.
  436. */
  437. reason &= ~MCSR_IF;
  438. }
  439. if (reason & MCSR_DCPERR_MC) {
  440. printk("Data Cache Parity Error\n");
  441. /*
  442. * In write shadow mode we auto-recover from the error, but it
  443. * may still get logged and cause a machine check. We should
  444. * only treat the non-write shadow case as non-recoverable.
  445. */
  446. if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
  447. recoverable = 0;
  448. }
  449. if (reason & MCSR_L2MMU_MHIT) {
  450. printk("Hit on multiple TLB entries\n");
  451. recoverable = 0;
  452. }
  453. if (reason & MCSR_NMI)
  454. printk("Non-maskable interrupt\n");
  455. if (reason & MCSR_IF) {
  456. printk("Instruction Fetch Error Report\n");
  457. recoverable = 0;
  458. }
  459. if (reason & MCSR_LD) {
  460. printk("Load Error Report\n");
  461. recoverable = 0;
  462. }
  463. if (reason & MCSR_ST) {
  464. printk("Store Error Report\n");
  465. recoverable = 0;
  466. }
  467. if (reason & MCSR_LDG) {
  468. printk("Guarded Load Error Report\n");
  469. recoverable = 0;
  470. }
  471. if (reason & MCSR_TLBSYNC)
  472. printk("Simultaneous tlbsync operations\n");
  473. if (reason & MCSR_BSL2_ERR) {
  474. printk("Level 2 Cache Error\n");
  475. recoverable = 0;
  476. }
  477. if (reason & MCSR_MAV) {
  478. u64 addr;
  479. addr = mfspr(SPRN_MCAR);
  480. addr |= (u64)mfspr(SPRN_MCARU) << 32;
  481. printk("Machine Check %s Address: %#llx\n",
  482. reason & MCSR_MEA ? "Effective" : "Physical", addr);
  483. }
  484. silent_out:
  485. mtspr(SPRN_MCSR, mcsr);
  486. return mfspr(SPRN_MCSR) == 0 && recoverable;
  487. }
  488. int machine_check_e500(struct pt_regs *regs)
  489. {
  490. unsigned long reason = get_mc_reason(regs);
  491. if (reason & MCSR_BUS_RBERR) {
  492. if (fsl_rio_mcheck_exception(regs))
  493. return 1;
  494. }
  495. printk("Machine check in kernel mode.\n");
  496. printk("Caused by (from MCSR=%lx): ", reason);
  497. if (reason & MCSR_MCP)
  498. printk("Machine Check Signal\n");
  499. if (reason & MCSR_ICPERR)
  500. printk("Instruction Cache Parity Error\n");
  501. if (reason & MCSR_DCP_PERR)
  502. printk("Data Cache Push Parity Error\n");
  503. if (reason & MCSR_DCPERR)
  504. printk("Data Cache Parity Error\n");
  505. if (reason & MCSR_BUS_IAERR)
  506. printk("Bus - Instruction Address Error\n");
  507. if (reason & MCSR_BUS_RAERR)
  508. printk("Bus - Read Address Error\n");
  509. if (reason & MCSR_BUS_WAERR)
  510. printk("Bus - Write Address Error\n");
  511. if (reason & MCSR_BUS_IBERR)
  512. printk("Bus - Instruction Data Error\n");
  513. if (reason & MCSR_BUS_RBERR)
  514. printk("Bus - Read Data Bus Error\n");
  515. if (reason & MCSR_BUS_WBERR)
  516. printk("Bus - Read Data Bus Error\n");
  517. if (reason & MCSR_BUS_IPERR)
  518. printk("Bus - Instruction Parity Error\n");
  519. if (reason & MCSR_BUS_RPERR)
  520. printk("Bus - Read Parity Error\n");
  521. return 0;
  522. }
  523. int machine_check_generic(struct pt_regs *regs)
  524. {
  525. return 0;
  526. }
  527. #elif defined(CONFIG_E200)
  528. int machine_check_e200(struct pt_regs *regs)
  529. {
  530. unsigned long reason = get_mc_reason(regs);
  531. printk("Machine check in kernel mode.\n");
  532. printk("Caused by (from MCSR=%lx): ", reason);
  533. if (reason & MCSR_MCP)
  534. printk("Machine Check Signal\n");
  535. if (reason & MCSR_CP_PERR)
  536. printk("Cache Push Parity Error\n");
  537. if (reason & MCSR_CPERR)
  538. printk("Cache Parity Error\n");
  539. if (reason & MCSR_EXCP_ERR)
  540. printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
  541. if (reason & MCSR_BUS_IRERR)
  542. printk("Bus - Read Bus Error on instruction fetch\n");
  543. if (reason & MCSR_BUS_DRERR)
  544. printk("Bus - Read Bus Error on data load\n");
  545. if (reason & MCSR_BUS_WRERR)
  546. printk("Bus - Write Bus Error on buffered store or cache line push\n");
  547. return 0;
  548. }
  549. #else
  550. int machine_check_generic(struct pt_regs *regs)
  551. {
  552. unsigned long reason = get_mc_reason(regs);
  553. printk("Machine check in kernel mode.\n");
  554. printk("Caused by (from SRR1=%lx): ", reason);
  555. switch (reason & 0x601F0000) {
  556. case 0x80000:
  557. printk("Machine check signal\n");
  558. break;
  559. case 0: /* for 601 */
  560. case 0x40000:
  561. case 0x140000: /* 7450 MSS error and TEA */
  562. printk("Transfer error ack signal\n");
  563. break;
  564. case 0x20000:
  565. printk("Data parity error signal\n");
  566. break;
  567. case 0x10000:
  568. printk("Address parity error signal\n");
  569. break;
  570. case 0x20000000:
  571. printk("L1 Data Cache error\n");
  572. break;
  573. case 0x40000000:
  574. printk("L1 Instruction Cache error\n");
  575. break;
  576. case 0x00100000:
  577. printk("L2 data cache parity error\n");
  578. break;
  579. default:
  580. printk("Unknown values in msr\n");
  581. }
  582. return 0;
  583. }
  584. #endif /* everything else */
  585. void machine_check_exception(struct pt_regs *regs)
  586. {
  587. enum ctx_state prev_state = exception_enter();
  588. int recover = 0;
  589. __get_cpu_var(irq_stat).mce_exceptions++;
  590. /* See if any machine dependent calls. In theory, we would want
  591. * to call the CPU first, and call the ppc_md. one if the CPU
  592. * one returns a positive number. However there is existing code
  593. * that assumes the board gets a first chance, so let's keep it
  594. * that way for now and fix things later. --BenH.
  595. */
  596. if (ppc_md.machine_check_exception)
  597. recover = ppc_md.machine_check_exception(regs);
  598. else if (cur_cpu_spec->machine_check)
  599. recover = cur_cpu_spec->machine_check(regs);
  600. if (recover > 0)
  601. goto bail;
  602. #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
  603. /* the qspan pci read routines can cause machine checks -- Cort
  604. *
  605. * yuck !!! that totally needs to go away ! There are better ways
  606. * to deal with that than having a wart in the mcheck handler.
  607. * -- BenH
  608. */
  609. bad_page_fault(regs, regs->dar, SIGBUS);
  610. goto bail;
  611. #endif
  612. if (debugger_fault_handler(regs))
  613. goto bail;
  614. if (check_io_access(regs))
  615. goto bail;
  616. die("Machine check", regs, SIGBUS);
  617. /* Must die if the interrupt is not recoverable */
  618. if (!(regs->msr & MSR_RI))
  619. panic("Unrecoverable Machine check");
  620. bail:
  621. exception_exit(prev_state);
  622. }
  623. void SMIException(struct pt_regs *regs)
  624. {
  625. die("System Management Interrupt", regs, SIGABRT);
  626. }
  627. void unknown_exception(struct pt_regs *regs)
  628. {
  629. enum ctx_state prev_state = exception_enter();
  630. printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
  631. regs->nip, regs->msr, regs->trap);
  632. _exception(SIGTRAP, regs, 0, 0);
  633. exception_exit(prev_state);
  634. }
  635. void instruction_breakpoint_exception(struct pt_regs *regs)
  636. {
  637. enum ctx_state prev_state = exception_enter();
  638. if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
  639. 5, SIGTRAP) == NOTIFY_STOP)
  640. goto bail;
  641. if (debugger_iabr_match(regs))
  642. goto bail;
  643. _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
  644. bail:
  645. exception_exit(prev_state);
  646. }
  647. void RunModeException(struct pt_regs *regs)
  648. {
  649. _exception(SIGTRAP, regs, 0, 0);
  650. }
  651. void __kprobes single_step_exception(struct pt_regs *regs)
  652. {
  653. enum ctx_state prev_state = exception_enter();
  654. clear_single_step(regs);
  655. if (notify_die(DIE_SSTEP, "single_step", regs, 5,
  656. 5, SIGTRAP) == NOTIFY_STOP)
  657. goto bail;
  658. if (debugger_sstep(regs))
  659. goto bail;
  660. _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
  661. bail:
  662. exception_exit(prev_state);
  663. }
  664. /*
  665. * After we have successfully emulated an instruction, we have to
  666. * check if the instruction was being single-stepped, and if so,
  667. * pretend we got a single-step exception. This was pointed out
  668. * by Kumar Gala. -- paulus
  669. */
  670. static void emulate_single_step(struct pt_regs *regs)
  671. {
  672. if (single_stepping(regs))
  673. single_step_exception(regs);
  674. }
  675. static inline int __parse_fpscr(unsigned long fpscr)
  676. {
  677. int ret = 0;
  678. /* Invalid operation */
  679. if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
  680. ret = FPE_FLTINV;
  681. /* Overflow */
  682. else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
  683. ret = FPE_FLTOVF;
  684. /* Underflow */
  685. else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
  686. ret = FPE_FLTUND;
  687. /* Divide by zero */
  688. else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
  689. ret = FPE_FLTDIV;
  690. /* Inexact result */
  691. else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
  692. ret = FPE_FLTRES;
  693. return ret;
  694. }
  695. static void parse_fpe(struct pt_regs *regs)
  696. {
  697. int code = 0;
  698. flush_fp_to_thread(current);
  699. code = __parse_fpscr(current->thread.fpscr.val);
  700. _exception(SIGFPE, regs, code, regs->nip);
  701. }
  702. /*
  703. * Illegal instruction emulation support. Originally written to
  704. * provide the PVR to user applications using the mfspr rd, PVR.
  705. * Return non-zero if we can't emulate, or -EFAULT if the associated
  706. * memory access caused an access fault. Return zero on success.
  707. *
  708. * There are a couple of ways to do this, either "decode" the instruction
  709. * or directly match lots of bits. In this case, matching lots of
  710. * bits is faster and easier.
  711. *
  712. */
  713. static int emulate_string_inst(struct pt_regs *regs, u32 instword)
  714. {
  715. u8 rT = (instword >> 21) & 0x1f;
  716. u8 rA = (instword >> 16) & 0x1f;
  717. u8 NB_RB = (instword >> 11) & 0x1f;
  718. u32 num_bytes;
  719. unsigned long EA;
  720. int pos = 0;
  721. /* Early out if we are an invalid form of lswx */
  722. if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
  723. if ((rT == rA) || (rT == NB_RB))
  724. return -EINVAL;
  725. EA = (rA == 0) ? 0 : regs->gpr[rA];
  726. switch (instword & PPC_INST_STRING_MASK) {
  727. case PPC_INST_LSWX:
  728. case PPC_INST_STSWX:
  729. EA += NB_RB;
  730. num_bytes = regs->xer & 0x7f;
  731. break;
  732. case PPC_INST_LSWI:
  733. case PPC_INST_STSWI:
  734. num_bytes = (NB_RB == 0) ? 32 : NB_RB;
  735. break;
  736. default:
  737. return -EINVAL;
  738. }
  739. while (num_bytes != 0)
  740. {
  741. u8 val;
  742. u32 shift = 8 * (3 - (pos & 0x3));
  743. /* if process is 32-bit, clear upper 32 bits of EA */
  744. if ((regs->msr & MSR_64BIT) == 0)
  745. EA &= 0xFFFFFFFF;
  746. switch ((instword & PPC_INST_STRING_MASK)) {
  747. case PPC_INST_LSWX:
  748. case PPC_INST_LSWI:
  749. if (get_user(val, (u8 __user *)EA))
  750. return -EFAULT;
  751. /* first time updating this reg,
  752. * zero it out */
  753. if (pos == 0)
  754. regs->gpr[rT] = 0;
  755. regs->gpr[rT] |= val << shift;
  756. break;
  757. case PPC_INST_STSWI:
  758. case PPC_INST_STSWX:
  759. val = regs->gpr[rT] >> shift;
  760. if (put_user(val, (u8 __user *)EA))
  761. return -EFAULT;
  762. break;
  763. }
  764. /* move EA to next address */
  765. EA += 1;
  766. num_bytes--;
  767. /* manage our position within the register */
  768. if (++pos == 4) {
  769. pos = 0;
  770. if (++rT == 32)
  771. rT = 0;
  772. }
  773. }
  774. return 0;
  775. }
  776. static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
  777. {
  778. u32 ra,rs;
  779. unsigned long tmp;
  780. ra = (instword >> 16) & 0x1f;
  781. rs = (instword >> 21) & 0x1f;
  782. tmp = regs->gpr[rs];
  783. tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
  784. tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
  785. tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
  786. regs->gpr[ra] = tmp;
  787. return 0;
  788. }
  789. static int emulate_isel(struct pt_regs *regs, u32 instword)
  790. {
  791. u8 rT = (instword >> 21) & 0x1f;
  792. u8 rA = (instword >> 16) & 0x1f;
  793. u8 rB = (instword >> 11) & 0x1f;
  794. u8 BC = (instword >> 6) & 0x1f;
  795. u8 bit;
  796. unsigned long tmp;
  797. tmp = (rA == 0) ? 0 : regs->gpr[rA];
  798. bit = (regs->ccr >> (31 - BC)) & 0x1;
  799. regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
  800. return 0;
  801. }
  802. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  803. static inline bool tm_abort_check(struct pt_regs *regs, int cause)
  804. {
  805. /* If we're emulating a load/store in an active transaction, we cannot
  806. * emulate it as the kernel operates in transaction suspended context.
  807. * We need to abort the transaction. This creates a persistent TM
  808. * abort so tell the user what caused it with a new code.
  809. */
  810. if (MSR_TM_TRANSACTIONAL(regs->msr)) {
  811. tm_enable();
  812. tm_abort(cause);
  813. return true;
  814. }
  815. return false;
  816. }
  817. #else
  818. static inline bool tm_abort_check(struct pt_regs *regs, int reason)
  819. {
  820. return false;
  821. }
  822. #endif
  823. static int emulate_instruction(struct pt_regs *regs)
  824. {
  825. u32 instword;
  826. u32 rd;
  827. if (!user_mode(regs) || (regs->msr & MSR_LE))
  828. return -EINVAL;
  829. CHECK_FULL_REGS(regs);
  830. if (get_user(instword, (u32 __user *)(regs->nip)))
  831. return -EFAULT;
  832. /* Emulate the mfspr rD, PVR. */
  833. if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
  834. PPC_WARN_EMULATED(mfpvr, regs);
  835. rd = (instword >> 21) & 0x1f;
  836. regs->gpr[rd] = mfspr(SPRN_PVR);
  837. return 0;
  838. }
  839. /* Emulating the dcba insn is just a no-op. */
  840. if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
  841. PPC_WARN_EMULATED(dcba, regs);
  842. return 0;
  843. }
  844. /* Emulate the mcrxr insn. */
  845. if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
  846. int shift = (instword >> 21) & 0x1c;
  847. unsigned long msk = 0xf0000000UL >> shift;
  848. PPC_WARN_EMULATED(mcrxr, regs);
  849. regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
  850. regs->xer &= ~0xf0000000UL;
  851. return 0;
  852. }
  853. /* Emulate load/store string insn. */
  854. if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
  855. if (tm_abort_check(regs,
  856. TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
  857. return -EINVAL;
  858. PPC_WARN_EMULATED(string, regs);
  859. return emulate_string_inst(regs, instword);
  860. }
  861. /* Emulate the popcntb (Population Count Bytes) instruction. */
  862. if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
  863. PPC_WARN_EMULATED(popcntb, regs);
  864. return emulate_popcntb_inst(regs, instword);
  865. }
  866. /* Emulate isel (Integer Select) instruction */
  867. if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
  868. PPC_WARN_EMULATED(isel, regs);
  869. return emulate_isel(regs, instword);
  870. }
  871. #ifdef CONFIG_PPC64
  872. /* Emulate the mfspr rD, DSCR. */
  873. if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
  874. PPC_INST_MFSPR_DSCR_USER) ||
  875. ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
  876. PPC_INST_MFSPR_DSCR)) &&
  877. cpu_has_feature(CPU_FTR_DSCR)) {
  878. PPC_WARN_EMULATED(mfdscr, regs);
  879. rd = (instword >> 21) & 0x1f;
  880. regs->gpr[rd] = mfspr(SPRN_DSCR);
  881. return 0;
  882. }
  883. /* Emulate the mtspr DSCR, rD. */
  884. if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
  885. PPC_INST_MTSPR_DSCR_USER) ||
  886. ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
  887. PPC_INST_MTSPR_DSCR)) &&
  888. cpu_has_feature(CPU_FTR_DSCR)) {
  889. PPC_WARN_EMULATED(mtdscr, regs);
  890. rd = (instword >> 21) & 0x1f;
  891. current->thread.dscr = regs->gpr[rd];
  892. current->thread.dscr_inherit = 1;
  893. mtspr(SPRN_DSCR, current->thread.dscr);
  894. return 0;
  895. }
  896. #endif
  897. return -EINVAL;
  898. }
  899. int is_valid_bugaddr(unsigned long addr)
  900. {
  901. return is_kernel_addr(addr);
  902. }
  903. void __kprobes program_check_exception(struct pt_regs *regs)
  904. {
  905. enum ctx_state prev_state = exception_enter();
  906. unsigned int reason = get_reason(regs);
  907. extern int do_mathemu(struct pt_regs *regs);
  908. /* We can now get here via a FP Unavailable exception if the core
  909. * has no FPU, in that case the reason flags will be 0 */
  910. if (reason & REASON_FP) {
  911. /* IEEE FP exception */
  912. parse_fpe(regs);
  913. goto bail;
  914. }
  915. if (reason & REASON_TRAP) {
  916. /* Debugger is first in line to stop recursive faults in
  917. * rcu_lock, notify_die, or atomic_notifier_call_chain */
  918. if (debugger_bpt(regs))
  919. goto bail;
  920. /* trap exception */
  921. if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
  922. == NOTIFY_STOP)
  923. goto bail;
  924. if (!(regs->msr & MSR_PR) && /* not user-mode */
  925. report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
  926. regs->nip += 4;
  927. goto bail;
  928. }
  929. _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
  930. goto bail;
  931. }
  932. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  933. if (reason & REASON_TM) {
  934. /* This is a TM "Bad Thing Exception" program check.
  935. * This occurs when:
  936. * - An rfid/hrfid/mtmsrd attempts to cause an illegal
  937. * transition in TM states.
  938. * - A trechkpt is attempted when transactional.
  939. * - A treclaim is attempted when non transactional.
  940. * - A tend is illegally attempted.
  941. * - writing a TM SPR when transactional.
  942. */
  943. if (!user_mode(regs) &&
  944. report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
  945. regs->nip += 4;
  946. goto bail;
  947. }
  948. /* If usermode caused this, it's done something illegal and
  949. * gets a SIGILL slap on the wrist. We call it an illegal
  950. * operand to distinguish from the instruction just being bad
  951. * (e.g. executing a 'tend' on a CPU without TM!); it's an
  952. * illegal /placement/ of a valid instruction.
  953. */
  954. if (user_mode(regs)) {
  955. _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
  956. goto bail;
  957. } else {
  958. printk(KERN_EMERG "Unexpected TM Bad Thing exception "
  959. "at %lx (msr 0x%x)\n", regs->nip, reason);
  960. die("Unrecoverable exception", regs, SIGABRT);
  961. }
  962. }
  963. #endif
  964. /* We restore the interrupt state now */
  965. if (!arch_irq_disabled_regs(regs))
  966. local_irq_enable();
  967. #ifdef CONFIG_MATH_EMULATION
  968. /* (reason & REASON_ILLEGAL) would be the obvious thing here,
  969. * but there seems to be a hardware bug on the 405GP (RevD)
  970. * that means ESR is sometimes set incorrectly - either to
  971. * ESR_DST (!?) or 0. In the process of chasing this with the
  972. * hardware people - not sure if it can happen on any illegal
  973. * instruction or only on FP instructions, whether there is a
  974. * pattern to occurrences etc. -dgibson 31/Mar/2003
  975. */
  976. /*
  977. * If we support a HW FPU, we need to ensure the FP state
  978. * if flushed into the thread_struct before attempting
  979. * emulation
  980. */
  981. #ifdef CONFIG_PPC_FPU
  982. flush_fp_to_thread(current);
  983. #endif
  984. switch (do_mathemu(regs)) {
  985. case 0:
  986. emulate_single_step(regs);
  987. goto bail;
  988. case 1: {
  989. int code = 0;
  990. code = __parse_fpscr(current->thread.fpscr.val);
  991. _exception(SIGFPE, regs, code, regs->nip);
  992. goto bail;
  993. }
  994. case -EFAULT:
  995. _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
  996. goto bail;
  997. }
  998. /* fall through on any other errors */
  999. #endif /* CONFIG_MATH_EMULATION */
  1000. /* Try to emulate it if we should. */
  1001. if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
  1002. switch (emulate_instruction(regs)) {
  1003. case 0:
  1004. regs->nip += 4;
  1005. emulate_single_step(regs);
  1006. goto bail;
  1007. case -EFAULT:
  1008. _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
  1009. goto bail;
  1010. }
  1011. }
  1012. if (reason & REASON_PRIVILEGED)
  1013. _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
  1014. else
  1015. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1016. bail:
  1017. exception_exit(prev_state);
  1018. }
  1019. void alignment_exception(struct pt_regs *regs)
  1020. {
  1021. enum ctx_state prev_state = exception_enter();
  1022. int sig, code, fixed = 0;
  1023. /* We restore the interrupt state now */
  1024. if (!arch_irq_disabled_regs(regs))
  1025. local_irq_enable();
  1026. if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
  1027. goto bail;
  1028. /* we don't implement logging of alignment exceptions */
  1029. if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
  1030. fixed = fix_alignment(regs);
  1031. if (fixed == 1) {
  1032. regs->nip += 4; /* skip over emulated instruction */
  1033. emulate_single_step(regs);
  1034. goto bail;
  1035. }
  1036. /* Operand address was bad */
  1037. if (fixed == -EFAULT) {
  1038. sig = SIGSEGV;
  1039. code = SEGV_ACCERR;
  1040. } else {
  1041. sig = SIGBUS;
  1042. code = BUS_ADRALN;
  1043. }
  1044. if (user_mode(regs))
  1045. _exception(sig, regs, code, regs->dar);
  1046. else
  1047. bad_page_fault(regs, regs->dar, sig);
  1048. bail:
  1049. exception_exit(prev_state);
  1050. }
  1051. void StackOverflow(struct pt_regs *regs)
  1052. {
  1053. printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
  1054. current, regs->gpr[1]);
  1055. debugger(regs);
  1056. show_regs(regs);
  1057. panic("kernel stack overflow");
  1058. }
  1059. void nonrecoverable_exception(struct pt_regs *regs)
  1060. {
  1061. printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
  1062. regs->nip, regs->msr);
  1063. debugger(regs);
  1064. die("nonrecoverable exception", regs, SIGKILL);
  1065. }
  1066. void trace_syscall(struct pt_regs *regs)
  1067. {
  1068. printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
  1069. current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
  1070. regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
  1071. }
  1072. void kernel_fp_unavailable_exception(struct pt_regs *regs)
  1073. {
  1074. enum ctx_state prev_state = exception_enter();
  1075. printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
  1076. "%lx at %lx\n", regs->trap, regs->nip);
  1077. die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
  1078. exception_exit(prev_state);
  1079. }
  1080. void altivec_unavailable_exception(struct pt_regs *regs)
  1081. {
  1082. enum ctx_state prev_state = exception_enter();
  1083. if (user_mode(regs)) {
  1084. /* A user program has executed an altivec instruction,
  1085. but this kernel doesn't support altivec. */
  1086. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1087. goto bail;
  1088. }
  1089. printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
  1090. "%lx at %lx\n", regs->trap, regs->nip);
  1091. die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
  1092. bail:
  1093. exception_exit(prev_state);
  1094. }
  1095. void vsx_unavailable_exception(struct pt_regs *regs)
  1096. {
  1097. if (user_mode(regs)) {
  1098. /* A user program has executed an vsx instruction,
  1099. but this kernel doesn't support vsx. */
  1100. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1101. return;
  1102. }
  1103. printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
  1104. "%lx at %lx\n", regs->trap, regs->nip);
  1105. die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
  1106. }
  1107. void tm_unavailable_exception(struct pt_regs *regs)
  1108. {
  1109. /* We restore the interrupt state now */
  1110. if (!arch_irq_disabled_regs(regs))
  1111. local_irq_enable();
  1112. /* Currently we never expect a TMU exception. Catch
  1113. * this and kill the process!
  1114. */
  1115. printk(KERN_EMERG "Unexpected TM unavailable exception at %lx "
  1116. "(msr %lx)\n",
  1117. regs->nip, regs->msr);
  1118. if (user_mode(regs)) {
  1119. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1120. return;
  1121. }
  1122. die("Unexpected TM unavailable exception", regs, SIGABRT);
  1123. }
  1124. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1125. extern void do_load_up_fpu(struct pt_regs *regs);
  1126. void fp_unavailable_tm(struct pt_regs *regs)
  1127. {
  1128. /* Note: This does not handle any kind of FP laziness. */
  1129. TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
  1130. regs->nip, regs->msr);
  1131. tm_enable();
  1132. /* We can only have got here if the task started using FP after
  1133. * beginning the transaction. So, the transactional regs are just a
  1134. * copy of the checkpointed ones. But, we still need to recheckpoint
  1135. * as we're enabling FP for the process; it will return, abort the
  1136. * transaction, and probably retry but now with FP enabled. So the
  1137. * checkpointed FP registers need to be loaded.
  1138. */
  1139. tm_reclaim(&current->thread, current->thread.regs->msr,
  1140. TM_CAUSE_FAC_UNAV);
  1141. /* Reclaim didn't save out any FPRs to transact_fprs. */
  1142. /* Enable FP for the task: */
  1143. regs->msr |= (MSR_FP | current->thread.fpexc_mode);
  1144. /* This loads and recheckpoints the FP registers from
  1145. * thread.fpr[]. They will remain in registers after the
  1146. * checkpoint so we don't need to reload them after.
  1147. */
  1148. tm_recheckpoint(&current->thread, regs->msr);
  1149. }
  1150. #ifdef CONFIG_ALTIVEC
  1151. extern void do_load_up_altivec(struct pt_regs *regs);
  1152. void altivec_unavailable_tm(struct pt_regs *regs)
  1153. {
  1154. /* See the comments in fp_unavailable_tm(). This function operates
  1155. * the same way.
  1156. */
  1157. TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
  1158. "MSR=%lx\n",
  1159. regs->nip, regs->msr);
  1160. tm_enable();
  1161. tm_reclaim(&current->thread, current->thread.regs->msr,
  1162. TM_CAUSE_FAC_UNAV);
  1163. regs->msr |= MSR_VEC;
  1164. tm_recheckpoint(&current->thread, regs->msr);
  1165. current->thread.used_vr = 1;
  1166. }
  1167. #endif
  1168. #ifdef CONFIG_VSX
  1169. void vsx_unavailable_tm(struct pt_regs *regs)
  1170. {
  1171. /* See the comments in fp_unavailable_tm(). This works similarly,
  1172. * though we're loading both FP and VEC registers in here.
  1173. *
  1174. * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
  1175. * regs. Either way, set MSR_VSX.
  1176. */
  1177. TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
  1178. "MSR=%lx\n",
  1179. regs->nip, regs->msr);
  1180. tm_enable();
  1181. /* This reclaims FP and/or VR regs if they're already enabled */
  1182. tm_reclaim(&current->thread, current->thread.regs->msr,
  1183. TM_CAUSE_FAC_UNAV);
  1184. regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
  1185. MSR_VSX;
  1186. /* This loads & recheckpoints FP and VRs. */
  1187. tm_recheckpoint(&current->thread, regs->msr);
  1188. current->thread.used_vsr = 1;
  1189. }
  1190. #endif
  1191. #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  1192. void performance_monitor_exception(struct pt_regs *regs)
  1193. {
  1194. __get_cpu_var(irq_stat).pmu_irqs++;
  1195. perf_irq(regs);
  1196. }
  1197. #ifdef CONFIG_8xx
  1198. void SoftwareEmulation(struct pt_regs *regs)
  1199. {
  1200. extern int do_mathemu(struct pt_regs *);
  1201. #if defined(CONFIG_MATH_EMULATION)
  1202. int errcode;
  1203. #endif
  1204. CHECK_FULL_REGS(regs);
  1205. if (!user_mode(regs)) {
  1206. debugger(regs);
  1207. die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
  1208. }
  1209. #ifdef CONFIG_MATH_EMULATION
  1210. errcode = do_mathemu(regs);
  1211. if (errcode >= 0)
  1212. PPC_WARN_EMULATED(math, regs);
  1213. switch (errcode) {
  1214. case 0:
  1215. emulate_single_step(regs);
  1216. return;
  1217. case 1: {
  1218. int code = 0;
  1219. code = __parse_fpscr(current->thread.fpscr.val);
  1220. _exception(SIGFPE, regs, code, regs->nip);
  1221. return;
  1222. }
  1223. case -EFAULT:
  1224. _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
  1225. return;
  1226. default:
  1227. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1228. return;
  1229. }
  1230. #else
  1231. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1232. #endif
  1233. }
  1234. #endif /* CONFIG_8xx */
  1235. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  1236. static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
  1237. {
  1238. int changed = 0;
  1239. /*
  1240. * Determine the cause of the debug event, clear the
  1241. * event flags and send a trap to the handler. Torez
  1242. */
  1243. if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
  1244. dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
  1245. #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
  1246. current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
  1247. #endif
  1248. do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
  1249. 5);
  1250. changed |= 0x01;
  1251. } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
  1252. dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
  1253. do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
  1254. 6);
  1255. changed |= 0x01;
  1256. } else if (debug_status & DBSR_IAC1) {
  1257. current->thread.dbcr0 &= ~DBCR0_IAC1;
  1258. dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
  1259. do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
  1260. 1);
  1261. changed |= 0x01;
  1262. } else if (debug_status & DBSR_IAC2) {
  1263. current->thread.dbcr0 &= ~DBCR0_IAC2;
  1264. do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
  1265. 2);
  1266. changed |= 0x01;
  1267. } else if (debug_status & DBSR_IAC3) {
  1268. current->thread.dbcr0 &= ~DBCR0_IAC3;
  1269. dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
  1270. do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
  1271. 3);
  1272. changed |= 0x01;
  1273. } else if (debug_status & DBSR_IAC4) {
  1274. current->thread.dbcr0 &= ~DBCR0_IAC4;
  1275. do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
  1276. 4);
  1277. changed |= 0x01;
  1278. }
  1279. /*
  1280. * At the point this routine was called, the MSR(DE) was turned off.
  1281. * Check all other debug flags and see if that bit needs to be turned
  1282. * back on or not.
  1283. */
  1284. if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
  1285. regs->msr |= MSR_DE;
  1286. else
  1287. /* Make sure the IDM flag is off */
  1288. current->thread.dbcr0 &= ~DBCR0_IDM;
  1289. if (changed & 0x01)
  1290. mtspr(SPRN_DBCR0, current->thread.dbcr0);
  1291. }
  1292. void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
  1293. {
  1294. current->thread.dbsr = debug_status;
  1295. /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
  1296. * on server, it stops on the target of the branch. In order to simulate
  1297. * the server behaviour, we thus restart right away with a single step
  1298. * instead of stopping here when hitting a BT
  1299. */
  1300. if (debug_status & DBSR_BT) {
  1301. regs->msr &= ~MSR_DE;
  1302. /* Disable BT */
  1303. mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
  1304. /* Clear the BT event */
  1305. mtspr(SPRN_DBSR, DBSR_BT);
  1306. /* Do the single step trick only when coming from userspace */
  1307. if (user_mode(regs)) {
  1308. current->thread.dbcr0 &= ~DBCR0_BT;
  1309. current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
  1310. regs->msr |= MSR_DE;
  1311. return;
  1312. }
  1313. if (notify_die(DIE_SSTEP, "block_step", regs, 5,
  1314. 5, SIGTRAP) == NOTIFY_STOP) {
  1315. return;
  1316. }
  1317. if (debugger_sstep(regs))
  1318. return;
  1319. } else if (debug_status & DBSR_IC) { /* Instruction complete */
  1320. regs->msr &= ~MSR_DE;
  1321. /* Disable instruction completion */
  1322. mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
  1323. /* Clear the instruction completion event */
  1324. mtspr(SPRN_DBSR, DBSR_IC);
  1325. if (notify_die(DIE_SSTEP, "single_step", regs, 5,
  1326. 5, SIGTRAP) == NOTIFY_STOP) {
  1327. return;
  1328. }
  1329. if (debugger_sstep(regs))
  1330. return;
  1331. if (user_mode(regs)) {
  1332. current->thread.dbcr0 &= ~DBCR0_IC;
  1333. if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
  1334. current->thread.dbcr1))
  1335. regs->msr |= MSR_DE;
  1336. else
  1337. /* Make sure the IDM bit is off */
  1338. current->thread.dbcr0 &= ~DBCR0_IDM;
  1339. }
  1340. _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
  1341. } else
  1342. handle_debug(regs, debug_status);
  1343. }
  1344. #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
  1345. #if !defined(CONFIG_TAU_INT)
  1346. void TAUException(struct pt_regs *regs)
  1347. {
  1348. printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
  1349. regs->nip, regs->msr, regs->trap, print_tainted());
  1350. }
  1351. #endif /* CONFIG_INT_TAU */
  1352. #ifdef CONFIG_ALTIVEC
  1353. void altivec_assist_exception(struct pt_regs *regs)
  1354. {
  1355. int err;
  1356. if (!user_mode(regs)) {
  1357. printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
  1358. " at %lx\n", regs->nip);
  1359. die("Kernel VMX/Altivec assist exception", regs, SIGILL);
  1360. }
  1361. flush_altivec_to_thread(current);
  1362. PPC_WARN_EMULATED(altivec, regs);
  1363. err = emulate_altivec(regs);
  1364. if (err == 0) {
  1365. regs->nip += 4; /* skip emulated instruction */
  1366. emulate_single_step(regs);
  1367. return;
  1368. }
  1369. if (err == -EFAULT) {
  1370. /* got an error reading the instruction */
  1371. _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
  1372. } else {
  1373. /* didn't recognize the instruction */
  1374. /* XXX quick hack for now: set the non-Java bit in the VSCR */
  1375. printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
  1376. "in %s at %lx\n", current->comm, regs->nip);
  1377. current->thread.vscr.u[3] |= 0x10000;
  1378. }
  1379. }
  1380. #endif /* CONFIG_ALTIVEC */
  1381. #ifdef CONFIG_VSX
  1382. void vsx_assist_exception(struct pt_regs *regs)
  1383. {
  1384. if (!user_mode(regs)) {
  1385. printk(KERN_EMERG "VSX assist exception in kernel mode"
  1386. " at %lx\n", regs->nip);
  1387. die("Kernel VSX assist exception", regs, SIGILL);
  1388. }
  1389. flush_vsx_to_thread(current);
  1390. printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip);
  1391. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1392. }
  1393. #endif /* CONFIG_VSX */
  1394. #ifdef CONFIG_FSL_BOOKE
  1395. void CacheLockingException(struct pt_regs *regs, unsigned long address,
  1396. unsigned long error_code)
  1397. {
  1398. /* We treat cache locking instructions from the user
  1399. * as priv ops, in the future we could try to do
  1400. * something smarter
  1401. */
  1402. if (error_code & (ESR_DLK|ESR_ILK))
  1403. _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
  1404. return;
  1405. }
  1406. #endif /* CONFIG_FSL_BOOKE */
  1407. #ifdef CONFIG_SPE
  1408. void SPEFloatingPointException(struct pt_regs *regs)
  1409. {
  1410. extern int do_spe_mathemu(struct pt_regs *regs);
  1411. unsigned long spefscr;
  1412. int fpexc_mode;
  1413. int code = 0;
  1414. int err;
  1415. flush_spe_to_thread(current);
  1416. spefscr = current->thread.spefscr;
  1417. fpexc_mode = current->thread.fpexc_mode;
  1418. if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
  1419. code = FPE_FLTOVF;
  1420. }
  1421. else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
  1422. code = FPE_FLTUND;
  1423. }
  1424. else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
  1425. code = FPE_FLTDIV;
  1426. else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
  1427. code = FPE_FLTINV;
  1428. }
  1429. else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
  1430. code = FPE_FLTRES;
  1431. err = do_spe_mathemu(regs);
  1432. if (err == 0) {
  1433. regs->nip += 4; /* skip emulated instruction */
  1434. emulate_single_step(regs);
  1435. return;
  1436. }
  1437. if (err == -EFAULT) {
  1438. /* got an error reading the instruction */
  1439. _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
  1440. } else if (err == -EINVAL) {
  1441. /* didn't recognize the instruction */
  1442. printk(KERN_ERR "unrecognized spe instruction "
  1443. "in %s at %lx\n", current->comm, regs->nip);
  1444. } else {
  1445. _exception(SIGFPE, regs, code, regs->nip);
  1446. }
  1447. return;
  1448. }
  1449. void SPEFloatingPointRoundException(struct pt_regs *regs)
  1450. {
  1451. extern int speround_handler(struct pt_regs *regs);
  1452. int err;
  1453. preempt_disable();
  1454. if (regs->msr & MSR_SPE)
  1455. giveup_spe(current);
  1456. preempt_enable();
  1457. regs->nip -= 4;
  1458. err = speround_handler(regs);
  1459. if (err == 0) {
  1460. regs->nip += 4; /* skip emulated instruction */
  1461. emulate_single_step(regs);
  1462. return;
  1463. }
  1464. if (err == -EFAULT) {
  1465. /* got an error reading the instruction */
  1466. _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
  1467. } else if (err == -EINVAL) {
  1468. /* didn't recognize the instruction */
  1469. printk(KERN_ERR "unrecognized spe instruction "
  1470. "in %s at %lx\n", current->comm, regs->nip);
  1471. } else {
  1472. _exception(SIGFPE, regs, 0, regs->nip);
  1473. return;
  1474. }
  1475. }
  1476. #endif
  1477. /*
  1478. * We enter here if we get an unrecoverable exception, that is, one
  1479. * that happened at a point where the RI (recoverable interrupt) bit
  1480. * in the MSR is 0. This indicates that SRR0/1 are live, and that
  1481. * we therefore lost state by taking this exception.
  1482. */
  1483. void unrecoverable_exception(struct pt_regs *regs)
  1484. {
  1485. printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
  1486. regs->trap, regs->nip);
  1487. die("Unrecoverable exception", regs, SIGABRT);
  1488. }
  1489. #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
  1490. /*
  1491. * Default handler for a Watchdog exception,
  1492. * spins until a reboot occurs
  1493. */
  1494. void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
  1495. {
  1496. /* Generic WatchdogHandler, implement your own */
  1497. mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
  1498. return;
  1499. }
  1500. void WatchdogException(struct pt_regs *regs)
  1501. {
  1502. printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
  1503. WatchdogHandler(regs);
  1504. }
  1505. #endif
  1506. /*
  1507. * We enter here if we discover during exception entry that we are
  1508. * running in supervisor mode with a userspace value in the stack pointer.
  1509. */
  1510. void kernel_bad_stack(struct pt_regs *regs)
  1511. {
  1512. printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
  1513. regs->gpr[1], regs->nip);
  1514. die("Bad kernel stack pointer", regs, SIGABRT);
  1515. }
  1516. void __init trap_init(void)
  1517. {
  1518. }
  1519. #ifdef CONFIG_PPC_EMULATED_STATS
  1520. #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
  1521. struct ppc_emulated ppc_emulated = {
  1522. #ifdef CONFIG_ALTIVEC
  1523. WARN_EMULATED_SETUP(altivec),
  1524. #endif
  1525. WARN_EMULATED_SETUP(dcba),
  1526. WARN_EMULATED_SETUP(dcbz),
  1527. WARN_EMULATED_SETUP(fp_pair),
  1528. WARN_EMULATED_SETUP(isel),
  1529. WARN_EMULATED_SETUP(mcrxr),
  1530. WARN_EMULATED_SETUP(mfpvr),
  1531. WARN_EMULATED_SETUP(multiple),
  1532. WARN_EMULATED_SETUP(popcntb),
  1533. WARN_EMULATED_SETUP(spe),
  1534. WARN_EMULATED_SETUP(string),
  1535. WARN_EMULATED_SETUP(unaligned),
  1536. #ifdef CONFIG_MATH_EMULATION
  1537. WARN_EMULATED_SETUP(math),
  1538. #endif
  1539. #ifdef CONFIG_VSX
  1540. WARN_EMULATED_SETUP(vsx),
  1541. #endif
  1542. #ifdef CONFIG_PPC64
  1543. WARN_EMULATED_SETUP(mfdscr),
  1544. WARN_EMULATED_SETUP(mtdscr),
  1545. #endif
  1546. };
  1547. u32 ppc_warn_emulated;
  1548. void ppc_warn_emulated_print(const char *type)
  1549. {
  1550. pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
  1551. type);
  1552. }
  1553. static int __init ppc_warn_emulated_init(void)
  1554. {
  1555. struct dentry *dir, *d;
  1556. unsigned int i;
  1557. struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
  1558. if (!powerpc_debugfs_root)
  1559. return -ENODEV;
  1560. dir = debugfs_create_dir("emulated_instructions",
  1561. powerpc_debugfs_root);
  1562. if (!dir)
  1563. return -ENOMEM;
  1564. d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
  1565. &ppc_warn_emulated);
  1566. if (!d)
  1567. goto fail;
  1568. for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
  1569. d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
  1570. (u32 *)&entries[i].val.counter);
  1571. if (!d)
  1572. goto fail;
  1573. }
  1574. return 0;
  1575. fail:
  1576. debugfs_remove_recursive(dir);
  1577. return -ENOMEM;
  1578. }
  1579. device_initcall(ppc_warn_emulated_init);
  1580. #endif /* CONFIG_PPC_EMULATED_STATS */