cputable.c 67 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/export.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. #include <asm/mmu.h>
  21. #include <asm/setup.h>
  22. struct cpu_spec* cur_cpu_spec = NULL;
  23. EXPORT_SYMBOL(cur_cpu_spec);
  24. /* The platform string corresponding to the real PVR */
  25. const char *powerpc_base_platform;
  26. /* NOTE:
  27. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  28. * the responsibility of the appropriate CPU save/restore functions to
  29. * eventually copy these settings over. Those save/restore aren't yet
  30. * part of the cputable though. That has to be fixed for both ppc32
  31. * and ppc64
  32. */
  33. #ifdef CONFIG_PPC32
  34. extern void __setup_cpu_e200(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);
  42. extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec);
  43. extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec);
  44. extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec);
  45. extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec);
  46. extern void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec);
  47. extern void __setup_cpu_apm821xx(unsigned long offset, struct cpu_spec *spec);
  48. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  49. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  50. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  51. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  52. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  53. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  54. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  55. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  56. #endif /* CONFIG_PPC32 */
  57. #ifdef CONFIG_PPC64
  58. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  59. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  60. extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
  61. extern void __setup_cpu_a2(unsigned long offset, struct cpu_spec* spec);
  62. extern void __restore_cpu_pa6t(void);
  63. extern void __restore_cpu_ppc970(void);
  64. extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
  65. extern void __restore_cpu_power7(void);
  66. extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
  67. extern void __restore_cpu_power8(void);
  68. extern void __restore_cpu_a2(void);
  69. #endif /* CONFIG_PPC64 */
  70. #if defined(CONFIG_E500)
  71. extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
  72. extern void __setup_cpu_e6500(unsigned long offset, struct cpu_spec* spec);
  73. extern void __restore_cpu_e5500(void);
  74. extern void __restore_cpu_e6500(void);
  75. #endif /* CONFIG_E500 */
  76. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  77. * ones as well...
  78. */
  79. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  80. PPC_FEATURE_HAS_MMU)
  81. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  82. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  83. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  84. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  85. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  86. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  87. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  88. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  89. PPC_FEATURE_TRUE_LE | \
  90. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  91. #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  92. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  93. PPC_FEATURE_TRUE_LE | \
  94. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  95. #define COMMON_USER2_POWER7 (PPC_FEATURE2_DSCR)
  96. #define COMMON_USER_POWER8 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  97. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  98. PPC_FEATURE_TRUE_LE | \
  99. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  100. #define COMMON_USER2_POWER8 (PPC_FEATURE2_ARCH_2_07 | \
  101. PPC_FEATURE2_HTM_COMP | PPC_FEATURE2_DSCR | \
  102. PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR)
  103. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  104. PPC_FEATURE_TRUE_LE | \
  105. PPC_FEATURE_HAS_ALTIVEC_COMP)
  106. #ifdef CONFIG_PPC_BOOK3E_64
  107. #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
  108. #else
  109. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  110. PPC_FEATURE_BOOKE)
  111. #endif
  112. static struct cpu_spec __initdata cpu_specs[] = {
  113. #ifdef CONFIG_PPC_BOOK3S_64
  114. { /* Power3 */
  115. .pvr_mask = 0xffff0000,
  116. .pvr_value = 0x00400000,
  117. .cpu_name = "POWER3 (630)",
  118. .cpu_features = CPU_FTRS_POWER3,
  119. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  120. .mmu_features = MMU_FTR_HPTE_TABLE,
  121. .icache_bsize = 128,
  122. .dcache_bsize = 128,
  123. .num_pmcs = 8,
  124. .pmc_type = PPC_PMC_IBM,
  125. .oprofile_cpu_type = "ppc64/power3",
  126. .oprofile_type = PPC_OPROFILE_RS64,
  127. .platform = "power3",
  128. },
  129. { /* Power3+ */
  130. .pvr_mask = 0xffff0000,
  131. .pvr_value = 0x00410000,
  132. .cpu_name = "POWER3 (630+)",
  133. .cpu_features = CPU_FTRS_POWER3,
  134. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  135. .mmu_features = MMU_FTR_HPTE_TABLE,
  136. .icache_bsize = 128,
  137. .dcache_bsize = 128,
  138. .num_pmcs = 8,
  139. .pmc_type = PPC_PMC_IBM,
  140. .oprofile_cpu_type = "ppc64/power3",
  141. .oprofile_type = PPC_OPROFILE_RS64,
  142. .platform = "power3",
  143. },
  144. { /* Northstar */
  145. .pvr_mask = 0xffff0000,
  146. .pvr_value = 0x00330000,
  147. .cpu_name = "RS64-II (northstar)",
  148. .cpu_features = CPU_FTRS_RS64,
  149. .cpu_user_features = COMMON_USER_PPC64,
  150. .mmu_features = MMU_FTR_HPTE_TABLE,
  151. .icache_bsize = 128,
  152. .dcache_bsize = 128,
  153. .num_pmcs = 8,
  154. .pmc_type = PPC_PMC_IBM,
  155. .oprofile_cpu_type = "ppc64/rs64",
  156. .oprofile_type = PPC_OPROFILE_RS64,
  157. .platform = "rs64",
  158. },
  159. { /* Pulsar */
  160. .pvr_mask = 0xffff0000,
  161. .pvr_value = 0x00340000,
  162. .cpu_name = "RS64-III (pulsar)",
  163. .cpu_features = CPU_FTRS_RS64,
  164. .cpu_user_features = COMMON_USER_PPC64,
  165. .mmu_features = MMU_FTR_HPTE_TABLE,
  166. .icache_bsize = 128,
  167. .dcache_bsize = 128,
  168. .num_pmcs = 8,
  169. .pmc_type = PPC_PMC_IBM,
  170. .oprofile_cpu_type = "ppc64/rs64",
  171. .oprofile_type = PPC_OPROFILE_RS64,
  172. .platform = "rs64",
  173. },
  174. { /* I-star */
  175. .pvr_mask = 0xffff0000,
  176. .pvr_value = 0x00360000,
  177. .cpu_name = "RS64-III (icestar)",
  178. .cpu_features = CPU_FTRS_RS64,
  179. .cpu_user_features = COMMON_USER_PPC64,
  180. .mmu_features = MMU_FTR_HPTE_TABLE,
  181. .icache_bsize = 128,
  182. .dcache_bsize = 128,
  183. .num_pmcs = 8,
  184. .pmc_type = PPC_PMC_IBM,
  185. .oprofile_cpu_type = "ppc64/rs64",
  186. .oprofile_type = PPC_OPROFILE_RS64,
  187. .platform = "rs64",
  188. },
  189. { /* S-star */
  190. .pvr_mask = 0xffff0000,
  191. .pvr_value = 0x00370000,
  192. .cpu_name = "RS64-IV (sstar)",
  193. .cpu_features = CPU_FTRS_RS64,
  194. .cpu_user_features = COMMON_USER_PPC64,
  195. .mmu_features = MMU_FTR_HPTE_TABLE,
  196. .icache_bsize = 128,
  197. .dcache_bsize = 128,
  198. .num_pmcs = 8,
  199. .pmc_type = PPC_PMC_IBM,
  200. .oprofile_cpu_type = "ppc64/rs64",
  201. .oprofile_type = PPC_OPROFILE_RS64,
  202. .platform = "rs64",
  203. },
  204. { /* Power4 */
  205. .pvr_mask = 0xffff0000,
  206. .pvr_value = 0x00350000,
  207. .cpu_name = "POWER4 (gp)",
  208. .cpu_features = CPU_FTRS_POWER4,
  209. .cpu_user_features = COMMON_USER_POWER4,
  210. .mmu_features = MMU_FTRS_POWER4,
  211. .icache_bsize = 128,
  212. .dcache_bsize = 128,
  213. .num_pmcs = 8,
  214. .pmc_type = PPC_PMC_IBM,
  215. .oprofile_cpu_type = "ppc64/power4",
  216. .oprofile_type = PPC_OPROFILE_POWER4,
  217. .platform = "power4",
  218. },
  219. { /* Power4+ */
  220. .pvr_mask = 0xffff0000,
  221. .pvr_value = 0x00380000,
  222. .cpu_name = "POWER4+ (gq)",
  223. .cpu_features = CPU_FTRS_POWER4,
  224. .cpu_user_features = COMMON_USER_POWER4,
  225. .mmu_features = MMU_FTRS_POWER4,
  226. .icache_bsize = 128,
  227. .dcache_bsize = 128,
  228. .num_pmcs = 8,
  229. .pmc_type = PPC_PMC_IBM,
  230. .oprofile_cpu_type = "ppc64/power4",
  231. .oprofile_type = PPC_OPROFILE_POWER4,
  232. .platform = "power4",
  233. },
  234. { /* PPC970 */
  235. .pvr_mask = 0xffff0000,
  236. .pvr_value = 0x00390000,
  237. .cpu_name = "PPC970",
  238. .cpu_features = CPU_FTRS_PPC970,
  239. .cpu_user_features = COMMON_USER_POWER4 |
  240. PPC_FEATURE_HAS_ALTIVEC_COMP,
  241. .mmu_features = MMU_FTRS_PPC970,
  242. .icache_bsize = 128,
  243. .dcache_bsize = 128,
  244. .num_pmcs = 8,
  245. .pmc_type = PPC_PMC_IBM,
  246. .cpu_setup = __setup_cpu_ppc970,
  247. .cpu_restore = __restore_cpu_ppc970,
  248. .oprofile_cpu_type = "ppc64/970",
  249. .oprofile_type = PPC_OPROFILE_POWER4,
  250. .platform = "ppc970",
  251. },
  252. { /* PPC970FX */
  253. .pvr_mask = 0xffff0000,
  254. .pvr_value = 0x003c0000,
  255. .cpu_name = "PPC970FX",
  256. .cpu_features = CPU_FTRS_PPC970,
  257. .cpu_user_features = COMMON_USER_POWER4 |
  258. PPC_FEATURE_HAS_ALTIVEC_COMP,
  259. .mmu_features = MMU_FTRS_PPC970,
  260. .icache_bsize = 128,
  261. .dcache_bsize = 128,
  262. .num_pmcs = 8,
  263. .pmc_type = PPC_PMC_IBM,
  264. .cpu_setup = __setup_cpu_ppc970,
  265. .cpu_restore = __restore_cpu_ppc970,
  266. .oprofile_cpu_type = "ppc64/970",
  267. .oprofile_type = PPC_OPROFILE_POWER4,
  268. .platform = "ppc970",
  269. },
  270. { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
  271. .pvr_mask = 0xffffffff,
  272. .pvr_value = 0x00440100,
  273. .cpu_name = "PPC970MP",
  274. .cpu_features = CPU_FTRS_PPC970,
  275. .cpu_user_features = COMMON_USER_POWER4 |
  276. PPC_FEATURE_HAS_ALTIVEC_COMP,
  277. .mmu_features = MMU_FTRS_PPC970,
  278. .icache_bsize = 128,
  279. .dcache_bsize = 128,
  280. .num_pmcs = 8,
  281. .pmc_type = PPC_PMC_IBM,
  282. .cpu_setup = __setup_cpu_ppc970,
  283. .cpu_restore = __restore_cpu_ppc970,
  284. .oprofile_cpu_type = "ppc64/970MP",
  285. .oprofile_type = PPC_OPROFILE_POWER4,
  286. .platform = "ppc970",
  287. },
  288. { /* PPC970MP */
  289. .pvr_mask = 0xffff0000,
  290. .pvr_value = 0x00440000,
  291. .cpu_name = "PPC970MP",
  292. .cpu_features = CPU_FTRS_PPC970,
  293. .cpu_user_features = COMMON_USER_POWER4 |
  294. PPC_FEATURE_HAS_ALTIVEC_COMP,
  295. .mmu_features = MMU_FTRS_PPC970,
  296. .icache_bsize = 128,
  297. .dcache_bsize = 128,
  298. .num_pmcs = 8,
  299. .pmc_type = PPC_PMC_IBM,
  300. .cpu_setup = __setup_cpu_ppc970MP,
  301. .cpu_restore = __restore_cpu_ppc970,
  302. .oprofile_cpu_type = "ppc64/970MP",
  303. .oprofile_type = PPC_OPROFILE_POWER4,
  304. .platform = "ppc970",
  305. },
  306. { /* PPC970GX */
  307. .pvr_mask = 0xffff0000,
  308. .pvr_value = 0x00450000,
  309. .cpu_name = "PPC970GX",
  310. .cpu_features = CPU_FTRS_PPC970,
  311. .cpu_user_features = COMMON_USER_POWER4 |
  312. PPC_FEATURE_HAS_ALTIVEC_COMP,
  313. .mmu_features = MMU_FTRS_PPC970,
  314. .icache_bsize = 128,
  315. .dcache_bsize = 128,
  316. .num_pmcs = 8,
  317. .pmc_type = PPC_PMC_IBM,
  318. .cpu_setup = __setup_cpu_ppc970,
  319. .oprofile_cpu_type = "ppc64/970",
  320. .oprofile_type = PPC_OPROFILE_POWER4,
  321. .platform = "ppc970",
  322. },
  323. { /* Power5 GR */
  324. .pvr_mask = 0xffff0000,
  325. .pvr_value = 0x003a0000,
  326. .cpu_name = "POWER5 (gr)",
  327. .cpu_features = CPU_FTRS_POWER5,
  328. .cpu_user_features = COMMON_USER_POWER5,
  329. .mmu_features = MMU_FTRS_POWER5,
  330. .icache_bsize = 128,
  331. .dcache_bsize = 128,
  332. .num_pmcs = 6,
  333. .pmc_type = PPC_PMC_IBM,
  334. .oprofile_cpu_type = "ppc64/power5",
  335. .oprofile_type = PPC_OPROFILE_POWER4,
  336. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  337. * and above but only works on POWER5 and above
  338. */
  339. .oprofile_mmcra_sihv = MMCRA_SIHV,
  340. .oprofile_mmcra_sipr = MMCRA_SIPR,
  341. .platform = "power5",
  342. },
  343. { /* Power5++ */
  344. .pvr_mask = 0xffffff00,
  345. .pvr_value = 0x003b0300,
  346. .cpu_name = "POWER5+ (gs)",
  347. .cpu_features = CPU_FTRS_POWER5,
  348. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  349. .mmu_features = MMU_FTRS_POWER5,
  350. .icache_bsize = 128,
  351. .dcache_bsize = 128,
  352. .num_pmcs = 6,
  353. .oprofile_cpu_type = "ppc64/power5++",
  354. .oprofile_type = PPC_OPROFILE_POWER4,
  355. .oprofile_mmcra_sihv = MMCRA_SIHV,
  356. .oprofile_mmcra_sipr = MMCRA_SIPR,
  357. .platform = "power5+",
  358. },
  359. { /* Power5 GS */
  360. .pvr_mask = 0xffff0000,
  361. .pvr_value = 0x003b0000,
  362. .cpu_name = "POWER5+ (gs)",
  363. .cpu_features = CPU_FTRS_POWER5,
  364. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  365. .mmu_features = MMU_FTRS_POWER5,
  366. .icache_bsize = 128,
  367. .dcache_bsize = 128,
  368. .num_pmcs = 6,
  369. .pmc_type = PPC_PMC_IBM,
  370. .oprofile_cpu_type = "ppc64/power5+",
  371. .oprofile_type = PPC_OPROFILE_POWER4,
  372. .oprofile_mmcra_sihv = MMCRA_SIHV,
  373. .oprofile_mmcra_sipr = MMCRA_SIPR,
  374. .platform = "power5+",
  375. },
  376. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  377. .pvr_mask = 0xffffffff,
  378. .pvr_value = 0x0f000001,
  379. .cpu_name = "POWER5+",
  380. .cpu_features = CPU_FTRS_POWER5,
  381. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  382. .mmu_features = MMU_FTRS_POWER5,
  383. .icache_bsize = 128,
  384. .dcache_bsize = 128,
  385. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  386. .oprofile_type = PPC_OPROFILE_POWER4,
  387. .platform = "power5+",
  388. },
  389. { /* Power6 */
  390. .pvr_mask = 0xffff0000,
  391. .pvr_value = 0x003e0000,
  392. .cpu_name = "POWER6 (raw)",
  393. .cpu_features = CPU_FTRS_POWER6,
  394. .cpu_user_features = COMMON_USER_POWER6 |
  395. PPC_FEATURE_POWER6_EXT,
  396. .mmu_features = MMU_FTRS_POWER6,
  397. .icache_bsize = 128,
  398. .dcache_bsize = 128,
  399. .num_pmcs = 6,
  400. .pmc_type = PPC_PMC_IBM,
  401. .oprofile_cpu_type = "ppc64/power6",
  402. .oprofile_type = PPC_OPROFILE_POWER4,
  403. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  404. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  405. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  406. POWER6_MMCRA_OTHER,
  407. .platform = "power6x",
  408. },
  409. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  410. .pvr_mask = 0xffffffff,
  411. .pvr_value = 0x0f000002,
  412. .cpu_name = "POWER6 (architected)",
  413. .cpu_features = CPU_FTRS_POWER6,
  414. .cpu_user_features = COMMON_USER_POWER6,
  415. .mmu_features = MMU_FTRS_POWER6,
  416. .icache_bsize = 128,
  417. .dcache_bsize = 128,
  418. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  419. .oprofile_type = PPC_OPROFILE_POWER4,
  420. .platform = "power6",
  421. },
  422. { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
  423. .pvr_mask = 0xffffffff,
  424. .pvr_value = 0x0f000003,
  425. .cpu_name = "POWER7 (architected)",
  426. .cpu_features = CPU_FTRS_POWER7,
  427. .cpu_user_features = COMMON_USER_POWER7,
  428. .cpu_user_features2 = COMMON_USER2_POWER7,
  429. .mmu_features = MMU_FTRS_POWER7,
  430. .icache_bsize = 128,
  431. .dcache_bsize = 128,
  432. .oprofile_type = PPC_OPROFILE_POWER4,
  433. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  434. .cpu_setup = __setup_cpu_power7,
  435. .cpu_restore = __restore_cpu_power7,
  436. .platform = "power7",
  437. },
  438. { /* 2.07-compliant processor, i.e. Power8 "architected" mode */
  439. .pvr_mask = 0xffffffff,
  440. .pvr_value = 0x0f000004,
  441. .cpu_name = "POWER8 (architected)",
  442. .cpu_features = CPU_FTRS_POWER8,
  443. .cpu_user_features = COMMON_USER_POWER8,
  444. .cpu_user_features2 = COMMON_USER2_POWER8,
  445. .mmu_features = MMU_FTRS_POWER8,
  446. .icache_bsize = 128,
  447. .dcache_bsize = 128,
  448. .oprofile_type = PPC_OPROFILE_INVALID,
  449. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  450. .cpu_setup = __setup_cpu_power8,
  451. .cpu_restore = __restore_cpu_power8,
  452. .platform = "power8",
  453. },
  454. { /* Power7 */
  455. .pvr_mask = 0xffff0000,
  456. .pvr_value = 0x003f0000,
  457. .cpu_name = "POWER7 (raw)",
  458. .cpu_features = CPU_FTRS_POWER7,
  459. .cpu_user_features = COMMON_USER_POWER7,
  460. .cpu_user_features2 = COMMON_USER2_POWER7,
  461. .mmu_features = MMU_FTRS_POWER7,
  462. .icache_bsize = 128,
  463. .dcache_bsize = 128,
  464. .num_pmcs = 6,
  465. .pmc_type = PPC_PMC_IBM,
  466. .oprofile_cpu_type = "ppc64/power7",
  467. .oprofile_type = PPC_OPROFILE_POWER4,
  468. .cpu_setup = __setup_cpu_power7,
  469. .cpu_restore = __restore_cpu_power7,
  470. .platform = "power7",
  471. },
  472. { /* Power7+ */
  473. .pvr_mask = 0xffff0000,
  474. .pvr_value = 0x004A0000,
  475. .cpu_name = "POWER7+ (raw)",
  476. .cpu_features = CPU_FTRS_POWER7,
  477. .cpu_user_features = COMMON_USER_POWER7,
  478. .cpu_user_features2 = COMMON_USER2_POWER7,
  479. .mmu_features = MMU_FTRS_POWER7,
  480. .icache_bsize = 128,
  481. .dcache_bsize = 128,
  482. .num_pmcs = 6,
  483. .pmc_type = PPC_PMC_IBM,
  484. .oprofile_cpu_type = "ppc64/power7",
  485. .oprofile_type = PPC_OPROFILE_POWER4,
  486. .cpu_setup = __setup_cpu_power7,
  487. .cpu_restore = __restore_cpu_power7,
  488. .platform = "power7+",
  489. },
  490. { /* Power8 */
  491. .pvr_mask = 0xffff0000,
  492. .pvr_value = 0x004b0000,
  493. .cpu_name = "POWER8 (raw)",
  494. .cpu_features = CPU_FTRS_POWER8,
  495. .cpu_user_features = COMMON_USER_POWER8,
  496. .cpu_user_features2 = COMMON_USER2_POWER8,
  497. .mmu_features = MMU_FTRS_POWER8,
  498. .icache_bsize = 128,
  499. .dcache_bsize = 128,
  500. .num_pmcs = 6,
  501. .pmc_type = PPC_PMC_IBM,
  502. .oprofile_cpu_type = "ppc64/power8",
  503. .oprofile_type = PPC_OPROFILE_INVALID,
  504. .cpu_setup = __setup_cpu_power8,
  505. .cpu_restore = __restore_cpu_power8,
  506. .platform = "power8",
  507. },
  508. { /* Cell Broadband Engine */
  509. .pvr_mask = 0xffff0000,
  510. .pvr_value = 0x00700000,
  511. .cpu_name = "Cell Broadband Engine",
  512. .cpu_features = CPU_FTRS_CELL,
  513. .cpu_user_features = COMMON_USER_PPC64 |
  514. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  515. PPC_FEATURE_SMT,
  516. .mmu_features = MMU_FTRS_CELL,
  517. .icache_bsize = 128,
  518. .dcache_bsize = 128,
  519. .num_pmcs = 4,
  520. .pmc_type = PPC_PMC_IBM,
  521. .oprofile_cpu_type = "ppc64/cell-be",
  522. .oprofile_type = PPC_OPROFILE_CELL,
  523. .platform = "ppc-cell-be",
  524. },
  525. { /* PA Semi PA6T */
  526. .pvr_mask = 0x7fff0000,
  527. .pvr_value = 0x00900000,
  528. .cpu_name = "PA6T",
  529. .cpu_features = CPU_FTRS_PA6T,
  530. .cpu_user_features = COMMON_USER_PA6T,
  531. .mmu_features = MMU_FTRS_PA6T,
  532. .icache_bsize = 64,
  533. .dcache_bsize = 64,
  534. .num_pmcs = 6,
  535. .pmc_type = PPC_PMC_PA6T,
  536. .cpu_setup = __setup_cpu_pa6t,
  537. .cpu_restore = __restore_cpu_pa6t,
  538. .oprofile_cpu_type = "ppc64/pa6t",
  539. .oprofile_type = PPC_OPROFILE_PA6T,
  540. .platform = "pa6t",
  541. },
  542. { /* default match */
  543. .pvr_mask = 0x00000000,
  544. .pvr_value = 0x00000000,
  545. .cpu_name = "POWER4 (compatible)",
  546. .cpu_features = CPU_FTRS_COMPATIBLE,
  547. .cpu_user_features = COMMON_USER_PPC64,
  548. .mmu_features = MMU_FTRS_DEFAULT_HPTE_ARCH_V2,
  549. .icache_bsize = 128,
  550. .dcache_bsize = 128,
  551. .num_pmcs = 6,
  552. .pmc_type = PPC_PMC_IBM,
  553. .platform = "power4",
  554. }
  555. #endif /* CONFIG_PPC_BOOK3S_64 */
  556. #ifdef CONFIG_PPC32
  557. #if CLASSIC_PPC
  558. { /* 601 */
  559. .pvr_mask = 0xffff0000,
  560. .pvr_value = 0x00010000,
  561. .cpu_name = "601",
  562. .cpu_features = CPU_FTRS_PPC601,
  563. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  564. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  565. .mmu_features = MMU_FTR_HPTE_TABLE,
  566. .icache_bsize = 32,
  567. .dcache_bsize = 32,
  568. .machine_check = machine_check_generic,
  569. .platform = "ppc601",
  570. },
  571. { /* 603 */
  572. .pvr_mask = 0xffff0000,
  573. .pvr_value = 0x00030000,
  574. .cpu_name = "603",
  575. .cpu_features = CPU_FTRS_603,
  576. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  577. .mmu_features = 0,
  578. .icache_bsize = 32,
  579. .dcache_bsize = 32,
  580. .cpu_setup = __setup_cpu_603,
  581. .machine_check = machine_check_generic,
  582. .platform = "ppc603",
  583. },
  584. { /* 603e */
  585. .pvr_mask = 0xffff0000,
  586. .pvr_value = 0x00060000,
  587. .cpu_name = "603e",
  588. .cpu_features = CPU_FTRS_603,
  589. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  590. .mmu_features = 0,
  591. .icache_bsize = 32,
  592. .dcache_bsize = 32,
  593. .cpu_setup = __setup_cpu_603,
  594. .machine_check = machine_check_generic,
  595. .platform = "ppc603",
  596. },
  597. { /* 603ev */
  598. .pvr_mask = 0xffff0000,
  599. .pvr_value = 0x00070000,
  600. .cpu_name = "603ev",
  601. .cpu_features = CPU_FTRS_603,
  602. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  603. .mmu_features = 0,
  604. .icache_bsize = 32,
  605. .dcache_bsize = 32,
  606. .cpu_setup = __setup_cpu_603,
  607. .machine_check = machine_check_generic,
  608. .platform = "ppc603",
  609. },
  610. { /* 604 */
  611. .pvr_mask = 0xffff0000,
  612. .pvr_value = 0x00040000,
  613. .cpu_name = "604",
  614. .cpu_features = CPU_FTRS_604,
  615. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  616. .mmu_features = MMU_FTR_HPTE_TABLE,
  617. .icache_bsize = 32,
  618. .dcache_bsize = 32,
  619. .num_pmcs = 2,
  620. .cpu_setup = __setup_cpu_604,
  621. .machine_check = machine_check_generic,
  622. .platform = "ppc604",
  623. },
  624. { /* 604e */
  625. .pvr_mask = 0xfffff000,
  626. .pvr_value = 0x00090000,
  627. .cpu_name = "604e",
  628. .cpu_features = CPU_FTRS_604,
  629. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  630. .mmu_features = MMU_FTR_HPTE_TABLE,
  631. .icache_bsize = 32,
  632. .dcache_bsize = 32,
  633. .num_pmcs = 4,
  634. .cpu_setup = __setup_cpu_604,
  635. .machine_check = machine_check_generic,
  636. .platform = "ppc604",
  637. },
  638. { /* 604r */
  639. .pvr_mask = 0xffff0000,
  640. .pvr_value = 0x00090000,
  641. .cpu_name = "604r",
  642. .cpu_features = CPU_FTRS_604,
  643. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  644. .mmu_features = MMU_FTR_HPTE_TABLE,
  645. .icache_bsize = 32,
  646. .dcache_bsize = 32,
  647. .num_pmcs = 4,
  648. .cpu_setup = __setup_cpu_604,
  649. .machine_check = machine_check_generic,
  650. .platform = "ppc604",
  651. },
  652. { /* 604ev */
  653. .pvr_mask = 0xffff0000,
  654. .pvr_value = 0x000a0000,
  655. .cpu_name = "604ev",
  656. .cpu_features = CPU_FTRS_604,
  657. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  658. .mmu_features = MMU_FTR_HPTE_TABLE,
  659. .icache_bsize = 32,
  660. .dcache_bsize = 32,
  661. .num_pmcs = 4,
  662. .cpu_setup = __setup_cpu_604,
  663. .machine_check = machine_check_generic,
  664. .platform = "ppc604",
  665. },
  666. { /* 740/750 (0x4202, don't support TAU ?) */
  667. .pvr_mask = 0xffffffff,
  668. .pvr_value = 0x00084202,
  669. .cpu_name = "740/750",
  670. .cpu_features = CPU_FTRS_740_NOTAU,
  671. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  672. .mmu_features = MMU_FTR_HPTE_TABLE,
  673. .icache_bsize = 32,
  674. .dcache_bsize = 32,
  675. .num_pmcs = 4,
  676. .cpu_setup = __setup_cpu_750,
  677. .machine_check = machine_check_generic,
  678. .platform = "ppc750",
  679. },
  680. { /* 750CX (80100 and 8010x?) */
  681. .pvr_mask = 0xfffffff0,
  682. .pvr_value = 0x00080100,
  683. .cpu_name = "750CX",
  684. .cpu_features = CPU_FTRS_750,
  685. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  686. .mmu_features = MMU_FTR_HPTE_TABLE,
  687. .icache_bsize = 32,
  688. .dcache_bsize = 32,
  689. .num_pmcs = 4,
  690. .cpu_setup = __setup_cpu_750cx,
  691. .machine_check = machine_check_generic,
  692. .platform = "ppc750",
  693. },
  694. { /* 750CX (82201 and 82202) */
  695. .pvr_mask = 0xfffffff0,
  696. .pvr_value = 0x00082200,
  697. .cpu_name = "750CX",
  698. .cpu_features = CPU_FTRS_750,
  699. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  700. .mmu_features = MMU_FTR_HPTE_TABLE,
  701. .icache_bsize = 32,
  702. .dcache_bsize = 32,
  703. .num_pmcs = 4,
  704. .pmc_type = PPC_PMC_IBM,
  705. .cpu_setup = __setup_cpu_750cx,
  706. .machine_check = machine_check_generic,
  707. .platform = "ppc750",
  708. },
  709. { /* 750CXe (82214) */
  710. .pvr_mask = 0xfffffff0,
  711. .pvr_value = 0x00082210,
  712. .cpu_name = "750CXe",
  713. .cpu_features = CPU_FTRS_750,
  714. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  715. .mmu_features = MMU_FTR_HPTE_TABLE,
  716. .icache_bsize = 32,
  717. .dcache_bsize = 32,
  718. .num_pmcs = 4,
  719. .pmc_type = PPC_PMC_IBM,
  720. .cpu_setup = __setup_cpu_750cx,
  721. .machine_check = machine_check_generic,
  722. .platform = "ppc750",
  723. },
  724. { /* 750CXe "Gekko" (83214) */
  725. .pvr_mask = 0xffffffff,
  726. .pvr_value = 0x00083214,
  727. .cpu_name = "750CXe",
  728. .cpu_features = CPU_FTRS_750,
  729. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  730. .mmu_features = MMU_FTR_HPTE_TABLE,
  731. .icache_bsize = 32,
  732. .dcache_bsize = 32,
  733. .num_pmcs = 4,
  734. .pmc_type = PPC_PMC_IBM,
  735. .cpu_setup = __setup_cpu_750cx,
  736. .machine_check = machine_check_generic,
  737. .platform = "ppc750",
  738. },
  739. { /* 750CL (and "Broadway") */
  740. .pvr_mask = 0xfffff0e0,
  741. .pvr_value = 0x00087000,
  742. .cpu_name = "750CL",
  743. .cpu_features = CPU_FTRS_750CL,
  744. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  745. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  746. .icache_bsize = 32,
  747. .dcache_bsize = 32,
  748. .num_pmcs = 4,
  749. .pmc_type = PPC_PMC_IBM,
  750. .cpu_setup = __setup_cpu_750,
  751. .machine_check = machine_check_generic,
  752. .platform = "ppc750",
  753. .oprofile_cpu_type = "ppc/750",
  754. .oprofile_type = PPC_OPROFILE_G4,
  755. },
  756. { /* 745/755 */
  757. .pvr_mask = 0xfffff000,
  758. .pvr_value = 0x00083000,
  759. .cpu_name = "745/755",
  760. .cpu_features = CPU_FTRS_750,
  761. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  762. .mmu_features = MMU_FTR_HPTE_TABLE,
  763. .icache_bsize = 32,
  764. .dcache_bsize = 32,
  765. .num_pmcs = 4,
  766. .pmc_type = PPC_PMC_IBM,
  767. .cpu_setup = __setup_cpu_750,
  768. .machine_check = machine_check_generic,
  769. .platform = "ppc750",
  770. },
  771. { /* 750FX rev 1.x */
  772. .pvr_mask = 0xffffff00,
  773. .pvr_value = 0x70000100,
  774. .cpu_name = "750FX",
  775. .cpu_features = CPU_FTRS_750FX1,
  776. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  777. .mmu_features = MMU_FTR_HPTE_TABLE,
  778. .icache_bsize = 32,
  779. .dcache_bsize = 32,
  780. .num_pmcs = 4,
  781. .pmc_type = PPC_PMC_IBM,
  782. .cpu_setup = __setup_cpu_750,
  783. .machine_check = machine_check_generic,
  784. .platform = "ppc750",
  785. .oprofile_cpu_type = "ppc/750",
  786. .oprofile_type = PPC_OPROFILE_G4,
  787. },
  788. { /* 750FX rev 2.0 must disable HID0[DPM] */
  789. .pvr_mask = 0xffffffff,
  790. .pvr_value = 0x70000200,
  791. .cpu_name = "750FX",
  792. .cpu_features = CPU_FTRS_750FX2,
  793. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  794. .mmu_features = MMU_FTR_HPTE_TABLE,
  795. .icache_bsize = 32,
  796. .dcache_bsize = 32,
  797. .num_pmcs = 4,
  798. .pmc_type = PPC_PMC_IBM,
  799. .cpu_setup = __setup_cpu_750,
  800. .machine_check = machine_check_generic,
  801. .platform = "ppc750",
  802. .oprofile_cpu_type = "ppc/750",
  803. .oprofile_type = PPC_OPROFILE_G4,
  804. },
  805. { /* 750FX (All revs except 2.0) */
  806. .pvr_mask = 0xffff0000,
  807. .pvr_value = 0x70000000,
  808. .cpu_name = "750FX",
  809. .cpu_features = CPU_FTRS_750FX,
  810. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  811. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  812. .icache_bsize = 32,
  813. .dcache_bsize = 32,
  814. .num_pmcs = 4,
  815. .pmc_type = PPC_PMC_IBM,
  816. .cpu_setup = __setup_cpu_750fx,
  817. .machine_check = machine_check_generic,
  818. .platform = "ppc750",
  819. .oprofile_cpu_type = "ppc/750",
  820. .oprofile_type = PPC_OPROFILE_G4,
  821. },
  822. { /* 750GX */
  823. .pvr_mask = 0xffff0000,
  824. .pvr_value = 0x70020000,
  825. .cpu_name = "750GX",
  826. .cpu_features = CPU_FTRS_750GX,
  827. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  828. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  829. .icache_bsize = 32,
  830. .dcache_bsize = 32,
  831. .num_pmcs = 4,
  832. .pmc_type = PPC_PMC_IBM,
  833. .cpu_setup = __setup_cpu_750fx,
  834. .machine_check = machine_check_generic,
  835. .platform = "ppc750",
  836. .oprofile_cpu_type = "ppc/750",
  837. .oprofile_type = PPC_OPROFILE_G4,
  838. },
  839. { /* 740/750 (L2CR bit need fixup for 740) */
  840. .pvr_mask = 0xffff0000,
  841. .pvr_value = 0x00080000,
  842. .cpu_name = "740/750",
  843. .cpu_features = CPU_FTRS_740,
  844. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  845. .mmu_features = MMU_FTR_HPTE_TABLE,
  846. .icache_bsize = 32,
  847. .dcache_bsize = 32,
  848. .num_pmcs = 4,
  849. .pmc_type = PPC_PMC_IBM,
  850. .cpu_setup = __setup_cpu_750,
  851. .machine_check = machine_check_generic,
  852. .platform = "ppc750",
  853. },
  854. { /* 7400 rev 1.1 ? (no TAU) */
  855. .pvr_mask = 0xffffffff,
  856. .pvr_value = 0x000c1101,
  857. .cpu_name = "7400 (1.1)",
  858. .cpu_features = CPU_FTRS_7400_NOTAU,
  859. .cpu_user_features = COMMON_USER |
  860. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  861. .mmu_features = MMU_FTR_HPTE_TABLE,
  862. .icache_bsize = 32,
  863. .dcache_bsize = 32,
  864. .num_pmcs = 4,
  865. .pmc_type = PPC_PMC_G4,
  866. .cpu_setup = __setup_cpu_7400,
  867. .machine_check = machine_check_generic,
  868. .platform = "ppc7400",
  869. },
  870. { /* 7400 */
  871. .pvr_mask = 0xffff0000,
  872. .pvr_value = 0x000c0000,
  873. .cpu_name = "7400",
  874. .cpu_features = CPU_FTRS_7400,
  875. .cpu_user_features = COMMON_USER |
  876. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  877. .mmu_features = MMU_FTR_HPTE_TABLE,
  878. .icache_bsize = 32,
  879. .dcache_bsize = 32,
  880. .num_pmcs = 4,
  881. .pmc_type = PPC_PMC_G4,
  882. .cpu_setup = __setup_cpu_7400,
  883. .machine_check = machine_check_generic,
  884. .platform = "ppc7400",
  885. },
  886. { /* 7410 */
  887. .pvr_mask = 0xffff0000,
  888. .pvr_value = 0x800c0000,
  889. .cpu_name = "7410",
  890. .cpu_features = CPU_FTRS_7400,
  891. .cpu_user_features = COMMON_USER |
  892. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  893. .mmu_features = MMU_FTR_HPTE_TABLE,
  894. .icache_bsize = 32,
  895. .dcache_bsize = 32,
  896. .num_pmcs = 4,
  897. .pmc_type = PPC_PMC_G4,
  898. .cpu_setup = __setup_cpu_7410,
  899. .machine_check = machine_check_generic,
  900. .platform = "ppc7400",
  901. },
  902. { /* 7450 2.0 - no doze/nap */
  903. .pvr_mask = 0xffffffff,
  904. .pvr_value = 0x80000200,
  905. .cpu_name = "7450",
  906. .cpu_features = CPU_FTRS_7450_20,
  907. .cpu_user_features = COMMON_USER |
  908. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  909. .mmu_features = MMU_FTR_HPTE_TABLE,
  910. .icache_bsize = 32,
  911. .dcache_bsize = 32,
  912. .num_pmcs = 6,
  913. .pmc_type = PPC_PMC_G4,
  914. .cpu_setup = __setup_cpu_745x,
  915. .oprofile_cpu_type = "ppc/7450",
  916. .oprofile_type = PPC_OPROFILE_G4,
  917. .machine_check = machine_check_generic,
  918. .platform = "ppc7450",
  919. },
  920. { /* 7450 2.1 */
  921. .pvr_mask = 0xffffffff,
  922. .pvr_value = 0x80000201,
  923. .cpu_name = "7450",
  924. .cpu_features = CPU_FTRS_7450_21,
  925. .cpu_user_features = COMMON_USER |
  926. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  927. .mmu_features = MMU_FTR_HPTE_TABLE,
  928. .icache_bsize = 32,
  929. .dcache_bsize = 32,
  930. .num_pmcs = 6,
  931. .pmc_type = PPC_PMC_G4,
  932. .cpu_setup = __setup_cpu_745x,
  933. .oprofile_cpu_type = "ppc/7450",
  934. .oprofile_type = PPC_OPROFILE_G4,
  935. .machine_check = machine_check_generic,
  936. .platform = "ppc7450",
  937. },
  938. { /* 7450 2.3 and newer */
  939. .pvr_mask = 0xffff0000,
  940. .pvr_value = 0x80000000,
  941. .cpu_name = "7450",
  942. .cpu_features = CPU_FTRS_7450_23,
  943. .cpu_user_features = COMMON_USER |
  944. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  945. .mmu_features = MMU_FTR_HPTE_TABLE,
  946. .icache_bsize = 32,
  947. .dcache_bsize = 32,
  948. .num_pmcs = 6,
  949. .pmc_type = PPC_PMC_G4,
  950. .cpu_setup = __setup_cpu_745x,
  951. .oprofile_cpu_type = "ppc/7450",
  952. .oprofile_type = PPC_OPROFILE_G4,
  953. .machine_check = machine_check_generic,
  954. .platform = "ppc7450",
  955. },
  956. { /* 7455 rev 1.x */
  957. .pvr_mask = 0xffffff00,
  958. .pvr_value = 0x80010100,
  959. .cpu_name = "7455",
  960. .cpu_features = CPU_FTRS_7455_1,
  961. .cpu_user_features = COMMON_USER |
  962. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  963. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  964. .icache_bsize = 32,
  965. .dcache_bsize = 32,
  966. .num_pmcs = 6,
  967. .pmc_type = PPC_PMC_G4,
  968. .cpu_setup = __setup_cpu_745x,
  969. .oprofile_cpu_type = "ppc/7450",
  970. .oprofile_type = PPC_OPROFILE_G4,
  971. .machine_check = machine_check_generic,
  972. .platform = "ppc7450",
  973. },
  974. { /* 7455 rev 2.0 */
  975. .pvr_mask = 0xffffffff,
  976. .pvr_value = 0x80010200,
  977. .cpu_name = "7455",
  978. .cpu_features = CPU_FTRS_7455_20,
  979. .cpu_user_features = COMMON_USER |
  980. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  981. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  982. .icache_bsize = 32,
  983. .dcache_bsize = 32,
  984. .num_pmcs = 6,
  985. .pmc_type = PPC_PMC_G4,
  986. .cpu_setup = __setup_cpu_745x,
  987. .oprofile_cpu_type = "ppc/7450",
  988. .oprofile_type = PPC_OPROFILE_G4,
  989. .machine_check = machine_check_generic,
  990. .platform = "ppc7450",
  991. },
  992. { /* 7455 others */
  993. .pvr_mask = 0xffff0000,
  994. .pvr_value = 0x80010000,
  995. .cpu_name = "7455",
  996. .cpu_features = CPU_FTRS_7455,
  997. .cpu_user_features = COMMON_USER |
  998. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  999. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1000. .icache_bsize = 32,
  1001. .dcache_bsize = 32,
  1002. .num_pmcs = 6,
  1003. .pmc_type = PPC_PMC_G4,
  1004. .cpu_setup = __setup_cpu_745x,
  1005. .oprofile_cpu_type = "ppc/7450",
  1006. .oprofile_type = PPC_OPROFILE_G4,
  1007. .machine_check = machine_check_generic,
  1008. .platform = "ppc7450",
  1009. },
  1010. { /* 7447/7457 Rev 1.0 */
  1011. .pvr_mask = 0xffffffff,
  1012. .pvr_value = 0x80020100,
  1013. .cpu_name = "7447/7457",
  1014. .cpu_features = CPU_FTRS_7447_10,
  1015. .cpu_user_features = COMMON_USER |
  1016. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1017. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1018. .icache_bsize = 32,
  1019. .dcache_bsize = 32,
  1020. .num_pmcs = 6,
  1021. .pmc_type = PPC_PMC_G4,
  1022. .cpu_setup = __setup_cpu_745x,
  1023. .oprofile_cpu_type = "ppc/7450",
  1024. .oprofile_type = PPC_OPROFILE_G4,
  1025. .machine_check = machine_check_generic,
  1026. .platform = "ppc7450",
  1027. },
  1028. { /* 7447/7457 Rev 1.1 */
  1029. .pvr_mask = 0xffffffff,
  1030. .pvr_value = 0x80020101,
  1031. .cpu_name = "7447/7457",
  1032. .cpu_features = CPU_FTRS_7447_10,
  1033. .cpu_user_features = COMMON_USER |
  1034. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1035. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1036. .icache_bsize = 32,
  1037. .dcache_bsize = 32,
  1038. .num_pmcs = 6,
  1039. .pmc_type = PPC_PMC_G4,
  1040. .cpu_setup = __setup_cpu_745x,
  1041. .oprofile_cpu_type = "ppc/7450",
  1042. .oprofile_type = PPC_OPROFILE_G4,
  1043. .machine_check = machine_check_generic,
  1044. .platform = "ppc7450",
  1045. },
  1046. { /* 7447/7457 Rev 1.2 and later */
  1047. .pvr_mask = 0xffff0000,
  1048. .pvr_value = 0x80020000,
  1049. .cpu_name = "7447/7457",
  1050. .cpu_features = CPU_FTRS_7447,
  1051. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1052. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1053. .icache_bsize = 32,
  1054. .dcache_bsize = 32,
  1055. .num_pmcs = 6,
  1056. .pmc_type = PPC_PMC_G4,
  1057. .cpu_setup = __setup_cpu_745x,
  1058. .oprofile_cpu_type = "ppc/7450",
  1059. .oprofile_type = PPC_OPROFILE_G4,
  1060. .machine_check = machine_check_generic,
  1061. .platform = "ppc7450",
  1062. },
  1063. { /* 7447A */
  1064. .pvr_mask = 0xffff0000,
  1065. .pvr_value = 0x80030000,
  1066. .cpu_name = "7447A",
  1067. .cpu_features = CPU_FTRS_7447A,
  1068. .cpu_user_features = COMMON_USER |
  1069. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1070. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1071. .icache_bsize = 32,
  1072. .dcache_bsize = 32,
  1073. .num_pmcs = 6,
  1074. .pmc_type = PPC_PMC_G4,
  1075. .cpu_setup = __setup_cpu_745x,
  1076. .oprofile_cpu_type = "ppc/7450",
  1077. .oprofile_type = PPC_OPROFILE_G4,
  1078. .machine_check = machine_check_generic,
  1079. .platform = "ppc7450",
  1080. },
  1081. { /* 7448 */
  1082. .pvr_mask = 0xffff0000,
  1083. .pvr_value = 0x80040000,
  1084. .cpu_name = "7448",
  1085. .cpu_features = CPU_FTRS_7448,
  1086. .cpu_user_features = COMMON_USER |
  1087. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1088. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1089. .icache_bsize = 32,
  1090. .dcache_bsize = 32,
  1091. .num_pmcs = 6,
  1092. .pmc_type = PPC_PMC_G4,
  1093. .cpu_setup = __setup_cpu_745x,
  1094. .oprofile_cpu_type = "ppc/7450",
  1095. .oprofile_type = PPC_OPROFILE_G4,
  1096. .machine_check = machine_check_generic,
  1097. .platform = "ppc7450",
  1098. },
  1099. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  1100. .pvr_mask = 0x7fff0000,
  1101. .pvr_value = 0x00810000,
  1102. .cpu_name = "82xx",
  1103. .cpu_features = CPU_FTRS_82XX,
  1104. .cpu_user_features = COMMON_USER,
  1105. .mmu_features = 0,
  1106. .icache_bsize = 32,
  1107. .dcache_bsize = 32,
  1108. .cpu_setup = __setup_cpu_603,
  1109. .machine_check = machine_check_generic,
  1110. .platform = "ppc603",
  1111. },
  1112. { /* All G2_LE (603e core, plus some) have the same pvr */
  1113. .pvr_mask = 0x7fff0000,
  1114. .pvr_value = 0x00820000,
  1115. .cpu_name = "G2_LE",
  1116. .cpu_features = CPU_FTRS_G2_LE,
  1117. .cpu_user_features = COMMON_USER,
  1118. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1119. .icache_bsize = 32,
  1120. .dcache_bsize = 32,
  1121. .cpu_setup = __setup_cpu_603,
  1122. .machine_check = machine_check_generic,
  1123. .platform = "ppc603",
  1124. },
  1125. { /* e300c1 (a 603e core, plus some) on 83xx */
  1126. .pvr_mask = 0x7fff0000,
  1127. .pvr_value = 0x00830000,
  1128. .cpu_name = "e300c1",
  1129. .cpu_features = CPU_FTRS_E300,
  1130. .cpu_user_features = COMMON_USER,
  1131. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1132. .icache_bsize = 32,
  1133. .dcache_bsize = 32,
  1134. .cpu_setup = __setup_cpu_603,
  1135. .machine_check = machine_check_generic,
  1136. .platform = "ppc603",
  1137. },
  1138. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  1139. .pvr_mask = 0x7fff0000,
  1140. .pvr_value = 0x00840000,
  1141. .cpu_name = "e300c2",
  1142. .cpu_features = CPU_FTRS_E300C2,
  1143. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1144. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1145. MMU_FTR_NEED_DTLB_SW_LRU,
  1146. .icache_bsize = 32,
  1147. .dcache_bsize = 32,
  1148. .cpu_setup = __setup_cpu_603,
  1149. .machine_check = machine_check_generic,
  1150. .platform = "ppc603",
  1151. },
  1152. { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
  1153. .pvr_mask = 0x7fff0000,
  1154. .pvr_value = 0x00850000,
  1155. .cpu_name = "e300c3",
  1156. .cpu_features = CPU_FTRS_E300,
  1157. .cpu_user_features = COMMON_USER,
  1158. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1159. MMU_FTR_NEED_DTLB_SW_LRU,
  1160. .icache_bsize = 32,
  1161. .dcache_bsize = 32,
  1162. .cpu_setup = __setup_cpu_603,
  1163. .num_pmcs = 4,
  1164. .oprofile_cpu_type = "ppc/e300",
  1165. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1166. .platform = "ppc603",
  1167. },
  1168. { /* e300c4 (e300c1, plus one IU) */
  1169. .pvr_mask = 0x7fff0000,
  1170. .pvr_value = 0x00860000,
  1171. .cpu_name = "e300c4",
  1172. .cpu_features = CPU_FTRS_E300,
  1173. .cpu_user_features = COMMON_USER,
  1174. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1175. MMU_FTR_NEED_DTLB_SW_LRU,
  1176. .icache_bsize = 32,
  1177. .dcache_bsize = 32,
  1178. .cpu_setup = __setup_cpu_603,
  1179. .machine_check = machine_check_generic,
  1180. .num_pmcs = 4,
  1181. .oprofile_cpu_type = "ppc/e300",
  1182. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1183. .platform = "ppc603",
  1184. },
  1185. { /* default match, we assume split I/D cache & TB (non-601)... */
  1186. .pvr_mask = 0x00000000,
  1187. .pvr_value = 0x00000000,
  1188. .cpu_name = "(generic PPC)",
  1189. .cpu_features = CPU_FTRS_CLASSIC32,
  1190. .cpu_user_features = COMMON_USER,
  1191. .mmu_features = MMU_FTR_HPTE_TABLE,
  1192. .icache_bsize = 32,
  1193. .dcache_bsize = 32,
  1194. .machine_check = machine_check_generic,
  1195. .platform = "ppc603",
  1196. },
  1197. #endif /* CLASSIC_PPC */
  1198. #ifdef CONFIG_8xx
  1199. { /* 8xx */
  1200. .pvr_mask = 0xffff0000,
  1201. .pvr_value = 0x00500000,
  1202. .cpu_name = "8xx",
  1203. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  1204. * if the 8xx code is there.... */
  1205. .cpu_features = CPU_FTRS_8XX,
  1206. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1207. .mmu_features = MMU_FTR_TYPE_8xx,
  1208. .icache_bsize = 16,
  1209. .dcache_bsize = 16,
  1210. .platform = "ppc823",
  1211. },
  1212. #endif /* CONFIG_8xx */
  1213. #ifdef CONFIG_40x
  1214. { /* 403GC */
  1215. .pvr_mask = 0xffffff00,
  1216. .pvr_value = 0x00200200,
  1217. .cpu_name = "403GC",
  1218. .cpu_features = CPU_FTRS_40X,
  1219. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1220. .mmu_features = MMU_FTR_TYPE_40x,
  1221. .icache_bsize = 16,
  1222. .dcache_bsize = 16,
  1223. .machine_check = machine_check_4xx,
  1224. .platform = "ppc403",
  1225. },
  1226. { /* 403GCX */
  1227. .pvr_mask = 0xffffff00,
  1228. .pvr_value = 0x00201400,
  1229. .cpu_name = "403GCX",
  1230. .cpu_features = CPU_FTRS_40X,
  1231. .cpu_user_features = PPC_FEATURE_32 |
  1232. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  1233. .mmu_features = MMU_FTR_TYPE_40x,
  1234. .icache_bsize = 16,
  1235. .dcache_bsize = 16,
  1236. .machine_check = machine_check_4xx,
  1237. .platform = "ppc403",
  1238. },
  1239. { /* 403G ?? */
  1240. .pvr_mask = 0xffff0000,
  1241. .pvr_value = 0x00200000,
  1242. .cpu_name = "403G ??",
  1243. .cpu_features = CPU_FTRS_40X,
  1244. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1245. .mmu_features = MMU_FTR_TYPE_40x,
  1246. .icache_bsize = 16,
  1247. .dcache_bsize = 16,
  1248. .machine_check = machine_check_4xx,
  1249. .platform = "ppc403",
  1250. },
  1251. { /* 405GP */
  1252. .pvr_mask = 0xffff0000,
  1253. .pvr_value = 0x40110000,
  1254. .cpu_name = "405GP",
  1255. .cpu_features = CPU_FTRS_40X,
  1256. .cpu_user_features = PPC_FEATURE_32 |
  1257. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1258. .mmu_features = MMU_FTR_TYPE_40x,
  1259. .icache_bsize = 32,
  1260. .dcache_bsize = 32,
  1261. .machine_check = machine_check_4xx,
  1262. .platform = "ppc405",
  1263. },
  1264. { /* STB 03xxx */
  1265. .pvr_mask = 0xffff0000,
  1266. .pvr_value = 0x40130000,
  1267. .cpu_name = "STB03xxx",
  1268. .cpu_features = CPU_FTRS_40X,
  1269. .cpu_user_features = PPC_FEATURE_32 |
  1270. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1271. .mmu_features = MMU_FTR_TYPE_40x,
  1272. .icache_bsize = 32,
  1273. .dcache_bsize = 32,
  1274. .machine_check = machine_check_4xx,
  1275. .platform = "ppc405",
  1276. },
  1277. { /* STB 04xxx */
  1278. .pvr_mask = 0xffff0000,
  1279. .pvr_value = 0x41810000,
  1280. .cpu_name = "STB04xxx",
  1281. .cpu_features = CPU_FTRS_40X,
  1282. .cpu_user_features = PPC_FEATURE_32 |
  1283. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1284. .mmu_features = MMU_FTR_TYPE_40x,
  1285. .icache_bsize = 32,
  1286. .dcache_bsize = 32,
  1287. .machine_check = machine_check_4xx,
  1288. .platform = "ppc405",
  1289. },
  1290. { /* NP405L */
  1291. .pvr_mask = 0xffff0000,
  1292. .pvr_value = 0x41610000,
  1293. .cpu_name = "NP405L",
  1294. .cpu_features = CPU_FTRS_40X,
  1295. .cpu_user_features = PPC_FEATURE_32 |
  1296. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1297. .mmu_features = MMU_FTR_TYPE_40x,
  1298. .icache_bsize = 32,
  1299. .dcache_bsize = 32,
  1300. .machine_check = machine_check_4xx,
  1301. .platform = "ppc405",
  1302. },
  1303. { /* NP4GS3 */
  1304. .pvr_mask = 0xffff0000,
  1305. .pvr_value = 0x40B10000,
  1306. .cpu_name = "NP4GS3",
  1307. .cpu_features = CPU_FTRS_40X,
  1308. .cpu_user_features = PPC_FEATURE_32 |
  1309. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1310. .mmu_features = MMU_FTR_TYPE_40x,
  1311. .icache_bsize = 32,
  1312. .dcache_bsize = 32,
  1313. .machine_check = machine_check_4xx,
  1314. .platform = "ppc405",
  1315. },
  1316. { /* NP405H */
  1317. .pvr_mask = 0xffff0000,
  1318. .pvr_value = 0x41410000,
  1319. .cpu_name = "NP405H",
  1320. .cpu_features = CPU_FTRS_40X,
  1321. .cpu_user_features = PPC_FEATURE_32 |
  1322. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1323. .mmu_features = MMU_FTR_TYPE_40x,
  1324. .icache_bsize = 32,
  1325. .dcache_bsize = 32,
  1326. .machine_check = machine_check_4xx,
  1327. .platform = "ppc405",
  1328. },
  1329. { /* 405GPr */
  1330. .pvr_mask = 0xffff0000,
  1331. .pvr_value = 0x50910000,
  1332. .cpu_name = "405GPr",
  1333. .cpu_features = CPU_FTRS_40X,
  1334. .cpu_user_features = PPC_FEATURE_32 |
  1335. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1336. .mmu_features = MMU_FTR_TYPE_40x,
  1337. .icache_bsize = 32,
  1338. .dcache_bsize = 32,
  1339. .machine_check = machine_check_4xx,
  1340. .platform = "ppc405",
  1341. },
  1342. { /* STBx25xx */
  1343. .pvr_mask = 0xffff0000,
  1344. .pvr_value = 0x51510000,
  1345. .cpu_name = "STBx25xx",
  1346. .cpu_features = CPU_FTRS_40X,
  1347. .cpu_user_features = PPC_FEATURE_32 |
  1348. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1349. .mmu_features = MMU_FTR_TYPE_40x,
  1350. .icache_bsize = 32,
  1351. .dcache_bsize = 32,
  1352. .machine_check = machine_check_4xx,
  1353. .platform = "ppc405",
  1354. },
  1355. { /* 405LP */
  1356. .pvr_mask = 0xffff0000,
  1357. .pvr_value = 0x41F10000,
  1358. .cpu_name = "405LP",
  1359. .cpu_features = CPU_FTRS_40X,
  1360. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1361. .mmu_features = MMU_FTR_TYPE_40x,
  1362. .icache_bsize = 32,
  1363. .dcache_bsize = 32,
  1364. .machine_check = machine_check_4xx,
  1365. .platform = "ppc405",
  1366. },
  1367. { /* Xilinx Virtex-II Pro */
  1368. .pvr_mask = 0xfffff000,
  1369. .pvr_value = 0x20010000,
  1370. .cpu_name = "Virtex-II Pro",
  1371. .cpu_features = CPU_FTRS_40X,
  1372. .cpu_user_features = PPC_FEATURE_32 |
  1373. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1374. .mmu_features = MMU_FTR_TYPE_40x,
  1375. .icache_bsize = 32,
  1376. .dcache_bsize = 32,
  1377. .machine_check = machine_check_4xx,
  1378. .platform = "ppc405",
  1379. },
  1380. { /* Xilinx Virtex-4 FX */
  1381. .pvr_mask = 0xfffff000,
  1382. .pvr_value = 0x20011000,
  1383. .cpu_name = "Virtex-4 FX",
  1384. .cpu_features = CPU_FTRS_40X,
  1385. .cpu_user_features = PPC_FEATURE_32 |
  1386. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1387. .mmu_features = MMU_FTR_TYPE_40x,
  1388. .icache_bsize = 32,
  1389. .dcache_bsize = 32,
  1390. .machine_check = machine_check_4xx,
  1391. .platform = "ppc405",
  1392. },
  1393. { /* 405EP */
  1394. .pvr_mask = 0xffff0000,
  1395. .pvr_value = 0x51210000,
  1396. .cpu_name = "405EP",
  1397. .cpu_features = CPU_FTRS_40X,
  1398. .cpu_user_features = PPC_FEATURE_32 |
  1399. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1400. .mmu_features = MMU_FTR_TYPE_40x,
  1401. .icache_bsize = 32,
  1402. .dcache_bsize = 32,
  1403. .machine_check = machine_check_4xx,
  1404. .platform = "ppc405",
  1405. },
  1406. { /* 405EX Rev. A/B with Security */
  1407. .pvr_mask = 0xffff000f,
  1408. .pvr_value = 0x12910007,
  1409. .cpu_name = "405EX Rev. A/B",
  1410. .cpu_features = CPU_FTRS_40X,
  1411. .cpu_user_features = PPC_FEATURE_32 |
  1412. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1413. .mmu_features = MMU_FTR_TYPE_40x,
  1414. .icache_bsize = 32,
  1415. .dcache_bsize = 32,
  1416. .machine_check = machine_check_4xx,
  1417. .platform = "ppc405",
  1418. },
  1419. { /* 405EX Rev. C without Security */
  1420. .pvr_mask = 0xffff000f,
  1421. .pvr_value = 0x1291000d,
  1422. .cpu_name = "405EX Rev. C",
  1423. .cpu_features = CPU_FTRS_40X,
  1424. .cpu_user_features = PPC_FEATURE_32 |
  1425. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1426. .mmu_features = MMU_FTR_TYPE_40x,
  1427. .icache_bsize = 32,
  1428. .dcache_bsize = 32,
  1429. .machine_check = machine_check_4xx,
  1430. .platform = "ppc405",
  1431. },
  1432. { /* 405EX Rev. C with Security */
  1433. .pvr_mask = 0xffff000f,
  1434. .pvr_value = 0x1291000f,
  1435. .cpu_name = "405EX Rev. C",
  1436. .cpu_features = CPU_FTRS_40X,
  1437. .cpu_user_features = PPC_FEATURE_32 |
  1438. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1439. .mmu_features = MMU_FTR_TYPE_40x,
  1440. .icache_bsize = 32,
  1441. .dcache_bsize = 32,
  1442. .machine_check = machine_check_4xx,
  1443. .platform = "ppc405",
  1444. },
  1445. { /* 405EX Rev. D without Security */
  1446. .pvr_mask = 0xffff000f,
  1447. .pvr_value = 0x12910003,
  1448. .cpu_name = "405EX Rev. D",
  1449. .cpu_features = CPU_FTRS_40X,
  1450. .cpu_user_features = PPC_FEATURE_32 |
  1451. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1452. .mmu_features = MMU_FTR_TYPE_40x,
  1453. .icache_bsize = 32,
  1454. .dcache_bsize = 32,
  1455. .machine_check = machine_check_4xx,
  1456. .platform = "ppc405",
  1457. },
  1458. { /* 405EX Rev. D with Security */
  1459. .pvr_mask = 0xffff000f,
  1460. .pvr_value = 0x12910005,
  1461. .cpu_name = "405EX Rev. D",
  1462. .cpu_features = CPU_FTRS_40X,
  1463. .cpu_user_features = PPC_FEATURE_32 |
  1464. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1465. .mmu_features = MMU_FTR_TYPE_40x,
  1466. .icache_bsize = 32,
  1467. .dcache_bsize = 32,
  1468. .machine_check = machine_check_4xx,
  1469. .platform = "ppc405",
  1470. },
  1471. { /* 405EXr Rev. A/B without Security */
  1472. .pvr_mask = 0xffff000f,
  1473. .pvr_value = 0x12910001,
  1474. .cpu_name = "405EXr Rev. A/B",
  1475. .cpu_features = CPU_FTRS_40X,
  1476. .cpu_user_features = PPC_FEATURE_32 |
  1477. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1478. .mmu_features = MMU_FTR_TYPE_40x,
  1479. .icache_bsize = 32,
  1480. .dcache_bsize = 32,
  1481. .machine_check = machine_check_4xx,
  1482. .platform = "ppc405",
  1483. },
  1484. { /* 405EXr Rev. C without Security */
  1485. .pvr_mask = 0xffff000f,
  1486. .pvr_value = 0x12910009,
  1487. .cpu_name = "405EXr Rev. C",
  1488. .cpu_features = CPU_FTRS_40X,
  1489. .cpu_user_features = PPC_FEATURE_32 |
  1490. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1491. .mmu_features = MMU_FTR_TYPE_40x,
  1492. .icache_bsize = 32,
  1493. .dcache_bsize = 32,
  1494. .machine_check = machine_check_4xx,
  1495. .platform = "ppc405",
  1496. },
  1497. { /* 405EXr Rev. C with Security */
  1498. .pvr_mask = 0xffff000f,
  1499. .pvr_value = 0x1291000b,
  1500. .cpu_name = "405EXr Rev. C",
  1501. .cpu_features = CPU_FTRS_40X,
  1502. .cpu_user_features = PPC_FEATURE_32 |
  1503. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1504. .mmu_features = MMU_FTR_TYPE_40x,
  1505. .icache_bsize = 32,
  1506. .dcache_bsize = 32,
  1507. .machine_check = machine_check_4xx,
  1508. .platform = "ppc405",
  1509. },
  1510. { /* 405EXr Rev. D without Security */
  1511. .pvr_mask = 0xffff000f,
  1512. .pvr_value = 0x12910000,
  1513. .cpu_name = "405EXr Rev. D",
  1514. .cpu_features = CPU_FTRS_40X,
  1515. .cpu_user_features = PPC_FEATURE_32 |
  1516. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1517. .mmu_features = MMU_FTR_TYPE_40x,
  1518. .icache_bsize = 32,
  1519. .dcache_bsize = 32,
  1520. .machine_check = machine_check_4xx,
  1521. .platform = "ppc405",
  1522. },
  1523. { /* 405EXr Rev. D with Security */
  1524. .pvr_mask = 0xffff000f,
  1525. .pvr_value = 0x12910002,
  1526. .cpu_name = "405EXr Rev. D",
  1527. .cpu_features = CPU_FTRS_40X,
  1528. .cpu_user_features = PPC_FEATURE_32 |
  1529. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1530. .mmu_features = MMU_FTR_TYPE_40x,
  1531. .icache_bsize = 32,
  1532. .dcache_bsize = 32,
  1533. .machine_check = machine_check_4xx,
  1534. .platform = "ppc405",
  1535. },
  1536. {
  1537. /* 405EZ */
  1538. .pvr_mask = 0xffff0000,
  1539. .pvr_value = 0x41510000,
  1540. .cpu_name = "405EZ",
  1541. .cpu_features = CPU_FTRS_40X,
  1542. .cpu_user_features = PPC_FEATURE_32 |
  1543. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1544. .mmu_features = MMU_FTR_TYPE_40x,
  1545. .icache_bsize = 32,
  1546. .dcache_bsize = 32,
  1547. .machine_check = machine_check_4xx,
  1548. .platform = "ppc405",
  1549. },
  1550. { /* APM8018X */
  1551. .pvr_mask = 0xffff0000,
  1552. .pvr_value = 0x7ff11432,
  1553. .cpu_name = "APM8018X",
  1554. .cpu_features = CPU_FTRS_40X,
  1555. .cpu_user_features = PPC_FEATURE_32 |
  1556. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1557. .mmu_features = MMU_FTR_TYPE_40x,
  1558. .icache_bsize = 32,
  1559. .dcache_bsize = 32,
  1560. .machine_check = machine_check_4xx,
  1561. .platform = "ppc405",
  1562. },
  1563. { /* default match */
  1564. .pvr_mask = 0x00000000,
  1565. .pvr_value = 0x00000000,
  1566. .cpu_name = "(generic 40x PPC)",
  1567. .cpu_features = CPU_FTRS_40X,
  1568. .cpu_user_features = PPC_FEATURE_32 |
  1569. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1570. .mmu_features = MMU_FTR_TYPE_40x,
  1571. .icache_bsize = 32,
  1572. .dcache_bsize = 32,
  1573. .machine_check = machine_check_4xx,
  1574. .platform = "ppc405",
  1575. }
  1576. #endif /* CONFIG_40x */
  1577. #ifdef CONFIG_44x
  1578. {
  1579. .pvr_mask = 0xf0000fff,
  1580. .pvr_value = 0x40000850,
  1581. .cpu_name = "440GR Rev. A",
  1582. .cpu_features = CPU_FTRS_44X,
  1583. .cpu_user_features = COMMON_USER_BOOKE,
  1584. .mmu_features = MMU_FTR_TYPE_44x,
  1585. .icache_bsize = 32,
  1586. .dcache_bsize = 32,
  1587. .machine_check = machine_check_4xx,
  1588. .platform = "ppc440",
  1589. },
  1590. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1591. .pvr_mask = 0xf0000fff,
  1592. .pvr_value = 0x40000858,
  1593. .cpu_name = "440EP Rev. A",
  1594. .cpu_features = CPU_FTRS_44X,
  1595. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1596. .mmu_features = MMU_FTR_TYPE_44x,
  1597. .icache_bsize = 32,
  1598. .dcache_bsize = 32,
  1599. .cpu_setup = __setup_cpu_440ep,
  1600. .machine_check = machine_check_4xx,
  1601. .platform = "ppc440",
  1602. },
  1603. {
  1604. .pvr_mask = 0xf0000fff,
  1605. .pvr_value = 0x400008d3,
  1606. .cpu_name = "440GR Rev. B",
  1607. .cpu_features = CPU_FTRS_44X,
  1608. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1609. .mmu_features = MMU_FTR_TYPE_44x,
  1610. .icache_bsize = 32,
  1611. .dcache_bsize = 32,
  1612. .machine_check = machine_check_4xx,
  1613. .platform = "ppc440",
  1614. },
  1615. { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1616. .pvr_mask = 0xf0000ff7,
  1617. .pvr_value = 0x400008d4,
  1618. .cpu_name = "440EP Rev. C",
  1619. .cpu_features = CPU_FTRS_44X,
  1620. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1621. .mmu_features = MMU_FTR_TYPE_44x,
  1622. .icache_bsize = 32,
  1623. .dcache_bsize = 32,
  1624. .cpu_setup = __setup_cpu_440ep,
  1625. .machine_check = machine_check_4xx,
  1626. .platform = "ppc440",
  1627. },
  1628. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1629. .pvr_mask = 0xf0000fff,
  1630. .pvr_value = 0x400008db,
  1631. .cpu_name = "440EP Rev. B",
  1632. .cpu_features = CPU_FTRS_44X,
  1633. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1634. .mmu_features = MMU_FTR_TYPE_44x,
  1635. .icache_bsize = 32,
  1636. .dcache_bsize = 32,
  1637. .cpu_setup = __setup_cpu_440ep,
  1638. .machine_check = machine_check_4xx,
  1639. .platform = "ppc440",
  1640. },
  1641. { /* 440GRX */
  1642. .pvr_mask = 0xf0000ffb,
  1643. .pvr_value = 0x200008D0,
  1644. .cpu_name = "440GRX",
  1645. .cpu_features = CPU_FTRS_44X,
  1646. .cpu_user_features = COMMON_USER_BOOKE,
  1647. .mmu_features = MMU_FTR_TYPE_44x,
  1648. .icache_bsize = 32,
  1649. .dcache_bsize = 32,
  1650. .cpu_setup = __setup_cpu_440grx,
  1651. .machine_check = machine_check_440A,
  1652. .platform = "ppc440",
  1653. },
  1654. { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
  1655. .pvr_mask = 0xf0000ffb,
  1656. .pvr_value = 0x200008D8,
  1657. .cpu_name = "440EPX",
  1658. .cpu_features = CPU_FTRS_44X,
  1659. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1660. .mmu_features = MMU_FTR_TYPE_44x,
  1661. .icache_bsize = 32,
  1662. .dcache_bsize = 32,
  1663. .cpu_setup = __setup_cpu_440epx,
  1664. .machine_check = machine_check_440A,
  1665. .platform = "ppc440",
  1666. },
  1667. { /* 440GP Rev. B */
  1668. .pvr_mask = 0xf0000fff,
  1669. .pvr_value = 0x40000440,
  1670. .cpu_name = "440GP Rev. B",
  1671. .cpu_features = CPU_FTRS_44X,
  1672. .cpu_user_features = COMMON_USER_BOOKE,
  1673. .mmu_features = MMU_FTR_TYPE_44x,
  1674. .icache_bsize = 32,
  1675. .dcache_bsize = 32,
  1676. .machine_check = machine_check_4xx,
  1677. .platform = "ppc440gp",
  1678. },
  1679. { /* 440GP Rev. C */
  1680. .pvr_mask = 0xf0000fff,
  1681. .pvr_value = 0x40000481,
  1682. .cpu_name = "440GP Rev. C",
  1683. .cpu_features = CPU_FTRS_44X,
  1684. .cpu_user_features = COMMON_USER_BOOKE,
  1685. .mmu_features = MMU_FTR_TYPE_44x,
  1686. .icache_bsize = 32,
  1687. .dcache_bsize = 32,
  1688. .machine_check = machine_check_4xx,
  1689. .platform = "ppc440gp",
  1690. },
  1691. { /* 440GX Rev. A */
  1692. .pvr_mask = 0xf0000fff,
  1693. .pvr_value = 0x50000850,
  1694. .cpu_name = "440GX Rev. A",
  1695. .cpu_features = CPU_FTRS_44X,
  1696. .cpu_user_features = COMMON_USER_BOOKE,
  1697. .mmu_features = MMU_FTR_TYPE_44x,
  1698. .icache_bsize = 32,
  1699. .dcache_bsize = 32,
  1700. .cpu_setup = __setup_cpu_440gx,
  1701. .machine_check = machine_check_440A,
  1702. .platform = "ppc440",
  1703. },
  1704. { /* 440GX Rev. B */
  1705. .pvr_mask = 0xf0000fff,
  1706. .pvr_value = 0x50000851,
  1707. .cpu_name = "440GX Rev. B",
  1708. .cpu_features = CPU_FTRS_44X,
  1709. .cpu_user_features = COMMON_USER_BOOKE,
  1710. .mmu_features = MMU_FTR_TYPE_44x,
  1711. .icache_bsize = 32,
  1712. .dcache_bsize = 32,
  1713. .cpu_setup = __setup_cpu_440gx,
  1714. .machine_check = machine_check_440A,
  1715. .platform = "ppc440",
  1716. },
  1717. { /* 440GX Rev. C */
  1718. .pvr_mask = 0xf0000fff,
  1719. .pvr_value = 0x50000892,
  1720. .cpu_name = "440GX Rev. C",
  1721. .cpu_features = CPU_FTRS_44X,
  1722. .cpu_user_features = COMMON_USER_BOOKE,
  1723. .mmu_features = MMU_FTR_TYPE_44x,
  1724. .icache_bsize = 32,
  1725. .dcache_bsize = 32,
  1726. .cpu_setup = __setup_cpu_440gx,
  1727. .machine_check = machine_check_440A,
  1728. .platform = "ppc440",
  1729. },
  1730. { /* 440GX Rev. F */
  1731. .pvr_mask = 0xf0000fff,
  1732. .pvr_value = 0x50000894,
  1733. .cpu_name = "440GX Rev. F",
  1734. .cpu_features = CPU_FTRS_44X,
  1735. .cpu_user_features = COMMON_USER_BOOKE,
  1736. .mmu_features = MMU_FTR_TYPE_44x,
  1737. .icache_bsize = 32,
  1738. .dcache_bsize = 32,
  1739. .cpu_setup = __setup_cpu_440gx,
  1740. .machine_check = machine_check_440A,
  1741. .platform = "ppc440",
  1742. },
  1743. { /* 440SP Rev. A */
  1744. .pvr_mask = 0xfff00fff,
  1745. .pvr_value = 0x53200891,
  1746. .cpu_name = "440SP Rev. A",
  1747. .cpu_features = CPU_FTRS_44X,
  1748. .cpu_user_features = COMMON_USER_BOOKE,
  1749. .mmu_features = MMU_FTR_TYPE_44x,
  1750. .icache_bsize = 32,
  1751. .dcache_bsize = 32,
  1752. .machine_check = machine_check_4xx,
  1753. .platform = "ppc440",
  1754. },
  1755. { /* 440SPe Rev. A */
  1756. .pvr_mask = 0xfff00fff,
  1757. .pvr_value = 0x53400890,
  1758. .cpu_name = "440SPe Rev. A",
  1759. .cpu_features = CPU_FTRS_44X,
  1760. .cpu_user_features = COMMON_USER_BOOKE,
  1761. .mmu_features = MMU_FTR_TYPE_44x,
  1762. .icache_bsize = 32,
  1763. .dcache_bsize = 32,
  1764. .cpu_setup = __setup_cpu_440spe,
  1765. .machine_check = machine_check_440A,
  1766. .platform = "ppc440",
  1767. },
  1768. { /* 440SPe Rev. B */
  1769. .pvr_mask = 0xfff00fff,
  1770. .pvr_value = 0x53400891,
  1771. .cpu_name = "440SPe Rev. B",
  1772. .cpu_features = CPU_FTRS_44X,
  1773. .cpu_user_features = COMMON_USER_BOOKE,
  1774. .mmu_features = MMU_FTR_TYPE_44x,
  1775. .icache_bsize = 32,
  1776. .dcache_bsize = 32,
  1777. .cpu_setup = __setup_cpu_440spe,
  1778. .machine_check = machine_check_440A,
  1779. .platform = "ppc440",
  1780. },
  1781. { /* 440 in Xilinx Virtex-5 FXT */
  1782. .pvr_mask = 0xfffffff0,
  1783. .pvr_value = 0x7ff21910,
  1784. .cpu_name = "440 in Virtex-5 FXT",
  1785. .cpu_features = CPU_FTRS_44X,
  1786. .cpu_user_features = COMMON_USER_BOOKE,
  1787. .mmu_features = MMU_FTR_TYPE_44x,
  1788. .icache_bsize = 32,
  1789. .dcache_bsize = 32,
  1790. .cpu_setup = __setup_cpu_440x5,
  1791. .machine_check = machine_check_440A,
  1792. .platform = "ppc440",
  1793. },
  1794. { /* 460EX */
  1795. .pvr_mask = 0xffff0006,
  1796. .pvr_value = 0x13020002,
  1797. .cpu_name = "460EX",
  1798. .cpu_features = CPU_FTRS_440x6,
  1799. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1800. .mmu_features = MMU_FTR_TYPE_44x,
  1801. .icache_bsize = 32,
  1802. .dcache_bsize = 32,
  1803. .cpu_setup = __setup_cpu_460ex,
  1804. .machine_check = machine_check_440A,
  1805. .platform = "ppc440",
  1806. },
  1807. { /* 460EX Rev B */
  1808. .pvr_mask = 0xffff0007,
  1809. .pvr_value = 0x13020004,
  1810. .cpu_name = "460EX Rev. B",
  1811. .cpu_features = CPU_FTRS_440x6,
  1812. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1813. .mmu_features = MMU_FTR_TYPE_44x,
  1814. .icache_bsize = 32,
  1815. .dcache_bsize = 32,
  1816. .cpu_setup = __setup_cpu_460ex,
  1817. .machine_check = machine_check_440A,
  1818. .platform = "ppc440",
  1819. },
  1820. { /* 460GT */
  1821. .pvr_mask = 0xffff0006,
  1822. .pvr_value = 0x13020000,
  1823. .cpu_name = "460GT",
  1824. .cpu_features = CPU_FTRS_440x6,
  1825. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1826. .mmu_features = MMU_FTR_TYPE_44x,
  1827. .icache_bsize = 32,
  1828. .dcache_bsize = 32,
  1829. .cpu_setup = __setup_cpu_460gt,
  1830. .machine_check = machine_check_440A,
  1831. .platform = "ppc440",
  1832. },
  1833. { /* 460GT Rev B */
  1834. .pvr_mask = 0xffff0007,
  1835. .pvr_value = 0x13020005,
  1836. .cpu_name = "460GT Rev. B",
  1837. .cpu_features = CPU_FTRS_440x6,
  1838. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1839. .mmu_features = MMU_FTR_TYPE_44x,
  1840. .icache_bsize = 32,
  1841. .dcache_bsize = 32,
  1842. .cpu_setup = __setup_cpu_460gt,
  1843. .machine_check = machine_check_440A,
  1844. .platform = "ppc440",
  1845. },
  1846. { /* 460SX */
  1847. .pvr_mask = 0xffffff00,
  1848. .pvr_value = 0x13541800,
  1849. .cpu_name = "460SX",
  1850. .cpu_features = CPU_FTRS_44X,
  1851. .cpu_user_features = COMMON_USER_BOOKE,
  1852. .mmu_features = MMU_FTR_TYPE_44x,
  1853. .icache_bsize = 32,
  1854. .dcache_bsize = 32,
  1855. .cpu_setup = __setup_cpu_460sx,
  1856. .machine_check = machine_check_440A,
  1857. .platform = "ppc440",
  1858. },
  1859. { /* 464 in APM821xx */
  1860. .pvr_mask = 0xfffffff0,
  1861. .pvr_value = 0x12C41C80,
  1862. .cpu_name = "APM821XX",
  1863. .cpu_features = CPU_FTRS_44X,
  1864. .cpu_user_features = COMMON_USER_BOOKE |
  1865. PPC_FEATURE_HAS_FPU,
  1866. .mmu_features = MMU_FTR_TYPE_44x,
  1867. .icache_bsize = 32,
  1868. .dcache_bsize = 32,
  1869. .cpu_setup = __setup_cpu_apm821xx,
  1870. .machine_check = machine_check_440A,
  1871. .platform = "ppc440",
  1872. },
  1873. { /* 476 DD2 core */
  1874. .pvr_mask = 0xffffffff,
  1875. .pvr_value = 0x11a52080,
  1876. .cpu_name = "476",
  1877. .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2,
  1878. .cpu_user_features = COMMON_USER_BOOKE |
  1879. PPC_FEATURE_HAS_FPU,
  1880. .mmu_features = MMU_FTR_TYPE_47x |
  1881. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1882. .icache_bsize = 32,
  1883. .dcache_bsize = 128,
  1884. .machine_check = machine_check_47x,
  1885. .platform = "ppc470",
  1886. },
  1887. { /* 476fpe */
  1888. .pvr_mask = 0xffff0000,
  1889. .pvr_value = 0x7ff50000,
  1890. .cpu_name = "476fpe",
  1891. .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2,
  1892. .cpu_user_features = COMMON_USER_BOOKE |
  1893. PPC_FEATURE_HAS_FPU,
  1894. .mmu_features = MMU_FTR_TYPE_47x |
  1895. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1896. .icache_bsize = 32,
  1897. .dcache_bsize = 128,
  1898. .machine_check = machine_check_47x,
  1899. .platform = "ppc470",
  1900. },
  1901. { /* 476 iss */
  1902. .pvr_mask = 0xffff0000,
  1903. .pvr_value = 0x00050000,
  1904. .cpu_name = "476",
  1905. .cpu_features = CPU_FTRS_47X,
  1906. .cpu_user_features = COMMON_USER_BOOKE |
  1907. PPC_FEATURE_HAS_FPU,
  1908. .mmu_features = MMU_FTR_TYPE_47x |
  1909. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1910. .icache_bsize = 32,
  1911. .dcache_bsize = 128,
  1912. .machine_check = machine_check_47x,
  1913. .platform = "ppc470",
  1914. },
  1915. { /* 476 others */
  1916. .pvr_mask = 0xffff0000,
  1917. .pvr_value = 0x11a50000,
  1918. .cpu_name = "476",
  1919. .cpu_features = CPU_FTRS_47X,
  1920. .cpu_user_features = COMMON_USER_BOOKE |
  1921. PPC_FEATURE_HAS_FPU,
  1922. .mmu_features = MMU_FTR_TYPE_47x |
  1923. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1924. .icache_bsize = 32,
  1925. .dcache_bsize = 128,
  1926. .machine_check = machine_check_47x,
  1927. .platform = "ppc470",
  1928. },
  1929. { /* default match */
  1930. .pvr_mask = 0x00000000,
  1931. .pvr_value = 0x00000000,
  1932. .cpu_name = "(generic 44x PPC)",
  1933. .cpu_features = CPU_FTRS_44X,
  1934. .cpu_user_features = COMMON_USER_BOOKE,
  1935. .mmu_features = MMU_FTR_TYPE_44x,
  1936. .icache_bsize = 32,
  1937. .dcache_bsize = 32,
  1938. .machine_check = machine_check_4xx,
  1939. .platform = "ppc440",
  1940. }
  1941. #endif /* CONFIG_44x */
  1942. #ifdef CONFIG_E200
  1943. { /* e200z5 */
  1944. .pvr_mask = 0xfff00000,
  1945. .pvr_value = 0x81000000,
  1946. .cpu_name = "e200z5",
  1947. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1948. .cpu_features = CPU_FTRS_E200,
  1949. .cpu_user_features = COMMON_USER_BOOKE |
  1950. PPC_FEATURE_HAS_EFP_SINGLE |
  1951. PPC_FEATURE_UNIFIED_CACHE,
  1952. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1953. .dcache_bsize = 32,
  1954. .machine_check = machine_check_e200,
  1955. .platform = "ppc5554",
  1956. },
  1957. { /* e200z6 */
  1958. .pvr_mask = 0xfff00000,
  1959. .pvr_value = 0x81100000,
  1960. .cpu_name = "e200z6",
  1961. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1962. .cpu_features = CPU_FTRS_E200,
  1963. .cpu_user_features = COMMON_USER_BOOKE |
  1964. PPC_FEATURE_HAS_SPE_COMP |
  1965. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1966. PPC_FEATURE_UNIFIED_CACHE,
  1967. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1968. .dcache_bsize = 32,
  1969. .machine_check = machine_check_e200,
  1970. .platform = "ppc5554",
  1971. },
  1972. { /* default match */
  1973. .pvr_mask = 0x00000000,
  1974. .pvr_value = 0x00000000,
  1975. .cpu_name = "(generic E200 PPC)",
  1976. .cpu_features = CPU_FTRS_E200,
  1977. .cpu_user_features = COMMON_USER_BOOKE |
  1978. PPC_FEATURE_HAS_EFP_SINGLE |
  1979. PPC_FEATURE_UNIFIED_CACHE,
  1980. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1981. .dcache_bsize = 32,
  1982. .cpu_setup = __setup_cpu_e200,
  1983. .machine_check = machine_check_e200,
  1984. .platform = "ppc5554",
  1985. }
  1986. #endif /* CONFIG_E200 */
  1987. #endif /* CONFIG_PPC32 */
  1988. #ifdef CONFIG_E500
  1989. #ifdef CONFIG_PPC32
  1990. { /* e500 */
  1991. .pvr_mask = 0xffff0000,
  1992. .pvr_value = 0x80200000,
  1993. .cpu_name = "e500",
  1994. .cpu_features = CPU_FTRS_E500,
  1995. .cpu_user_features = COMMON_USER_BOOKE |
  1996. PPC_FEATURE_HAS_SPE_COMP |
  1997. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1998. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  1999. .mmu_features = MMU_FTR_TYPE_FSL_E,
  2000. .icache_bsize = 32,
  2001. .dcache_bsize = 32,
  2002. .num_pmcs = 4,
  2003. .oprofile_cpu_type = "ppc/e500",
  2004. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2005. .cpu_setup = __setup_cpu_e500v1,
  2006. .machine_check = machine_check_e500,
  2007. .platform = "ppc8540",
  2008. },
  2009. { /* e500v2 */
  2010. .pvr_mask = 0xffff0000,
  2011. .pvr_value = 0x80210000,
  2012. .cpu_name = "e500v2",
  2013. .cpu_features = CPU_FTRS_E500_2,
  2014. .cpu_user_features = COMMON_USER_BOOKE |
  2015. PPC_FEATURE_HAS_SPE_COMP |
  2016. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  2017. PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
  2018. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  2019. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS,
  2020. .icache_bsize = 32,
  2021. .dcache_bsize = 32,
  2022. .num_pmcs = 4,
  2023. .oprofile_cpu_type = "ppc/e500",
  2024. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2025. .cpu_setup = __setup_cpu_e500v2,
  2026. .machine_check = machine_check_e500,
  2027. .platform = "ppc8548",
  2028. },
  2029. { /* e500mc */
  2030. .pvr_mask = 0xffff0000,
  2031. .pvr_value = 0x80230000,
  2032. .cpu_name = "e500mc",
  2033. .cpu_features = CPU_FTRS_E500MC,
  2034. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  2035. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  2036. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2037. MMU_FTR_USE_TLBILX,
  2038. .icache_bsize = 64,
  2039. .dcache_bsize = 64,
  2040. .num_pmcs = 4,
  2041. .oprofile_cpu_type = "ppc/e500mc",
  2042. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2043. .cpu_setup = __setup_cpu_e500mc,
  2044. .machine_check = machine_check_e500mc,
  2045. .platform = "ppce500mc",
  2046. },
  2047. #endif /* CONFIG_PPC32 */
  2048. { /* e5500 */
  2049. .pvr_mask = 0xffff0000,
  2050. .pvr_value = 0x80240000,
  2051. .cpu_name = "e5500",
  2052. .cpu_features = CPU_FTRS_E5500,
  2053. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  2054. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  2055. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2056. MMU_FTR_USE_TLBILX,
  2057. .icache_bsize = 64,
  2058. .dcache_bsize = 64,
  2059. .num_pmcs = 4,
  2060. .oprofile_cpu_type = "ppc/e500mc",
  2061. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2062. .cpu_setup = __setup_cpu_e5500,
  2063. #ifndef CONFIG_PPC32
  2064. .cpu_restore = __restore_cpu_e5500,
  2065. #endif
  2066. .machine_check = machine_check_e500mc,
  2067. .platform = "ppce5500",
  2068. },
  2069. { /* e6500 */
  2070. .pvr_mask = 0xffff0000,
  2071. .pvr_value = 0x80400000,
  2072. .cpu_name = "e6500",
  2073. .cpu_features = CPU_FTRS_E6500,
  2074. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU |
  2075. PPC_FEATURE_HAS_ALTIVEC_COMP,
  2076. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  2077. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2078. MMU_FTR_USE_TLBILX,
  2079. .icache_bsize = 64,
  2080. .dcache_bsize = 64,
  2081. .num_pmcs = 4,
  2082. .oprofile_cpu_type = "ppc/e6500",
  2083. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2084. .cpu_setup = __setup_cpu_e6500,
  2085. #ifndef CONFIG_PPC32
  2086. .cpu_restore = __restore_cpu_e6500,
  2087. #endif
  2088. .machine_check = machine_check_e500mc,
  2089. .platform = "ppce6500",
  2090. },
  2091. #ifdef CONFIG_PPC32
  2092. { /* default match */
  2093. .pvr_mask = 0x00000000,
  2094. .pvr_value = 0x00000000,
  2095. .cpu_name = "(generic E500 PPC)",
  2096. .cpu_features = CPU_FTRS_E500,
  2097. .cpu_user_features = COMMON_USER_BOOKE |
  2098. PPC_FEATURE_HAS_SPE_COMP |
  2099. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  2100. .mmu_features = MMU_FTR_TYPE_FSL_E,
  2101. .icache_bsize = 32,
  2102. .dcache_bsize = 32,
  2103. .machine_check = machine_check_e500,
  2104. .platform = "powerpc",
  2105. }
  2106. #endif /* CONFIG_PPC32 */
  2107. #endif /* CONFIG_E500 */
  2108. #ifdef CONFIG_PPC_A2
  2109. { /* Standard A2 (>= DD2) + FPU core */
  2110. .pvr_mask = 0xffff0000,
  2111. .pvr_value = 0x00480000,
  2112. .cpu_name = "A2 (>= DD2)",
  2113. .cpu_features = CPU_FTRS_A2,
  2114. .cpu_user_features = COMMON_USER_PPC64,
  2115. .mmu_features = MMU_FTRS_A2,
  2116. .icache_bsize = 64,
  2117. .dcache_bsize = 64,
  2118. .num_pmcs = 0,
  2119. .cpu_setup = __setup_cpu_a2,
  2120. .cpu_restore = __restore_cpu_a2,
  2121. .machine_check = machine_check_generic,
  2122. .platform = "ppca2",
  2123. },
  2124. { /* This is a default entry to get going, to be replaced by
  2125. * a real one at some stage
  2126. */
  2127. #define CPU_FTRS_BASE_BOOK3E (CPU_FTR_USE_TB | \
  2128. CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_SMT | \
  2129. CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
  2130. .pvr_mask = 0x00000000,
  2131. .pvr_value = 0x00000000,
  2132. .cpu_name = "Book3E",
  2133. .cpu_features = CPU_FTRS_BASE_BOOK3E,
  2134. .cpu_user_features = COMMON_USER_PPC64,
  2135. .mmu_features = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
  2136. MMU_FTR_USE_TLBIVAX_BCAST |
  2137. MMU_FTR_LOCK_BCAST_INVAL,
  2138. .icache_bsize = 64,
  2139. .dcache_bsize = 64,
  2140. .num_pmcs = 0,
  2141. .machine_check = machine_check_generic,
  2142. .platform = "power6",
  2143. },
  2144. #endif /* CONFIG_PPC_A2 */
  2145. };
  2146. static struct cpu_spec the_cpu_spec;
  2147. static struct cpu_spec * __init setup_cpu_spec(unsigned long offset,
  2148. struct cpu_spec *s)
  2149. {
  2150. struct cpu_spec *t = &the_cpu_spec;
  2151. struct cpu_spec old;
  2152. t = PTRRELOC(t);
  2153. old = *t;
  2154. /* Copy everything, then do fixups */
  2155. *t = *s;
  2156. /*
  2157. * If we are overriding a previous value derived from the real
  2158. * PVR with a new value obtained using a logical PVR value,
  2159. * don't modify the performance monitor fields.
  2160. */
  2161. if (old.num_pmcs && !s->num_pmcs) {
  2162. t->num_pmcs = old.num_pmcs;
  2163. t->pmc_type = old.pmc_type;
  2164. t->oprofile_type = old.oprofile_type;
  2165. t->oprofile_mmcra_sihv = old.oprofile_mmcra_sihv;
  2166. t->oprofile_mmcra_sipr = old.oprofile_mmcra_sipr;
  2167. t->oprofile_mmcra_clear = old.oprofile_mmcra_clear;
  2168. /*
  2169. * If we have passed through this logic once before and
  2170. * have pulled the default case because the real PVR was
  2171. * not found inside cpu_specs[], then we are possibly
  2172. * running in compatibility mode. In that case, let the
  2173. * oprofiler know which set of compatibility counters to
  2174. * pull from by making sure the oprofile_cpu_type string
  2175. * is set to that of compatibility mode. If the
  2176. * oprofile_cpu_type already has a value, then we are
  2177. * possibly overriding a real PVR with a logical one,
  2178. * and, in that case, keep the current value for
  2179. * oprofile_cpu_type.
  2180. */
  2181. if (old.oprofile_cpu_type != NULL) {
  2182. t->oprofile_cpu_type = old.oprofile_cpu_type;
  2183. t->oprofile_type = old.oprofile_type;
  2184. }
  2185. }
  2186. *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
  2187. /*
  2188. * Set the base platform string once; assumes
  2189. * we're called with real pvr first.
  2190. */
  2191. if (*PTRRELOC(&powerpc_base_platform) == NULL)
  2192. *PTRRELOC(&powerpc_base_platform) = t->platform;
  2193. #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
  2194. /* ppc64 and booke expect identify_cpu to also call setup_cpu for
  2195. * that processor. I will consolidate that at a later time, for now,
  2196. * just use #ifdef. We also don't need to PTRRELOC the function
  2197. * pointer on ppc64 and booke as we are running at 0 in real mode
  2198. * on ppc64 and reloc_offset is always 0 on booke.
  2199. */
  2200. if (t->cpu_setup) {
  2201. t->cpu_setup(offset, t);
  2202. }
  2203. #endif /* CONFIG_PPC64 || CONFIG_BOOKE */
  2204. return t;
  2205. }
  2206. struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
  2207. {
  2208. struct cpu_spec *s = cpu_specs;
  2209. int i;
  2210. s = PTRRELOC(s);
  2211. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) {
  2212. if ((pvr & s->pvr_mask) == s->pvr_value)
  2213. return setup_cpu_spec(offset, s);
  2214. }
  2215. BUG();
  2216. return NULL;
  2217. }