iwl-core.c 92 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/etherdevice.h>
  31. #include <net/mac80211.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h" /* FIXME: remove */
  34. #include "iwl-debug.h"
  35. #include "iwl-core.h"
  36. #include "iwl-io.h"
  37. #include "iwl-power.h"
  38. #include "iwl-sta.h"
  39. #include "iwl-helpers.h"
  40. MODULE_DESCRIPTION("iwl core");
  41. MODULE_VERSION(IWLWIFI_VERSION);
  42. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  43. MODULE_LICENSE("GPL");
  44. static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
  45. {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
  46. 0, COEX_UNASSOC_IDLE_FLAGS},
  47. {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
  48. 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
  49. {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
  50. 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
  51. {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
  52. 0, COEX_CALIBRATION_FLAGS},
  53. {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
  54. 0, COEX_PERIODIC_CALIBRATION_FLAGS},
  55. {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
  56. 0, COEX_CONNECTION_ESTAB_FLAGS},
  57. {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
  58. 0, COEX_ASSOCIATED_IDLE_FLAGS},
  59. {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
  60. 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
  61. {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
  62. 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
  63. {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
  64. 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
  65. {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
  66. {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
  67. {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
  68. 0, COEX_STAND_ALONE_DEBUG_FLAGS},
  69. {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
  70. 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
  71. {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
  72. {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
  73. };
  74. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  75. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  76. IWL_RATE_SISO_##s##M_PLCP, \
  77. IWL_RATE_MIMO2_##s##M_PLCP,\
  78. IWL_RATE_MIMO3_##s##M_PLCP,\
  79. IWL_RATE_##r##M_IEEE, \
  80. IWL_RATE_##ip##M_INDEX, \
  81. IWL_RATE_##in##M_INDEX, \
  82. IWL_RATE_##rp##M_INDEX, \
  83. IWL_RATE_##rn##M_INDEX, \
  84. IWL_RATE_##pp##M_INDEX, \
  85. IWL_RATE_##np##M_INDEX }
  86. u32 iwl_debug_level;
  87. EXPORT_SYMBOL(iwl_debug_level);
  88. static irqreturn_t iwl_isr(int irq, void *data);
  89. /*
  90. * Parameter order:
  91. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  92. *
  93. * If there isn't a valid next or previous rate then INV is used which
  94. * maps to IWL_RATE_INVALID
  95. *
  96. */
  97. const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  98. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  99. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  100. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  101. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  102. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  103. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  104. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  105. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  106. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  107. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  108. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  109. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  110. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  111. /* FIXME:RS: ^^ should be INV (legacy) */
  112. };
  113. EXPORT_SYMBOL(iwl_rates);
  114. /**
  115. * translate ucode response to mac80211 tx status control values
  116. */
  117. void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  118. struct ieee80211_tx_info *info)
  119. {
  120. struct ieee80211_tx_rate *r = &info->control.rates[0];
  121. info->antenna_sel_tx =
  122. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  123. if (rate_n_flags & RATE_MCS_HT_MSK)
  124. r->flags |= IEEE80211_TX_RC_MCS;
  125. if (rate_n_flags & RATE_MCS_GF_MSK)
  126. r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
  127. if (rate_n_flags & RATE_MCS_HT40_MSK)
  128. r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
  129. if (rate_n_flags & RATE_MCS_DUP_MSK)
  130. r->flags |= IEEE80211_TX_RC_DUP_DATA;
  131. if (rate_n_flags & RATE_MCS_SGI_MSK)
  132. r->flags |= IEEE80211_TX_RC_SHORT_GI;
  133. r->idx = iwl_hwrate_to_mac80211_idx(rate_n_flags, info->band);
  134. }
  135. EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
  136. int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
  137. {
  138. int idx = 0;
  139. /* HT rate format */
  140. if (rate_n_flags & RATE_MCS_HT_MSK) {
  141. idx = (rate_n_flags & 0xff);
  142. if (idx >= IWL_RATE_MIMO3_6M_PLCP)
  143. idx = idx - IWL_RATE_MIMO3_6M_PLCP;
  144. else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  145. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  146. idx += IWL_FIRST_OFDM_RATE;
  147. /* skip 9M not supported in ht*/
  148. if (idx >= IWL_RATE_9M_INDEX)
  149. idx += 1;
  150. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  151. return idx;
  152. /* legacy rate format, search for match in table */
  153. } else {
  154. for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
  155. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  156. return idx;
  157. }
  158. return -1;
  159. }
  160. EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
  161. int iwl_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
  162. {
  163. int idx = 0;
  164. int band_offset = 0;
  165. /* HT rate format: mac80211 wants an MCS number, which is just LSB */
  166. if (rate_n_flags & RATE_MCS_HT_MSK) {
  167. idx = (rate_n_flags & 0xff);
  168. return idx;
  169. /* Legacy rate format, search for match in table */
  170. } else {
  171. if (band == IEEE80211_BAND_5GHZ)
  172. band_offset = IWL_FIRST_OFDM_RATE;
  173. for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
  174. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  175. return idx - band_offset;
  176. }
  177. return -1;
  178. }
  179. u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
  180. {
  181. int i;
  182. u8 ind = ant;
  183. for (i = 0; i < RATE_ANT_NUM - 1; i++) {
  184. ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
  185. if (priv->hw_params.valid_tx_ant & BIT(ind))
  186. return ind;
  187. }
  188. return ant;
  189. }
  190. EXPORT_SYMBOL(iwl_toggle_tx_ant);
  191. const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  192. EXPORT_SYMBOL(iwl_bcast_addr);
  193. /* This function both allocates and initializes hw and priv. */
  194. struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
  195. struct ieee80211_ops *hw_ops)
  196. {
  197. struct iwl_priv *priv;
  198. /* mac80211 allocates memory for this device instance, including
  199. * space for this driver's private structure */
  200. struct ieee80211_hw *hw =
  201. ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
  202. if (hw == NULL) {
  203. printk(KERN_ERR "%s: Can not allocate network device\n",
  204. cfg->name);
  205. goto out;
  206. }
  207. priv = hw->priv;
  208. priv->hw = hw;
  209. out:
  210. return hw;
  211. }
  212. EXPORT_SYMBOL(iwl_alloc_all);
  213. void iwl_hw_detect(struct iwl_priv *priv)
  214. {
  215. priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
  216. priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
  217. pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
  218. }
  219. EXPORT_SYMBOL(iwl_hw_detect);
  220. int iwl_hw_nic_init(struct iwl_priv *priv)
  221. {
  222. unsigned long flags;
  223. struct iwl_rx_queue *rxq = &priv->rxq;
  224. int ret;
  225. /* nic_init */
  226. spin_lock_irqsave(&priv->lock, flags);
  227. priv->cfg->ops->lib->apm_ops.init(priv);
  228. /* Set interrupt coalescing timer to 512 usecs */
  229. iwl_write8(priv, CSR_INT_COALESCING, 512 / 32);
  230. spin_unlock_irqrestore(&priv->lock, flags);
  231. ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
  232. priv->cfg->ops->lib->apm_ops.config(priv);
  233. /* Allocate the RX queue, or reset if it is already allocated */
  234. if (!rxq->bd) {
  235. ret = iwl_rx_queue_alloc(priv);
  236. if (ret) {
  237. IWL_ERR(priv, "Unable to initialize Rx queue\n");
  238. return -ENOMEM;
  239. }
  240. } else
  241. iwl_rx_queue_reset(priv, rxq);
  242. iwl_rx_replenish(priv);
  243. iwl_rx_init(priv, rxq);
  244. spin_lock_irqsave(&priv->lock, flags);
  245. rxq->need_update = 1;
  246. iwl_rx_queue_update_write_ptr(priv, rxq);
  247. spin_unlock_irqrestore(&priv->lock, flags);
  248. /* Allocate and init all Tx and Command queues */
  249. ret = iwl_txq_ctx_reset(priv);
  250. if (ret)
  251. return ret;
  252. set_bit(STATUS_INIT, &priv->status);
  253. return 0;
  254. }
  255. EXPORT_SYMBOL(iwl_hw_nic_init);
  256. /*
  257. * QoS support
  258. */
  259. void iwl_activate_qos(struct iwl_priv *priv, u8 force)
  260. {
  261. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  262. return;
  263. priv->qos_data.def_qos_parm.qos_flags = 0;
  264. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  265. !priv->qos_data.qos_cap.q_AP.txop_request)
  266. priv->qos_data.def_qos_parm.qos_flags |=
  267. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  268. if (priv->qos_data.qos_active)
  269. priv->qos_data.def_qos_parm.qos_flags |=
  270. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  271. if (priv->current_ht_config.is_ht)
  272. priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  273. if (force || iwl_is_associated(priv)) {
  274. IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  275. priv->qos_data.qos_active,
  276. priv->qos_data.def_qos_parm.qos_flags);
  277. iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
  278. sizeof(struct iwl_qosparam_cmd),
  279. &priv->qos_data.def_qos_parm, NULL);
  280. }
  281. }
  282. EXPORT_SYMBOL(iwl_activate_qos);
  283. /*
  284. * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
  285. * (802.11b) (802.11a/g)
  286. * AC_BK 15 1023 7 0 0
  287. * AC_BE 15 1023 3 0 0
  288. * AC_VI 7 15 2 6.016ms 3.008ms
  289. * AC_VO 3 7 2 3.264ms 1.504ms
  290. */
  291. void iwl_reset_qos(struct iwl_priv *priv)
  292. {
  293. u16 cw_min = 15;
  294. u16 cw_max = 1023;
  295. u8 aifs = 2;
  296. bool is_legacy = false;
  297. unsigned long flags;
  298. int i;
  299. spin_lock_irqsave(&priv->lock, flags);
  300. /* QoS always active in AP and ADHOC mode
  301. * In STA mode wait for association
  302. */
  303. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  304. priv->iw_mode == NL80211_IFTYPE_AP)
  305. priv->qos_data.qos_active = 1;
  306. else
  307. priv->qos_data.qos_active = 0;
  308. /* check for legacy mode */
  309. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  310. (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
  311. (priv->iw_mode == NL80211_IFTYPE_STATION &&
  312. (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
  313. cw_min = 31;
  314. is_legacy = 1;
  315. }
  316. if (priv->qos_data.qos_active)
  317. aifs = 3;
  318. /* AC_BE */
  319. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  320. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  321. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  322. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  323. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  324. if (priv->qos_data.qos_active) {
  325. /* AC_BK */
  326. i = 1;
  327. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  328. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  329. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  330. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  331. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  332. /* AC_VI */
  333. i = 2;
  334. priv->qos_data.def_qos_parm.ac[i].cw_min =
  335. cpu_to_le16((cw_min + 1) / 2 - 1);
  336. priv->qos_data.def_qos_parm.ac[i].cw_max =
  337. cpu_to_le16(cw_min);
  338. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  339. if (is_legacy)
  340. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  341. cpu_to_le16(6016);
  342. else
  343. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  344. cpu_to_le16(3008);
  345. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  346. /* AC_VO */
  347. i = 3;
  348. priv->qos_data.def_qos_parm.ac[i].cw_min =
  349. cpu_to_le16((cw_min + 1) / 4 - 1);
  350. priv->qos_data.def_qos_parm.ac[i].cw_max =
  351. cpu_to_le16((cw_min + 1) / 2 - 1);
  352. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  353. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  354. if (is_legacy)
  355. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  356. cpu_to_le16(3264);
  357. else
  358. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  359. cpu_to_le16(1504);
  360. } else {
  361. for (i = 1; i < 4; i++) {
  362. priv->qos_data.def_qos_parm.ac[i].cw_min =
  363. cpu_to_le16(cw_min);
  364. priv->qos_data.def_qos_parm.ac[i].cw_max =
  365. cpu_to_le16(cw_max);
  366. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  367. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  368. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  369. }
  370. }
  371. IWL_DEBUG_QOS(priv, "set QoS to default \n");
  372. spin_unlock_irqrestore(&priv->lock, flags);
  373. }
  374. EXPORT_SYMBOL(iwl_reset_qos);
  375. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  376. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  377. static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
  378. struct ieee80211_sta_ht_cap *ht_info,
  379. enum ieee80211_band band)
  380. {
  381. u16 max_bit_rate = 0;
  382. u8 rx_chains_num = priv->hw_params.rx_chains_num;
  383. u8 tx_chains_num = priv->hw_params.tx_chains_num;
  384. ht_info->cap = 0;
  385. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  386. ht_info->ht_supported = true;
  387. if (priv->cfg->ht_greenfield_support)
  388. ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
  389. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  390. ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
  391. (priv->cfg->sm_ps_mode << 2));
  392. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  393. if (priv->hw_params.ht40_channel & BIT(band)) {
  394. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  395. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  396. ht_info->mcs.rx_mask[4] = 0x01;
  397. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  398. }
  399. if (priv->cfg->mod_params->amsdu_size_8K)
  400. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  401. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  402. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  403. ht_info->mcs.rx_mask[0] = 0xFF;
  404. if (rx_chains_num >= 2)
  405. ht_info->mcs.rx_mask[1] = 0xFF;
  406. if (rx_chains_num >= 3)
  407. ht_info->mcs.rx_mask[2] = 0xFF;
  408. /* Highest supported Rx data rate */
  409. max_bit_rate *= rx_chains_num;
  410. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  411. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  412. /* Tx MCS capabilities */
  413. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  414. if (tx_chains_num != rx_chains_num) {
  415. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  416. ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
  417. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  418. }
  419. }
  420. /**
  421. * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
  422. */
  423. int iwlcore_init_geos(struct iwl_priv *priv)
  424. {
  425. struct iwl_channel_info *ch;
  426. struct ieee80211_supported_band *sband;
  427. struct ieee80211_channel *channels;
  428. struct ieee80211_channel *geo_ch;
  429. struct ieee80211_rate *rates;
  430. int i = 0;
  431. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  432. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  433. IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
  434. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  435. return 0;
  436. }
  437. channels = kzalloc(sizeof(struct ieee80211_channel) *
  438. priv->channel_count, GFP_KERNEL);
  439. if (!channels)
  440. return -ENOMEM;
  441. rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY),
  442. GFP_KERNEL);
  443. if (!rates) {
  444. kfree(channels);
  445. return -ENOMEM;
  446. }
  447. /* 5.2GHz channels start after the 2.4GHz channels */
  448. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  449. sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
  450. /* just OFDM */
  451. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  452. sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
  453. if (priv->cfg->sku & IWL_SKU_N)
  454. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  455. IEEE80211_BAND_5GHZ);
  456. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  457. sband->channels = channels;
  458. /* OFDM & CCK */
  459. sband->bitrates = rates;
  460. sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
  461. if (priv->cfg->sku & IWL_SKU_N)
  462. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  463. IEEE80211_BAND_2GHZ);
  464. priv->ieee_channels = channels;
  465. priv->ieee_rates = rates;
  466. for (i = 0; i < priv->channel_count; i++) {
  467. ch = &priv->channel_info[i];
  468. /* FIXME: might be removed if scan is OK */
  469. if (!is_channel_valid(ch))
  470. continue;
  471. if (is_channel_a_band(ch))
  472. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  473. else
  474. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  475. geo_ch = &sband->channels[sband->n_channels++];
  476. geo_ch->center_freq =
  477. ieee80211_channel_to_frequency(ch->channel);
  478. geo_ch->max_power = ch->max_power_avg;
  479. geo_ch->max_antenna_gain = 0xff;
  480. geo_ch->hw_value = ch->channel;
  481. if (is_channel_valid(ch)) {
  482. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  483. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  484. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  485. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  486. if (ch->flags & EEPROM_CHANNEL_RADAR)
  487. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  488. geo_ch->flags |= ch->ht40_extension_channel;
  489. if (ch->max_power_avg > priv->tx_power_device_lmt)
  490. priv->tx_power_device_lmt = ch->max_power_avg;
  491. } else {
  492. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  493. }
  494. IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
  495. ch->channel, geo_ch->center_freq,
  496. is_channel_a_band(ch) ? "5.2" : "2.4",
  497. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  498. "restricted" : "valid",
  499. geo_ch->flags);
  500. }
  501. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  502. priv->cfg->sku & IWL_SKU_A) {
  503. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  504. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  505. priv->pci_dev->device,
  506. priv->pci_dev->subsystem_device);
  507. priv->cfg->sku &= ~IWL_SKU_A;
  508. }
  509. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  510. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  511. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  512. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  513. return 0;
  514. }
  515. EXPORT_SYMBOL(iwlcore_init_geos);
  516. /*
  517. * iwlcore_free_geos - undo allocations in iwlcore_init_geos
  518. */
  519. void iwlcore_free_geos(struct iwl_priv *priv)
  520. {
  521. kfree(priv->ieee_channels);
  522. kfree(priv->ieee_rates);
  523. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  524. }
  525. EXPORT_SYMBOL(iwlcore_free_geos);
  526. /*
  527. * iwlcore_rts_tx_cmd_flag: Set rts/cts. 3945 and 4965 only share this
  528. * function.
  529. */
  530. void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
  531. __le32 *tx_flags)
  532. {
  533. if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  534. *tx_flags |= TX_CMD_FLG_RTS_MSK;
  535. *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  536. } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  537. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  538. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  539. }
  540. }
  541. EXPORT_SYMBOL(iwlcore_rts_tx_cmd_flag);
  542. static bool is_single_rx_stream(struct iwl_priv *priv)
  543. {
  544. return !priv->current_ht_config.is_ht ||
  545. priv->current_ht_config.single_chain_sufficient;
  546. }
  547. static u8 iwl_is_channel_extension(struct iwl_priv *priv,
  548. enum ieee80211_band band,
  549. u16 channel, u8 extension_chan_offset)
  550. {
  551. const struct iwl_channel_info *ch_info;
  552. ch_info = iwl_get_channel_info(priv, band, channel);
  553. if (!is_channel_valid(ch_info))
  554. return 0;
  555. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  556. return !(ch_info->ht40_extension_channel &
  557. IEEE80211_CHAN_NO_HT40PLUS);
  558. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  559. return !(ch_info->ht40_extension_channel &
  560. IEEE80211_CHAN_NO_HT40MINUS);
  561. return 0;
  562. }
  563. u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
  564. struct ieee80211_sta_ht_cap *sta_ht_inf)
  565. {
  566. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  567. if (!ht_conf->is_ht || !ht_conf->is_40mhz)
  568. return 0;
  569. /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  570. * the bit will not set if it is pure 40MHz case
  571. */
  572. if (sta_ht_inf) {
  573. if (!sta_ht_inf->ht_supported)
  574. return 0;
  575. }
  576. #ifdef CONFIG_IWLWIFI_DEBUG
  577. if (priv->disable_ht40)
  578. return 0;
  579. #endif
  580. return iwl_is_channel_extension(priv, priv->band,
  581. le16_to_cpu(priv->staging_rxon.channel),
  582. ht_conf->extension_chan_offset);
  583. }
  584. EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
  585. static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
  586. {
  587. u16 new_val = 0;
  588. u16 beacon_factor = 0;
  589. beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
  590. new_val = beacon_val / beacon_factor;
  591. if (!new_val)
  592. new_val = max_beacon_val;
  593. return new_val;
  594. }
  595. void iwl_setup_rxon_timing(struct iwl_priv *priv)
  596. {
  597. u64 tsf;
  598. s32 interval_tm, rem;
  599. unsigned long flags;
  600. struct ieee80211_conf *conf = NULL;
  601. u16 beacon_int;
  602. conf = ieee80211_get_hw_conf(priv->hw);
  603. spin_lock_irqsave(&priv->lock, flags);
  604. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  605. priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
  606. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  607. beacon_int = priv->beacon_int;
  608. priv->rxon_timing.atim_window = 0;
  609. } else {
  610. beacon_int = priv->vif->bss_conf.beacon_int;
  611. /* TODO: we need to get atim_window from upper stack
  612. * for now we set to 0 */
  613. priv->rxon_timing.atim_window = 0;
  614. }
  615. beacon_int = iwl_adjust_beacon_interval(beacon_int,
  616. priv->hw_params.max_beacon_itrvl * 1024);
  617. priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
  618. tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
  619. interval_tm = beacon_int * 1024;
  620. rem = do_div(tsf, interval_tm);
  621. priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  622. spin_unlock_irqrestore(&priv->lock, flags);
  623. IWL_DEBUG_ASSOC(priv,
  624. "beacon interval %d beacon timer %d beacon tim %d\n",
  625. le16_to_cpu(priv->rxon_timing.beacon_interval),
  626. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  627. le16_to_cpu(priv->rxon_timing.atim_window));
  628. }
  629. EXPORT_SYMBOL(iwl_setup_rxon_timing);
  630. void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  631. {
  632. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  633. if (hw_decrypt)
  634. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  635. else
  636. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  637. }
  638. EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
  639. /**
  640. * iwl_check_rxon_cmd - validate RXON structure is valid
  641. *
  642. * NOTE: This is really only useful during development and can eventually
  643. * be #ifdef'd out once the driver is stable and folks aren't actively
  644. * making changes
  645. */
  646. int iwl_check_rxon_cmd(struct iwl_priv *priv)
  647. {
  648. int error = 0;
  649. int counter = 1;
  650. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  651. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  652. error |= le32_to_cpu(rxon->flags &
  653. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  654. RXON_FLG_RADAR_DETECT_MSK));
  655. if (error)
  656. IWL_WARN(priv, "check 24G fields %d | %d\n",
  657. counter++, error);
  658. } else {
  659. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  660. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  661. if (error)
  662. IWL_WARN(priv, "check 52 fields %d | %d\n",
  663. counter++, error);
  664. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  665. if (error)
  666. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  667. counter++, error);
  668. }
  669. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  670. if (error)
  671. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  672. /* make sure basic rates 6Mbps and 1Mbps are supported */
  673. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  674. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  675. if (error)
  676. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  677. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  678. if (error)
  679. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  680. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  681. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  682. if (error)
  683. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  684. counter++, error);
  685. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  686. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  687. if (error)
  688. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  689. counter++, error);
  690. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  691. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  692. if (error)
  693. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  694. counter++, error);
  695. if (error)
  696. IWL_WARN(priv, "Tuning to channel %d\n",
  697. le16_to_cpu(rxon->channel));
  698. if (error) {
  699. IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
  700. return -1;
  701. }
  702. return 0;
  703. }
  704. EXPORT_SYMBOL(iwl_check_rxon_cmd);
  705. /**
  706. * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  707. * @priv: staging_rxon is compared to active_rxon
  708. *
  709. * If the RXON structure is changing enough to require a new tune,
  710. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  711. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  712. */
  713. int iwl_full_rxon_required(struct iwl_priv *priv)
  714. {
  715. /* These items are only settable from the full RXON command */
  716. if (!(iwl_is_associated(priv)) ||
  717. compare_ether_addr(priv->staging_rxon.bssid_addr,
  718. priv->active_rxon.bssid_addr) ||
  719. compare_ether_addr(priv->staging_rxon.node_addr,
  720. priv->active_rxon.node_addr) ||
  721. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  722. priv->active_rxon.wlap_bssid_addr) ||
  723. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  724. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  725. (priv->staging_rxon.air_propagation !=
  726. priv->active_rxon.air_propagation) ||
  727. (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
  728. priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
  729. (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
  730. priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
  731. (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
  732. priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
  733. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  734. return 1;
  735. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  736. * be updated with the RXON_ASSOC command -- however only some
  737. * flag transitions are allowed using RXON_ASSOC */
  738. /* Check if we are not switching bands */
  739. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  740. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  741. return 1;
  742. /* Check if we are switching association toggle */
  743. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  744. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  745. return 1;
  746. return 0;
  747. }
  748. EXPORT_SYMBOL(iwl_full_rxon_required);
  749. u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
  750. {
  751. int i;
  752. int rate_mask;
  753. /* Set rate mask*/
  754. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  755. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  756. else
  757. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  758. /* Find lowest valid rate */
  759. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  760. i = iwl_rates[i].next_ieee) {
  761. if (rate_mask & (1 << i))
  762. return iwl_rates[i].plcp;
  763. }
  764. /* No valid rate was found. Assign the lowest one */
  765. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  766. return IWL_RATE_1M_PLCP;
  767. else
  768. return IWL_RATE_6M_PLCP;
  769. }
  770. EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
  771. void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf)
  772. {
  773. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  774. if (!ht_conf->is_ht) {
  775. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  776. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
  777. RXON_FLG_HT40_PROT_MSK |
  778. RXON_FLG_HT_PROT_MSK);
  779. return;
  780. }
  781. /* FIXME: if the definition of ht_protection changed, the "translation"
  782. * will be needed for rxon->flags
  783. */
  784. rxon->flags |= cpu_to_le32(ht_conf->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
  785. /* Set up channel bandwidth:
  786. * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
  787. /* clear the HT channel mode before set the mode */
  788. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  789. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  790. if (iwl_is_ht40_tx_allowed(priv, NULL)) {
  791. /* pure ht40 */
  792. if (ht_conf->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
  793. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  794. /* Note: control channel is opposite of extension channel */
  795. switch (ht_conf->extension_chan_offset) {
  796. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  797. rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  798. break;
  799. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  800. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  801. break;
  802. }
  803. } else {
  804. /* Note: control channel is opposite of extension channel */
  805. switch (ht_conf->extension_chan_offset) {
  806. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  807. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  808. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  809. break;
  810. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  811. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  812. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  813. break;
  814. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  815. default:
  816. /* channel location only valid if in Mixed mode */
  817. IWL_ERR(priv, "invalid extension channel offset\n");
  818. break;
  819. }
  820. }
  821. } else {
  822. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  823. }
  824. if (priv->cfg->ops->hcmd->set_rxon_chain)
  825. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  826. IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
  827. "extension channel offset 0x%x\n",
  828. le32_to_cpu(rxon->flags), ht_conf->ht_protection,
  829. ht_conf->extension_chan_offset);
  830. return;
  831. }
  832. EXPORT_SYMBOL(iwl_set_rxon_ht);
  833. #define IWL_NUM_RX_CHAINS_MULTIPLE 3
  834. #define IWL_NUM_RX_CHAINS_SINGLE 2
  835. #define IWL_NUM_IDLE_CHAINS_DUAL 2
  836. #define IWL_NUM_IDLE_CHAINS_SINGLE 1
  837. /*
  838. * Determine how many receiver/antenna chains to use.
  839. *
  840. * More provides better reception via diversity. Fewer saves power
  841. * at the expense of throughput, but only when not in powersave to
  842. * start with.
  843. *
  844. * MIMO (dual stream) requires at least 2, but works better with 3.
  845. * This does not determine *which* chains to use, just how many.
  846. */
  847. static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
  848. {
  849. /* # of Rx chains to use when expecting MIMO. */
  850. if (is_single_rx_stream(priv))
  851. return IWL_NUM_RX_CHAINS_SINGLE;
  852. else
  853. return IWL_NUM_RX_CHAINS_MULTIPLE;
  854. }
  855. /*
  856. * When we are in power saving mode, unless device support spatial
  857. * multiplexing power save, use the active count for rx chain count.
  858. */
  859. static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
  860. {
  861. int idle_cnt = active_cnt;
  862. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  863. /* # Rx chains when idling and maybe trying to save power */
  864. switch (priv->cfg->sm_ps_mode) {
  865. case WLAN_HT_CAP_SM_PS_STATIC:
  866. idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
  867. break;
  868. case WLAN_HT_CAP_SM_PS_DYNAMIC:
  869. idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
  870. IWL_NUM_IDLE_CHAINS_SINGLE;
  871. break;
  872. case WLAN_HT_CAP_SM_PS_DISABLED:
  873. break;
  874. case WLAN_HT_CAP_SM_PS_INVALID:
  875. default:
  876. IWL_ERR(priv, "invalid sm_ps mode %u\n",
  877. priv->cfg->sm_ps_mode);
  878. WARN_ON(1);
  879. break;
  880. }
  881. return idle_cnt;
  882. }
  883. /* up to 4 chains */
  884. static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
  885. {
  886. u8 res;
  887. res = (chain_bitmap & BIT(0)) >> 0;
  888. res += (chain_bitmap & BIT(1)) >> 1;
  889. res += (chain_bitmap & BIT(2)) >> 2;
  890. res += (chain_bitmap & BIT(3)) >> 3;
  891. return res;
  892. }
  893. /**
  894. * iwl_is_monitor_mode - Determine if interface in monitor mode
  895. *
  896. * priv->iw_mode is set in add_interface, but add_interface is
  897. * never called for monitor mode. The only way mac80211 informs us about
  898. * monitor mode is through configuring filters (call to configure_filter).
  899. */
  900. bool iwl_is_monitor_mode(struct iwl_priv *priv)
  901. {
  902. return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
  903. }
  904. EXPORT_SYMBOL(iwl_is_monitor_mode);
  905. /**
  906. * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  907. *
  908. * Selects how many and which Rx receivers/antennas/chains to use.
  909. * This should not be used for scan command ... it puts data in wrong place.
  910. */
  911. void iwl_set_rxon_chain(struct iwl_priv *priv)
  912. {
  913. bool is_single = is_single_rx_stream(priv);
  914. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  915. u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
  916. u32 active_chains;
  917. u16 rx_chain;
  918. /* Tell uCode which antennas are actually connected.
  919. * Before first association, we assume all antennas are connected.
  920. * Just after first association, iwl_chain_noise_calibration()
  921. * checks which antennas actually *are* connected. */
  922. if (priv->chain_noise_data.active_chains)
  923. active_chains = priv->chain_noise_data.active_chains;
  924. else
  925. active_chains = priv->hw_params.valid_rx_ant;
  926. rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
  927. /* How many receivers should we use? */
  928. active_rx_cnt = iwl_get_active_rx_chain_count(priv);
  929. idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
  930. /* correct rx chain count according hw settings
  931. * and chain noise calibration
  932. */
  933. valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
  934. if (valid_rx_cnt < active_rx_cnt)
  935. active_rx_cnt = valid_rx_cnt;
  936. if (valid_rx_cnt < idle_rx_cnt)
  937. idle_rx_cnt = valid_rx_cnt;
  938. rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
  939. rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
  940. /* copied from 'iwl_bg_request_scan()' */
  941. /* Force use of chains B and C (0x6) for Rx for 4965
  942. * Avoid A (0x1) because of its off-channel reception on A-band.
  943. * MIMO is not used here, but value is required */
  944. if (iwl_is_monitor_mode(priv) &&
  945. !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
  946. ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
  947. rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
  948. rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
  949. rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
  950. rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
  951. }
  952. priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
  953. if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
  954. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  955. else
  956. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  957. IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
  958. priv->staging_rxon.rx_chain,
  959. active_rx_cnt, idle_rx_cnt);
  960. WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
  961. active_rx_cnt < idle_rx_cnt);
  962. }
  963. EXPORT_SYMBOL(iwl_set_rxon_chain);
  964. /**
  965. * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
  966. * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
  967. * @channel: Any channel valid for the requested phymode
  968. * In addition to setting the staging RXON, priv->phymode is also set.
  969. *
  970. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  971. * in the staging RXON flag structure based on the phymode
  972. */
  973. int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
  974. {
  975. enum ieee80211_band band = ch->band;
  976. u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
  977. if (!iwl_get_channel_info(priv, band, channel)) {
  978. IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
  979. channel, band);
  980. return -EINVAL;
  981. }
  982. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  983. (priv->band == band))
  984. return 0;
  985. priv->staging_rxon.channel = cpu_to_le16(channel);
  986. if (band == IEEE80211_BAND_5GHZ)
  987. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  988. else
  989. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  990. priv->band = band;
  991. IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
  992. return 0;
  993. }
  994. EXPORT_SYMBOL(iwl_set_rxon_channel);
  995. void iwl_set_flags_for_band(struct iwl_priv *priv,
  996. enum ieee80211_band band)
  997. {
  998. if (band == IEEE80211_BAND_5GHZ) {
  999. priv->staging_rxon.flags &=
  1000. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1001. | RXON_FLG_CCK_MSK);
  1002. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1003. } else {
  1004. /* Copied from iwl_post_associate() */
  1005. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1006. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1007. else
  1008. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1009. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1010. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1011. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1012. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1013. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1014. }
  1015. }
  1016. /*
  1017. * initialize rxon structure with default values from eeprom
  1018. */
  1019. void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
  1020. {
  1021. const struct iwl_channel_info *ch_info;
  1022. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1023. switch (mode) {
  1024. case NL80211_IFTYPE_AP:
  1025. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1026. break;
  1027. case NL80211_IFTYPE_STATION:
  1028. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1029. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1030. break;
  1031. case NL80211_IFTYPE_ADHOC:
  1032. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1033. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1034. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1035. RXON_FILTER_ACCEPT_GRP_MSK;
  1036. break;
  1037. default:
  1038. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  1039. break;
  1040. }
  1041. #if 0
  1042. /* TODO: Figure out when short_preamble would be set and cache from
  1043. * that */
  1044. if (!hw_to_local(priv->hw)->short_preamble)
  1045. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1046. else
  1047. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1048. #endif
  1049. ch_info = iwl_get_channel_info(priv, priv->band,
  1050. le16_to_cpu(priv->active_rxon.channel));
  1051. if (!ch_info)
  1052. ch_info = &priv->channel_info[0];
  1053. /*
  1054. * in some case A channels are all non IBSS
  1055. * in this case force B/G channel
  1056. */
  1057. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
  1058. !(is_channel_ibss(ch_info)))
  1059. ch_info = &priv->channel_info[0];
  1060. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1061. priv->band = ch_info->band;
  1062. iwl_set_flags_for_band(priv, priv->band);
  1063. priv->staging_rxon.ofdm_basic_rates =
  1064. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1065. priv->staging_rxon.cck_basic_rates =
  1066. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1067. /* clear both MIX and PURE40 mode flag */
  1068. priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
  1069. RXON_FLG_CHANNEL_MODE_PURE_40);
  1070. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1071. memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
  1072. priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
  1073. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
  1074. priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
  1075. }
  1076. EXPORT_SYMBOL(iwl_connection_init_rx_config);
  1077. static void iwl_set_rate(struct iwl_priv *priv)
  1078. {
  1079. const struct ieee80211_supported_band *hw = NULL;
  1080. struct ieee80211_rate *rate;
  1081. int i;
  1082. hw = iwl_get_hw_mode(priv, priv->band);
  1083. if (!hw) {
  1084. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  1085. return;
  1086. }
  1087. priv->active_rate = 0;
  1088. priv->active_rate_basic = 0;
  1089. for (i = 0; i < hw->n_bitrates; i++) {
  1090. rate = &(hw->bitrates[i]);
  1091. if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
  1092. priv->active_rate |= (1 << rate->hw_value);
  1093. }
  1094. IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
  1095. priv->active_rate, priv->active_rate_basic);
  1096. /*
  1097. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  1098. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  1099. * OFDM
  1100. */
  1101. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  1102. priv->staging_rxon.cck_basic_rates =
  1103. ((priv->active_rate_basic &
  1104. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  1105. else
  1106. priv->staging_rxon.cck_basic_rates =
  1107. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1108. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  1109. priv->staging_rxon.ofdm_basic_rates =
  1110. ((priv->active_rate_basic &
  1111. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  1112. IWL_FIRST_OFDM_RATE) & 0xFF;
  1113. else
  1114. priv->staging_rxon.ofdm_basic_rates =
  1115. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1116. }
  1117. void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  1118. {
  1119. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1120. struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
  1121. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  1122. if (priv->switch_rxon.switch_in_progress) {
  1123. if (!le32_to_cpu(csa->status) &&
  1124. (csa->channel == priv->switch_rxon.channel)) {
  1125. rxon->channel = csa->channel;
  1126. priv->staging_rxon.channel = csa->channel;
  1127. IWL_DEBUG_11H(priv, "CSA notif: channel %d\n",
  1128. le16_to_cpu(csa->channel));
  1129. } else
  1130. IWL_ERR(priv, "CSA notif (fail) : channel %d\n",
  1131. le16_to_cpu(csa->channel));
  1132. priv->switch_rxon.switch_in_progress = false;
  1133. }
  1134. }
  1135. EXPORT_SYMBOL(iwl_rx_csa);
  1136. #ifdef CONFIG_IWLWIFI_DEBUG
  1137. void iwl_print_rx_config_cmd(struct iwl_priv *priv)
  1138. {
  1139. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  1140. IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
  1141. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  1142. IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  1143. IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  1144. IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
  1145. le32_to_cpu(rxon->filter_flags));
  1146. IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
  1147. IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
  1148. rxon->ofdm_basic_rates);
  1149. IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  1150. IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
  1151. IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  1152. IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  1153. }
  1154. EXPORT_SYMBOL(iwl_print_rx_config_cmd);
  1155. #endif
  1156. /**
  1157. * iwl_irq_handle_error - called for HW or SW error interrupt from card
  1158. */
  1159. void iwl_irq_handle_error(struct iwl_priv *priv)
  1160. {
  1161. /* Set the FW error flag -- cleared on iwl_down */
  1162. set_bit(STATUS_FW_ERROR, &priv->status);
  1163. /* Cancel currently queued command. */
  1164. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  1165. priv->cfg->ops->lib->dump_nic_error_log(priv);
  1166. priv->cfg->ops->lib->dump_nic_event_log(priv, false);
  1167. #ifdef CONFIG_IWLWIFI_DEBUG
  1168. if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS)
  1169. iwl_print_rx_config_cmd(priv);
  1170. #endif
  1171. wake_up_interruptible(&priv->wait_command_queue);
  1172. /* Keep the restart process from trying to send host
  1173. * commands by clearing the INIT status bit */
  1174. clear_bit(STATUS_READY, &priv->status);
  1175. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1176. IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
  1177. "Restarting adapter due to uCode error.\n");
  1178. if (priv->cfg->mod_params->restart_fw)
  1179. queue_work(priv->workqueue, &priv->restart);
  1180. }
  1181. }
  1182. EXPORT_SYMBOL(iwl_irq_handle_error);
  1183. int iwl_apm_stop_master(struct iwl_priv *priv)
  1184. {
  1185. int ret = 0;
  1186. /* stop device's busmaster DMA activity */
  1187. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  1188. ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
  1189. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  1190. if (ret)
  1191. IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
  1192. IWL_DEBUG_INFO(priv, "stop master\n");
  1193. return ret;
  1194. }
  1195. EXPORT_SYMBOL(iwl_apm_stop_master);
  1196. void iwl_apm_stop(struct iwl_priv *priv)
  1197. {
  1198. IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
  1199. /* Stop device's DMA activity */
  1200. iwl_apm_stop_master(priv);
  1201. /* Reset the entire device */
  1202. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  1203. udelay(10);
  1204. /*
  1205. * Clear "initialization complete" bit to move adapter from
  1206. * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
  1207. */
  1208. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  1209. }
  1210. EXPORT_SYMBOL(iwl_apm_stop);
  1211. /*
  1212. * Start up NIC's basic functionality after it has been reset
  1213. * (e.g. after platform boot, or shutdown via iwl_apm_stop())
  1214. * NOTE: This does not load uCode nor start the embedded processor
  1215. */
  1216. int iwl_apm_init(struct iwl_priv *priv)
  1217. {
  1218. int ret = 0;
  1219. u16 lctl;
  1220. IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
  1221. /*
  1222. * Use "set_bit" below rather than "write", to preserve any hardware
  1223. * bits already set by default after reset.
  1224. */
  1225. /* Disable L0S exit timer (platform NMI Work/Around) */
  1226. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  1227. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  1228. /*
  1229. * Disable L0s without affecting L1;
  1230. * don't wait for ICH L0s (ICH bug W/A)
  1231. */
  1232. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  1233. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  1234. /* Set FH wait threshold to maximum (HW error during stress W/A) */
  1235. iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  1236. /*
  1237. * Enable HAP INTA (interrupt from management bus) to
  1238. * wake device's PCI Express link L1a -> L0s
  1239. * NOTE: This is no-op for 3945 (non-existant bit)
  1240. */
  1241. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1242. CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
  1243. /*
  1244. * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
  1245. * Check if BIOS (or OS) enabled L1-ASPM on this device.
  1246. * If so (likely), disable L0S, so device moves directly L0->L1;
  1247. * costs negligible amount of power savings.
  1248. * If not (unlikely), enable L0S, so there is at least some
  1249. * power savings, even without L1.
  1250. */
  1251. if (priv->cfg->set_l0s) {
  1252. lctl = iwl_pcie_link_ctl(priv);
  1253. if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
  1254. PCI_CFG_LINK_CTRL_VAL_L1_EN) {
  1255. /* L1-ASPM enabled; disable(!) L0S */
  1256. iwl_set_bit(priv, CSR_GIO_REG,
  1257. CSR_GIO_REG_VAL_L0S_ENABLED);
  1258. IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
  1259. } else {
  1260. /* L1-ASPM disabled; enable(!) L0S */
  1261. iwl_clear_bit(priv, CSR_GIO_REG,
  1262. CSR_GIO_REG_VAL_L0S_ENABLED);
  1263. IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
  1264. }
  1265. }
  1266. /* Configure analog phase-lock-loop before activating to D0A */
  1267. if (priv->cfg->pll_cfg_val)
  1268. iwl_set_bit(priv, CSR_ANA_PLL_CFG, priv->cfg->pll_cfg_val);
  1269. /*
  1270. * Set "initialization complete" bit to move adapter from
  1271. * D0U* --> D0A* (powered-up active) state.
  1272. */
  1273. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  1274. /*
  1275. * Wait for clock stabilization; once stabilized, access to
  1276. * device-internal resources is supported, e.g. iwl_write_prph()
  1277. * and accesses to uCode SRAM.
  1278. */
  1279. ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
  1280. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  1281. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  1282. if (ret < 0) {
  1283. IWL_DEBUG_INFO(priv, "Failed to init the card\n");
  1284. goto out;
  1285. }
  1286. /*
  1287. * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
  1288. * BSM (Boostrap State Machine) is only in 3945 and 4965;
  1289. * later devices (i.e. 5000 and later) have non-volatile SRAM,
  1290. * and don't need BSM to restore data after power-saving sleep.
  1291. *
  1292. * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
  1293. * do not disable clocks. This preserves any hardware bits already
  1294. * set by default in "CLK_CTRL_REG" after reset.
  1295. */
  1296. if (priv->cfg->use_bsm)
  1297. iwl_write_prph(priv, APMG_CLK_EN_REG,
  1298. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  1299. else
  1300. iwl_write_prph(priv, APMG_CLK_EN_REG,
  1301. APMG_CLK_VAL_DMA_CLK_RQT);
  1302. udelay(20);
  1303. /* Disable L1-Active */
  1304. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  1305. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  1306. out:
  1307. return ret;
  1308. }
  1309. EXPORT_SYMBOL(iwl_apm_init);
  1310. void iwl_configure_filter(struct ieee80211_hw *hw,
  1311. unsigned int changed_flags,
  1312. unsigned int *total_flags,
  1313. u64 multicast)
  1314. {
  1315. struct iwl_priv *priv = hw->priv;
  1316. __le32 *filter_flags = &priv->staging_rxon.filter_flags;
  1317. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  1318. changed_flags, *total_flags);
  1319. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  1320. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  1321. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  1322. else
  1323. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  1324. }
  1325. if (changed_flags & FIF_ALLMULTI) {
  1326. if (*total_flags & FIF_ALLMULTI)
  1327. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  1328. else
  1329. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  1330. }
  1331. if (changed_flags & FIF_CONTROL) {
  1332. if (*total_flags & FIF_CONTROL)
  1333. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  1334. else
  1335. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  1336. }
  1337. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  1338. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1339. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  1340. else
  1341. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  1342. }
  1343. /* We avoid iwl_commit_rxon here to commit the new filter flags
  1344. * since mac80211 will call ieee80211_hw_config immediately.
  1345. * (mc_list is not supported at this time). Otherwise, we need to
  1346. * queue a background iwl_commit_rxon work.
  1347. */
  1348. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  1349. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  1350. }
  1351. EXPORT_SYMBOL(iwl_configure_filter);
  1352. int iwl_set_hw_params(struct iwl_priv *priv)
  1353. {
  1354. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  1355. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1356. if (priv->cfg->mod_params->amsdu_size_8K)
  1357. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
  1358. else
  1359. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
  1360. priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
  1361. if (priv->cfg->mod_params->disable_11n)
  1362. priv->cfg->sku &= ~IWL_SKU_N;
  1363. /* Device-specific setup */
  1364. return priv->cfg->ops->lib->set_hw_params(priv);
  1365. }
  1366. EXPORT_SYMBOL(iwl_set_hw_params);
  1367. int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
  1368. {
  1369. int ret = 0;
  1370. s8 prev_tx_power = priv->tx_power_user_lmt;
  1371. if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
  1372. IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
  1373. tx_power,
  1374. IWL_TX_POWER_TARGET_POWER_MIN);
  1375. return -EINVAL;
  1376. }
  1377. if (tx_power > priv->tx_power_device_lmt) {
  1378. IWL_WARN(priv,
  1379. "Requested user TXPOWER %d above upper limit %d.\n",
  1380. tx_power, priv->tx_power_device_lmt);
  1381. return -EINVAL;
  1382. }
  1383. if (priv->tx_power_user_lmt != tx_power)
  1384. force = true;
  1385. /* if nic is not up don't send command */
  1386. if (iwl_is_ready_rf(priv)) {
  1387. priv->tx_power_user_lmt = tx_power;
  1388. if (force && priv->cfg->ops->lib->send_tx_power)
  1389. ret = priv->cfg->ops->lib->send_tx_power(priv);
  1390. else if (!priv->cfg->ops->lib->send_tx_power)
  1391. ret = -EOPNOTSUPP;
  1392. /*
  1393. * if fail to set tx_power, restore the orig. tx power
  1394. */
  1395. if (ret)
  1396. priv->tx_power_user_lmt = prev_tx_power;
  1397. }
  1398. /*
  1399. * Even this is an async host command, the command
  1400. * will always report success from uCode
  1401. * So once driver can placing the command into the queue
  1402. * successfully, driver can use priv->tx_power_user_lmt
  1403. * to reflect the current tx power
  1404. */
  1405. return ret;
  1406. }
  1407. EXPORT_SYMBOL(iwl_set_tx_power);
  1408. #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
  1409. /* Free dram table */
  1410. void iwl_free_isr_ict(struct iwl_priv *priv)
  1411. {
  1412. if (priv->ict_tbl_vir) {
  1413. pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
  1414. PAGE_SIZE, priv->ict_tbl_vir,
  1415. priv->ict_tbl_dma);
  1416. priv->ict_tbl_vir = NULL;
  1417. }
  1418. }
  1419. EXPORT_SYMBOL(iwl_free_isr_ict);
  1420. /* allocate dram shared table it is a PAGE_SIZE aligned
  1421. * also reset all data related to ICT table interrupt.
  1422. */
  1423. int iwl_alloc_isr_ict(struct iwl_priv *priv)
  1424. {
  1425. if (priv->cfg->use_isr_legacy)
  1426. return 0;
  1427. /* allocate shrared data table */
  1428. priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
  1429. ICT_COUNT) + PAGE_SIZE,
  1430. &priv->ict_tbl_dma);
  1431. if (!priv->ict_tbl_vir)
  1432. return -ENOMEM;
  1433. /* align table to PAGE_SIZE boundry */
  1434. priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
  1435. IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
  1436. (unsigned long long)priv->ict_tbl_dma,
  1437. (unsigned long long)priv->aligned_ict_tbl_dma,
  1438. (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
  1439. priv->ict_tbl = priv->ict_tbl_vir +
  1440. (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
  1441. IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
  1442. priv->ict_tbl, priv->ict_tbl_vir,
  1443. (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
  1444. /* reset table and index to all 0 */
  1445. memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
  1446. priv->ict_index = 0;
  1447. /* add periodic RX interrupt */
  1448. priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
  1449. return 0;
  1450. }
  1451. EXPORT_SYMBOL(iwl_alloc_isr_ict);
  1452. /* Device is going up inform it about using ICT interrupt table,
  1453. * also we need to tell the driver to start using ICT interrupt.
  1454. */
  1455. int iwl_reset_ict(struct iwl_priv *priv)
  1456. {
  1457. u32 val;
  1458. unsigned long flags;
  1459. if (!priv->ict_tbl_vir)
  1460. return 0;
  1461. spin_lock_irqsave(&priv->lock, flags);
  1462. iwl_disable_interrupts(priv);
  1463. memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
  1464. val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
  1465. val |= CSR_DRAM_INT_TBL_ENABLE;
  1466. val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
  1467. IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
  1468. "aligned dma address %Lx\n",
  1469. val, (unsigned long long)priv->aligned_ict_tbl_dma);
  1470. iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
  1471. priv->use_ict = true;
  1472. priv->ict_index = 0;
  1473. iwl_write32(priv, CSR_INT, priv->inta_mask);
  1474. iwl_enable_interrupts(priv);
  1475. spin_unlock_irqrestore(&priv->lock, flags);
  1476. return 0;
  1477. }
  1478. EXPORT_SYMBOL(iwl_reset_ict);
  1479. /* Device is going down disable ict interrupt usage */
  1480. void iwl_disable_ict(struct iwl_priv *priv)
  1481. {
  1482. unsigned long flags;
  1483. spin_lock_irqsave(&priv->lock, flags);
  1484. priv->use_ict = false;
  1485. spin_unlock_irqrestore(&priv->lock, flags);
  1486. }
  1487. EXPORT_SYMBOL(iwl_disable_ict);
  1488. /* interrupt handler using ict table, with this interrupt driver will
  1489. * stop using INTA register to get device's interrupt, reading this register
  1490. * is expensive, device will write interrupts in ICT dram table, increment
  1491. * index then will fire interrupt to driver, driver will OR all ICT table
  1492. * entries from current index up to table entry with 0 value. the result is
  1493. * the interrupt we need to service, driver will set the entries back to 0 and
  1494. * set index.
  1495. */
  1496. irqreturn_t iwl_isr_ict(int irq, void *data)
  1497. {
  1498. struct iwl_priv *priv = data;
  1499. u32 inta, inta_mask;
  1500. u32 val = 0;
  1501. if (!priv)
  1502. return IRQ_NONE;
  1503. /* dram interrupt table not set yet,
  1504. * use legacy interrupt.
  1505. */
  1506. if (!priv->use_ict)
  1507. return iwl_isr(irq, data);
  1508. spin_lock(&priv->lock);
  1509. /* Disable (but don't clear!) interrupts here to avoid
  1510. * back-to-back ISRs and sporadic interrupts from our NIC.
  1511. * If we have something to service, the tasklet will re-enable ints.
  1512. * If we *don't* have something, we'll re-enable before leaving here.
  1513. */
  1514. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1515. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1516. /* Ignore interrupt if there's nothing in NIC to service.
  1517. * This may be due to IRQ shared with another device,
  1518. * or due to sporadic interrupts thrown from our NIC. */
  1519. if (!priv->ict_tbl[priv->ict_index]) {
  1520. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
  1521. goto none;
  1522. }
  1523. /* read all entries that not 0 start with ict_index */
  1524. while (priv->ict_tbl[priv->ict_index]) {
  1525. val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
  1526. IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
  1527. priv->ict_index,
  1528. le32_to_cpu(priv->ict_tbl[priv->ict_index]));
  1529. priv->ict_tbl[priv->ict_index] = 0;
  1530. priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
  1531. ICT_COUNT);
  1532. }
  1533. /* We should not get this value, just ignore it. */
  1534. if (val == 0xffffffff)
  1535. val = 0;
  1536. inta = (0xff & val) | ((0xff00 & val) << 16);
  1537. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
  1538. inta, inta_mask, val);
  1539. inta &= priv->inta_mask;
  1540. priv->inta |= inta;
  1541. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1542. if (likely(inta))
  1543. tasklet_schedule(&priv->irq_tasklet);
  1544. else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
  1545. /* Allow interrupt if was disabled by this handler and
  1546. * no tasklet was schedules, We should not enable interrupt,
  1547. * tasklet will enable it.
  1548. */
  1549. iwl_enable_interrupts(priv);
  1550. }
  1551. spin_unlock(&priv->lock);
  1552. return IRQ_HANDLED;
  1553. none:
  1554. /* re-enable interrupts here since we don't have anything to service.
  1555. * only Re-enable if disabled by irq.
  1556. */
  1557. if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1558. iwl_enable_interrupts(priv);
  1559. spin_unlock(&priv->lock);
  1560. return IRQ_NONE;
  1561. }
  1562. EXPORT_SYMBOL(iwl_isr_ict);
  1563. static irqreturn_t iwl_isr(int irq, void *data)
  1564. {
  1565. struct iwl_priv *priv = data;
  1566. u32 inta, inta_mask;
  1567. #ifdef CONFIG_IWLWIFI_DEBUG
  1568. u32 inta_fh;
  1569. #endif
  1570. if (!priv)
  1571. return IRQ_NONE;
  1572. spin_lock(&priv->lock);
  1573. /* Disable (but don't clear!) interrupts here to avoid
  1574. * back-to-back ISRs and sporadic interrupts from our NIC.
  1575. * If we have something to service, the tasklet will re-enable ints.
  1576. * If we *don't* have something, we'll re-enable before leaving here. */
  1577. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1578. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1579. /* Discover which interrupts are active/pending */
  1580. inta = iwl_read32(priv, CSR_INT);
  1581. /* Ignore interrupt if there's nothing in NIC to service.
  1582. * This may be due to IRQ shared with another device,
  1583. * or due to sporadic interrupts thrown from our NIC. */
  1584. if (!inta) {
  1585. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
  1586. goto none;
  1587. }
  1588. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1589. /* Hardware disappeared. It might have already raised
  1590. * an interrupt */
  1591. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1592. goto unplugged;
  1593. }
  1594. #ifdef CONFIG_IWLWIFI_DEBUG
  1595. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1596. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1597. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
  1598. "fh 0x%08x\n", inta, inta_mask, inta_fh);
  1599. }
  1600. #endif
  1601. priv->inta |= inta;
  1602. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1603. if (likely(inta))
  1604. tasklet_schedule(&priv->irq_tasklet);
  1605. else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1606. iwl_enable_interrupts(priv);
  1607. unplugged:
  1608. spin_unlock(&priv->lock);
  1609. return IRQ_HANDLED;
  1610. none:
  1611. /* re-enable interrupts here since we don't have anything to service. */
  1612. /* only Re-enable if diabled by irq and no schedules tasklet. */
  1613. if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1614. iwl_enable_interrupts(priv);
  1615. spin_unlock(&priv->lock);
  1616. return IRQ_NONE;
  1617. }
  1618. irqreturn_t iwl_isr_legacy(int irq, void *data)
  1619. {
  1620. struct iwl_priv *priv = data;
  1621. u32 inta, inta_mask;
  1622. u32 inta_fh;
  1623. if (!priv)
  1624. return IRQ_NONE;
  1625. spin_lock(&priv->lock);
  1626. /* Disable (but don't clear!) interrupts here to avoid
  1627. * back-to-back ISRs and sporadic interrupts from our NIC.
  1628. * If we have something to service, the tasklet will re-enable ints.
  1629. * If we *don't* have something, we'll re-enable before leaving here. */
  1630. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1631. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1632. /* Discover which interrupts are active/pending */
  1633. inta = iwl_read32(priv, CSR_INT);
  1634. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1635. /* Ignore interrupt if there's nothing in NIC to service.
  1636. * This may be due to IRQ shared with another device,
  1637. * or due to sporadic interrupts thrown from our NIC. */
  1638. if (!inta && !inta_fh) {
  1639. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
  1640. goto none;
  1641. }
  1642. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1643. /* Hardware disappeared. It might have already raised
  1644. * an interrupt */
  1645. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1646. goto unplugged;
  1647. }
  1648. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1649. inta, inta_mask, inta_fh);
  1650. inta &= ~CSR_INT_BIT_SCD;
  1651. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1652. if (likely(inta || inta_fh))
  1653. tasklet_schedule(&priv->irq_tasklet);
  1654. unplugged:
  1655. spin_unlock(&priv->lock);
  1656. return IRQ_HANDLED;
  1657. none:
  1658. /* re-enable interrupts here since we don't have anything to service. */
  1659. /* only Re-enable if diabled by irq */
  1660. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1661. iwl_enable_interrupts(priv);
  1662. spin_unlock(&priv->lock);
  1663. return IRQ_NONE;
  1664. }
  1665. EXPORT_SYMBOL(iwl_isr_legacy);
  1666. int iwl_send_bt_config(struct iwl_priv *priv)
  1667. {
  1668. struct iwl_bt_cmd bt_cmd = {
  1669. .flags = BT_COEX_MODE_4W,
  1670. .lead_time = BT_LEAD_TIME_DEF,
  1671. .max_kill = BT_MAX_KILL_DEF,
  1672. .kill_ack_mask = 0,
  1673. .kill_cts_mask = 0,
  1674. };
  1675. return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1676. sizeof(struct iwl_bt_cmd), &bt_cmd);
  1677. }
  1678. EXPORT_SYMBOL(iwl_send_bt_config);
  1679. int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear)
  1680. {
  1681. struct iwl_statistics_cmd statistics_cmd = {
  1682. .configuration_flags =
  1683. clear ? IWL_STATS_CONF_CLEAR_STATS : 0,
  1684. };
  1685. if (flags & CMD_ASYNC)
  1686. return iwl_send_cmd_pdu_async(priv, REPLY_STATISTICS_CMD,
  1687. sizeof(struct iwl_statistics_cmd),
  1688. &statistics_cmd, NULL);
  1689. else
  1690. return iwl_send_cmd_pdu(priv, REPLY_STATISTICS_CMD,
  1691. sizeof(struct iwl_statistics_cmd),
  1692. &statistics_cmd);
  1693. }
  1694. EXPORT_SYMBOL(iwl_send_statistics_request);
  1695. /**
  1696. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1697. * using sample data 100 bytes apart. If these sample points are good,
  1698. * it's a pretty good bet that everything between them is good, too.
  1699. */
  1700. static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  1701. {
  1702. u32 val;
  1703. int ret = 0;
  1704. u32 errcnt = 0;
  1705. u32 i;
  1706. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1707. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1708. /* read data comes through single port, auto-incr addr */
  1709. /* NOTE: Use the debugless read so we don't flood kernel log
  1710. * if IWL_DL_IO is set */
  1711. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1712. i + IWL49_RTC_INST_LOWER_BOUND);
  1713. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1714. if (val != le32_to_cpu(*image)) {
  1715. ret = -EIO;
  1716. errcnt++;
  1717. if (errcnt >= 3)
  1718. break;
  1719. }
  1720. }
  1721. return ret;
  1722. }
  1723. /**
  1724. * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
  1725. * looking at all data.
  1726. */
  1727. static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
  1728. u32 len)
  1729. {
  1730. u32 val;
  1731. u32 save_len = len;
  1732. int ret = 0;
  1733. u32 errcnt;
  1734. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1735. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1736. IWL49_RTC_INST_LOWER_BOUND);
  1737. errcnt = 0;
  1738. for (; len > 0; len -= sizeof(u32), image++) {
  1739. /* read data comes through single port, auto-incr addr */
  1740. /* NOTE: Use the debugless read so we don't flood kernel log
  1741. * if IWL_DL_IO is set */
  1742. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1743. if (val != le32_to_cpu(*image)) {
  1744. IWL_ERR(priv, "uCode INST section is invalid at "
  1745. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1746. save_len - len, val, le32_to_cpu(*image));
  1747. ret = -EIO;
  1748. errcnt++;
  1749. if (errcnt >= 20)
  1750. break;
  1751. }
  1752. }
  1753. if (!errcnt)
  1754. IWL_DEBUG_INFO(priv,
  1755. "ucode image in INSTRUCTION memory is good\n");
  1756. return ret;
  1757. }
  1758. /**
  1759. * iwl_verify_ucode - determine which instruction image is in SRAM,
  1760. * and verify its contents
  1761. */
  1762. int iwl_verify_ucode(struct iwl_priv *priv)
  1763. {
  1764. __le32 *image;
  1765. u32 len;
  1766. int ret;
  1767. /* Try bootstrap */
  1768. image = (__le32 *)priv->ucode_boot.v_addr;
  1769. len = priv->ucode_boot.len;
  1770. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1771. if (!ret) {
  1772. IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
  1773. return 0;
  1774. }
  1775. /* Try initialize */
  1776. image = (__le32 *)priv->ucode_init.v_addr;
  1777. len = priv->ucode_init.len;
  1778. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1779. if (!ret) {
  1780. IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
  1781. return 0;
  1782. }
  1783. /* Try runtime/protocol */
  1784. image = (__le32 *)priv->ucode_code.v_addr;
  1785. len = priv->ucode_code.len;
  1786. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1787. if (!ret) {
  1788. IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
  1789. return 0;
  1790. }
  1791. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1792. /* Since nothing seems to match, show first several data entries in
  1793. * instruction SRAM, so maybe visual inspection will give a clue.
  1794. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1795. image = (__le32 *)priv->ucode_boot.v_addr;
  1796. len = priv->ucode_boot.len;
  1797. ret = iwl_verify_inst_full(priv, image, len);
  1798. return ret;
  1799. }
  1800. EXPORT_SYMBOL(iwl_verify_ucode);
  1801. void iwl_rf_kill_ct_config(struct iwl_priv *priv)
  1802. {
  1803. struct iwl_ct_kill_config cmd;
  1804. struct iwl_ct_kill_throttling_config adv_cmd;
  1805. unsigned long flags;
  1806. int ret = 0;
  1807. spin_lock_irqsave(&priv->lock, flags);
  1808. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1809. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  1810. spin_unlock_irqrestore(&priv->lock, flags);
  1811. priv->thermal_throttle.ct_kill_toggle = false;
  1812. if (priv->cfg->support_ct_kill_exit) {
  1813. adv_cmd.critical_temperature_enter =
  1814. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1815. adv_cmd.critical_temperature_exit =
  1816. cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
  1817. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1818. sizeof(adv_cmd), &adv_cmd);
  1819. if (ret)
  1820. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1821. else
  1822. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1823. "succeeded, "
  1824. "critical temperature enter is %d,"
  1825. "exit is %d\n",
  1826. priv->hw_params.ct_kill_threshold,
  1827. priv->hw_params.ct_kill_exit_threshold);
  1828. } else {
  1829. cmd.critical_temperature_R =
  1830. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1831. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1832. sizeof(cmd), &cmd);
  1833. if (ret)
  1834. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1835. else
  1836. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1837. "succeeded, "
  1838. "critical temperature is %d\n",
  1839. priv->hw_params.ct_kill_threshold);
  1840. }
  1841. }
  1842. EXPORT_SYMBOL(iwl_rf_kill_ct_config);
  1843. /*
  1844. * CARD_STATE_CMD
  1845. *
  1846. * Use: Sets the device's internal card state to enable, disable, or halt
  1847. *
  1848. * When in the 'enable' state the card operates as normal.
  1849. * When in the 'disable' state, the card enters into a low power mode.
  1850. * When in the 'halt' state, the card is shut down and must be fully
  1851. * restarted to come back on.
  1852. */
  1853. int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
  1854. {
  1855. struct iwl_host_cmd cmd = {
  1856. .id = REPLY_CARD_STATE_CMD,
  1857. .len = sizeof(u32),
  1858. .data = &flags,
  1859. .flags = meta_flag,
  1860. };
  1861. return iwl_send_cmd(priv, &cmd);
  1862. }
  1863. void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
  1864. struct iwl_rx_mem_buffer *rxb)
  1865. {
  1866. #ifdef CONFIG_IWLWIFI_DEBUG
  1867. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1868. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  1869. IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
  1870. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  1871. #endif
  1872. }
  1873. EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
  1874. void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  1875. struct iwl_rx_mem_buffer *rxb)
  1876. {
  1877. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1878. u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  1879. IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
  1880. "notification for %s:\n", len,
  1881. get_cmd_string(pkt->hdr.cmd));
  1882. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len);
  1883. }
  1884. EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
  1885. void iwl_rx_reply_error(struct iwl_priv *priv,
  1886. struct iwl_rx_mem_buffer *rxb)
  1887. {
  1888. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1889. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  1890. "seq 0x%04X ser 0x%08X\n",
  1891. le32_to_cpu(pkt->u.err_resp.error_type),
  1892. get_cmd_string(pkt->u.err_resp.cmd_id),
  1893. pkt->u.err_resp.cmd_id,
  1894. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  1895. le32_to_cpu(pkt->u.err_resp.error_info));
  1896. }
  1897. EXPORT_SYMBOL(iwl_rx_reply_error);
  1898. void iwl_clear_isr_stats(struct iwl_priv *priv)
  1899. {
  1900. memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
  1901. }
  1902. int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1903. const struct ieee80211_tx_queue_params *params)
  1904. {
  1905. struct iwl_priv *priv = hw->priv;
  1906. unsigned long flags;
  1907. int q;
  1908. IWL_DEBUG_MAC80211(priv, "enter\n");
  1909. if (!iwl_is_ready_rf(priv)) {
  1910. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  1911. return -EIO;
  1912. }
  1913. if (queue >= AC_NUM) {
  1914. IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
  1915. return 0;
  1916. }
  1917. q = AC_NUM - 1 - queue;
  1918. spin_lock_irqsave(&priv->lock, flags);
  1919. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  1920. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  1921. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  1922. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  1923. cpu_to_le16((params->txop * 32));
  1924. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  1925. priv->qos_data.qos_active = 1;
  1926. if (priv->iw_mode == NL80211_IFTYPE_AP)
  1927. iwl_activate_qos(priv, 1);
  1928. else if (priv->assoc_id && iwl_is_associated(priv))
  1929. iwl_activate_qos(priv, 0);
  1930. spin_unlock_irqrestore(&priv->lock, flags);
  1931. IWL_DEBUG_MAC80211(priv, "leave\n");
  1932. return 0;
  1933. }
  1934. EXPORT_SYMBOL(iwl_mac_conf_tx);
  1935. static void iwl_ht_conf(struct iwl_priv *priv,
  1936. struct ieee80211_bss_conf *bss_conf)
  1937. {
  1938. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  1939. struct ieee80211_sta *sta;
  1940. IWL_DEBUG_MAC80211(priv, "enter: \n");
  1941. if (!ht_conf->is_ht)
  1942. return;
  1943. ht_conf->ht_protection =
  1944. bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
  1945. ht_conf->non_GF_STA_present =
  1946. !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  1947. ht_conf->single_chain_sufficient = false;
  1948. switch (priv->iw_mode) {
  1949. case NL80211_IFTYPE_STATION:
  1950. rcu_read_lock();
  1951. sta = ieee80211_find_sta(priv->vif, priv->bssid);
  1952. if (sta) {
  1953. struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
  1954. int maxstreams;
  1955. maxstreams = (ht_cap->mcs.tx_params &
  1956. IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
  1957. >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  1958. maxstreams += 1;
  1959. if ((ht_cap->mcs.rx_mask[1] == 0) &&
  1960. (ht_cap->mcs.rx_mask[2] == 0))
  1961. ht_conf->single_chain_sufficient = true;
  1962. if (maxstreams <= 1)
  1963. ht_conf->single_chain_sufficient = true;
  1964. } else {
  1965. /*
  1966. * If at all, this can only happen through a race
  1967. * when the AP disconnects us while we're still
  1968. * setting up the connection, in that case mac80211
  1969. * will soon tell us about that.
  1970. */
  1971. ht_conf->single_chain_sufficient = true;
  1972. }
  1973. rcu_read_unlock();
  1974. break;
  1975. case NL80211_IFTYPE_ADHOC:
  1976. ht_conf->single_chain_sufficient = true;
  1977. break;
  1978. default:
  1979. break;
  1980. }
  1981. IWL_DEBUG_MAC80211(priv, "leave\n");
  1982. }
  1983. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  1984. void iwl_bss_info_changed(struct ieee80211_hw *hw,
  1985. struct ieee80211_vif *vif,
  1986. struct ieee80211_bss_conf *bss_conf,
  1987. u32 changes)
  1988. {
  1989. struct iwl_priv *priv = hw->priv;
  1990. int ret;
  1991. IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
  1992. if (!iwl_is_alive(priv))
  1993. return;
  1994. mutex_lock(&priv->mutex);
  1995. if (changes & BSS_CHANGED_BEACON &&
  1996. priv->iw_mode == NL80211_IFTYPE_AP) {
  1997. dev_kfree_skb(priv->ibss_beacon);
  1998. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  1999. }
  2000. if (changes & BSS_CHANGED_BEACON_INT) {
  2001. priv->beacon_int = bss_conf->beacon_int;
  2002. /* TODO: in AP mode, do something to make this take effect */
  2003. }
  2004. if (changes & BSS_CHANGED_BSSID) {
  2005. IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
  2006. /*
  2007. * If there is currently a HW scan going on in the
  2008. * background then we need to cancel it else the RXON
  2009. * below/in post_associate will fail.
  2010. */
  2011. if (iwl_scan_cancel_timeout(priv, 100)) {
  2012. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  2013. IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
  2014. mutex_unlock(&priv->mutex);
  2015. return;
  2016. }
  2017. /* mac80211 only sets assoc when in STATION mode */
  2018. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  2019. bss_conf->assoc) {
  2020. memcpy(priv->staging_rxon.bssid_addr,
  2021. bss_conf->bssid, ETH_ALEN);
  2022. /* currently needed in a few places */
  2023. memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
  2024. } else {
  2025. priv->staging_rxon.filter_flags &=
  2026. ~RXON_FILTER_ASSOC_MSK;
  2027. }
  2028. }
  2029. /*
  2030. * This needs to be after setting the BSSID in case
  2031. * mac80211 decides to do both changes at once because
  2032. * it will invoke post_associate.
  2033. */
  2034. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  2035. changes & BSS_CHANGED_BEACON) {
  2036. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  2037. if (beacon)
  2038. iwl_mac_beacon_update(hw, beacon);
  2039. }
  2040. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  2041. IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
  2042. bss_conf->use_short_preamble);
  2043. if (bss_conf->use_short_preamble)
  2044. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2045. else
  2046. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2047. }
  2048. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  2049. IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
  2050. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  2051. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  2052. else
  2053. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  2054. }
  2055. if (changes & BSS_CHANGED_BASIC_RATES) {
  2056. /* XXX use this information
  2057. *
  2058. * To do that, remove code from iwl_set_rate() and put something
  2059. * like this here:
  2060. *
  2061. if (A-band)
  2062. priv->staging_rxon.ofdm_basic_rates =
  2063. bss_conf->basic_rates;
  2064. else
  2065. priv->staging_rxon.ofdm_basic_rates =
  2066. bss_conf->basic_rates >> 4;
  2067. priv->staging_rxon.cck_basic_rates =
  2068. bss_conf->basic_rates & 0xF;
  2069. */
  2070. }
  2071. if (changes & BSS_CHANGED_HT) {
  2072. iwl_ht_conf(priv, bss_conf);
  2073. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2074. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2075. }
  2076. if (changes & BSS_CHANGED_ASSOC) {
  2077. IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
  2078. if (bss_conf->assoc) {
  2079. priv->assoc_id = bss_conf->aid;
  2080. priv->beacon_int = bss_conf->beacon_int;
  2081. priv->timestamp = bss_conf->timestamp;
  2082. priv->assoc_capability = bss_conf->assoc_capability;
  2083. iwl_led_associate(priv);
  2084. /*
  2085. * We have just associated, don't start scan too early
  2086. * leave time for EAPOL exchange to complete.
  2087. *
  2088. * XXX: do this in mac80211
  2089. */
  2090. priv->next_scan_jiffies = jiffies +
  2091. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  2092. if (!iwl_is_rfkill(priv))
  2093. priv->cfg->ops->lib->post_associate(priv);
  2094. } else {
  2095. priv->assoc_id = 0;
  2096. iwl_led_disassociate(priv);
  2097. /*
  2098. * inform the ucode that there is no longer an
  2099. * association and that no more packets should be
  2100. * send
  2101. */
  2102. priv->staging_rxon.filter_flags &=
  2103. ~RXON_FILTER_ASSOC_MSK;
  2104. priv->staging_rxon.assoc_id = 0;
  2105. iwlcore_commit_rxon(priv);
  2106. }
  2107. }
  2108. if (changes && iwl_is_associated(priv) && priv->assoc_id) {
  2109. IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
  2110. changes);
  2111. ret = iwl_send_rxon_assoc(priv);
  2112. if (!ret) {
  2113. /* Sync active_rxon with latest change. */
  2114. memcpy((void *)&priv->active_rxon,
  2115. &priv->staging_rxon,
  2116. sizeof(struct iwl_rxon_cmd));
  2117. }
  2118. }
  2119. if ((changes & BSS_CHANGED_BEACON_ENABLED) &&
  2120. vif->bss_conf.enable_beacon) {
  2121. memcpy(priv->staging_rxon.bssid_addr,
  2122. bss_conf->bssid, ETH_ALEN);
  2123. memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
  2124. iwlcore_config_ap(priv);
  2125. }
  2126. mutex_unlock(&priv->mutex);
  2127. IWL_DEBUG_MAC80211(priv, "leave\n");
  2128. }
  2129. EXPORT_SYMBOL(iwl_bss_info_changed);
  2130. int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  2131. {
  2132. struct iwl_priv *priv = hw->priv;
  2133. unsigned long flags;
  2134. __le64 timestamp;
  2135. IWL_DEBUG_MAC80211(priv, "enter\n");
  2136. if (!iwl_is_ready_rf(priv)) {
  2137. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2138. return -EIO;
  2139. }
  2140. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  2141. IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
  2142. return -EIO;
  2143. }
  2144. spin_lock_irqsave(&priv->lock, flags);
  2145. if (priv->ibss_beacon)
  2146. dev_kfree_skb(priv->ibss_beacon);
  2147. priv->ibss_beacon = skb;
  2148. priv->assoc_id = 0;
  2149. timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
  2150. priv->timestamp = le64_to_cpu(timestamp);
  2151. IWL_DEBUG_MAC80211(priv, "leave\n");
  2152. spin_unlock_irqrestore(&priv->lock, flags);
  2153. iwl_reset_qos(priv);
  2154. priv->cfg->ops->lib->post_associate(priv);
  2155. return 0;
  2156. }
  2157. EXPORT_SYMBOL(iwl_mac_beacon_update);
  2158. int iwl_set_mode(struct iwl_priv *priv, int mode)
  2159. {
  2160. if (mode == NL80211_IFTYPE_ADHOC) {
  2161. const struct iwl_channel_info *ch_info;
  2162. ch_info = iwl_get_channel_info(priv,
  2163. priv->band,
  2164. le16_to_cpu(priv->staging_rxon.channel));
  2165. if (!ch_info || !is_channel_ibss(ch_info)) {
  2166. IWL_ERR(priv, "channel %d not IBSS channel\n",
  2167. le16_to_cpu(priv->staging_rxon.channel));
  2168. return -EINVAL;
  2169. }
  2170. }
  2171. iwl_connection_init_rx_config(priv, mode);
  2172. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2173. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2174. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2175. iwl_clear_stations_table(priv);
  2176. /* dont commit rxon if rf-kill is on*/
  2177. if (!iwl_is_ready_rf(priv))
  2178. return -EAGAIN;
  2179. iwlcore_commit_rxon(priv);
  2180. return 0;
  2181. }
  2182. EXPORT_SYMBOL(iwl_set_mode);
  2183. int iwl_mac_add_interface(struct ieee80211_hw *hw,
  2184. struct ieee80211_if_init_conf *conf)
  2185. {
  2186. struct iwl_priv *priv = hw->priv;
  2187. unsigned long flags;
  2188. IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
  2189. if (priv->vif) {
  2190. IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
  2191. return -EOPNOTSUPP;
  2192. }
  2193. spin_lock_irqsave(&priv->lock, flags);
  2194. priv->vif = conf->vif;
  2195. priv->iw_mode = conf->type;
  2196. spin_unlock_irqrestore(&priv->lock, flags);
  2197. mutex_lock(&priv->mutex);
  2198. if (conf->mac_addr) {
  2199. IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
  2200. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  2201. }
  2202. if (iwl_set_mode(priv, conf->type) == -EAGAIN)
  2203. /* we are not ready, will run again when ready */
  2204. set_bit(STATUS_MODE_PENDING, &priv->status);
  2205. mutex_unlock(&priv->mutex);
  2206. IWL_DEBUG_MAC80211(priv, "leave\n");
  2207. return 0;
  2208. }
  2209. EXPORT_SYMBOL(iwl_mac_add_interface);
  2210. void iwl_mac_remove_interface(struct ieee80211_hw *hw,
  2211. struct ieee80211_if_init_conf *conf)
  2212. {
  2213. struct iwl_priv *priv = hw->priv;
  2214. IWL_DEBUG_MAC80211(priv, "enter\n");
  2215. mutex_lock(&priv->mutex);
  2216. if (iwl_is_ready_rf(priv)) {
  2217. iwl_scan_cancel_timeout(priv, 100);
  2218. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2219. iwlcore_commit_rxon(priv);
  2220. }
  2221. if (priv->vif == conf->vif) {
  2222. priv->vif = NULL;
  2223. memset(priv->bssid, 0, ETH_ALEN);
  2224. }
  2225. mutex_unlock(&priv->mutex);
  2226. IWL_DEBUG_MAC80211(priv, "leave\n");
  2227. }
  2228. EXPORT_SYMBOL(iwl_mac_remove_interface);
  2229. /**
  2230. * iwl_mac_config - mac80211 config callback
  2231. *
  2232. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  2233. * be set inappropriately and the driver currently sets the hardware up to
  2234. * use it whenever needed.
  2235. */
  2236. int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
  2237. {
  2238. struct iwl_priv *priv = hw->priv;
  2239. const struct iwl_channel_info *ch_info;
  2240. struct ieee80211_conf *conf = &hw->conf;
  2241. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  2242. unsigned long flags = 0;
  2243. int ret = 0;
  2244. u16 ch;
  2245. int scan_active = 0;
  2246. mutex_lock(&priv->mutex);
  2247. IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
  2248. conf->channel->hw_value, changed);
  2249. if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
  2250. test_bit(STATUS_SCANNING, &priv->status))) {
  2251. scan_active = 1;
  2252. IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
  2253. }
  2254. /* during scanning mac80211 will delay channel setting until
  2255. * scan finish with changed = 0
  2256. */
  2257. if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  2258. if (scan_active)
  2259. goto set_ch_out;
  2260. ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
  2261. ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
  2262. if (!is_channel_valid(ch_info)) {
  2263. IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
  2264. ret = -EINVAL;
  2265. goto set_ch_out;
  2266. }
  2267. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  2268. !is_channel_ibss(ch_info)) {
  2269. IWL_ERR(priv, "channel %d in band %d not "
  2270. "IBSS channel\n",
  2271. conf->channel->hw_value, conf->channel->band);
  2272. ret = -EINVAL;
  2273. goto set_ch_out;
  2274. }
  2275. spin_lock_irqsave(&priv->lock, flags);
  2276. /* Configure HT40 channels */
  2277. ht_conf->is_ht = conf_is_ht(conf);
  2278. if (ht_conf->is_ht) {
  2279. if (conf_is_ht40_minus(conf)) {
  2280. ht_conf->extension_chan_offset =
  2281. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  2282. ht_conf->is_40mhz = true;
  2283. } else if (conf_is_ht40_plus(conf)) {
  2284. ht_conf->extension_chan_offset =
  2285. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  2286. ht_conf->is_40mhz = true;
  2287. } else {
  2288. ht_conf->extension_chan_offset =
  2289. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  2290. ht_conf->is_40mhz = false;
  2291. }
  2292. } else
  2293. ht_conf->is_40mhz = false;
  2294. /* Default to no protection. Protection mode will later be set
  2295. * from BSS config in iwl_ht_conf */
  2296. ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
  2297. /* if we are switching from ht to 2.4 clear flags
  2298. * from any ht related info since 2.4 does not
  2299. * support ht */
  2300. if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
  2301. priv->staging_rxon.flags = 0;
  2302. iwl_set_rxon_channel(priv, conf->channel);
  2303. iwl_set_flags_for_band(priv, conf->channel->band);
  2304. spin_unlock_irqrestore(&priv->lock, flags);
  2305. if (iwl_is_associated(priv) &&
  2306. (le16_to_cpu(priv->active_rxon.channel) != ch) &&
  2307. priv->cfg->ops->lib->set_channel_switch) {
  2308. iwl_set_rate(priv);
  2309. /*
  2310. * at this point, staging_rxon has the
  2311. * configuration for channel switch
  2312. */
  2313. ret = priv->cfg->ops->lib->set_channel_switch(priv,
  2314. ch);
  2315. if (!ret) {
  2316. iwl_print_rx_config_cmd(priv);
  2317. goto out;
  2318. }
  2319. priv->switch_rxon.switch_in_progress = false;
  2320. }
  2321. set_ch_out:
  2322. /* The list of supported rates and rate mask can be different
  2323. * for each band; since the band may have changed, reset
  2324. * the rate mask to what mac80211 lists */
  2325. iwl_set_rate(priv);
  2326. }
  2327. if (changed & (IEEE80211_CONF_CHANGE_PS |
  2328. IEEE80211_CONF_CHANGE_IDLE)) {
  2329. ret = iwl_power_update_mode(priv, false);
  2330. if (ret)
  2331. IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
  2332. }
  2333. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  2334. IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
  2335. priv->tx_power_user_lmt, conf->power_level);
  2336. iwl_set_tx_power(priv, conf->power_level, false);
  2337. }
  2338. /* call to ensure that 4965 rx_chain is set properly in monitor mode */
  2339. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2340. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2341. if (!iwl_is_ready(priv)) {
  2342. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2343. goto out;
  2344. }
  2345. if (scan_active)
  2346. goto out;
  2347. if (memcmp(&priv->active_rxon,
  2348. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  2349. iwlcore_commit_rxon(priv);
  2350. else
  2351. IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
  2352. out:
  2353. IWL_DEBUG_MAC80211(priv, "leave\n");
  2354. mutex_unlock(&priv->mutex);
  2355. return ret;
  2356. }
  2357. EXPORT_SYMBOL(iwl_mac_config);
  2358. int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
  2359. struct ieee80211_tx_queue_stats *stats)
  2360. {
  2361. struct iwl_priv *priv = hw->priv;
  2362. int i, avail;
  2363. struct iwl_tx_queue *txq;
  2364. struct iwl_queue *q;
  2365. unsigned long flags;
  2366. IWL_DEBUG_MAC80211(priv, "enter\n");
  2367. if (!iwl_is_ready_rf(priv)) {
  2368. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2369. return -EIO;
  2370. }
  2371. spin_lock_irqsave(&priv->lock, flags);
  2372. for (i = 0; i < AC_NUM; i++) {
  2373. txq = &priv->txq[i];
  2374. q = &txq->q;
  2375. avail = iwl_queue_space(q);
  2376. stats[i].len = q->n_window - avail;
  2377. stats[i].limit = q->n_window - q->high_mark;
  2378. stats[i].count = q->n_window;
  2379. }
  2380. spin_unlock_irqrestore(&priv->lock, flags);
  2381. IWL_DEBUG_MAC80211(priv, "leave\n");
  2382. return 0;
  2383. }
  2384. EXPORT_SYMBOL(iwl_mac_get_tx_stats);
  2385. void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
  2386. {
  2387. struct iwl_priv *priv = hw->priv;
  2388. unsigned long flags;
  2389. mutex_lock(&priv->mutex);
  2390. IWL_DEBUG_MAC80211(priv, "enter\n");
  2391. spin_lock_irqsave(&priv->lock, flags);
  2392. memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
  2393. spin_unlock_irqrestore(&priv->lock, flags);
  2394. iwl_reset_qos(priv);
  2395. spin_lock_irqsave(&priv->lock, flags);
  2396. priv->assoc_id = 0;
  2397. priv->assoc_capability = 0;
  2398. priv->assoc_station_added = 0;
  2399. /* new association get rid of ibss beacon skb */
  2400. if (priv->ibss_beacon)
  2401. dev_kfree_skb(priv->ibss_beacon);
  2402. priv->ibss_beacon = NULL;
  2403. priv->beacon_int = priv->vif->bss_conf.beacon_int;
  2404. priv->timestamp = 0;
  2405. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  2406. priv->beacon_int = 0;
  2407. spin_unlock_irqrestore(&priv->lock, flags);
  2408. if (!iwl_is_ready_rf(priv)) {
  2409. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2410. mutex_unlock(&priv->mutex);
  2411. return;
  2412. }
  2413. /* we are restarting association process
  2414. * clear RXON_FILTER_ASSOC_MSK bit
  2415. */
  2416. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2417. iwl_scan_cancel_timeout(priv, 100);
  2418. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2419. iwlcore_commit_rxon(priv);
  2420. }
  2421. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  2422. IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
  2423. mutex_unlock(&priv->mutex);
  2424. return;
  2425. }
  2426. iwl_set_rate(priv);
  2427. mutex_unlock(&priv->mutex);
  2428. IWL_DEBUG_MAC80211(priv, "leave\n");
  2429. }
  2430. EXPORT_SYMBOL(iwl_mac_reset_tsf);
  2431. int iwl_alloc_txq_mem(struct iwl_priv *priv)
  2432. {
  2433. if (!priv->txq)
  2434. priv->txq = kzalloc(
  2435. sizeof(struct iwl_tx_queue) * priv->cfg->num_of_queues,
  2436. GFP_KERNEL);
  2437. if (!priv->txq) {
  2438. IWL_ERR(priv, "Not enough memory for txq \n");
  2439. return -ENOMEM;
  2440. }
  2441. return 0;
  2442. }
  2443. EXPORT_SYMBOL(iwl_alloc_txq_mem);
  2444. void iwl_free_txq_mem(struct iwl_priv *priv)
  2445. {
  2446. kfree(priv->txq);
  2447. priv->txq = NULL;
  2448. }
  2449. EXPORT_SYMBOL(iwl_free_txq_mem);
  2450. int iwl_send_wimax_coex(struct iwl_priv *priv)
  2451. {
  2452. struct iwl_wimax_coex_cmd uninitialized_var(coex_cmd);
  2453. if (priv->cfg->support_wimax_coexist) {
  2454. /* UnMask wake up src at associated sleep */
  2455. coex_cmd.flags |= COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
  2456. /* UnMask wake up src at unassociated sleep */
  2457. coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
  2458. memcpy(coex_cmd.sta_prio, cu_priorities,
  2459. sizeof(struct iwl_wimax_coex_event_entry) *
  2460. COEX_NUM_OF_EVENTS);
  2461. /* enabling the coexistence feature */
  2462. coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
  2463. /* enabling the priorities tables */
  2464. coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
  2465. } else {
  2466. /* coexistence is disabled */
  2467. memset(&coex_cmd, 0, sizeof(coex_cmd));
  2468. }
  2469. return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
  2470. sizeof(coex_cmd), &coex_cmd);
  2471. }
  2472. EXPORT_SYMBOL(iwl_send_wimax_coex);
  2473. #ifdef CONFIG_IWLWIFI_DEBUGFS
  2474. #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
  2475. void iwl_reset_traffic_log(struct iwl_priv *priv)
  2476. {
  2477. priv->tx_traffic_idx = 0;
  2478. priv->rx_traffic_idx = 0;
  2479. if (priv->tx_traffic)
  2480. memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
  2481. if (priv->rx_traffic)
  2482. memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
  2483. }
  2484. int iwl_alloc_traffic_mem(struct iwl_priv *priv)
  2485. {
  2486. u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
  2487. if (iwl_debug_level & IWL_DL_TX) {
  2488. if (!priv->tx_traffic) {
  2489. priv->tx_traffic =
  2490. kzalloc(traffic_size, GFP_KERNEL);
  2491. if (!priv->tx_traffic)
  2492. return -ENOMEM;
  2493. }
  2494. }
  2495. if (iwl_debug_level & IWL_DL_RX) {
  2496. if (!priv->rx_traffic) {
  2497. priv->rx_traffic =
  2498. kzalloc(traffic_size, GFP_KERNEL);
  2499. if (!priv->rx_traffic)
  2500. return -ENOMEM;
  2501. }
  2502. }
  2503. iwl_reset_traffic_log(priv);
  2504. return 0;
  2505. }
  2506. EXPORT_SYMBOL(iwl_alloc_traffic_mem);
  2507. void iwl_free_traffic_mem(struct iwl_priv *priv)
  2508. {
  2509. kfree(priv->tx_traffic);
  2510. priv->tx_traffic = NULL;
  2511. kfree(priv->rx_traffic);
  2512. priv->rx_traffic = NULL;
  2513. }
  2514. EXPORT_SYMBOL(iwl_free_traffic_mem);
  2515. void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
  2516. u16 length, struct ieee80211_hdr *header)
  2517. {
  2518. __le16 fc;
  2519. u16 len;
  2520. if (likely(!(iwl_debug_level & IWL_DL_TX)))
  2521. return;
  2522. if (!priv->tx_traffic)
  2523. return;
  2524. fc = header->frame_control;
  2525. if (ieee80211_is_data(fc)) {
  2526. len = (length > IWL_TRAFFIC_ENTRY_SIZE)
  2527. ? IWL_TRAFFIC_ENTRY_SIZE : length;
  2528. memcpy((priv->tx_traffic +
  2529. (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
  2530. header, len);
  2531. priv->tx_traffic_idx =
  2532. (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
  2533. }
  2534. }
  2535. EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
  2536. void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
  2537. u16 length, struct ieee80211_hdr *header)
  2538. {
  2539. __le16 fc;
  2540. u16 len;
  2541. if (likely(!(iwl_debug_level & IWL_DL_RX)))
  2542. return;
  2543. if (!priv->rx_traffic)
  2544. return;
  2545. fc = header->frame_control;
  2546. if (ieee80211_is_data(fc)) {
  2547. len = (length > IWL_TRAFFIC_ENTRY_SIZE)
  2548. ? IWL_TRAFFIC_ENTRY_SIZE : length;
  2549. memcpy((priv->rx_traffic +
  2550. (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
  2551. header, len);
  2552. priv->rx_traffic_idx =
  2553. (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
  2554. }
  2555. }
  2556. EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
  2557. const char *get_mgmt_string(int cmd)
  2558. {
  2559. switch (cmd) {
  2560. IWL_CMD(MANAGEMENT_ASSOC_REQ);
  2561. IWL_CMD(MANAGEMENT_ASSOC_RESP);
  2562. IWL_CMD(MANAGEMENT_REASSOC_REQ);
  2563. IWL_CMD(MANAGEMENT_REASSOC_RESP);
  2564. IWL_CMD(MANAGEMENT_PROBE_REQ);
  2565. IWL_CMD(MANAGEMENT_PROBE_RESP);
  2566. IWL_CMD(MANAGEMENT_BEACON);
  2567. IWL_CMD(MANAGEMENT_ATIM);
  2568. IWL_CMD(MANAGEMENT_DISASSOC);
  2569. IWL_CMD(MANAGEMENT_AUTH);
  2570. IWL_CMD(MANAGEMENT_DEAUTH);
  2571. IWL_CMD(MANAGEMENT_ACTION);
  2572. default:
  2573. return "UNKNOWN";
  2574. }
  2575. }
  2576. const char *get_ctrl_string(int cmd)
  2577. {
  2578. switch (cmd) {
  2579. IWL_CMD(CONTROL_BACK_REQ);
  2580. IWL_CMD(CONTROL_BACK);
  2581. IWL_CMD(CONTROL_PSPOLL);
  2582. IWL_CMD(CONTROL_RTS);
  2583. IWL_CMD(CONTROL_CTS);
  2584. IWL_CMD(CONTROL_ACK);
  2585. IWL_CMD(CONTROL_CFEND);
  2586. IWL_CMD(CONTROL_CFENDACK);
  2587. default:
  2588. return "UNKNOWN";
  2589. }
  2590. }
  2591. void iwl_clear_traffic_stats(struct iwl_priv *priv)
  2592. {
  2593. memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
  2594. memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
  2595. priv->led_tpt = 0;
  2596. }
  2597. /*
  2598. * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
  2599. * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
  2600. * Use debugFs to display the rx/rx_statistics
  2601. * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
  2602. * information will be recorded, but DATA pkt still will be recorded
  2603. * for the reason of iwl_led.c need to control the led blinking based on
  2604. * number of tx and rx data.
  2605. *
  2606. */
  2607. void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
  2608. {
  2609. struct traffic_stats *stats;
  2610. if (is_tx)
  2611. stats = &priv->tx_stats;
  2612. else
  2613. stats = &priv->rx_stats;
  2614. if (ieee80211_is_mgmt(fc)) {
  2615. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  2616. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  2617. stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
  2618. break;
  2619. case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
  2620. stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
  2621. break;
  2622. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  2623. stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
  2624. break;
  2625. case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
  2626. stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
  2627. break;
  2628. case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
  2629. stats->mgmt[MANAGEMENT_PROBE_REQ]++;
  2630. break;
  2631. case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
  2632. stats->mgmt[MANAGEMENT_PROBE_RESP]++;
  2633. break;
  2634. case cpu_to_le16(IEEE80211_STYPE_BEACON):
  2635. stats->mgmt[MANAGEMENT_BEACON]++;
  2636. break;
  2637. case cpu_to_le16(IEEE80211_STYPE_ATIM):
  2638. stats->mgmt[MANAGEMENT_ATIM]++;
  2639. break;
  2640. case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
  2641. stats->mgmt[MANAGEMENT_DISASSOC]++;
  2642. break;
  2643. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  2644. stats->mgmt[MANAGEMENT_AUTH]++;
  2645. break;
  2646. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  2647. stats->mgmt[MANAGEMENT_DEAUTH]++;
  2648. break;
  2649. case cpu_to_le16(IEEE80211_STYPE_ACTION):
  2650. stats->mgmt[MANAGEMENT_ACTION]++;
  2651. break;
  2652. }
  2653. } else if (ieee80211_is_ctl(fc)) {
  2654. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  2655. case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
  2656. stats->ctrl[CONTROL_BACK_REQ]++;
  2657. break;
  2658. case cpu_to_le16(IEEE80211_STYPE_BACK):
  2659. stats->ctrl[CONTROL_BACK]++;
  2660. break;
  2661. case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
  2662. stats->ctrl[CONTROL_PSPOLL]++;
  2663. break;
  2664. case cpu_to_le16(IEEE80211_STYPE_RTS):
  2665. stats->ctrl[CONTROL_RTS]++;
  2666. break;
  2667. case cpu_to_le16(IEEE80211_STYPE_CTS):
  2668. stats->ctrl[CONTROL_CTS]++;
  2669. break;
  2670. case cpu_to_le16(IEEE80211_STYPE_ACK):
  2671. stats->ctrl[CONTROL_ACK]++;
  2672. break;
  2673. case cpu_to_le16(IEEE80211_STYPE_CFEND):
  2674. stats->ctrl[CONTROL_CFEND]++;
  2675. break;
  2676. case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
  2677. stats->ctrl[CONTROL_CFENDACK]++;
  2678. break;
  2679. }
  2680. } else {
  2681. /* data */
  2682. stats->data_cnt++;
  2683. stats->data_bytes += len;
  2684. }
  2685. iwl_leds_background(priv);
  2686. }
  2687. EXPORT_SYMBOL(iwl_update_stats);
  2688. #endif
  2689. #ifdef CONFIG_PM
  2690. int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  2691. {
  2692. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2693. /*
  2694. * This function is called when system goes into suspend state
  2695. * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
  2696. * first but since iwl_mac_stop() has no knowledge of who the caller is,
  2697. * it will not call apm_ops.stop() to stop the DMA operation.
  2698. * Calling apm_ops.stop here to make sure we stop the DMA.
  2699. */
  2700. priv->cfg->ops->lib->apm_ops.stop(priv);
  2701. pci_save_state(pdev);
  2702. pci_disable_device(pdev);
  2703. pci_set_power_state(pdev, PCI_D3hot);
  2704. return 0;
  2705. }
  2706. EXPORT_SYMBOL(iwl_pci_suspend);
  2707. int iwl_pci_resume(struct pci_dev *pdev)
  2708. {
  2709. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2710. int ret;
  2711. pci_set_power_state(pdev, PCI_D0);
  2712. ret = pci_enable_device(pdev);
  2713. if (ret)
  2714. return ret;
  2715. pci_restore_state(pdev);
  2716. iwl_enable_interrupts(priv);
  2717. return 0;
  2718. }
  2719. EXPORT_SYMBOL(iwl_pci_resume);
  2720. #endif /* CONFIG_PM */