ehci-fsl.c 19 KB

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  1. /*
  2. * Copyright 2005-2009 MontaVista Software, Inc.
  3. * Copyright 2008,2012 Freescale Semiconductor, Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  13. * for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software Foundation,
  17. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. *
  19. * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
  20. * by Hunter Wu.
  21. * Power Management support by Dave Liu <daveliu@freescale.com>,
  22. * Jerry Huang <Chang-Ming.Huang@freescale.com> and
  23. * Anton Vorontsov <avorontsov@ru.mvista.com>.
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/types.h>
  27. #include <linux/delay.h>
  28. #include <linux/pm.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/fsl_devices.h>
  31. #include "ehci-fsl.h"
  32. /* configure so an HC device and id are always provided */
  33. /* always called with process context; sleeping is OK */
  34. /**
  35. * usb_hcd_fsl_probe - initialize FSL-based HCDs
  36. * @drvier: Driver to be used for this HCD
  37. * @pdev: USB Host Controller being probed
  38. * Context: !in_interrupt()
  39. *
  40. * Allocates basic resources for this USB host controller.
  41. *
  42. */
  43. static int usb_hcd_fsl_probe(const struct hc_driver *driver,
  44. struct platform_device *pdev)
  45. {
  46. struct fsl_usb2_platform_data *pdata;
  47. struct usb_hcd *hcd;
  48. struct resource *res;
  49. int irq;
  50. int retval;
  51. pr_debug("initializing FSL-SOC USB Controller\n");
  52. /* Need platform data for setup */
  53. pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
  54. if (!pdata) {
  55. dev_err(&pdev->dev,
  56. "No platform data for %s.\n", dev_name(&pdev->dev));
  57. return -ENODEV;
  58. }
  59. /*
  60. * This is a host mode driver, verify that we're supposed to be
  61. * in host mode.
  62. */
  63. if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  64. (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
  65. (pdata->operating_mode == FSL_USB2_DR_OTG))) {
  66. dev_err(&pdev->dev,
  67. "Non Host Mode configured for %s. Wrong driver linked.\n",
  68. dev_name(&pdev->dev));
  69. return -ENODEV;
  70. }
  71. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  72. if (!res) {
  73. dev_err(&pdev->dev,
  74. "Found HC with no IRQ. Check %s setup!\n",
  75. dev_name(&pdev->dev));
  76. return -ENODEV;
  77. }
  78. irq = res->start;
  79. hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
  80. if (!hcd) {
  81. retval = -ENOMEM;
  82. goto err1;
  83. }
  84. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  85. if (!res) {
  86. dev_err(&pdev->dev,
  87. "Found HC with no register addr. Check %s setup!\n",
  88. dev_name(&pdev->dev));
  89. retval = -ENODEV;
  90. goto err2;
  91. }
  92. hcd->rsrc_start = res->start;
  93. hcd->rsrc_len = resource_size(res);
  94. if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
  95. driver->description)) {
  96. dev_dbg(&pdev->dev, "controller already in use\n");
  97. retval = -EBUSY;
  98. goto err2;
  99. }
  100. hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
  101. if (hcd->regs == NULL) {
  102. dev_dbg(&pdev->dev, "error mapping memory\n");
  103. retval = -EFAULT;
  104. goto err3;
  105. }
  106. pdata->regs = hcd->regs;
  107. if (pdata->power_budget)
  108. hcd->power_budget = pdata->power_budget;
  109. /*
  110. * do platform specific init: check the clock, grab/config pins, etc.
  111. */
  112. if (pdata->init && pdata->init(pdev)) {
  113. retval = -ENODEV;
  114. goto err4;
  115. }
  116. /* Enable USB controller, 83xx or 8536 */
  117. if (pdata->have_sysif_regs)
  118. setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
  119. /* Don't need to set host mode here. It will be done by tdi_reset() */
  120. retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
  121. if (retval != 0)
  122. goto err4;
  123. #ifdef CONFIG_USB_OTG
  124. if (pdata->operating_mode == FSL_USB2_DR_OTG) {
  125. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  126. hcd->phy = usb_get_transceiver();
  127. dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
  128. hcd, ehci, hcd->phy);
  129. if (hcd->phy) {
  130. retval = otg_set_host(hcd->phy->otg,
  131. &ehci_to_hcd(ehci)->self);
  132. if (retval) {
  133. usb_put_transceiver(hcd->phy);
  134. goto err4;
  135. }
  136. } else {
  137. dev_err(&pdev->dev, "can't find phy\n");
  138. retval = -ENODEV;
  139. goto err4;
  140. }
  141. }
  142. #endif
  143. return retval;
  144. err4:
  145. iounmap(hcd->regs);
  146. err3:
  147. release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
  148. err2:
  149. usb_put_hcd(hcd);
  150. err1:
  151. dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
  152. if (pdata->exit)
  153. pdata->exit(pdev);
  154. return retval;
  155. }
  156. /* may be called without controller electrically present */
  157. /* may be called with controller, bus, and devices active */
  158. /**
  159. * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs
  160. * @dev: USB Host Controller being removed
  161. * Context: !in_interrupt()
  162. *
  163. * Reverses the effect of usb_hcd_fsl_probe().
  164. *
  165. */
  166. static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
  167. struct platform_device *pdev)
  168. {
  169. struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
  170. if (hcd->phy) {
  171. otg_set_host(hcd->phy->otg, NULL);
  172. usb_put_transceiver(hcd->phy);
  173. }
  174. usb_remove_hcd(hcd);
  175. /*
  176. * do platform specific un-initialization:
  177. * release iomux pins, disable clock, etc.
  178. */
  179. if (pdata->exit)
  180. pdata->exit(pdev);
  181. iounmap(hcd->regs);
  182. release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
  183. usb_put_hcd(hcd);
  184. }
  185. static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
  186. enum fsl_usb2_phy_modes phy_mode,
  187. unsigned int port_offset)
  188. {
  189. u32 portsc, temp;
  190. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  191. void __iomem *non_ehci = hcd->regs;
  192. struct device *dev = hcd->self.controller;
  193. struct fsl_usb2_platform_data *pdata = dev->platform_data;
  194. if (pdata->controller_ver < 0) {
  195. dev_warn(hcd->self.controller, "Could not get controller version\n");
  196. return;
  197. }
  198. portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
  199. portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
  200. switch (phy_mode) {
  201. case FSL_USB2_PHY_ULPI:
  202. if (pdata->controller_ver) {
  203. /* controller version 1.6 or above */
  204. temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
  205. out_be32(non_ehci + FSL_SOC_USB_CTRL, temp |
  206. USB_CTRL_USB_EN | ULPI_PHY_CLK_SEL);
  207. }
  208. portsc |= PORT_PTS_ULPI;
  209. break;
  210. case FSL_USB2_PHY_SERIAL:
  211. portsc |= PORT_PTS_SERIAL;
  212. break;
  213. case FSL_USB2_PHY_UTMI_WIDE:
  214. portsc |= PORT_PTS_PTW;
  215. /* fall through */
  216. case FSL_USB2_PHY_UTMI:
  217. if (pdata->controller_ver) {
  218. /* controller version 1.6 or above */
  219. temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
  220. out_be32(non_ehci + FSL_SOC_USB_CTRL, temp |
  221. UTMI_PHY_EN | USB_CTRL_USB_EN);
  222. mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
  223. become stable - 10ms*/
  224. }
  225. /* enable UTMI PHY */
  226. if (pdata->have_sysif_regs)
  227. setbits32(non_ehci + FSL_SOC_USB_CTRL,
  228. CTRL_UTMI_PHY_EN);
  229. portsc |= PORT_PTS_UTMI;
  230. break;
  231. case FSL_USB2_PHY_NONE:
  232. break;
  233. }
  234. ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
  235. }
  236. static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
  237. {
  238. struct usb_hcd *hcd = ehci_to_hcd(ehci);
  239. struct fsl_usb2_platform_data *pdata;
  240. void __iomem *non_ehci = hcd->regs;
  241. u32 temp;
  242. pdata = hcd->self.controller->platform_data;
  243. /* Enable PHY interface in the control reg. */
  244. if (pdata->have_sysif_regs) {
  245. temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
  246. out_be32(non_ehci + FSL_SOC_USB_CTRL, temp | 0x00000004);
  247. /*
  248. * Turn on cache snooping hardware, since some PowerPC platforms
  249. * wholly rely on hardware to deal with cache coherent
  250. */
  251. /* Setup Snooping for all the 4GB space */
  252. /* SNOOP1 starts from 0x0, size 2G */
  253. out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB);
  254. /* SNOOP2 starts from 0x80000000, size 2G */
  255. out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
  256. }
  257. if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  258. (pdata->operating_mode == FSL_USB2_DR_OTG))
  259. ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0);
  260. if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
  261. unsigned int chip, rev, svr;
  262. svr = mfspr(SPRN_SVR);
  263. chip = svr >> 16;
  264. rev = (svr >> 4) & 0xf;
  265. /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
  266. if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
  267. ehci->has_fsl_port_bug = 1;
  268. if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
  269. ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0);
  270. if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
  271. ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1);
  272. }
  273. if (pdata->have_sysif_regs) {
  274. #ifdef CONFIG_PPC_85xx
  275. out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
  276. out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080);
  277. #else
  278. out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c);
  279. out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040);
  280. #endif
  281. out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
  282. }
  283. }
  284. /* called after powerup, by probe or system-pm "wakeup" */
  285. static int ehci_fsl_reinit(struct ehci_hcd *ehci)
  286. {
  287. ehci_fsl_usb_setup(ehci);
  288. ehci_port_power(ehci, 0);
  289. return 0;
  290. }
  291. /* called during probe() after chip reset completes */
  292. static int ehci_fsl_setup(struct usb_hcd *hcd)
  293. {
  294. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  295. int retval;
  296. struct fsl_usb2_platform_data *pdata;
  297. struct device *dev;
  298. dev = hcd->self.controller;
  299. pdata = hcd->self.controller->platform_data;
  300. ehci->big_endian_desc = pdata->big_endian_desc;
  301. ehci->big_endian_mmio = pdata->big_endian_mmio;
  302. /* EHCI registers start at offset 0x100 */
  303. ehci->caps = hcd->regs + 0x100;
  304. ehci->regs = hcd->regs + 0x100 +
  305. HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
  306. dbg_hcs_params(ehci, "reset");
  307. dbg_hcc_params(ehci, "reset");
  308. /* cache this readonly data; minimize chip reads */
  309. ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
  310. hcd->has_tt = 1;
  311. retval = ehci_halt(ehci);
  312. if (retval)
  313. return retval;
  314. /* data structure init */
  315. retval = ehci_init(hcd);
  316. if (retval)
  317. return retval;
  318. ehci->sbrn = 0x20;
  319. ehci_reset(ehci);
  320. if (of_device_is_compatible(dev->parent->of_node,
  321. "fsl,mpc5121-usb2-dr")) {
  322. /*
  323. * set SBUSCFG:AHBBRST so that control msgs don't
  324. * fail when doing heavy PATA writes.
  325. */
  326. ehci_writel(ehci, SBUSCFG_INCR8,
  327. hcd->regs + FSL_SOC_USB_SBUSCFG);
  328. }
  329. retval = ehci_fsl_reinit(ehci);
  330. return retval;
  331. }
  332. struct ehci_fsl {
  333. struct ehci_hcd ehci;
  334. #ifdef CONFIG_PM
  335. /* Saved USB PHY settings, need to restore after deep sleep. */
  336. u32 usb_ctrl;
  337. #endif
  338. };
  339. #ifdef CONFIG_PM
  340. #ifdef CONFIG_PPC_MPC512x
  341. static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
  342. {
  343. struct usb_hcd *hcd = dev_get_drvdata(dev);
  344. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  345. struct fsl_usb2_platform_data *pdata = dev->platform_data;
  346. u32 tmp;
  347. #ifdef DEBUG
  348. u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
  349. mode &= USBMODE_CM_MASK;
  350. tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
  351. dev_dbg(dev, "suspend=%d already_suspended=%d "
  352. "mode=%d usbcmd %08x\n", pdata->suspended,
  353. pdata->already_suspended, mode, tmp);
  354. #endif
  355. /*
  356. * If the controller is already suspended, then this must be a
  357. * PM suspend. Remember this fact, so that we will leave the
  358. * controller suspended at PM resume time.
  359. */
  360. if (pdata->suspended) {
  361. dev_dbg(dev, "already suspended, leaving early\n");
  362. pdata->already_suspended = 1;
  363. return 0;
  364. }
  365. dev_dbg(dev, "suspending...\n");
  366. ehci->rh_state = EHCI_RH_SUSPENDED;
  367. dev->power.power_state = PMSG_SUSPEND;
  368. /* ignore non-host interrupts */
  369. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  370. /* stop the controller */
  371. tmp = ehci_readl(ehci, &ehci->regs->command);
  372. tmp &= ~CMD_RUN;
  373. ehci_writel(ehci, tmp, &ehci->regs->command);
  374. /* save EHCI registers */
  375. pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
  376. pdata->pm_command &= ~CMD_RUN;
  377. pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
  378. pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
  379. pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
  380. pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
  381. pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
  382. pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
  383. pdata->pm_configured_flag =
  384. ehci_readl(ehci, &ehci->regs->configured_flag);
  385. pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
  386. pdata->pm_usbgenctrl = ehci_readl(ehci,
  387. hcd->regs + FSL_SOC_USB_USBGENCTRL);
  388. /* clear the W1C bits */
  389. pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
  390. pdata->suspended = 1;
  391. /* clear PP to cut power to the port */
  392. tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
  393. tmp &= ~PORT_POWER;
  394. ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
  395. return 0;
  396. }
  397. static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
  398. {
  399. struct usb_hcd *hcd = dev_get_drvdata(dev);
  400. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  401. struct fsl_usb2_platform_data *pdata = dev->platform_data;
  402. u32 tmp;
  403. dev_dbg(dev, "suspend=%d already_suspended=%d\n",
  404. pdata->suspended, pdata->already_suspended);
  405. /*
  406. * If the controller was already suspended at suspend time,
  407. * then don't resume it now.
  408. */
  409. if (pdata->already_suspended) {
  410. dev_dbg(dev, "already suspended, leaving early\n");
  411. pdata->already_suspended = 0;
  412. return 0;
  413. }
  414. if (!pdata->suspended) {
  415. dev_dbg(dev, "not suspended, leaving early\n");
  416. return 0;
  417. }
  418. pdata->suspended = 0;
  419. dev_dbg(dev, "resuming...\n");
  420. /* set host mode */
  421. tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
  422. ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
  423. ehci_writel(ehci, pdata->pm_usbgenctrl,
  424. hcd->regs + FSL_SOC_USB_USBGENCTRL);
  425. ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
  426. hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
  427. ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
  428. /* restore EHCI registers */
  429. ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
  430. ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
  431. ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
  432. ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
  433. ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
  434. ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
  435. ehci_writel(ehci, pdata->pm_configured_flag,
  436. &ehci->regs->configured_flag);
  437. ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
  438. set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  439. ehci->rh_state = EHCI_RH_RUNNING;
  440. dev->power.power_state = PMSG_ON;
  441. tmp = ehci_readl(ehci, &ehci->regs->command);
  442. tmp |= CMD_RUN;
  443. ehci_writel(ehci, tmp, &ehci->regs->command);
  444. usb_hcd_resume_root_hub(hcd);
  445. return 0;
  446. }
  447. #else
  448. static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
  449. {
  450. return 0;
  451. }
  452. static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
  453. {
  454. return 0;
  455. }
  456. #endif /* CONFIG_PPC_MPC512x */
  457. static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
  458. {
  459. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  460. return container_of(ehci, struct ehci_fsl, ehci);
  461. }
  462. static int ehci_fsl_drv_suspend(struct device *dev)
  463. {
  464. struct usb_hcd *hcd = dev_get_drvdata(dev);
  465. struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  466. void __iomem *non_ehci = hcd->regs;
  467. if (of_device_is_compatible(dev->parent->of_node,
  468. "fsl,mpc5121-usb2-dr")) {
  469. return ehci_fsl_mpc512x_drv_suspend(dev);
  470. }
  471. ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
  472. device_may_wakeup(dev));
  473. if (!fsl_deep_sleep())
  474. return 0;
  475. ehci_fsl->usb_ctrl = in_be32(non_ehci + FSL_SOC_USB_CTRL);
  476. return 0;
  477. }
  478. static int ehci_fsl_drv_resume(struct device *dev)
  479. {
  480. struct usb_hcd *hcd = dev_get_drvdata(dev);
  481. struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  482. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  483. void __iomem *non_ehci = hcd->regs;
  484. if (of_device_is_compatible(dev->parent->of_node,
  485. "fsl,mpc5121-usb2-dr")) {
  486. return ehci_fsl_mpc512x_drv_resume(dev);
  487. }
  488. ehci_prepare_ports_for_controller_resume(ehci);
  489. if (!fsl_deep_sleep())
  490. return 0;
  491. usb_root_hub_lost_power(hcd->self.root_hub);
  492. /* Restore USB PHY settings and enable the controller. */
  493. out_be32(non_ehci + FSL_SOC_USB_CTRL, ehci_fsl->usb_ctrl);
  494. ehci_reset(ehci);
  495. ehci_fsl_reinit(ehci);
  496. return 0;
  497. }
  498. static int ehci_fsl_drv_restore(struct device *dev)
  499. {
  500. struct usb_hcd *hcd = dev_get_drvdata(dev);
  501. usb_root_hub_lost_power(hcd->self.root_hub);
  502. return 0;
  503. }
  504. static struct dev_pm_ops ehci_fsl_pm_ops = {
  505. .suspend = ehci_fsl_drv_suspend,
  506. .resume = ehci_fsl_drv_resume,
  507. .restore = ehci_fsl_drv_restore,
  508. };
  509. #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
  510. #else
  511. #define EHCI_FSL_PM_OPS NULL
  512. #endif /* CONFIG_PM */
  513. #ifdef CONFIG_USB_OTG
  514. static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
  515. {
  516. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  517. u32 status;
  518. if (!port)
  519. return -EINVAL;
  520. port--;
  521. /* start port reset before HNP protocol time out */
  522. status = readl(&ehci->regs->port_status[port]);
  523. if (!(status & PORT_CONNECT))
  524. return -ENODEV;
  525. /* khubd will finish the reset later */
  526. if (ehci_is_TDI(ehci)) {
  527. writel(PORT_RESET |
  528. (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
  529. &ehci->regs->port_status[port]);
  530. } else {
  531. writel(PORT_RESET, &ehci->regs->port_status[port]);
  532. }
  533. return 0;
  534. }
  535. #else
  536. #define ehci_start_port_reset NULL
  537. #endif /* CONFIG_USB_OTG */
  538. static const struct hc_driver ehci_fsl_hc_driver = {
  539. .description = hcd_name,
  540. .product_desc = "Freescale On-Chip EHCI Host Controller",
  541. .hcd_priv_size = sizeof(struct ehci_fsl),
  542. /*
  543. * generic hardware linkage
  544. */
  545. .irq = ehci_irq,
  546. .flags = HCD_USB2 | HCD_MEMORY,
  547. /*
  548. * basic lifecycle operations
  549. */
  550. .reset = ehci_fsl_setup,
  551. .start = ehci_run,
  552. .stop = ehci_stop,
  553. .shutdown = ehci_shutdown,
  554. /*
  555. * managing i/o requests and associated device resources
  556. */
  557. .urb_enqueue = ehci_urb_enqueue,
  558. .urb_dequeue = ehci_urb_dequeue,
  559. .endpoint_disable = ehci_endpoint_disable,
  560. .endpoint_reset = ehci_endpoint_reset,
  561. /*
  562. * scheduling support
  563. */
  564. .get_frame_number = ehci_get_frame,
  565. /*
  566. * root hub support
  567. */
  568. .hub_status_data = ehci_hub_status_data,
  569. .hub_control = ehci_hub_control,
  570. .bus_suspend = ehci_bus_suspend,
  571. .bus_resume = ehci_bus_resume,
  572. .start_port_reset = ehci_start_port_reset,
  573. .relinquish_port = ehci_relinquish_port,
  574. .port_handed_over = ehci_port_handed_over,
  575. .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
  576. };
  577. static int ehci_fsl_drv_probe(struct platform_device *pdev)
  578. {
  579. if (usb_disabled())
  580. return -ENODEV;
  581. /* FIXME we only want one one probe() not two */
  582. return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev);
  583. }
  584. static int ehci_fsl_drv_remove(struct platform_device *pdev)
  585. {
  586. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  587. /* FIXME we only want one one remove() not two */
  588. usb_hcd_fsl_remove(hcd, pdev);
  589. return 0;
  590. }
  591. MODULE_ALIAS("platform:fsl-ehci");
  592. static struct platform_driver ehci_fsl_driver = {
  593. .probe = ehci_fsl_drv_probe,
  594. .remove = ehci_fsl_drv_remove,
  595. .shutdown = usb_hcd_platform_shutdown,
  596. .driver = {
  597. .name = "fsl-ehci",
  598. .pm = EHCI_FSL_PM_OPS,
  599. },
  600. };